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-rw-r--r--arch/mips/Kconfig9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e4198c5c2aa8..04a413d52b26 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -890,6 +890,7 @@ config MACH_TX39XX
config MACH_TX49XX
bool "Toshiba TX49 series based machines"
+ select WAR_TX49XX_ICACHE_INDEX_INV
config MIKROTIK_RB532
bool "Mikrotik RB532 boards"
@@ -2657,6 +2658,14 @@ config WAR_R4600_V1_HIT_CACHEOP
config WAR_R4600_V2_HIT_CACHEOP
bool
+# From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
+# the line which this instruction itself exists, the following
+# operation is not guaranteed."
+#
+# Workaround: do two phase flushing for Index_Invalidate_I
+config WAR_TX49XX_ICACHE_INDEX_INV
+ bool
+
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed