diff options
Diffstat (limited to 'arch/mips/ath79')
32 files changed, 621 insertions, 2901 deletions
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 3995e31a73e2..04154128c4de 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -1,128 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0 if ATH79 -menu "Atheros AR71XX/AR724X/AR913X machine selection" - -config ATH79_MACH_AP121 - bool "Atheros AP121 reference board" - select SOC_AR933X - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO - select ATH79_DEV_SPI - select ATH79_DEV_USB - select ATH79_DEV_WMAC - help - Say 'Y' here if you want your kernel to support the - Atheros AP121 reference board. - -config ATH79_MACH_AP136 - bool "Atheros AP136 reference board" - select SOC_QCA955X - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO - select ATH79_DEV_SPI - select ATH79_DEV_USB - select ATH79_DEV_WMAC - help - Say 'Y' here if you want your kernel to support the - Atheros AP136 reference board. - -config ATH79_MACH_AP81 - bool "Atheros AP81 reference board" - select SOC_AR913X - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO - select ATH79_DEV_SPI - select ATH79_DEV_USB - select ATH79_DEV_WMAC - help - Say 'Y' here if you want your kernel to support the - Atheros AP81 reference board. - -config ATH79_MACH_DB120 - bool "Atheros DB120 reference board" - select SOC_AR934X - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO - select ATH79_DEV_SPI - select ATH79_DEV_USB - select ATH79_DEV_WMAC - help - Say 'Y' here if you want your kernel to support the - Atheros DB120 reference board. - -config ATH79_MACH_PB44 - bool "Atheros PB44 reference board" - select SOC_AR71XX - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO - select ATH79_DEV_SPI - select ATH79_DEV_USB - help - Say 'Y' here if you want your kernel to support the - Atheros PB44 reference board. - -config ATH79_MACH_UBNT_XM - bool "Ubiquiti Networks XM (rev 1.0) board" - select SOC_AR724X - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO - select ATH79_DEV_SPI - help - Say 'Y' here if you want your kernel to support the - Ubiquiti Networks XM (rev 1.0) board. - -endmenu - config SOC_AR71XX - select USB_ARCH_HAS_EHCI - select USB_ARCH_HAS_OHCI - select HW_HAS_PCI + select HAVE_PCI def_bool n config SOC_AR724X - select USB_ARCH_HAS_EHCI - select USB_ARCH_HAS_OHCI - select HW_HAS_PCI + select HAVE_PCI select PCI_AR724X if PCI def_bool n config SOC_AR913X - select USB_ARCH_HAS_EHCI def_bool n config SOC_AR933X - select USB_ARCH_HAS_EHCI def_bool n config SOC_AR934X - select USB_ARCH_HAS_EHCI - select HW_HAS_PCI + select HAVE_PCI select PCI_AR724X if PCI def_bool n config SOC_QCA955X - select USB_ARCH_HAS_EHCI - select HW_HAS_PCI + select HAVE_PCI select PCI_AR724X if PCI def_bool n config PCI_AR724X def_bool n -config ATH79_DEV_GPIO_BUTTONS - def_bool n - -config ATH79_DEV_LEDS_GPIO - def_bool n - -config ATH79_DEV_SPI - def_bool n - -config ATH79_DEV_USB - def_bool n - -config ATH79_DEV_WMAC - depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) - def_bool n - endif diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile index 5c9ff692ff3c..0fb3aaf42149 100644 --- a/arch/mips/ath79/Makefile +++ b/arch/mips/ath79/Makefile @@ -1,34 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only # # Makefile for the Atheros AR71XX/AR724X/AR913X specific parts of the kernel # # Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> # Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> # -# This program is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License version 2 as published -# by the Free Software Foundation. -obj-y := prom.o setup.o irq.o common.o clock.o gpio.o +obj-y := prom.o setup.o common.o clock.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -obj-$(CONFIG_PCI) += pci.o - -# -# Devices -# -obj-y += dev-common.o -obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o -obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o -obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o -obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o -obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o - -# -# Machines -# -obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o -obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o -obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o -obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o -obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o -obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o diff --git a/arch/mips/ath79/Platform b/arch/mips/ath79/Platform index 2bd663647d27..57744472ed2e 100644 --- a/arch/mips/ath79/Platform +++ b/arch/mips/ath79/Platform @@ -2,6 +2,5 @@ # Atheros AR71xx/AR724x/AR913x # -platform-$(CONFIG_ATH79) += ath79/ cflags-$(CONFIG_ATH79) += -I$(srctree)/arch/mips/include/asm/mach-ath79 load-$(CONFIG_ATH79) = 0xffffffff80060000 diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c index 765ef30e3e1c..050f6553f398 100644 --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Atheros AR71XX/AR724X/AR913X common routines * @@ -5,17 +6,18 @@ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> * * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. */ #include <linux/kernel.h> -#include <linux/module.h> #include <linux/init.h> +#include <linux/io.h> #include <linux/err.h> #include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <dt-bindings/clock/ath79-clk.h> #include <asm/div64.h> @@ -24,148 +26,187 @@ #include "common.h" #define AR71XX_BASE_FREQ 40000000 -#define AR724X_BASE_FREQ 5000000 -#define AR913X_BASE_FREQ 5000000 +#define AR724X_BASE_FREQ 40000000 -struct clk { - unsigned long rate; +static struct clk *clks[ATH79_CLK_END]; +static struct clk_onecell_data clk_data = { + .clks = clks, + .clk_num = ARRAY_SIZE(clks), }; -static struct clk ath79_ref_clk; -static struct clk ath79_cpu_clk; -static struct clk ath79_ddr_clk; -static struct clk ath79_ahb_clk; -static struct clk ath79_wdt_clk; -static struct clk ath79_uart_clk; +static const char * const clk_names[ATH79_CLK_END] = { + [ATH79_CLK_CPU] = "cpu", + [ATH79_CLK_DDR] = "ddr", + [ATH79_CLK_AHB] = "ahb", + [ATH79_CLK_REF] = "ref", + [ATH79_CLK_MDIO] = "mdio", +}; -static void __init ar71xx_clocks_init(void) +static const char * __init ath79_clk_name(int type) { - u32 pll; - u32 freq; - u32 div; + BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]); + return clk_names[type]; +} - ath79_ref_clk.rate = AR71XX_BASE_FREQ; +static void __init __ath79_set_clk(int type, const char *name, struct clk *clk) +{ + if (IS_ERR(clk)) + panic("failed to allocate %s clock structure", clk_names[type]); - pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); + clks[type] = clk; + clk_register_clkdev(clk, name, NULL); +} - div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; - freq = div * ath79_ref_clk.rate; +static struct clk * __init ath79_set_clk(int type, unsigned long rate) +{ + const char *name = ath79_clk_name(type); + struct clk *clk; - div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; - ath79_cpu_clk.rate = freq / div; + clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate); + __ath79_set_clk(type, name, clk); + return clk; +} - div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; - ath79_ddr_clk.rate = freq / div; +static struct clk * __init ath79_set_ff_clk(int type, const char *parent, + unsigned int mult, unsigned int div) +{ + const char *name = ath79_clk_name(type); + struct clk *clk; - div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; - ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; + clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div); + __ath79_set_clk(type, name, clk); + return clk; +} + +static unsigned long __init ath79_setup_ref_clk(unsigned long rate) +{ + struct clk *clk = clks[ATH79_CLK_REF]; + + if (clk) + rate = clk_get_rate(clk); + else + clk = ath79_set_clk(ATH79_CLK_REF, rate); - ath79_wdt_clk.rate = ath79_ahb_clk.rate; - ath79_uart_clk.rate = ath79_ahb_clk.rate; + return rate; } -static void __init ar724x_clocks_init(void) +static void __init ar71xx_clocks_init(void __iomem *pll_base) { + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; u32 pll; u32 freq; u32 div; - ath79_ref_clk.rate = AR724X_BASE_FREQ; - pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); + ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ); - div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); - freq = div * ath79_ref_clk.rate; + pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); - div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); - freq *= div; + div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; + freq = div * ref_rate; - ath79_cpu_clk.rate = freq; + div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; + cpu_rate = freq / div; - div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; - ath79_ddr_clk.rate = freq / div; + div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; + ddr_rate = freq / div; - div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; - ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; + div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; + ahb_rate = cpu_rate / div; - ath79_wdt_clk.rate = ath79_ahb_clk.rate; - ath79_uart_clk.rate = ath79_ahb_clk.rate; + ath79_set_clk(ATH79_CLK_CPU, cpu_rate); + ath79_set_clk(ATH79_CLK_DDR, ddr_rate); + ath79_set_clk(ATH79_CLK_AHB, ahb_rate); } -static void __init ar913x_clocks_init(void) +static void __init ar724x_clocks_init(void __iomem *pll_base) { + u32 mult, div, ddr_div, ahb_div; u32 pll; - u32 freq; - u32 div; - ath79_ref_clk.rate = AR913X_BASE_FREQ; - pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG); + ath79_setup_ref_clk(AR71XX_BASE_FREQ); - div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK); - freq = div * ath79_ref_clk.rate; + pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); - ath79_cpu_clk.rate = freq; + mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); + div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; - div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1; - ath79_ddr_clk.rate = freq / div; + ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; + ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; - div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2; - ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; - - ath79_wdt_clk.rate = ath79_ahb_clk.rate; - ath79_uart_clk.rate = ath79_ahb_clk.rate; + ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div); + ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div); + ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div); } -static void __init ar933x_clocks_init(void) +static void __init ar933x_clocks_init(void __iomem *pll_base) { + unsigned long ref_rate; u32 clock_ctrl; - u32 cpu_config; - u32 freq; + u32 ref_div; + u32 ninit_mul; + u32 out_div; + + u32 cpu_div; + u32 ddr_div; + u32 ahb_div; u32 t; t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); if (t & AR933X_BOOTSTRAP_REF_CLK_40) - ath79_ref_clk.rate = (40 * 1000 * 1000); + ref_rate = (40 * 1000 * 1000); else - ath79_ref_clk.rate = (25 * 1000 * 1000); + ref_rate = (25 * 1000 * 1000); - clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG); + ath79_setup_ref_clk(ref_rate); + + clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { - ath79_cpu_clk.rate = ath79_ref_clk.rate; - ath79_ahb_clk.rate = ath79_ref_clk.rate; - ath79_ddr_clk.rate = ath79_ref_clk.rate; + ref_div = 1; + ninit_mul = 1; + out_div = 1; + + cpu_div = 1; + ddr_div = 1; + ahb_div = 1; } else { - cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG); + u32 cpu_config; + u32 t; + + cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG); t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & AR933X_PLL_CPU_CONFIG_REFDIV_MASK; - freq = ath79_ref_clk.rate / t; + ref_div = t; - t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & + ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & AR933X_PLL_CPU_CONFIG_NINT_MASK; - freq *= t; t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; if (t == 0) t = 1; - freq >>= t; + out_div = (1 << t); - t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & + cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; - ath79_cpu_clk.rate = freq / t; - t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & + ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; - ath79_ddr_clk.rate = freq / t; - t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & + ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; - ath79_ahb_clk.rate = freq / t; } - ath79_wdt_clk.rate = ath79_ref_clk.rate; - ath79_uart_clk.rate = ath79_ref_clk.rate; + ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul, + ref_div * out_div * cpu_div); + ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul, + ref_div * out_div * ddr_div); + ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul, + ref_div * out_div * ahb_div); } static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, @@ -174,12 +215,12 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, u64 t; u32 ret; - t = ath79_ref_clk.rate; + t = ref; t *= nint; do_div(t, ref_div); ret = t; - t = ath79_ref_clk.rate; + t = ref; t *= nfrac; do_div(t, ref_div * frac); ret += t; @@ -188,8 +229,12 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, return ret; } -static void __init ar934x_clocks_init(void) +static void __init ar934x_clocks_init(void __iomem *pll_base) { + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; u32 cpu_pll, ddr_pll; u32 bootstrap; @@ -199,9 +244,11 @@ static void __init ar934x_clocks_init(void) bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) - ath79_ref_clk.rate = 40 * 1000 * 1000; + ref_rate = 40 * 1000 * 1000; else - ath79_ref_clk.rate = 25 * 1000 * 1000; + ref_rate = 25 * 1000 * 1000; + + ref_rate = ath79_setup_ref_clk(ref_rate); pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { @@ -215,7 +262,7 @@ static void __init ar934x_clocks_init(void) AR934X_SRIF_DPLL1_REFDIV_MASK; frac = 1 << 18; } else { - pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); + pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & @@ -227,7 +274,7 @@ static void __init ar934x_clocks_init(void) frac = 1 << 6; } - cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, + cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, nfrac, frac, out_div); pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); @@ -242,7 +289,7 @@ static void __init ar934x_clocks_init(void) AR934X_SRIF_DPLL1_REFDIV_MASK; frac = 1 << 18; } else { - pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); + pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & @@ -254,60 +301,154 @@ static void __init ar934x_clocks_init(void) frac = 1 << 10; } - ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint, + ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, nfrac, frac, out_div); - clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); + clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) - ath79_cpu_clk.rate = ath79_ref_clk.rate; + cpu_rate = ref_rate; else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) - ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); + cpu_rate = cpu_pll / (postdiv + 1); else - ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); + cpu_rate = ddr_pll / (postdiv + 1); postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) - ath79_ddr_clk.rate = ath79_ref_clk.rate; + ddr_rate = ref_rate; else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) - ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); + ddr_rate = ddr_pll / (postdiv + 1); else - ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); + ddr_rate = cpu_pll / (postdiv + 1); postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) - ath79_ahb_clk.rate = ath79_ref_clk.rate; + ahb_rate = ref_rate; else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) - ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); + ahb_rate = ddr_pll / (postdiv + 1); else - ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); + ahb_rate = cpu_pll / (postdiv + 1); + + ath79_set_clk(ATH79_CLK_CPU, cpu_rate); + ath79_set_clk(ATH79_CLK_DDR, ddr_rate); + ath79_set_clk(ATH79_CLK_AHB, ahb_rate); - ath79_wdt_clk.rate = ath79_ref_clk.rate; - ath79_uart_clk.rate = ath79_ref_clk.rate; + clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); + if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) + ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000); iounmap(dpll_base); } -static void __init qca955x_clocks_init(void) +static void __init qca953x_clocks_init(void __iomem *pll_base) { + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; + u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; + u32 cpu_pll, ddr_pll; + u32 bootstrap; + + bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); + if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40) + ref_rate = 40 * 1000 * 1000; + else + ref_rate = 25 * 1000 * 1000; + + ref_rate = ath79_setup_ref_clk(ref_rate); + + pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG); + out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; + ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + QCA953X_PLL_CPU_CONFIG_REFDIV_MASK; + nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) & + QCA953X_PLL_CPU_CONFIG_NINT_MASK; + frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) & + QCA953X_PLL_CPU_CONFIG_NFRAC_MASK; + + cpu_pll = nint * ref_rate / ref_div; + cpu_pll += frac * (ref_rate >> 6) / ref_div; + cpu_pll /= (1 << out_div); + + pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG); + out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & + QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK; + ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & + QCA953X_PLL_DDR_CONFIG_REFDIV_MASK; + nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) & + QCA953X_PLL_DDR_CONFIG_NINT_MASK; + frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) & + QCA953X_PLL_DDR_CONFIG_NFRAC_MASK; + + ddr_pll = nint * ref_rate / ref_div; + ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4); + ddr_pll /= (1 << out_div); + + clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG); + + postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & + QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; + + if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS) + cpu_rate = ref_rate; + else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) + cpu_rate = cpu_pll / (postdiv + 1); + else + cpu_rate = ddr_pll / (postdiv + 1); + + postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & + QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; + + if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS) + ddr_rate = ref_rate; + else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) + ddr_rate = ddr_pll / (postdiv + 1); + else + ddr_rate = cpu_pll / (postdiv + 1); + + postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & + QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; + + if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS) + ahb_rate = ref_rate; + else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) + ahb_rate = ddr_pll / (postdiv + 1); + else + ahb_rate = cpu_pll / (postdiv + 1); + + ath79_set_clk(ATH79_CLK_CPU, cpu_rate); + ath79_set_clk(ATH79_CLK_DDR, ddr_rate); + ath79_set_clk(ATH79_CLK_AHB, ahb_rate); +} + +static void __init qca955x_clocks_init(void __iomem *pll_base) +{ + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; u32 cpu_pll, ddr_pll; u32 bootstrap; bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) - ath79_ref_clk.rate = 40 * 1000 * 1000; + ref_rate = 40 * 1000 * 1000; else - ath79_ref_clk.rate = 25 * 1000 * 1000; + ref_rate = 25 * 1000 * 1000; + + ref_rate = ath79_setup_ref_clk(ref_rate); - pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); + pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG); out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & @@ -317,11 +458,11 @@ static void __init qca955x_clocks_init(void) frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; - cpu_pll = nint * ath79_ref_clk.rate / ref_div; - cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6)); + cpu_pll = nint * ref_rate / ref_div; + cpu_pll += frac * ref_rate / (ref_div * (1 << 6)); cpu_pll /= (1 << out_div); - pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); + pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG); out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & @@ -331,120 +472,202 @@ static void __init qca955x_clocks_init(void) frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; - ddr_pll = nint * ath79_ref_clk.rate / ref_div; - ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10)); + ddr_pll = nint * ref_rate / ref_div; + ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); ddr_pll /= (1 << out_div); - clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); + clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG); postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) - ath79_cpu_clk.rate = ath79_ref_clk.rate; + cpu_rate = ref_rate; else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) - ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); + cpu_rate = ddr_pll / (postdiv + 1); else - ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); + cpu_rate = cpu_pll / (postdiv + 1); postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) - ath79_ddr_clk.rate = ath79_ref_clk.rate; + ddr_rate = ref_rate; else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) - ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); + ddr_rate = cpu_pll / (postdiv + 1); else - ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); + ddr_rate = ddr_pll / (postdiv + 1); postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) - ath79_ahb_clk.rate = ath79_ref_clk.rate; + ahb_rate = ref_rate; else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) - ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); + ahb_rate = ddr_pll / (postdiv + 1); else - ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); + ahb_rate = cpu_pll / (postdiv + 1); - ath79_wdt_clk.rate = ath79_ref_clk.rate; - ath79_uart_clk.rate = ath79_ref_clk.rate; + ath79_set_clk(ATH79_CLK_CPU, cpu_rate); + ath79_set_clk(ATH79_CLK_DDR, ddr_rate); + ath79_set_clk(ATH79_CLK_AHB, ahb_rate); } -void __init ath79_clocks_init(void) +static void __init qca956x_clocks_init(void __iomem *pll_base) { - if (soc_is_ar71xx()) - ar71xx_clocks_init(); - else if (soc_is_ar724x()) - ar724x_clocks_init(); - else if (soc_is_ar913x()) - ar913x_clocks_init(); - else if (soc_is_ar933x()) - ar933x_clocks_init(); - else if (soc_is_ar934x()) - ar934x_clocks_init(); - else if (soc_is_qca955x()) - qca955x_clocks_init(); + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; + u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; + u32 cpu_pll, ddr_pll; + u32 bootstrap; + + /* + * QCA956x timer init workaround has to be applied right before setting + * up the clock. Else, there will be no jiffies + */ + u32 misc; + + misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); + misc |= MISC_INT_MIPS_SI_TIMERINT_MASK; + ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); + + bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP); + if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40) + ref_rate = 40 * 1000 * 1000; else - BUG(); - - pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, " - "Ref:%lu.%03luMHz", - ath79_cpu_clk.rate / 1000000, - (ath79_cpu_clk.rate / 1000) % 1000, - ath79_ddr_clk.rate / 1000000, - (ath79_ddr_clk.rate / 1000) % 1000, - ath79_ahb_clk.rate / 1000000, - (ath79_ahb_clk.rate / 1000) % 1000, - ath79_ref_clk.rate / 1000000, - (ath79_ref_clk.rate / 1000) % 1000); -} + ref_rate = 25 * 1000 * 1000; + + ref_rate = ath79_setup_ref_clk(ref_rate); + + pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG); + out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK; + ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + QCA956X_PLL_CPU_CONFIG_REFDIV_MASK; + + pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG); + nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) & + QCA956X_PLL_CPU_CONFIG1_NINT_MASK; + hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) & + QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK; + lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) & + QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK; + + cpu_pll = nint * ref_rate / ref_div; + cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); + cpu_pll += (hfrac >> 13) * ref_rate / ref_div; + cpu_pll /= (1 << out_div); -/* - * Linux clock API - */ -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "ref")) - return &ath79_ref_clk; + pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG); + out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & + QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK; + ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) & + QCA956X_PLL_DDR_CONFIG_REFDIV_MASK; + pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG); + nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) & + QCA956X_PLL_DDR_CONFIG1_NINT_MASK; + hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) & + QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK; + lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) & + QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK; + + ddr_pll = nint * ref_rate / ref_div; + ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); + ddr_pll += (hfrac >> 13) * ref_rate / ref_div; + ddr_pll /= (1 << out_div); - if (!strcmp(id, "cpu")) - return &ath79_cpu_clk; + clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG); - if (!strcmp(id, "ddr")) - return &ath79_ddr_clk; + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & + QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; - if (!strcmp(id, "ahb")) - return &ath79_ahb_clk; + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS) + cpu_rate = ref_rate; + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL) + cpu_rate = ddr_pll / (postdiv + 1); + else + cpu_rate = cpu_pll / (postdiv + 1); - if (!strcmp(id, "wdt")) - return &ath79_wdt_clk; + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & + QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; - if (!strcmp(id, "uart")) - return &ath79_uart_clk; + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS) + ddr_rate = ref_rate; + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL) + ddr_rate = cpu_pll / (postdiv + 1); + else + ddr_rate = ddr_pll / (postdiv + 1); - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); + postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & + QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); + if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS) + ahb_rate = ref_rate; + else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) + ahb_rate = ddr_pll / (postdiv + 1); + else + ahb_rate = cpu_pll / (postdiv + 1); -void clk_disable(struct clk *clk) -{ + ath79_set_clk(ATH79_CLK_CPU, cpu_rate); + ath79_set_clk(ATH79_CLK_DDR, ddr_rate); + ath79_set_clk(ATH79_CLK_AHB, ahb_rate); } -EXPORT_SYMBOL(clk_disable); -unsigned long clk_get_rate(struct clk *clk) +static void __init ath79_clocks_init_dt(struct device_node *np) { - return clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); + struct clk *ref_clk; + void __iomem *pll_base; -void clk_put(struct clk *clk) -{ + ref_clk = of_clk_get(np, 0); + if (!IS_ERR(ref_clk)) + clks[ATH79_CLK_REF] = ref_clk; + + pll_base = of_iomap(np, 0); + if (!pll_base) { + pr_err("%pOF: can't map pll registers\n", np); + goto err_clk; + } + + if (of_device_is_compatible(np, "qca,ar7100-pll")) + ar71xx_clocks_init(pll_base); + else if (of_device_is_compatible(np, "qca,ar7240-pll") || + of_device_is_compatible(np, "qca,ar9130-pll")) + ar724x_clocks_init(pll_base); + else if (of_device_is_compatible(np, "qca,ar9330-pll")) + ar933x_clocks_init(pll_base); + else if (of_device_is_compatible(np, "qca,ar9340-pll")) + ar934x_clocks_init(pll_base); + else if (of_device_is_compatible(np, "qca,qca9530-pll")) + qca953x_clocks_init(pll_base); + else if (of_device_is_compatible(np, "qca,qca9550-pll")) + qca955x_clocks_init(pll_base); + else if (of_device_is_compatible(np, "qca,qca9560-pll")) + qca956x_clocks_init(pll_base); + + if (!clks[ATH79_CLK_MDIO]) + clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF]; + + if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { + pr_err("%pOF: could not register clk provider\n", np); + goto err_iounmap; + } + + return; + +err_iounmap: + iounmap(pll_base); + +err_clk: + clk_put(ref_clk); } -EXPORT_SYMBOL(clk_put); + +CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt); +CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt); +CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt); +CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt); +CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt); +CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt); +CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt); +CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt); diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c index eb3966cd8cfc..137abbc65c60 100644 --- a/arch/mips/ath79/common.c +++ b/arch/mips/ath79/common.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Atheros AR71XX/AR724X/AR913X common routines * @@ -6,14 +7,10 @@ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> * * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. */ #include <linux/kernel.h> -#include <linux/module.h> +#include <linux/export.h> #include <linux/types.h> #include <linux/spinlock.h> @@ -38,11 +35,27 @@ unsigned int ath79_soc_rev; void __iomem *ath79_pll_base; void __iomem *ath79_reset_base; EXPORT_SYMBOL_GPL(ath79_reset_base); -void __iomem *ath79_ddr_base; +static void __iomem *ath79_ddr_base; +static void __iomem *ath79_ddr_wb_flush_base; +static void __iomem *ath79_ddr_pci_win_base; + +void ath79_ddr_ctrl_init(void) +{ + ath79_ddr_base = ioremap(AR71XX_DDR_CTRL_BASE, + AR71XX_DDR_CTRL_SIZE); + if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) { + ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c; + ath79_ddr_pci_win_base = 0; + } else { + ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; + ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; + } +} +EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init); void ath79_ddr_wb_flush(u32 reg) { - void __iomem *flush_reg = ath79_ddr_base + reg; + void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4); /* Flush the DDR write buffer. */ __raw_writel(0x1, flush_reg); @@ -56,6 +69,21 @@ void ath79_ddr_wb_flush(u32 reg) } EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush); +void ath79_ddr_set_pci_windows(void) +{ + BUG_ON(!ath79_ddr_pci_win_base); + + __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0); + __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4); + __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8); + __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc); + __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10); + __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14); + __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18); + __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c); +} +EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows); + void ath79_device_reset_set(u32 mask) { unsigned long flags; @@ -72,8 +100,12 @@ void ath79_device_reset_set(u32 mask) reg = AR933X_RESET_REG_RESET_MODULE; else if (soc_is_ar934x()) reg = AR934X_RESET_REG_RESET_MODULE; + else if (soc_is_qca953x()) + reg = QCA953X_RESET_REG_RESET_MODULE; else if (soc_is_qca955x()) reg = QCA955X_RESET_REG_RESET_MODULE; + else if (soc_is_qca956x() || soc_is_tp9343()) + reg = QCA956X_RESET_REG_RESET_MODULE; else BUG(); @@ -100,8 +132,12 @@ void ath79_device_reset_clear(u32 mask) reg = AR933X_RESET_REG_RESET_MODULE; else if (soc_is_ar934x()) reg = AR934X_RESET_REG_RESET_MODULE; + else if (soc_is_qca953x()) + reg = QCA953X_RESET_REG_RESET_MODULE; else if (soc_is_qca955x()) reg = QCA955X_RESET_REG_RESET_MODULE; + else if (soc_is_qca956x() || soc_is_tp9343()) + reg = QCA956X_RESET_REG_RESET_MODULE; else BUG(); diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h index 561906c2345e..47fb66d7b282 100644 --- a/arch/mips/ath79/common.h +++ b/arch/mips/ath79/common.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Atheros AR71XX/AR724X/AR913X common definitions * @@ -5,27 +6,16 @@ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> * * Parts of this file are based on Atheros' 2.6.15 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. */ #ifndef __ATH79_COMMON_H #define __ATH79_COMMON_H #include <linux/types.h> -#include <linux/init.h> #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) -#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024) - -void ath79_clocks_init(void); -void ath79_ddr_wb_flush(unsigned int reg); +#define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024) -void ath79_gpio_function_enable(u32 mask); -void ath79_gpio_function_disable(u32 mask); -void ath79_gpio_function_setup(u32 set, u32 clear); -void ath79_gpio_init(void); +void ath79_ddr_ctrl_init(void); #endif /* __ATH79_COMMON_H */ diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c deleted file mode 100644 index a3a2741d0688..000000000000 --- a/arch/mips/ath79/dev-common.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Atheros AR71XX/AR724X/AR913X common devices - * - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * Parts of this file are based on Atheros' 2.6.15 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/clk.h> -#include <linux/err.h> - -#include <asm/mach-ath79/ath79.h> -#include <asm/mach-ath79/ar71xx_regs.h> -#include <asm/mach-ath79/ar933x_uart_platform.h> -#include "common.h" -#include "dev-common.h" - -static struct resource ath79_uart_resources[] = { - { - .start = AR71XX_UART_BASE, - .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) -static struct plat_serial8250_port ath79_uart_data[] = { - { - .mapbase = AR71XX_UART_BASE, - .irq = ATH79_MISC_IRQ(3), - .flags = AR71XX_UART_FLAGS, - .iotype = UPIO_MEM32, - .regshift = 2, - }, { - /* terminating entry */ - } -}; - -static struct platform_device ath79_uart_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .resource = ath79_uart_resources, - .num_resources = ARRAY_SIZE(ath79_uart_resources), - .dev = { - .platform_data = ath79_uart_data - }, -}; - -static struct resource ar933x_uart_resources[] = { - { - .start = AR933X_UART_BASE, - .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = ATH79_MISC_IRQ(3), - .end = ATH79_MISC_IRQ(3), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct ar933x_uart_platform_data ar933x_uart_data; -static struct platform_device ar933x_uart_device = { - .name = "ar933x-uart", - .id = -1, - .resource = ar933x_uart_resources, - .num_resources = ARRAY_SIZE(ar933x_uart_resources), - .dev = { - .platform_data = &ar933x_uart_data, - }, -}; - -void __init ath79_register_uart(void) -{ - struct clk *clk; - - clk = clk_get(NULL, "uart"); - if (IS_ERR(clk)) - panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); - - if (soc_is_ar71xx() || - soc_is_ar724x() || - soc_is_ar913x() || - soc_is_ar934x() || - soc_is_qca955x()) { - ath79_uart_data[0].uartclk = clk_get_rate(clk); - platform_device_register(&ath79_uart_device); - } else if (soc_is_ar933x()) { - ar933x_uart_data.uartclk = clk_get_rate(clk); - platform_device_register(&ar933x_uart_device); - } else { - BUG(); - } -} - -void __init ath79_register_wdt(void) -{ - struct resource res; - - memset(&res, 0, sizeof(res)); - - res.flags = IORESOURCE_MEM; - res.start = AR71XX_RESET_BASE + AR71XX_RESET_REG_WDOG_CTRL; - res.end = res.start + 0x8 - 1; - - platform_device_register_simple("ath79-wdt", -1, &res, 1); -} diff --git a/arch/mips/ath79/dev-common.h b/arch/mips/ath79/dev-common.h deleted file mode 100644 index 0f514e1affce..000000000000 --- a/arch/mips/ath79/dev-common.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Atheros AR71XX/AR724X/AR913X common devices - * - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _ATH79_DEV_COMMON_H -#define _ATH79_DEV_COMMON_H - -void ath79_register_uart(void); -void ath79_register_wdt(void); - -#endif /* _ATH79_DEV_COMMON_H */ diff --git a/arch/mips/ath79/dev-gpio-buttons.c b/arch/mips/ath79/dev-gpio-buttons.c deleted file mode 100644 index 366b35fb164d..000000000000 --- a/arch/mips/ath79/dev-gpio-buttons.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Atheros AR71XX/AR724X/AR913X GPIO button support - * - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include "linux/init.h" -#include "linux/slab.h" -#include <linux/platform_device.h> - -#include "dev-gpio-buttons.h" - -void __init ath79_register_gpio_keys_polled(int id, - unsigned poll_interval, - unsigned nbuttons, - struct gpio_keys_button *buttons) -{ - struct platform_device *pdev; - struct gpio_keys_platform_data pdata; - struct gpio_keys_button *p; - int err; - - p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL); - if (!p) - return; - - pdev = platform_device_alloc("gpio-keys-polled", id); - if (!pdev) - goto err_free_buttons; - - memset(&pdata, 0, sizeof(pdata)); - pdata.poll_interval = poll_interval; - pdata.nbuttons = nbuttons; - pdata.buttons = p; - - err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); - if (err) - goto err_put_pdev; - - err = platform_device_add(pdev); - if (err) - goto err_put_pdev; - - return; - -err_put_pdev: - platform_device_put(pdev); - -err_free_buttons: - kfree(p); -} diff --git a/arch/mips/ath79/dev-gpio-buttons.h b/arch/mips/ath79/dev-gpio-buttons.h deleted file mode 100644 index 481847ac1cba..000000000000 --- a/arch/mips/ath79/dev-gpio-buttons.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Atheros AR71XX/AR724X/AR913X GPIO button support - * - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _ATH79_DEV_GPIO_BUTTONS_H -#define _ATH79_DEV_GPIO_BUTTONS_H - -#include <linux/input.h> -#include <linux/gpio_keys.h> - -void ath79_register_gpio_keys_polled(int id, - unsigned poll_interval, - unsigned nbuttons, - struct gpio_keys_button *buttons); - -#endif /* _ATH79_DEV_GPIO_BUTTONS_H */ diff --git a/arch/mips/ath79/dev-leds-gpio.c b/arch/mips/ath79/dev-leds-gpio.c deleted file mode 100644 index dcb1debcefb8..000000000000 --- a/arch/mips/ath79/dev-leds-gpio.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support - * - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/platform_device.h> - -#include "dev-leds-gpio.h" - -void __init ath79_register_leds_gpio(int id, - unsigned num_leds, - struct gpio_led *leds) -{ - struct platform_device *pdev; - struct gpio_led_platform_data pdata; - struct gpio_led *p; - int err; - - p = kmemdup(leds, num_leds * sizeof(*p), GFP_KERNEL); - if (!p) - return; - - pdev = platform_device_alloc("leds-gpio", id); - if (!pdev) - goto err_free_leds; - - memset(&pdata, 0, sizeof(pdata)); - pdata.num_leds = num_leds; - pdata.leds = p; - - err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); - if (err) - goto err_put_pdev; - - err = platform_device_add(pdev); - if (err) - goto err_put_pdev; - - return; - -err_put_pdev: - platform_device_put(pdev); - -err_free_leds: - kfree(p); -} diff --git a/arch/mips/ath79/dev-leds-gpio.h b/arch/mips/ath79/dev-leds-gpio.h deleted file mode 100644 index 6e5d8851ebcf..000000000000 --- a/arch/mips/ath79/dev-leds-gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Atheros AR71XX/AR724X/AR913X common GPIO LEDs support - * - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _ATH79_DEV_LEDS_GPIO_H -#define _ATH79_DEV_LEDS_GPIO_H - -#include <linux/leds.h> - -void ath79_register_leds_gpio(int id, - unsigned num_leds, - struct gpio_led *leds); - -#endif /* _ATH79_DEV_LEDS_GPIO_H */ diff --git a/arch/mips/ath79/dev-spi.c b/arch/mips/ath79/dev-spi.c deleted file mode 100644 index aa30163efbfd..000000000000 --- a/arch/mips/ath79/dev-spi.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Atheros AR71XX/AR724X/AR913X SPI controller device - * - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/platform_device.h> -#include <asm/mach-ath79/ar71xx_regs.h> -#include "dev-spi.h" - -static struct resource ath79_spi_resources[] = { - { - .start = AR71XX_SPI_BASE, - .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device ath79_spi_device = { - .name = "ath79-spi", - .id = -1, - .resource = ath79_spi_resources, - .num_resources = ARRAY_SIZE(ath79_spi_resources), -}; - -void __init ath79_register_spi(struct ath79_spi_platform_data *pdata, - struct spi_board_info const *info, - unsigned n) -{ - spi_register_board_info(info, n); - ath79_spi_device.dev.platform_data = pdata; - platform_device_register(&ath79_spi_device); -} diff --git a/arch/mips/ath79/dev-spi.h b/arch/mips/ath79/dev-spi.h deleted file mode 100644 index d732565ca736..000000000000 --- a/arch/mips/ath79/dev-spi.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Atheros AR71XX/AR724X/AR913X SPI controller device - * - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _ATH79_DEV_SPI_H -#define _ATH79_DEV_SPI_H - -#include <linux/spi/spi.h> -#include <asm/mach-ath79/ath79_spi_platform.h> - -void ath79_register_spi(struct ath79_spi_platform_data *pdata, - struct spi_board_info const *info, - unsigned n); - -#endif /* _ATH79_DEV_SPI_H */ diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c deleted file mode 100644 index 8227265bcc2d..000000000000 --- a/arch/mips/ath79/dev-usb.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Atheros AR7XXX/AR9XXX USB Host Controller device - * - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * Parts of this file are based on Atheros' 2.6.15 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/irq.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/usb/ehci_pdriver.h> -#include <linux/usb/ohci_pdriver.h> - -#include <asm/mach-ath79/ath79.h> -#include <asm/mach-ath79/ar71xx_regs.h> -#include "common.h" -#include "dev-usb.h" - -static u64 ath79_usb_dmamask = DMA_BIT_MASK(32); - -static struct usb_ohci_pdata ath79_ohci_pdata = { -}; - -static struct usb_ehci_pdata ath79_ehci_pdata_v1 = { - .has_synopsys_hc_bug = 1, -}; - -static struct usb_ehci_pdata ath79_ehci_pdata_v2 = { - .caps_offset = 0x100, - .has_tt = 1, -}; - -static void __init ath79_usb_register(const char *name, int id, - unsigned long base, unsigned long size, - int irq, const void *data, - size_t data_size) -{ - struct resource res[2]; - struct platform_device *pdev; - - memset(res, 0, sizeof(res)); - - res[0].flags = IORESOURCE_MEM; - res[0].start = base; - res[0].end = base + size - 1; - - res[1].flags = IORESOURCE_IRQ; - res[1].start = irq; - res[1].end = irq; - - pdev = platform_device_register_resndata(NULL, name, id, - res, ARRAY_SIZE(res), - data, data_size); - - if (IS_ERR(pdev)) { - pr_err("ath79: unable to register USB at %08lx, err=%d\n", - base, (int) PTR_ERR(pdev)); - return; - } - - pdev->dev.dma_mask = &ath79_usb_dmamask; - pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); -} - -#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ - AR71XX_RESET_USB_PHY | \ - AR71XX_RESET_USB_OHCI_DLL) - -static void __init ath79_usb_setup(void) -{ - void __iomem *usb_ctrl_base; - - ath79_device_reset_set(AR71XX_USB_RESET_MASK); - mdelay(1000); - ath79_device_reset_clear(AR71XX_USB_RESET_MASK); - - usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE); - - /* Turning on the Buff and Desc swap bits */ - __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG); - - /* WAR for HW bug. Here it adjusts the duration between two SOFS */ - __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); - - iounmap(usb_ctrl_base); - - mdelay(900); - - ath79_usb_register("ohci-platform", -1, - AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE, - ATH79_MISC_IRQ(6), - &ath79_ohci_pdata, sizeof(ath79_ohci_pdata)); - - ath79_usb_register("ehci-platform", -1, - AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE, - ATH79_CPU_IRQ(3), - &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1)); -} - -static void __init ar7240_usb_setup(void) -{ - void __iomem *usb_ctrl_base; - - ath79_device_reset_clear(AR7240_RESET_OHCI_DLL); - ath79_device_reset_set(AR7240_RESET_USB_HOST); - - mdelay(1000); - - ath79_device_reset_set(AR7240_RESET_OHCI_DLL); - ath79_device_reset_clear(AR7240_RESET_USB_HOST); - - usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE); - - /* WAR for HW bug. Here it adjusts the duration between two SOFS */ - __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ); - - iounmap(usb_ctrl_base); - - ath79_usb_register("ohci-platform", -1, - AR7240_OHCI_BASE, AR7240_OHCI_SIZE, - ATH79_CPU_IRQ(3), - &ath79_ohci_pdata, sizeof(ath79_ohci_pdata)); -} - -static void __init ar724x_usb_setup(void) -{ - ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE); - mdelay(10); - - ath79_device_reset_clear(AR724X_RESET_USB_HOST); - mdelay(10); - - ath79_device_reset_clear(AR724X_RESET_USB_PHY); - mdelay(10); - - ath79_usb_register("ehci-platform", -1, - AR724X_EHCI_BASE, AR724X_EHCI_SIZE, - ATH79_CPU_IRQ(3), - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -} - -static void __init ar913x_usb_setup(void) -{ - ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE); - mdelay(10); - - ath79_device_reset_clear(AR913X_RESET_USB_HOST); - mdelay(10); - - ath79_device_reset_clear(AR913X_RESET_USB_PHY); - mdelay(10); - - ath79_usb_register("ehci-platform", -1, - AR913X_EHCI_BASE, AR913X_EHCI_SIZE, - ATH79_CPU_IRQ(3), - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -} - -static void __init ar933x_usb_setup(void) -{ - ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE); - mdelay(10); - - ath79_device_reset_clear(AR933X_RESET_USB_HOST); - mdelay(10); - - ath79_device_reset_clear(AR933X_RESET_USB_PHY); - mdelay(10); - - ath79_usb_register("ehci-platform", -1, - AR933X_EHCI_BASE, AR933X_EHCI_SIZE, - ATH79_CPU_IRQ(3), - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -} - -static void __init ar934x_usb_setup(void) -{ - u32 bootstrap; - - bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); - if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) - return; - - ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE); - udelay(1000); - - ath79_device_reset_clear(AR934X_RESET_USB_PHY); - udelay(1000); - - ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG); - udelay(1000); - - ath79_device_reset_clear(AR934X_RESET_USB_HOST); - udelay(1000); - - ath79_usb_register("ehci-platform", -1, - AR934X_EHCI_BASE, AR934X_EHCI_SIZE, - ATH79_CPU_IRQ(3), - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -} - -static void __init qca955x_usb_setup(void) -{ - ath79_usb_register("ehci-platform", 0, - QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE, - ATH79_IP3_IRQ(0), - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); - - ath79_usb_register("ehci-platform", 1, - QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE, - ATH79_IP3_IRQ(1), - &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); -} - -void __init ath79_register_usb(void) -{ - if (soc_is_ar71xx()) - ath79_usb_setup(); - else if (soc_is_ar7240()) - ar7240_usb_setup(); - else if (soc_is_ar7241() || soc_is_ar7242()) - ar724x_usb_setup(); - else if (soc_is_ar913x()) - ar913x_usb_setup(); - else if (soc_is_ar933x()) - ar933x_usb_setup(); - else if (soc_is_ar934x()) - ar934x_usb_setup(); - else if (soc_is_qca955x()) - qca955x_usb_setup(); - else - BUG(); -} diff --git a/arch/mips/ath79/dev-usb.h b/arch/mips/ath79/dev-usb.h deleted file mode 100644 index 4b86a69ca080..000000000000 --- a/arch/mips/ath79/dev-usb.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Atheros AR71XX/AR724X/AR913X USB Host Controller support - * - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _ATH79_DEV_USB_H -#define _ATH79_DEV_USB_H - -void ath79_register_usb(void); - -#endif /* _ATH79_DEV_USB_H */ diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c deleted file mode 100644 index da190b1b87ce..000000000000 --- a/arch/mips/ath79/dev-wmac.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Atheros AR913X/AR933X SoC built-in WMAC device support - * - * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/ath9k_platform.h> - -#include <asm/mach-ath79/ath79.h> -#include <asm/mach-ath79/ar71xx_regs.h> -#include "dev-wmac.h" - -static struct ath9k_platform_data ath79_wmac_data; - -static struct resource ath79_wmac_resources[] = { - { - /* .start and .end fields are filled dynamically */ - .flags = IORESOURCE_MEM, - }, { - /* .start and .end fields are filled dynamically */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ath79_wmac_device = { - .name = "ath9k", - .id = -1, - .resource = ath79_wmac_resources, - .num_resources = ARRAY_SIZE(ath79_wmac_resources), - .dev = { - .platform_data = &ath79_wmac_data, - }, -}; - -static void __init ar913x_wmac_setup(void) -{ - /* reset the WMAC */ - ath79_device_reset_set(AR913X_RESET_AMBA2WMAC); - mdelay(10); - - ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC); - mdelay(10); - - ath79_wmac_resources[0].start = AR913X_WMAC_BASE; - ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; - ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); - ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); -} - - -static int ar933x_wmac_reset(void) -{ - ath79_device_reset_set(AR933X_RESET_WMAC); - ath79_device_reset_clear(AR933X_RESET_WMAC); - - return 0; -} - -static int ar933x_r1_get_wmac_revision(void) -{ - return ath79_soc_rev; -} - -static void __init ar933x_wmac_setup(void) -{ - u32 t; - - ar933x_wmac_reset(); - - ath79_wmac_device.name = "ar933x_wmac"; - - ath79_wmac_resources[0].start = AR933X_WMAC_BASE; - ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; - ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); - ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); - - t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); - if (t & AR933X_BOOTSTRAP_REF_CLK_40) - ath79_wmac_data.is_clk_25mhz = false; - else - ath79_wmac_data.is_clk_25mhz = true; - - if (ath79_soc_rev == 1) - ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision; - - ath79_wmac_data.external_reset = ar933x_wmac_reset; -} - -static void ar934x_wmac_setup(void) -{ - u32 t; - - ath79_wmac_device.name = "ar934x_wmac"; - - ath79_wmac_resources[0].start = AR934X_WMAC_BASE; - ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; - ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); - ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); - - t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); - if (t & AR934X_BOOTSTRAP_REF_CLK_40) - ath79_wmac_data.is_clk_25mhz = false; - else - ath79_wmac_data.is_clk_25mhz = true; -} - -static void qca955x_wmac_setup(void) -{ - u32 t; - - ath79_wmac_device.name = "qca955x_wmac"; - - ath79_wmac_resources[0].start = QCA955X_WMAC_BASE; - ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1; - ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); - ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); - - t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); - if (t & QCA955X_BOOTSTRAP_REF_CLK_40) - ath79_wmac_data.is_clk_25mhz = false; - else - ath79_wmac_data.is_clk_25mhz = true; -} - -void __init ath79_register_wmac(u8 *cal_data) -{ - if (soc_is_ar913x()) - ar913x_wmac_setup(); - else if (soc_is_ar933x()) - ar933x_wmac_setup(); - else if (soc_is_ar934x()) - ar934x_wmac_setup(); - else if (soc_is_qca955x()) - qca955x_wmac_setup(); - else - BUG(); - - if (cal_data) - memcpy(ath79_wmac_data.eeprom_data, cal_data, - sizeof(ath79_wmac_data.eeprom_data)); - - platform_device_register(&ath79_wmac_device); -} diff --git a/arch/mips/ath79/dev-wmac.h b/arch/mips/ath79/dev-wmac.h deleted file mode 100644 index c9cd8709f090..000000000000 --- a/arch/mips/ath79/dev-wmac.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Atheros AR913X/AR933X SoC built-in WMAC device support - * - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _ATH79_DEV_WMAC_H -#define _ATH79_DEV_WMAC_H - -void ath79_register_wmac(u8 *cal_data); - -#endif /* _ATH79_DEV_WMAC_H */ diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c index b955fafc58ba..34c4dfdf46b4 100644 --- a/arch/mips/ath79/early_printk.c +++ b/arch/mips/ath79/early_printk.c @@ -1,61 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Atheros AR7XXX/AR9XXX SoC early printk support * * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. */ #include <linux/io.h> #include <linux/errno.h> +#include <linux/serial.h> #include <linux/serial_reg.h> #include <asm/addrspace.h> +#include <asm/setup.h> #include <asm/mach-ath79/ath79.h> #include <asm/mach-ath79/ar71xx_regs.h> #include <asm/mach-ath79/ar933x_uart.h> -static void (*_prom_putchar) (unsigned char); +static void (*_prom_putchar)(char); -static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val) +static inline void prom_putchar_wait(void __iomem *reg, u32 val) { u32 t; do { t = __raw_readl(reg); - if ((t & mask) == val) + if ((t & val) == val) break; } while (1); } -static void prom_putchar_ar71xx(unsigned char ch) +static void prom_putchar_ar71xx(char ch) { void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); - prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE); - __raw_writel(ch, base + UART_TX * 4); - prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE); + prom_putchar_wait(base + UART_LSR * 4, UART_LSR_BOTH_EMPTY); + __raw_writel((unsigned char)ch, base + UART_TX * 4); + prom_putchar_wait(base + UART_LSR * 4, UART_LSR_BOTH_EMPTY); } -static void prom_putchar_ar933x(unsigned char ch) +static void prom_putchar_ar933x(char ch) { void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE)); - prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, - AR933X_UART_DATA_TX_CSR); - __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG); - prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, - AR933X_UART_DATA_TX_CSR); + prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR); + __raw_writel(AR933X_UART_DATA_TX_CSR | (unsigned char)ch, + base + AR933X_UART_DATA_REG); + prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR); } -static void prom_putchar_dummy(unsigned char ch) +static void prom_putchar_dummy(char ch) { /* nothing to do */ } +static void prom_enable_uart(u32 id) +{ + void __iomem *gpio_base; + u32 uart_en; + u32 t; + + switch (id) { + case REV_ID_MAJOR_AR71XX: + uart_en = AR71XX_GPIO_FUNC_UART_EN; + break; + + case REV_ID_MAJOR_AR7240: + case REV_ID_MAJOR_AR7241: + case REV_ID_MAJOR_AR7242: + uart_en = AR724X_GPIO_FUNC_UART_EN; + break; + + case REV_ID_MAJOR_AR913X: + uart_en = AR913X_GPIO_FUNC_UART_EN; + break; + + case REV_ID_MAJOR_AR9330: + case REV_ID_MAJOR_AR9331: + uart_en = AR933X_GPIO_FUNC_UART_EN; + break; + + case REV_ID_MAJOR_AR9341: + case REV_ID_MAJOR_AR9342: + case REV_ID_MAJOR_AR9344: + /* TODO */ + default: + return; + } + + gpio_base = (void __iomem *)KSEG1ADDR(AR71XX_GPIO_BASE); + t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC); + t |= uart_en; + __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC); +} + static void prom_putchar_init(void) { void __iomem *base; @@ -74,8 +112,13 @@ static void prom_putchar_init(void) case REV_ID_MAJOR_AR9341: case REV_ID_MAJOR_AR9342: case REV_ID_MAJOR_AR9344: + case REV_ID_MAJOR_QCA9533: + case REV_ID_MAJOR_QCA9533_V2: case REV_ID_MAJOR_QCA9556: case REV_ID_MAJOR_QCA9558: + case REV_ID_MAJOR_TP9343: + case REV_ID_MAJOR_QCA956X: + case REV_ID_MAJOR_QCN550X: _prom_putchar = prom_putchar_ar71xx; break; @@ -86,11 +129,13 @@ static void prom_putchar_init(void) default: _prom_putchar = prom_putchar_dummy; - break; + return; } + + prom_enable_uart(id); } -void prom_putchar(unsigned char ch) +void prom_putchar(char ch) { if (!_prom_putchar) prom_putchar_init(); diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c deleted file mode 100644 index 8d025b028bb1..000000000000 --- a/arch/mips/ath79/gpio.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Atheros AR71XX/AR724X/AR913X GPIO API support - * - * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/spinlock.h> -#include <linux/io.h> -#include <linux/ioport.h> -#include <linux/gpio.h> - -#include <asm/mach-ath79/ar71xx_regs.h> -#include <asm/mach-ath79/ath79.h> -#include "common.h" - -static void __iomem *ath79_gpio_base; -static unsigned long ath79_gpio_count; -static DEFINE_SPINLOCK(ath79_gpio_lock); - -static void __ath79_gpio_set_value(unsigned gpio, int value) -{ - void __iomem *base = ath79_gpio_base; - - if (value) - __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET); - else - __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR); -} - -static int __ath79_gpio_get_value(unsigned gpio) -{ - return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1; -} - -static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset) -{ - return __ath79_gpio_get_value(offset); -} - -static void ath79_gpio_set_value(struct gpio_chip *chip, - unsigned offset, int value) -{ - __ath79_gpio_set_value(offset, value); -} - -static int ath79_gpio_direction_input(struct gpio_chip *chip, - unsigned offset) -{ - void __iomem *base = ath79_gpio_base; - unsigned long flags; - - spin_lock_irqsave(&ath79_gpio_lock, flags); - - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), - base + AR71XX_GPIO_REG_OE); - - spin_unlock_irqrestore(&ath79_gpio_lock, flags); - - return 0; -} - -static int ath79_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - void __iomem *base = ath79_gpio_base; - unsigned long flags; - - spin_lock_irqsave(&ath79_gpio_lock, flags); - - if (value) - __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); - else - __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); - - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), - base + AR71XX_GPIO_REG_OE); - - spin_unlock_irqrestore(&ath79_gpio_lock, flags); - - return 0; -} - -static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - void __iomem *base = ath79_gpio_base; - unsigned long flags; - - spin_lock_irqsave(&ath79_gpio_lock, flags); - - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), - base + AR71XX_GPIO_REG_OE); - - spin_unlock_irqrestore(&ath79_gpio_lock, flags); - - return 0; -} - -static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset, - int value) -{ - void __iomem *base = ath79_gpio_base; - unsigned long flags; - - spin_lock_irqsave(&ath79_gpio_lock, flags); - - if (value) - __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); - else - __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); - - __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), - base + AR71XX_GPIO_REG_OE); - - spin_unlock_irqrestore(&ath79_gpio_lock, flags); - - return 0; -} - -static struct gpio_chip ath79_gpio_chip = { - .label = "ath79", - .get = ath79_gpio_get_value, - .set = ath79_gpio_set_value, - .direction_input = ath79_gpio_direction_input, - .direction_output = ath79_gpio_direction_output, - .base = 0, -}; - -static void __iomem *ath79_gpio_get_function_reg(void) -{ - u32 reg = 0; - - if (soc_is_ar71xx() || - soc_is_ar724x() || - soc_is_ar913x() || - soc_is_ar933x()) - reg = AR71XX_GPIO_REG_FUNC; - else if (soc_is_ar934x()) - reg = AR934X_GPIO_REG_FUNC; - else - BUG(); - - return ath79_gpio_base + reg; -} - -void ath79_gpio_function_setup(u32 set, u32 clear) -{ - void __iomem *reg = ath79_gpio_get_function_reg(); - unsigned long flags; - - spin_lock_irqsave(&ath79_gpio_lock, flags); - - __raw_writel((__raw_readl(reg) & ~clear) | set, reg); - /* flush write */ - __raw_readl(reg); - - spin_unlock_irqrestore(&ath79_gpio_lock, flags); -} - -void ath79_gpio_function_enable(u32 mask) -{ - ath79_gpio_function_setup(mask, 0); -} - -void ath79_gpio_function_disable(u32 mask) -{ - ath79_gpio_function_setup(0, mask); -} - -void __init ath79_gpio_init(void) -{ - int err; - - if (soc_is_ar71xx()) - ath79_gpio_count = AR71XX_GPIO_COUNT; - else if (soc_is_ar7240()) - ath79_gpio_count = AR7240_GPIO_COUNT; - else if (soc_is_ar7241() || soc_is_ar7242()) - ath79_gpio_count = AR7241_GPIO_COUNT; - else if (soc_is_ar913x()) - ath79_gpio_count = AR913X_GPIO_COUNT; - else if (soc_is_ar933x()) - ath79_gpio_count = AR933X_GPIO_COUNT; - else if (soc_is_ar934x()) - ath79_gpio_count = AR934X_GPIO_COUNT; - else if (soc_is_qca955x()) - ath79_gpio_count = QCA955X_GPIO_COUNT; - else - BUG(); - - ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); - ath79_gpio_chip.ngpio = ath79_gpio_count; - if (soc_is_ar934x() || soc_is_qca955x()) { - ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; - ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; - } - - err = gpiochip_add(&ath79_gpio_chip); - if (err) - panic("cannot add AR71xx GPIO chip, error=%d", err); -} - -int gpio_get_value(unsigned gpio) -{ - if (gpio < ath79_gpio_count) - return __ath79_gpio_get_value(gpio); - - return __gpio_get_value(gpio); -} -EXPORT_SYMBOL(gpio_get_value); - -void gpio_set_value(unsigned gpio, int value) -{ - if (gpio < ath79_gpio_count) - __ath79_gpio_set_value(gpio, value); - else - __gpio_set_value(gpio, value); -} -EXPORT_SYMBOL(gpio_set_value); - -int gpio_to_irq(unsigned gpio) -{ - /* FIXME */ - return -EINVAL; -} -EXPORT_SYMBOL(gpio_to_irq); - -int irq_to_gpio(unsigned irq) -{ - /* FIXME */ - return -EINVAL; -} -EXPORT_SYMBOL(irq_to_gpio); diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c deleted file mode 100644 index 9c0e1761773f..000000000000 --- a/arch/mips/ath79/irq.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Atheros AR71xx/AR724x/AR913x specific interrupt handling - * - * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> - -#include <asm/irq_cpu.h> -#include <asm/mipsregs.h> - -#include <asm/mach-ath79/ath79.h> -#include <asm/mach-ath79/ar71xx_regs.h> -#include "common.h" - -static void (*ath79_ip2_handler)(void); -static void (*ath79_ip3_handler)(void); - -static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - void __iomem *base = ath79_reset_base; - u32 pending; - - pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & - __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); - - if (!pending) { - spurious_interrupt(); - return; - } - - while (pending) { - int bit = __ffs(pending); - - generic_handle_irq(ATH79_MISC_IRQ(bit)); - pending &= ~BIT(bit); - } -} - -static void ar71xx_misc_irq_unmask(struct irq_data *d) -{ - unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE; - void __iomem *base = ath79_reset_base; - u32 t; - - t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); - __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); - - /* flush write */ - __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -} - -static void ar71xx_misc_irq_mask(struct irq_data *d) -{ - unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE; - void __iomem *base = ath79_reset_base; - u32 t; - - t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); - __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); - - /* flush write */ - __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -} - -static void ar724x_misc_irq_ack(struct irq_data *d) -{ - unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE; - void __iomem *base = ath79_reset_base; - u32 t; - - t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); - __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); - - /* flush write */ - __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); -} - -static struct irq_chip ath79_misc_irq_chip = { - .name = "MISC", - .irq_unmask = ar71xx_misc_irq_unmask, - .irq_mask = ar71xx_misc_irq_mask, -}; - -static void __init ath79_misc_irq_init(void) -{ - void __iomem *base = ath79_reset_base; - int i; - - __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); - __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); - - if (soc_is_ar71xx() || soc_is_ar913x()) - ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; - else if (soc_is_ar724x() || - soc_is_ar933x() || - soc_is_ar934x() || - soc_is_qca955x()) - ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; - else - BUG(); - - for (i = ATH79_MISC_IRQ_BASE; - i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { - irq_set_chip_and_handler(i, &ath79_misc_irq_chip, - handle_level_irq); - } - - irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler); -} - -static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) -{ - u32 status; - - disable_irq_nosync(irq); - - status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); - - if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) { - ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE); - generic_handle_irq(ATH79_IP2_IRQ(0)); - } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { - ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC); - generic_handle_irq(ATH79_IP2_IRQ(1)); - } else { - spurious_interrupt(); - } - - enable_irq(irq); -} - -static void ar934x_ip2_irq_init(void) -{ - int i; - - for (i = ATH79_IP2_IRQ_BASE; - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) - irq_set_chip_and_handler(i, &dummy_irq_chip, - handle_level_irq); - - irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); -} - -static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) -{ - u32 status; - - disable_irq_nosync(irq); - - status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); - status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL; - - if (status == 0) { - spurious_interrupt(); - goto enable; - } - - if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { - /* TODO: flush DDR? */ - generic_handle_irq(ATH79_IP2_IRQ(0)); - } - - if (status & QCA955X_EXT_INT_WMAC_ALL) { - /* TODO: flush DDR? */ - generic_handle_irq(ATH79_IP2_IRQ(1)); - } - -enable: - enable_irq(irq); -} - -static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc) -{ - u32 status; - - disable_irq_nosync(irq); - - status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); - status &= QCA955X_EXT_INT_PCIE_RC2_ALL | - QCA955X_EXT_INT_USB1 | - QCA955X_EXT_INT_USB2; - - if (status == 0) { - spurious_interrupt(); - goto enable; - } - - if (status & QCA955X_EXT_INT_USB1) { - /* TODO: flush DDR? */ - generic_handle_irq(ATH79_IP3_IRQ(0)); - } - - if (status & QCA955X_EXT_INT_USB2) { - /* TODO: flush DDR? */ - generic_handle_irq(ATH79_IP3_IRQ(1)); - } - - if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) { - /* TODO: flush DDR? */ - generic_handle_irq(ATH79_IP3_IRQ(2)); - } - -enable: - enable_irq(irq); -} - -static void qca955x_irq_init(void) -{ - int i; - - for (i = ATH79_IP2_IRQ_BASE; - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) - irq_set_chip_and_handler(i, &dummy_irq_chip, - handle_level_irq); - - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); - - for (i = ATH79_IP3_IRQ_BASE; - i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) - irq_set_chip_and_handler(i, &dummy_irq_chip, - handle_level_irq); - - irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned long pending; - - pending = read_c0_status() & read_c0_cause() & ST0_IM; - - if (pending & STATUSF_IP7) - do_IRQ(ATH79_CPU_IRQ(7)); - - else if (pending & STATUSF_IP2) - ath79_ip2_handler(); - - else if (pending & STATUSF_IP4) - do_IRQ(ATH79_CPU_IRQ(4)); - - else if (pending & STATUSF_IP5) - do_IRQ(ATH79_CPU_IRQ(5)); - - else if (pending & STATUSF_IP3) - ath79_ip3_handler(); - - else if (pending & STATUSF_IP6) - do_IRQ(ATH79_CPU_IRQ(6)); - - else - spurious_interrupt(); -} - -/* - * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for - * these devices typically allocate coherent DMA memory, however the - * DMA controller may still have some unsynchronized data in the FIFO. - * Issue a flush in the handlers to ensure that the driver sees - * the update. - */ - -static void ath79_default_ip2_handler(void) -{ - do_IRQ(ATH79_CPU_IRQ(2)); -} - -static void ath79_default_ip3_handler(void) -{ - do_IRQ(ATH79_CPU_IRQ(3)); -} - -static void ar71xx_ip2_handler(void) -{ - ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); - do_IRQ(ATH79_CPU_IRQ(2)); -} - -static void ar724x_ip2_handler(void) -{ - ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE); - do_IRQ(ATH79_CPU_IRQ(2)); -} - -static void ar913x_ip2_handler(void) -{ - ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC); - do_IRQ(ATH79_CPU_IRQ(2)); -} - -static void ar933x_ip2_handler(void) -{ - ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC); - do_IRQ(ATH79_CPU_IRQ(2)); -} - -static void ar71xx_ip3_handler(void) -{ - ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); - do_IRQ(ATH79_CPU_IRQ(3)); -} - -static void ar724x_ip3_handler(void) -{ - ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB); - do_IRQ(ATH79_CPU_IRQ(3)); -} - -static void ar913x_ip3_handler(void) -{ - ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB); - do_IRQ(ATH79_CPU_IRQ(3)); -} - -static void ar933x_ip3_handler(void) -{ - ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB); - do_IRQ(ATH79_CPU_IRQ(3)); -} - -static void ar934x_ip3_handler(void) -{ - ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB); - do_IRQ(ATH79_CPU_IRQ(3)); -} - -void __init arch_init_irq(void) -{ - if (soc_is_ar71xx()) { - ath79_ip2_handler = ar71xx_ip2_handler; - ath79_ip3_handler = ar71xx_ip3_handler; - } else if (soc_is_ar724x()) { - ath79_ip2_handler = ar724x_ip2_handler; - ath79_ip3_handler = ar724x_ip3_handler; - } else if (soc_is_ar913x()) { - ath79_ip2_handler = ar913x_ip2_handler; - ath79_ip3_handler = ar913x_ip3_handler; - } else if (soc_is_ar933x()) { - ath79_ip2_handler = ar933x_ip2_handler; - ath79_ip3_handler = ar933x_ip3_handler; - } else if (soc_is_ar934x()) { - ath79_ip2_handler = ath79_default_ip2_handler; - ath79_ip3_handler = ar934x_ip3_handler; - } else if (soc_is_qca955x()) { - ath79_ip2_handler = ath79_default_ip2_handler; - ath79_ip3_handler = ath79_default_ip3_handler; - } else { - BUG(); - } - - cp0_perfcount_irq = ATH79_MISC_IRQ(5); - mips_cpu_irq_init(); - ath79_misc_irq_init(); - - if (soc_is_ar934x()) - ar934x_ip2_irq_init(); - else if (soc_is_qca955x()) - qca955x_irq_init(); -} diff --git a/arch/mips/ath79/mach-ap121.c b/arch/mips/ath79/mach-ap121.c deleted file mode 100644 index 1bf73f2a069d..000000000000 --- a/arch/mips/ath79/mach-ap121.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Atheros AP121 board support - * - * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include "machtypes.h" -#include "dev-gpio-buttons.h" -#include "dev-leds-gpio.h" -#include "dev-spi.h" -#include "dev-usb.h" -#include "dev-wmac.h" - -#define AP121_GPIO_LED_WLAN 0 -#define AP121_GPIO_LED_USB 1 - -#define AP121_GPIO_BTN_JUMPSTART 11 -#define AP121_GPIO_BTN_RESET 12 - -#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */ -#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL) - -#define AP121_CAL_DATA_ADDR 0x1fff1000 - -static struct gpio_led ap121_leds_gpio[] __initdata = { - { - .name = "ap121:green:usb", - .gpio = AP121_GPIO_LED_USB, - .active_low = 0, - }, - { - .name = "ap121:green:wlan", - .gpio = AP121_GPIO_LED_WLAN, - .active_low = 0, - }, -}; - -static struct gpio_keys_button ap121_gpio_keys[] __initdata = { - { - .desc = "jumpstart button", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, - .gpio = AP121_GPIO_BTN_JUMPSTART, - .active_low = 1, - }, - { - .desc = "reset button", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, - .gpio = AP121_GPIO_BTN_RESET, - .active_low = 1, - } -}; - -static struct spi_board_info ap121_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "mx25l1606e", - } -}; - -static struct ath79_spi_platform_data ap121_spi_data = { - .bus_num = 0, - .num_chipselect = 1, -}; - -static void __init ap121_setup(void) -{ - u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR); - - ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio), - ap121_leds_gpio); - ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, - ARRAY_SIZE(ap121_gpio_keys), - ap121_gpio_keys); - - ath79_register_spi(&ap121_spi_data, ap121_spi_info, - ARRAY_SIZE(ap121_spi_info)); - ath79_register_usb(); - ath79_register_wmac(cal_data); -} - -MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", - ap121_setup); diff --git a/arch/mips/ath79/mach-ap136.c b/arch/mips/ath79/mach-ap136.c deleted file mode 100644 index 07eac58c3641..000000000000 --- a/arch/mips/ath79/mach-ap136.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Qualcomm Atheros AP136 reference board support - * - * Copyright (c) 2012 Qualcomm Atheros - * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include <linux/pci.h> -#include <linux/ath9k_platform.h> - -#include "machtypes.h" -#include "dev-gpio-buttons.h" -#include "dev-leds-gpio.h" -#include "dev-spi.h" -#include "dev-usb.h" -#include "dev-wmac.h" -#include "pci.h" - -#define AP136_GPIO_LED_STATUS_RED 14 -#define AP136_GPIO_LED_STATUS_GREEN 19 -#define AP136_GPIO_LED_USB 4 -#define AP136_GPIO_LED_WLAN_2G 13 -#define AP136_GPIO_LED_WLAN_5G 12 -#define AP136_GPIO_LED_WPS_RED 15 -#define AP136_GPIO_LED_WPS_GREEN 20 - -#define AP136_GPIO_BTN_WPS 16 -#define AP136_GPIO_BTN_RFKILL 21 - -#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ -#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) - -#define AP136_WMAC_CALDATA_OFFSET 0x1000 -#define AP136_PCIE_CALDATA_OFFSET 0x5000 - -static struct gpio_led ap136_leds_gpio[] __initdata = { - { - .name = "qca:green:status", - .gpio = AP136_GPIO_LED_STATUS_GREEN, - .active_low = 1, - }, - { - .name = "qca:red:status", - .gpio = AP136_GPIO_LED_STATUS_RED, - .active_low = 1, - }, - { - .name = "qca:green:wps", - .gpio = AP136_GPIO_LED_WPS_GREEN, - .active_low = 1, - }, - { - .name = "qca:red:wps", - .gpio = AP136_GPIO_LED_WPS_RED, - .active_low = 1, - }, - { - .name = "qca:red:wlan-2g", - .gpio = AP136_GPIO_LED_WLAN_2G, - .active_low = 1, - }, - { - .name = "qca:red:usb", - .gpio = AP136_GPIO_LED_USB, - .active_low = 1, - } -}; - -static struct gpio_keys_button ap136_gpio_keys[] __initdata = { - { - .desc = "WPS button", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, - .gpio = AP136_GPIO_BTN_WPS, - .active_low = 1, - }, - { - .desc = "RFKILL button", - .type = EV_KEY, - .code = KEY_RFKILL, - .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL, - .gpio = AP136_GPIO_BTN_RFKILL, - .active_low = 1, - }, -}; - -static struct spi_board_info ap136_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "mx25l6405d", - } -}; - -static struct ath79_spi_platform_data ap136_spi_data = { - .bus_num = 0, - .num_chipselect = 1, -}; - -#ifdef CONFIG_PCI -static struct ath9k_platform_data ap136_ath9k_data; - -static int ap136_pci_plat_dev_init(struct pci_dev *dev) -{ - if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) - dev->dev.platform_data = &ap136_ath9k_data; - - return 0; -} - -static void __init ap136_pci_init(u8 *eeprom) -{ - memcpy(ap136_ath9k_data.eeprom_data, eeprom, - sizeof(ap136_ath9k_data.eeprom_data)); - - ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); - ath79_register_pci(); -} -#else -static inline void ap136_pci_init(u8 *eeprom) {} -#endif /* CONFIG_PCI */ - -static void __init ap136_setup(void) -{ - u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); - - ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), - ap136_leds_gpio); - ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, - ARRAY_SIZE(ap136_gpio_keys), - ap136_gpio_keys); - ath79_register_spi(&ap136_spi_data, ap136_spi_info, - ARRAY_SIZE(ap136_spi_info)); - ath79_register_usb(); - ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); - ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); -} - -MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", - "Atheros AP136-010 reference board", - ap136_setup); diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c deleted file mode 100644 index 1c78d497f930..000000000000 --- a/arch/mips/ath79/mach-ap81.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Atheros AP81 board support - * - * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include "machtypes.h" -#include "dev-wmac.h" -#include "dev-gpio-buttons.h" -#include "dev-leds-gpio.h" -#include "dev-spi.h" -#include "dev-usb.h" - -#define AP81_GPIO_LED_STATUS 1 -#define AP81_GPIO_LED_AOSS 3 -#define AP81_GPIO_LED_WLAN 6 -#define AP81_GPIO_LED_POWER 14 - -#define AP81_GPIO_BTN_SW4 12 -#define AP81_GPIO_BTN_SW1 21 - -#define AP81_KEYS_POLL_INTERVAL 20 /* msecs */ -#define AP81_KEYS_DEBOUNCE_INTERVAL (3 * AP81_KEYS_POLL_INTERVAL) - -#define AP81_CAL_DATA_ADDR 0x1fff1000 - -static struct gpio_led ap81_leds_gpio[] __initdata = { - { - .name = "ap81:green:status", - .gpio = AP81_GPIO_LED_STATUS, - .active_low = 1, - }, { - .name = "ap81:amber:aoss", - .gpio = AP81_GPIO_LED_AOSS, - .active_low = 1, - }, { - .name = "ap81:green:wlan", - .gpio = AP81_GPIO_LED_WLAN, - .active_low = 1, - }, { - .name = "ap81:green:power", - .gpio = AP81_GPIO_LED_POWER, - .active_low = 1, - } -}; - -static struct gpio_keys_button ap81_gpio_keys[] __initdata = { - { - .desc = "sw1", - .type = EV_KEY, - .code = BTN_0, - .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, - .gpio = AP81_GPIO_BTN_SW1, - .active_low = 1, - } , { - .desc = "sw4", - .type = EV_KEY, - .code = BTN_1, - .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, - .gpio = AP81_GPIO_BTN_SW4, - .active_low = 1, - } -}; - -static struct spi_board_info ap81_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "m25p64", - } -}; - -static struct ath79_spi_platform_data ap81_spi_data = { - .bus_num = 0, - .num_chipselect = 1, -}; - -static void __init ap81_setup(void) -{ - u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR); - - ath79_register_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), - ap81_leds_gpio); - ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL, - ARRAY_SIZE(ap81_gpio_keys), - ap81_gpio_keys); - ath79_register_spi(&ap81_spi_data, ap81_spi_info, - ARRAY_SIZE(ap81_spi_info)); - ath79_register_wmac(cal_data); - ath79_register_usb(); -} - -MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", - ap81_setup); diff --git a/arch/mips/ath79/mach-db120.c b/arch/mips/ath79/mach-db120.c deleted file mode 100644 index 4d661a1d2dae..000000000000 --- a/arch/mips/ath79/mach-db120.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Atheros DB120 reference board support - * - * Copyright (c) 2011 Qualcomm Atheros - * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include <linux/pci.h> -#include <linux/ath9k_platform.h> - -#include "machtypes.h" -#include "dev-gpio-buttons.h" -#include "dev-leds-gpio.h" -#include "dev-spi.h" -#include "dev-usb.h" -#include "dev-wmac.h" -#include "pci.h" - -#define DB120_GPIO_LED_WLAN_5G 12 -#define DB120_GPIO_LED_WLAN_2G 13 -#define DB120_GPIO_LED_STATUS 14 -#define DB120_GPIO_LED_WPS 15 - -#define DB120_GPIO_BTN_WPS 16 - -#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ -#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) - -#define DB120_WMAC_CALDATA_OFFSET 0x1000 -#define DB120_PCIE_CALDATA_OFFSET 0x5000 - -static struct gpio_led db120_leds_gpio[] __initdata = { - { - .name = "db120:green:status", - .gpio = DB120_GPIO_LED_STATUS, - .active_low = 1, - }, - { - .name = "db120:green:wps", - .gpio = DB120_GPIO_LED_WPS, - .active_low = 1, - }, - { - .name = "db120:green:wlan-5g", - .gpio = DB120_GPIO_LED_WLAN_5G, - .active_low = 1, - }, - { - .name = "db120:green:wlan-2g", - .gpio = DB120_GPIO_LED_WLAN_2G, - .active_low = 1, - }, -}; - -static struct gpio_keys_button db120_gpio_keys[] __initdata = { - { - .desc = "WPS button", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL, - .gpio = DB120_GPIO_BTN_WPS, - .active_low = 1, - }, -}; - -static struct spi_board_info db120_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "s25sl064a", - } -}; - -static struct ath79_spi_platform_data db120_spi_data = { - .bus_num = 0, - .num_chipselect = 1, -}; - -#ifdef CONFIG_PCI -static struct ath9k_platform_data db120_ath9k_data; - -static int db120_pci_plat_dev_init(struct pci_dev *dev) -{ - switch (PCI_SLOT(dev->devfn)) { - case 0: - dev->dev.platform_data = &db120_ath9k_data; - break; - } - - return 0; -} - -static void __init db120_pci_init(u8 *eeprom) -{ - memcpy(db120_ath9k_data.eeprom_data, eeprom, - sizeof(db120_ath9k_data.eeprom_data)); - - ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); - ath79_register_pci(); -} -#else -static inline void db120_pci_init(void) {} -#endif /* CONFIG_PCI */ - -static void __init db120_setup(void) -{ - u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); - - ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), - db120_leds_gpio); - ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, - ARRAY_SIZE(db120_gpio_keys), - db120_gpio_keys); - ath79_register_spi(&db120_spi_data, db120_spi_info, - ARRAY_SIZE(db120_spi_info)); - ath79_register_usb(); - ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); - db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); -} - -MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", - db120_setup); diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c deleted file mode 100644 index 67b980d94fb7..000000000000 --- a/arch/mips/ath79/mach-pb44.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Atheros PB44 reference board support - * - * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/i2c-gpio.h> -#include <linux/i2c/pcf857x.h> - -#include "machtypes.h" -#include "dev-gpio-buttons.h" -#include "dev-leds-gpio.h" -#include "dev-spi.h" -#include "dev-usb.h" -#include "pci.h" - -#define PB44_GPIO_I2C_SCL 0 -#define PB44_GPIO_I2C_SDA 1 - -#define PB44_GPIO_EXP_BASE 16 -#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6) -#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8) -#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) -#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + 10) - -#define PB44_KEYS_POLL_INTERVAL 20 /* msecs */ -#define PB44_KEYS_DEBOUNCE_INTERVAL (3 * PB44_KEYS_POLL_INTERVAL) - -static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { - .sda_pin = PB44_GPIO_I2C_SDA, - .scl_pin = PB44_GPIO_I2C_SCL, -}; - -static struct platform_device pb44_i2c_gpio_device = { - .name = "i2c-gpio", - .id = 0, - .dev = { - .platform_data = &pb44_i2c_gpio_data, - } -}; - -static struct pcf857x_platform_data pb44_pcf857x_data = { - .gpio_base = PB44_GPIO_EXP_BASE, -}; - -static struct i2c_board_info pb44_i2c_board_info[] __initdata = { - { - I2C_BOARD_INFO("pcf8575", 0x20), - .platform_data = &pb44_pcf857x_data, - }, -}; - -static struct gpio_led pb44_leds_gpio[] __initdata = { - { - .name = "pb44:amber:jump1", - .gpio = PB44_GPIO_LED_JUMP1, - .active_low = 1, - }, { - .name = "pb44:green:jump2", - .gpio = PB44_GPIO_LED_JUMP2, - .active_low = 1, - }, -}; - -static struct gpio_keys_button pb44_gpio_keys[] __initdata = { - { - .desc = "soft_reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, - .gpio = PB44_GPIO_SW_RESET, - .active_low = 1, - } , { - .desc = "jumpstart", - .type = EV_KEY, - .code = KEY_WPS_BUTTON, - .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, - .gpio = PB44_GPIO_SW_JUMP, - .active_low = 1, - } -}; - -static struct spi_board_info pb44_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "m25p64", - }, -}; - -static struct ath79_spi_platform_data pb44_spi_data = { - .bus_num = 0, - .num_chipselect = 1, -}; - -static void __init pb44_init(void) -{ - i2c_register_board_info(0, pb44_i2c_board_info, - ARRAY_SIZE(pb44_i2c_board_info)); - platform_device_register(&pb44_i2c_gpio_device); - - ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), - pb44_leds_gpio); - ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL, - ARRAY_SIZE(pb44_gpio_keys), - pb44_gpio_keys); - ath79_register_spi(&pb44_spi_data, pb44_spi_info, - ARRAY_SIZE(pb44_spi_info)); - ath79_register_usb(); - ath79_register_pci(); -} - -MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", - pb44_init); diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c deleted file mode 100644 index 4a3c60694c75..000000000000 --- a/arch/mips/ath79/mach-ubnt-xm.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Ubiquiti Networks XM (rev 1.0) board support - * - * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> - * - * Derived from: mach-pb44.c - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/ath9k_platform.h> - -#include <asm/mach-ath79/irq.h> - -#include "machtypes.h" -#include "dev-gpio-buttons.h" -#include "dev-leds-gpio.h" -#include "dev-spi.h" -#include "pci.h" - -#define UBNT_XM_GPIO_LED_L1 0 -#define UBNT_XM_GPIO_LED_L2 1 -#define UBNT_XM_GPIO_LED_L3 11 -#define UBNT_XM_GPIO_LED_L4 7 - -#define UBNT_XM_GPIO_BTN_RESET 12 - -#define UBNT_XM_KEYS_POLL_INTERVAL 20 -#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) - -#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000) - -static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { - { - .name = "ubnt-xm:red:link1", - .gpio = UBNT_XM_GPIO_LED_L1, - .active_low = 0, - }, { - .name = "ubnt-xm:orange:link2", - .gpio = UBNT_XM_GPIO_LED_L2, - .active_low = 0, - }, { - .name = "ubnt-xm:green:link3", - .gpio = UBNT_XM_GPIO_LED_L3, - .active_low = 0, - }, { - .name = "ubnt-xm:green:link4", - .gpio = UBNT_XM_GPIO_LED_L4, - .active_low = 0, - }, -}; - -static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = { - { - .desc = "reset", - .type = EV_KEY, - .code = KEY_RESTART, - .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, - .gpio = UBNT_XM_GPIO_BTN_RESET, - .active_low = 1, - } -}; - -static struct spi_board_info ubnt_xm_spi_info[] = { - { - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 25000000, - .modalias = "mx25l6405d", - } -}; - -static struct ath79_spi_platform_data ubnt_xm_spi_data = { - .bus_num = 0, - .num_chipselect = 1, -}; - -#ifdef CONFIG_PCI -static struct ath9k_platform_data ubnt_xm_eeprom_data; - -static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) -{ - switch (PCI_SLOT(dev->devfn)) { - case 0: - dev->dev.platform_data = &ubnt_xm_eeprom_data; - break; - } - - return 0; -} - -static void __init ubnt_xm_pci_init(void) -{ - memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, - sizeof(ubnt_xm_eeprom_data.eeprom_data)); - - ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); - ath79_register_pci(); -} -#else -static inline void ubnt_xm_pci_init(void) {} -#endif /* CONFIG_PCI */ - -static void __init ubnt_xm_init(void) -{ - ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio), - ubnt_xm_leds_gpio); - - ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, - ARRAY_SIZE(ubnt_xm_gpio_keys), - ubnt_xm_gpio_keys); - - ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info, - ARRAY_SIZE(ubnt_xm_spi_info)); - - ubnt_xm_pci_init(); -} - -MIPS_MACHINE(ATH79_MACH_UBNT_XM, - "UBNT-XM", - "Ubiquiti Networks XM (rev 1.0) board", - ubnt_xm_init); diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h deleted file mode 100644 index 26254058c545..000000000000 --- a/arch/mips/ath79/machtypes.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Atheros AR71XX/AR724X/AR913X machine type definitions - * - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _ATH79_MACHTYPE_H -#define _ATH79_MACHTYPE_H - -#include <asm/mips_machine.h> - -enum ath79_mach_type { - ATH79_MACH_GENERIC = 0, - ATH79_MACH_AP121, /* Atheros AP121 reference board */ - ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ - ATH79_MACH_AP81, /* Atheros AP81 reference board */ - ATH79_MACH_DB120, /* Atheros DB120 reference board */ - ATH79_MACH_PB44, /* Atheros PB44 reference board */ - ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ -}; - -#endif /* _ATH79_MACHTYPE_H */ diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c deleted file mode 100644 index 730c0b03060d..000000000000 --- a/arch/mips/ath79/pci.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Atheros AR71XX/AR724X specific PCI setup code - * - * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * Parts of this file are based on Atheros' 2.6.15 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/resource.h> -#include <linux/platform_device.h> -#include <asm/mach-ath79/ar71xx_regs.h> -#include <asm/mach-ath79/ath79.h> -#include <asm/mach-ath79/irq.h> -#include "pci.h" - -static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); -static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; -static unsigned ath79_pci_nr_irqs __initdata; - -static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { - { - .slot = 17, - .pin = 1, - .irq = ATH79_PCI_IRQ(0), - }, { - .slot = 18, - .pin = 1, - .irq = ATH79_PCI_IRQ(1), - }, { - .slot = 19, - .pin = 1, - .irq = ATH79_PCI_IRQ(2), - } -}; - -static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = { - { - .slot = 0, - .pin = 1, - .irq = ATH79_PCI_IRQ(0), - } -}; - -static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = { - { - .bus = 0, - .slot = 0, - .pin = 1, - .irq = ATH79_PCI_IRQ(0), - }, - { - .bus = 1, - .slot = 0, - .pin = 1, - .irq = ATH79_PCI_IRQ(1), - }, -}; - -int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) -{ - int irq = -1; - int i; - - if (ath79_pci_nr_irqs == 0 || - ath79_pci_irq_map == NULL) { - if (soc_is_ar71xx()) { - ath79_pci_irq_map = ar71xx_pci_irq_map; - ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); - } else if (soc_is_ar724x() || - soc_is_ar9342() || - soc_is_ar9344()) { - ath79_pci_irq_map = ar724x_pci_irq_map; - ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); - } else if (soc_is_qca955x()) { - ath79_pci_irq_map = qca955x_pci_irq_map; - ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); - } else { - pr_crit("pci %s: invalid irq map\n", - pci_name((struct pci_dev *) dev)); - return irq; - } - } - - for (i = 0; i < ath79_pci_nr_irqs; i++) { - const struct ath79_pci_irq *entry; - - entry = &ath79_pci_irq_map[i]; - if (entry->bus == dev->bus->number && - entry->slot == slot && - entry->pin == pin) { - irq = entry->irq; - break; - } - } - - if (irq < 0) - pr_crit("pci %s: no irq found for pin %u\n", - pci_name((struct pci_dev *) dev), pin); - else - pr_info("pci %s: using irq %d for pin %u\n", - pci_name((struct pci_dev *) dev), irq, pin); - - return irq; -} - -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - if (ath79_pci_plat_dev_init) - return ath79_pci_plat_dev_init(dev); - - return 0; -} - -void __init ath79_pci_set_irq_map(unsigned nr_irqs, - const struct ath79_pci_irq *map) -{ - ath79_pci_nr_irqs = nr_irqs; - ath79_pci_irq_map = map; -} - -void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)) -{ - ath79_pci_plat_dev_init = func; -} - -static struct platform_device * -ath79_register_pci_ar71xx(void) -{ - struct platform_device *pdev; - struct resource res[4]; - - memset(res, 0, sizeof(res)); - - res[0].name = "cfg_base"; - res[0].flags = IORESOURCE_MEM; - res[0].start = AR71XX_PCI_CFG_BASE; - res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1; - - res[1].flags = IORESOURCE_IRQ; - res[1].start = ATH79_CPU_IRQ(2); - res[1].end = ATH79_CPU_IRQ(2); - - res[2].name = "io_base"; - res[2].flags = IORESOURCE_IO; - res[2].start = 0; - res[2].end = 0; - - res[3].name = "mem_base"; - res[3].flags = IORESOURCE_MEM; - res[3].start = AR71XX_PCI_MEM_BASE; - res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1; - - pdev = platform_device_register_simple("ar71xx-pci", -1, - res, ARRAY_SIZE(res)); - return pdev; -} - -static struct platform_device * -ath79_register_pci_ar724x(int id, - unsigned long cfg_base, - unsigned long ctrl_base, - unsigned long crp_base, - unsigned long mem_base, - unsigned long mem_size, - unsigned long io_base, - int irq) -{ - struct platform_device *pdev; - struct resource res[6]; - - memset(res, 0, sizeof(res)); - - res[0].name = "cfg_base"; - res[0].flags = IORESOURCE_MEM; - res[0].start = cfg_base; - res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1; - - res[1].name = "ctrl_base"; - res[1].flags = IORESOURCE_MEM; - res[1].start = ctrl_base; - res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1; - - res[2].flags = IORESOURCE_IRQ; - res[2].start = irq; - res[2].end = irq; - - res[3].name = "mem_base"; - res[3].flags = IORESOURCE_MEM; - res[3].start = mem_base; - res[3].end = mem_base + mem_size - 1; - - res[4].name = "io_base"; - res[4].flags = IORESOURCE_IO; - res[4].start = io_base; - res[4].end = io_base; - - res[5].name = "crp_base"; - res[5].flags = IORESOURCE_MEM; - res[5].start = crp_base; - res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1; - - pdev = platform_device_register_simple("ar724x-pci", id, - res, ARRAY_SIZE(res)); - return pdev; -} - -int __init ath79_register_pci(void) -{ - struct platform_device *pdev = NULL; - - if (soc_is_ar71xx()) { - pdev = ath79_register_pci_ar71xx(); - } else if (soc_is_ar724x()) { - pdev = ath79_register_pci_ar724x(-1, - AR724X_PCI_CFG_BASE, - AR724X_PCI_CTRL_BASE, - AR724X_PCI_CRP_BASE, - AR724X_PCI_MEM_BASE, - AR724X_PCI_MEM_SIZE, - 0, - ATH79_CPU_IRQ(2)); - } else if (soc_is_ar9342() || - soc_is_ar9344()) { - u32 bootstrap; - - bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); - if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0) - return -ENODEV; - - pdev = ath79_register_pci_ar724x(-1, - AR724X_PCI_CFG_BASE, - AR724X_PCI_CTRL_BASE, - AR724X_PCI_CRP_BASE, - AR724X_PCI_MEM_BASE, - AR724X_PCI_MEM_SIZE, - 0, - ATH79_IP2_IRQ(0)); - } else if (soc_is_qca9558()) { - pdev = ath79_register_pci_ar724x(0, - QCA955X_PCI_CFG_BASE0, - QCA955X_PCI_CTRL_BASE0, - QCA955X_PCI_CRP_BASE0, - QCA955X_PCI_MEM_BASE0, - QCA955X_PCI_MEM_SIZE, - 0, - ATH79_IP2_IRQ(0)); - - pdev = ath79_register_pci_ar724x(1, - QCA955X_PCI_CFG_BASE1, - QCA955X_PCI_CTRL_BASE1, - QCA955X_PCI_CRP_BASE1, - QCA955X_PCI_MEM_BASE1, - QCA955X_PCI_MEM_SIZE, - 1, - ATH79_IP3_IRQ(2)); - } else { - /* No PCI support */ - return -ENODEV; - } - - if (!pdev) - pr_err("unable to register PCI controller device\n"); - - return pdev ? 0 : -ENODEV; -} diff --git a/arch/mips/ath79/pci.h b/arch/mips/ath79/pci.h deleted file mode 100644 index 1d00a3803c37..000000000000 --- a/arch/mips/ath79/pci.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Atheros AR71XX/AR724X PCI support - * - * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com> - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef _ATH79_PCI_H -#define _ATH79_PCI_H - -struct ath79_pci_irq { - int bus; - u8 slot; - u8 pin; - int irq; -}; - -#ifdef CONFIG_PCI -void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map); -void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev)); -int ath79_register_pci(void); -#else -static inline void -ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {} -static inline void -ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {} -static inline int ath79_register_pci(void) { return 0; } -#endif - -#endif /* _ATH79_PCI_H */ diff --git a/arch/mips/ath79/prom.c b/arch/mips/ath79/prom.c index e9cbd7c2918f..cc6dc5600677 100644 --- a/arch/mips/ath79/prom.c +++ b/arch/mips/ath79/prom.c @@ -1,57 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Atheros AR71XX/AR724X/AR913X specific prom routines * + * Copyright (C) 2015 Laurent Fasnacht <l@libres.ch> * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. */ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> #include <linux/string.h> +#include <linux/initrd.h> #include <asm/bootinfo.h> #include <asm/addrspace.h> +#include <asm/fw/fw.h> #include "common.h" -static inline int is_valid_ram_addr(void *addr) -{ - if (((u32) addr > KSEG0) && - ((u32) addr < (KSEG0 + ATH79_MEM_SIZE_MAX))) - return 1; - - if (((u32) addr > KSEG1) && - ((u32) addr < (KSEG1 + ATH79_MEM_SIZE_MAX))) - return 1; - - return 0; -} - -static __init void ath79_prom_init_cmdline(int argc, char **argv) -{ - int i; - - if (!is_valid_ram_addr(argv)) - return; - - for (i = 0; i < argc; i++) - if (is_valid_ram_addr(argv[i])) { - strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); - strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); - } -} - void __init prom_init(void) { - ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1); -} - -void __init prom_free_prom_memory(void) -{ - /* We do not have to prom memory to free */ + fw_init_cmdline(); + +#ifdef CONFIG_BLK_DEV_INITRD + /* Read the initrd address from the firmware environment */ + initrd_start = fw_getenvl("initrd_start"); + if (initrd_start) { + initrd_start = KSEG0ADDR(initrd_start); + initrd_end = initrd_start + fw_getenvl("initrd_size"); + } +#endif } diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 8be4e856b8b8..4e18cdcf65a0 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Atheros AR71XX/AR724X/AR913X specific setup * @@ -6,46 +7,33 @@ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> * * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. */ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/bootmem.h> +#include <linux/io.h> +#include <linux/memblock.h> #include <linux/err.h> #include <linux/clk.h> +#include <linux/of_clk.h> +#include <linux/of_fdt.h> +#include <linux/irqchip.h> #include <asm/bootinfo.h> #include <asm/idle.h> #include <asm/time.h> /* for mips_hpt_frequency */ #include <asm/reboot.h> /* for _machine_{restart,halt} */ -#include <asm/mips_machine.h> +#include <asm/prom.h> +#include <asm/fw/fw.h> #include <asm/mach-ath79/ath79.h> #include <asm/mach-ath79/ar71xx_regs.h> #include "common.h" -#include "dev-common.h" -#include "machtypes.h" #define ATH79_SYS_TYPE_LEN 64 -#define AR71XX_BASE_FREQ 40000000 -#define AR724X_BASE_FREQ 5000000 -#define AR913X_BASE_FREQ 5000000 - static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; -static void ath79_restart(char *command) -{ - ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); - for (;;) - if (cpu_wait) - cpu_wait(); -} - static void ath79_halt(void) { while (1) @@ -59,6 +47,7 @@ static void __init ath79_detect_sys_type(void) u32 major; u32 minor; u32 rev = 0; + u32 ver = 1; id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); major = id & REV_ID_MAJOR_MASK; @@ -151,6 +140,16 @@ static void __init ath79_detect_sys_type(void) rev = id & AR934X_REV_ID_REVISION_MASK; break; + case REV_ID_MAJOR_QCA9533_V2: + ver = 2; + ath79_soc_rev = 2; + fallthrough; + case REV_ID_MAJOR_QCA9533: + ath79_soc = ATH79_SOC_QCA9533; + chip = "9533"; + rev = id & QCA953X_REV_ID_REVISION_MASK; + break; + case REV_ID_MAJOR_QCA9556: ath79_soc = ATH79_SOC_QCA9556; chip = "9556"; @@ -163,14 +162,36 @@ static void __init ath79_detect_sys_type(void) rev = id & QCA955X_REV_ID_REVISION_MASK; break; + case REV_ID_MAJOR_QCA956X: + ath79_soc = ATH79_SOC_QCA956X; + chip = "956X"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_QCN550X: + ath79_soc = ATH79_SOC_QCA956X; + chip = "550X"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + + case REV_ID_MAJOR_TP9343: + ath79_soc = ATH79_SOC_TP9343; + chip = "9343"; + rev = id & QCA956X_REV_ID_REVISION_MASK; + break; + default: panic("ath79: unknown SoC, id:0x%08x", id); } - ath79_soc_rev = rev; + if (ver == 1) + ath79_soc_rev = rev; - if (soc_is_qca955x()) - sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", + if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x()) + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", + chip, ver, rev); + else if (soc_is_tp9343()) + sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", chip, rev); else sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); @@ -182,61 +203,69 @@ const char *get_system_type(void) return ath79_sys_type; } -unsigned int __cpuinit get_c0_compare_int(void) +unsigned int get_c0_compare_int(void) { return CP0_LEGACY_COMPARE_IRQ; } void __init plat_mem_setup(void) { + void *dtb; + set_io_port_base(KSEG1); - ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, + /* Get the position of the FDT passed by the bootloader */ + dtb = (void *)fw_getenvl("fdt_start"); + if (dtb == NULL) + dtb = get_fdt(); + + if (dtb) + __dt_setup_arch((void *)KSEG0ADDR(dtb)); + + ath79_reset_base = ioremap(AR71XX_RESET_BASE, AR71XX_RESET_SIZE); - ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, + ath79_pll_base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); - ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, - AR71XX_DDR_CTRL_SIZE); - ath79_detect_sys_type(); + ath79_ddr_ctrl_init(); + detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); - ath79_clocks_init(); - _machine_restart = ath79_restart; _machine_halt = ath79_halt; pm_power_off = ath79_halt; } void __init plat_time_init(void) { + struct device_node *np; struct clk *clk; + unsigned long cpu_clk_rate; - clk = clk_get(NULL, "cpu"); - if (IS_ERR(clk)) - panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + of_clk_init(NULL); - mips_hpt_frequency = clk_get_rate(clk) / 2; -} + np = of_get_cpu_node(0, NULL); + if (!np) { + pr_err("Failed to get CPU node\n"); + return; + } -static int __init ath79_setup(void) -{ - ath79_gpio_init(); - ath79_register_uart(); - ath79_register_wdt(); + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); + return; + } - mips_machine_setup(); + cpu_clk_rate = clk_get_rate(clk); - return 0; -} + pr_info("CPU clock: %lu.%03lu MHz\n", + cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000); -arch_initcall(ath79_setup); + mips_hpt_frequency = cpu_clk_rate / 2; -static void __init ath79_generic_init(void) -{ - /* Nothing to do */ + clk_put(clk); } -MIPS_MACHINE(ATH79_MACH_GENERIC, - "Generic", - "Generic AR71XX/AR724X/AR913X based board", - ath79_generic_init); +void __init arch_init_irq(void) +{ + irqchip_init(); +} |