summaryrefslogtreecommitdiff
path: root/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi')
-rw-r--r--arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi292
1 files changed, 0 insertions, 292 deletions
diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
deleted file mode 100644
index 78f5533a95c6..000000000000
--- a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi
+++ /dev/null
@@ -1,292 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Copyright 2023 Mobileye Vision Technologies Ltd.
- */
-
-/ {
- /* Fixed clock */
- pll_cpu: pll-cpu {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1500000000>;
- };
-
- pll_vdi: pll-vdi {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1280000000>;
- };
-
- pll_per: pll-per {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <2000000000>;
- };
-
- pll_ddr0: pll-ddr0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1857210000>;
- };
-
- pll_ddr1: pll-ddr1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1857210000>;
- };
-
-/* PLL_CPU derivatives */
- occ_cpu: occ-cpu {
- compatible = "fixed-factor-clock";
- clocks = <&pll_cpu>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */
- compatible = "fixed-factor-clock";
- clocks = <&occ_cpu>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- cpc_clk: cpc-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- core0_clk: core0-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- core1_clk: core1-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- core2_clk: core2-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- core3_clk: core3-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- cm_clk: cm-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- mem_clk: mem-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- occ_isram: occ-isram {
- compatible = "fixed-factor-clock";
- clocks = <&pll_cpu>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
- isram_clk: isram-clk { /* gate ClkRstGen_isram */
- compatible = "fixed-factor-clock";
- clocks = <&occ_isram>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- occ_dbu: occ-dbu {
- compatible = "fixed-factor-clock";
- clocks = <&pll_cpu>;
- #clock-cells = <0>;
- clock-div = <10>;
- clock-mult = <1>;
- };
- si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */
- compatible = "fixed-factor-clock";
- clocks = <&occ_dbu>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
-/* PLL_VDI derivatives */
- occ_vdi: occ-vdi {
- compatible = "fixed-factor-clock";
- clocks = <&pll_vdi>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
- vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */
- compatible = "fixed-factor-clock";
- clocks = <&occ_vdi>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- occ_can_ser: occ-can-ser {
- compatible = "fixed-factor-clock";
- clocks = <&pll_vdi>;
- #clock-cells = <0>;
- clock-div = <16>;
- clock-mult = <1>;
- };
- can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */
- compatible = "fixed-factor-clock";
- clocks = <&occ_can_ser>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- i2c_ser_clk: i2c-ser-clk {
- compatible = "fixed-factor-clock";
- clocks = <&pll_vdi>;
- #clock-cells = <0>;
- clock-div = <20>;
- clock-mult = <1>;
- };
-/* PLL_PER derivatives */
- occ_periph: occ-periph {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <16>;
- clock-mult = <1>;
- };
- periph_clk: periph-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- can_clk: can-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- spi_clk: spi-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- uart_clk: uart-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- i2c_clk: i2c-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "i2c_clk";
- };
- timer_clk: timer-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "timer_clk";
- };
- gpio_clk: gpio-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "gpio_clk";
- };
- emmc_sys_clk: emmc-sys-clk {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <10>;
- clock-mult = <1>;
- clock-output-names = "emmc_sys_clk";
- };
- ccf_ctrl_clk: ccf-ctrl-clk {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <4>;
- clock-mult = <1>;
- clock-output-names = "ccf_ctrl_clk";
- };
- occ_mjpeg_core: occ-mjpeg-core {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- clock-output-names = "occ_mjpeg_core";
- };
- hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */
- compatible = "fixed-factor-clock";
- clocks = <&occ_mjpeg_core>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "hsm_clk";
- };
- mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */
- compatible = "fixed-factor-clock";
- clocks = <&occ_mjpeg_core>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "mjpeg_core_clk";
- };
- fcmu_a_clk: fcmu-a-clk {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <20>;
- clock-mult = <1>;
- clock-output-names = "fcmu_a_clk";
- };
- occ_pci_sys: occ-pci-sys {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <8>;
- clock-mult = <1>;
- clock-output-names = "occ_pci_sys";
- };
- pclk: pclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <250000000>; /* 250MHz */
- };
- tsu_clk: tsu-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>; /* 125MHz */
- };
-};
generated by cgit (git 2.34.1) at 2025-03-22 12:10:53 +0000