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-rw-r--r--arch/mips/boot/dts/ralink/Makefile2
-rw-r--r--arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts2
-rw-r--r--arch/mips/boot/dts/ralink/mt7620a.dtsi10
-rw-r--r--arch/mips/boot/dts/ralink/mt7620a_eval.dts2
-rw-r--r--arch/mips/boot/dts/ralink/mt7621.dtsi430
-rw-r--r--arch/mips/boot/dts/ralink/mt7628a.dtsi40
-rw-r--r--arch/mips/boot/dts/ralink/omega2p.dts2
-rw-r--r--arch/mips/boot/dts/ralink/rt2880.dtsi10
-rw-r--r--arch/mips/boot/dts/ralink/rt2880_eval.dts2
-rw-r--r--arch/mips/boot/dts/ralink/rt3050.dtsi10
-rw-r--r--arch/mips/boot/dts/ralink/rt3883.dtsi10
-rw-r--r--arch/mips/boot/dts/ralink/rt3883_eval.dts2
12 files changed, 301 insertions, 221 deletions
diff --git a/arch/mips/boot/dts/ralink/Makefile b/arch/mips/boot/dts/ralink/Makefile
index d27d7e8c700f..dc002152d843 100644
--- a/arch/mips/boot/dts/ralink/Makefile
+++ b/arch/mips/boot/dts/ralink/Makefile
@@ -10,5 +10,3 @@ dtb-$(CONFIG_SOC_MT7621) += \
mt7621-gnubee-gb-pc1.dtb \
mt7621-gnubee-gb-pc2.dtb \
mt7621-tplink-hc220-g5-v1.dtb
-
-obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts b/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
index 18107ca0a06b..7743d014631a 100644
--- a/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
+++ b/arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
@@ -5,7 +5,7 @@
/dts-v1/;
-/include/ "mt7628a.dtsi"
+#include "mt7628a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 1f6e5320f486..d66045948a83 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -1,4 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -25,9 +27,11 @@
#address-cells = <1>;
#size-cells = <1>;
- sysc@0 {
- compatible = "ralink,mt7620a-sysc";
+ sysc: syscon@0 {
+ compatible = "ralink,mt7620-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
intc: intc@200 {
@@ -50,6 +54,8 @@
compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
+ clocks = <&sysc MT7620_CLK_UARTLITE>;
+
interrupt-parent = <&intc>;
interrupts = <12>;
diff --git a/arch/mips/boot/dts/ralink/mt7620a_eval.dts b/arch/mips/boot/dts/ralink/mt7620a_eval.dts
index 8de8f89f31b8..da483ee65b61 100644
--- a/arch/mips/boot/dts/ralink/mt7620a_eval.dts
+++ b/arch/mips/boot/dts/ralink/mt7620a_eval.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-/include/ "mt7620a.dtsi"
+#include "mt7620a.dtsi"
/ {
compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index 6e95e6f19a6a..0704eab4a80b 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -5,50 +5,143 @@
#include <dt-bindings/reset/mt7621-reset.h>
/ {
+ compatible = "mediatek,mt7621-soc";
+
#address-cells = <1>;
#size-cells = <1>;
- compatible = "mediatek,mt7621-soc";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
- device_type = "cpu";
compatible = "mips,mips1004Kc";
reg = <0>;
+ device_type = "cpu";
};
cpu@1 {
- device_type = "cpu";
compatible = "mips,mips1004Kc";
reg = <1>;
+ device_type = "cpu";
};
};
cpuintc: cpuintc {
+ compatible = "mti,cpu-interrupt-controller";
+
#address-cells = <0>;
#interrupt-cells = <1>;
+
interrupt-controller;
- compatible = "mti,cpu-interrupt-controller";
};
mmc_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
- regulator-name = "mmc_power";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+
enable-active-high;
+
regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "mmc_power";
};
mmc_fixed_1v8_io: regulator-1v8 {
compatible = "regulator-fixed";
- regulator-name = "mmc_io";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+
enable-active-high;
+
regulator-always-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "mmc_io";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "ralink,mt7621-pinctrl";
+
+ i2c_pins: i2c0-pins {
+ pinmux {
+ groups = "i2c";
+ function = "i2c";
+ };
+ };
+
+ mdio_pins: mdio0-pins {
+ pinmux {
+ groups = "mdio";
+ function = "mdio";
+ };
+ };
+
+ nand_pins: nand0-pins {
+ sdhci-pinmux {
+ groups = "sdhci";
+ function = "nand2";
+ };
+
+ spi-pinmux {
+ groups = "spi";
+ function = "nand1";
+ };
+ };
+
+ pcie_pins: pcie0-pins {
+ pinmux {
+ groups = "pcie";
+ function = "gpio";
+ };
+ };
+
+ rgmii1_pins: rgmii1-pins {
+ pinmux {
+ groups = "rgmii1";
+ function = "rgmii1";
+ };
+ };
+
+ rgmii2_pins: rgmii2-pins {
+ pinmux {
+ groups = "rgmii2";
+ function = "rgmii2";
+ };
+ };
+
+ sdhci_pins: sdhci0-pins {
+ pinmux {
+ groups = "sdhci";
+ function = "sdhci";
+ };
+ };
+
+ spi_pins: spi0-pins {
+ pinmux {
+ groups = "spi";
+ function = "spi";
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pinmux {
+ groups = "uart1";
+ function = "uart1";
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ pinmux {
+ groups = "uart2";
+ function = "uart2";
+ };
+ };
+
+ uart3_pins: uart3-pins {
+ pinmux {
+ groups = "uart3";
+ function = "uart3";
+ };
+ };
};
palmbus: palmbus@1e000000 {
@@ -62,12 +155,15 @@
sysc: syscon@0 {
compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
+
#clock-cells = <1>;
#reset-cells = <1>;
- ralink,memctl = <&memc>;
+
clock-output-names = "xtal", "cpu", "bus",
"50m", "125m", "150m",
"250m", "270m";
+
+ ralink,memctl = <&memc>;
};
wdt: watchdog@100 {
@@ -77,13 +173,16 @@
};
gpio: gpio@600 {
+ compatible = "mediatek,mt7621-gpio";
+ reg = <0x600 0x100>;
+
#gpio-cells = <2>;
#interrupt-cells = <2>;
- compatible = "mediatek,mt7621-gpio";
+
gpio-controller;
gpio-ranges = <&pinctrl 0 0 95>;
+
interrupt-controller;
- reg = <0x600 0x100>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -92,18 +191,19 @@
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
- clocks = <&sysc MT7621_CLK_I2C>;
- clock-names = "i2c";
- resets = <&sysc MT7621_RST_I2C>;
- reset-names = "i2c";
-
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
+ clocks = <&sysc MT7621_CLK_I2C>;
+ clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins>;
+
+ resets = <&sysc MT7621_RST_I2C>;
+ reset-names = "i2c";
+
+ status = "disabled";
};
memc: memory-controller@5000 {
@@ -170,135 +270,53 @@
};
spi0: spi@b00 {
- status = "disabled";
-
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
- clocks = <&sysc MT7621_CLK_SPI>;
- clock-names = "spi";
-
- resets = <&sysc MT7621_RST_SPI>;
- reset-names = "spi";
-
#address-cells = <1>;
#size-cells = <0>;
+ clock-names = "spi";
+ clocks = <&sysc MT7621_CLK_SPI>;
+
pinctrl-names = "default";
pinctrl-0 = <&spi_pins>;
- };
- };
-
- pinctrl: pinctrl {
- compatible = "ralink,mt7621-pinctrl";
-
- i2c_pins: i2c0-pins {
- pinmux {
- groups = "i2c";
- function = "i2c";
- };
- };
-
- spi_pins: spi0-pins {
- pinmux {
- groups = "spi";
- function = "spi";
- };
- };
-
- uart1_pins: uart1-pins {
- pinmux {
- groups = "uart1";
- function = "uart1";
- };
- };
-
- uart2_pins: uart2-pins {
- pinmux {
- groups = "uart2";
- function = "uart2";
- };
- };
-
- uart3_pins: uart3-pins {
- pinmux {
- groups = "uart3";
- function = "uart3";
- };
- };
-
- rgmii1_pins: rgmii1-pins {
- pinmux {
- groups = "rgmii1";
- function = "rgmii1";
- };
- };
-
- rgmii2_pins: rgmii2-pins {
- pinmux {
- groups = "rgmii2";
- function = "rgmii2";
- };
- };
-
- mdio_pins: mdio0-pins {
- pinmux {
- groups = "mdio";
- function = "mdio";
- };
- };
-
- pcie_pins: pcie0-pins {
- pinmux {
- groups = "pcie";
- function = "gpio";
- };
- };
-
- nand_pins: nand0-pins {
- spi-pinmux {
- groups = "spi";
- function = "nand1";
- };
- sdhci-pinmux {
- groups = "sdhci";
- function = "nand2";
- };
- };
+ reset-names = "spi";
+ resets = <&sysc MT7621_RST_SPI>;
- sdhci_pins: sdhci0-pins {
- pinmux {
- groups = "sdhci";
- function = "sdhci";
- };
+ status = "disabled";
};
};
mmc: mmc@1e130000 {
- status = "disabled";
-
compatible = "mediatek,mt7620-mmc";
reg = <0x1e130000 0x4000>;
bus-width = <4>;
- max-frequency = <48000000>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- vmmc-supply = <&mmc_fixed_3v3>;
- vqmmc-supply = <&mmc_fixed_1v8_io>;
- disable-wp;
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&sdhci_pins>;
- pinctrl-1 = <&sdhci_pins>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
clocks = <&sysc MT7621_CLK_SHXC>,
<&sysc MT7621_CLK_50M>;
clock-names = "source", "hclk";
+ disable-wp;
+
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
+
+ max-frequency = <48000000>;
+
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&sdhci_pins>;
+ pinctrl-1 = <&sdhci_pins>;
+
+ vmmc-supply = <&mmc_fixed_3v3>;
+ vqmmc-supply = <&mmc_fixed_1v8_io>;
+
+ status = "disabled";
};
usb: usb@1e1c0000 {
@@ -321,15 +339,15 @@
compatible = "mti,gic";
reg = <0x1fbc0000 0x2000>;
- interrupt-controller;
#interrupt-cells = <3>;
+ interrupt-controller;
mti,reserved-cpu-vectors = <7>;
timer {
compatible = "mti,gic-timer";
- interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clocks = <&sysc MT7621_CLK_CPU>;
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
};
};
@@ -347,46 +365,22 @@
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
- clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
- clock-names = "fe", "ethif";
-
#address-cells = <1>;
#size-cells = <0>;
- resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
- reset-names = "fe", "eth";
+ clock-names = "fe", "ethif";
+ clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
- mediatek,ethsys = <&sysc>;
-
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
- gmac0: mac@0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "trgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
-
- gmac1: mac@1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- phy-mode = "rgmii";
+ reset-names = "fe", "eth";
+ resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
+ mediatek,ethsys = <&sysc>;
mdio: mdio-bus {
#address-cells = <1>;
@@ -395,73 +389,105 @@
switch0: switch@1f {
compatible = "mediatek,mt7621";
reg = <0x1f>;
- mediatek,mcm;
- resets = <&sysc MT7621_RST_MCM>;
- reset-names = "mcm";
- interrupt-controller;
+
#interrupt-cells = <1>;
+ interrupt-controller;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
+ reset-names = "mcm";
+ resets = <&sysc MT7621_RST_MCM>;
+
+ mediatek,mcm;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
- status = "disabled";
reg = <0>;
label = "swp0";
+ status = "disabled";
};
port@1 {
- status = "disabled";
reg = <1>;
label = "swp1";
+ status = "disabled";
};
port@2 {
- status = "disabled";
reg = <2>;
label = "swp2";
+ status = "disabled";
};
port@3 {
- status = "disabled";
reg = <3>;
label = "swp3";
+ status = "disabled";
};
port@4 {
- status = "disabled";
reg = <4>;
label = "swp4";
+ status = "disabled";
};
port@5 {
reg = <5>;
+
ethernet = <&gmac1>;
phy-mode = "rgmii";
fixed-link {
- speed = <1000>;
full-duplex;
pause;
+ speed = <1000>;
};
};
port@6 {
reg = <6>;
+
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
- speed = <1000>;
full-duplex;
pause;
+ speed = <1000>;
};
};
};
};
};
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+
+ phy-mode = "trgmii";
+
+ fixed-link {
+ full-duplex;
+ pause;
+ speed = <1000>;
+ };
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+
+ phy-mode = "rgmii";
+
+ fixed-link {
+ full-duplex;
+ pause;
+ speed = <1000>;
+ };
+ };
+
};
pcie: pcie@1e140000 {
@@ -470,84 +496,106 @@
<0x1e142000 0x100>, /* pcie port 0 RC control registers */
<0x1e143000 0x100>, /* pcie port 1 RC control registers */
<0x1e144000 0x100>; /* pcie port 2 RC control registers */
+ ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
+ <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
+
#address-cells = <3>;
+ #interrupt-cells = <1>;
#size-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pins>;
-
device_type = "pci";
- ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
- <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0xF800 0 0 0>;
- interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
+ interrupt-map-mask = <0xf800 0 0 0>;
+ interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
+ ranges;
+
#address-cells = <3>;
+ #interrupt-cells = <1>;
#size-cells = <2>;
+
+ clocks = <&sysc MT7621_CLK_PCIE0>;
+
device_type = "pci";
- #interrupt-cells = <1>;
+
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&sysc MT7621_RST_PCIE0>;
- clocks = <&sysc MT7621_CLK_PCIE0>;
- phys = <&pcie0_phy 1>;
+
phy-names = "pcie-phy0";
- ranges;
+ phys = <&pcie0_phy 1>;
+
+ resets = <&sysc MT7621_RST_PCIE0>;
};
pcie@1,0 {
reg = <0x0800 0 0 0 0>;
+ ranges;
+
#address-cells = <3>;
+ #interrupt-cells = <1>;
#size-cells = <2>;
+
+ clocks = <&sysc MT7621_CLK_PCIE1>;
+
device_type = "pci";
- #interrupt-cells = <1>;
+
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&sysc MT7621_RST_PCIE1>;
- clocks = <&sysc MT7621_CLK_PCIE1>;
- phys = <&pcie0_phy 1>;
+
phy-names = "pcie-phy1";
- ranges;
+ phys = <&pcie0_phy 1>;
+
+ resets = <&sysc MT7621_RST_PCIE1>;
};
pcie@2,0 {
reg = <0x1000 0 0 0 0>;
+ ranges;
+
#address-cells = <3>;
+ #interrupt-cells = <1>;
#size-cells = <2>;
+
+ clocks = <&sysc MT7621_CLK_PCIE2>;
+
device_type = "pci";
- #interrupt-cells = <1>;
+
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&sysc MT7621_RST_PCIE2>;
- clocks = <&sysc MT7621_CLK_PCIE2>;
- phys = <&pcie2_phy 0>;
+
phy-names = "pcie-phy2";
- ranges;
+ phys = <&pcie2_phy 0>;
+
+ resets = <&sysc MT7621_RST_PCIE2>;
};
};
pcie0_phy: pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e149000 0x0700>;
- clocks = <&sysc MT7621_CLK_XTAL>;
+
#phy-cells = <1>;
+
+ clocks = <&sysc MT7621_CLK_XTAL>;
};
pcie2_phy: pcie-phy@1e14a000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e14a000 0x0700>;
- clocks = <&sysc MT7621_CLK_XTAL>;
+
#phy-cells = <1>;
+
+ clocks = <&sysc MT7621_CLK_XTAL>;
};
};
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
index 45a15e005cc4..0212700c4fb4 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
/ {
#address-cells = <1>;
@@ -16,11 +17,6 @@
};
};
- resetc: reset-controller {
- compatible = "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
@@ -36,9 +32,11 @@
#address-cells = <1>;
#size-cells = <1>;
- sysc: system-controller@0 {
- compatible = "ralink,mt7620a-sysc", "syscon";
+ sysc: syscon@0 {
+ compatible = "ralink,mt7628-sysc", "syscon";
reg = <0x0 0x60>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
pinmux: pinmux@60 {
@@ -138,7 +136,7 @@
compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x30>;
- resets = <&resetc 8>;
+ resets = <&sysc 8>;
reset-names = "wdt";
interrupt-parent = <&intc>;
@@ -154,7 +152,7 @@
interrupt-controller;
#interrupt-cells = <1>;
- resets = <&resetc 9>;
+ resets = <&sysc 9>;
reset-names = "intc";
interrupt-parent = <&cpuintc>;
@@ -190,7 +188,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_spi_spi>;
- resets = <&resetc 18>;
+ clocks = <&sysc MT76X8_CLK_SPI1>;
+
+ resets = <&sysc 18>;
reset-names = "spi";
#address-cells = <1>;
@@ -206,7 +206,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_i2c_i2c>;
- resets = <&resetc 16>;
+ clocks = <&sysc MT76X8_CLK_I2C>;
+
+ resets = <&sysc 16>;
reset-names = "i2c";
#address-cells = <1>;
@@ -222,7 +224,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_uart0_uart>;
- resets = <&resetc 12>;
+ clocks = <&sysc MT76X8_CLK_UART0>;
+
+ resets = <&sysc 12>;
reset-names = "uart0";
interrupt-parent = <&intc>;
@@ -238,7 +242,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_uart1_uart>;
- resets = <&resetc 19>;
+ clocks = <&sysc MT76X8_CLK_UART1>;
+
+ resets = <&sysc 19>;
reset-names = "uart1";
interrupt-parent = <&intc>;
@@ -254,7 +260,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinmux_uart2_uart>;
- resets = <&resetc 20>;
+ clocks = <&sysc MT76X8_CLK_UART2>;
+
+ resets = <&sysc 20>;
reset-names = "uart2";
interrupt-parent = <&intc>;
@@ -271,7 +279,7 @@
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
- resets = <&resetc 22 &resetc 25>;
+ resets = <&sysc 22 &sysc 25>;
reset-names = "host", "device";
};
@@ -290,6 +298,8 @@
compatible = "mediatek,mt7628-wmac";
reg = <0x10300000 0x100000>;
+ clocks = <&sysc MT76X8_CLK_WMAC>;
+
interrupt-parent = <&cpuintc>;
interrupts = <6>;
diff --git a/arch/mips/boot/dts/ralink/omega2p.dts b/arch/mips/boot/dts/ralink/omega2p.dts
index 5884fd48f59a..51a40ab6df2b 100644
--- a/arch/mips/boot/dts/ralink/omega2p.dts
+++ b/arch/mips/boot/dts/ralink/omega2p.dts
@@ -1,6 +1,6 @@
/dts-v1/;
-/include/ "mt7628a.dtsi"
+#include "mt7628a.dtsi"
/ {
compatible = "onion,omega2+", "ralink,mt7688a-soc", "ralink,mt7628a-soc";
diff --git a/arch/mips/boot/dts/ralink/rt2880.dtsi b/arch/mips/boot/dts/ralink/rt2880.dtsi
index 8fc1987d9063..1f2ea3434324 100644
--- a/arch/mips/boot/dts/ralink/rt2880.dtsi
+++ b/arch/mips/boot/dts/ralink/rt2880.dtsi
@@ -1,4 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -25,9 +27,11 @@
#address-cells = <1>;
#size-cells = <1>;
- sysc@0 {
- compatible = "ralink,rt2880-sysc";
+ sysc: syscon@0 {
+ compatible = "ralink,rt2880-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
intc: intc@200 {
@@ -50,6 +54,8 @@
compatible = "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
+ clocks = <&sysc RT2880_CLK_UARTLITE>;
+
interrupt-parent = <&intc>;
interrupts = <8>;
diff --git a/arch/mips/boot/dts/ralink/rt2880_eval.dts b/arch/mips/boot/dts/ralink/rt2880_eval.dts
index 759bc1dd5b83..9854a4b120e9 100644
--- a/arch/mips/boot/dts/ralink/rt2880_eval.dts
+++ b/arch/mips/boot/dts/ralink/rt2880_eval.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-/include/ "rt2880.dtsi"
+#include "rt2880.dtsi"
/ {
compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";
diff --git a/arch/mips/boot/dts/ralink/rt3050.dtsi b/arch/mips/boot/dts/ralink/rt3050.dtsi
index 23062333a76d..a7d9bb9bc1af 100644
--- a/arch/mips/boot/dts/ralink/rt3050.dtsi
+++ b/arch/mips/boot/dts/ralink/rt3050.dtsi
@@ -1,4 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -25,9 +27,11 @@
#address-cells = <1>;
#size-cells = <1>;
- sysc@0 {
- compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc";
+ sysc: syscon@0 {
+ compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
intc: intc@200 {
@@ -50,6 +54,8 @@
compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
+ clocks = <&sysc RT305X_CLK_UARTLITE>;
+
interrupt-parent = <&intc>;
interrupts = <12>;
diff --git a/arch/mips/boot/dts/ralink/rt3883.dtsi b/arch/mips/boot/dts/ralink/rt3883.dtsi
index 61132cf157e5..11d111a06037 100644
--- a/arch/mips/boot/dts/ralink/rt3883.dtsi
+++ b/arch/mips/boot/dts/ralink/rt3883.dtsi
@@ -1,4 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -25,9 +27,11 @@
#address-cells = <1>;
#size-cells = <1>;
- sysc@0 {
- compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
+ sysc: syscon@0 {
+ compatible = "ralink,rt3883-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
intc: intc@200 {
@@ -50,6 +54,8 @@
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
+ clocks = <&sysc RT3883_CLK_UARTLITE>;
+
interrupt-parent = <&intc>;
interrupts = <12>;
diff --git a/arch/mips/boot/dts/ralink/rt3883_eval.dts b/arch/mips/boot/dts/ralink/rt3883_eval.dts
index c22bc84df219..a095a1fe9415 100644
--- a/arch/mips/boot/dts/ralink/rt3883_eval.dts
+++ b/arch/mips/boot/dts/ralink/rt3883_eval.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-/include/ "rt3883.dtsi"
+#include "rt3883.dtsi"
/ {
compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc";
generated by cgit (git 2.34.1) at 2025-07-23 18:32:38 +0000