diff options
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 46 |
1 files changed, 34 insertions, 12 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 724dfddcab92..404390bb87ea 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -64,6 +64,8 @@ ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt))) #define __isa_range_or_flag(ge, lt, flag) \ (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag))) +#define __isa_range_and_ase(ge, lt, ase) \ + (__isa_range(ge, lt) && __ase(ase)) /* * SMP assumption: Options of CPU 0 are a superset of all processors. @@ -115,16 +117,28 @@ #ifndef cpu_has_3k_cache #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) #endif -#define cpu_has_6k_cache 0 -#define cpu_has_8k_cache 0 #ifndef cpu_has_4k_cache -#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) -#endif -#ifndef cpu_has_tx39_cache -#define cpu_has_tx39_cache __opt(MIPS_CPU_TX39_CACHE) +#define cpu_has_4k_cache __opt(MIPS_CPU_4K_CACHE) #endif #ifndef cpu_has_octeon_cache -#define cpu_has_octeon_cache 0 +#define cpu_has_octeon_cache \ +({ \ + int __res; \ + \ + switch (boot_cpu_type()) { \ + case CPU_CAVIUM_OCTEON: \ + case CPU_CAVIUM_OCTEON_PLUS: \ + case CPU_CAVIUM_OCTEON2: \ + case CPU_CAVIUM_OCTEON3: \ + __res = 1; \ + break; \ + \ + default: \ + __res = 0; \ + } \ + \ + __res; \ +}) #endif /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ #ifndef cpu_has_fpu @@ -136,6 +150,9 @@ # define raw_cpu_has_fpu 0 # endif #else +# if cpu_has_fpu +# error "Forcing `cpu_has_fpu' to non-zero is not supported" +# endif # define raw_cpu_has_fpu cpu_has_fpu #endif #ifndef cpu_has_32fpr @@ -171,9 +188,6 @@ #ifndef cpu_has_llsc #define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC) #endif -#ifndef cpu_has_bp_ghist -#define cpu_has_bp_ghist __opt(MIPS_CPU_BP_GHIST) -#endif #ifndef kernel_uses_llsc #define kernel_uses_llsc cpu_has_llsc #endif @@ -354,7 +368,7 @@ ({ \ int __res; \ \ - switch (current_cpu_type()) { \ + switch (boot_cpu_type()) { \ case CPU_M14KC: \ case CPU_74K: \ case CPU_1074K: \ @@ -426,7 +440,7 @@ #endif #ifndef cpu_has_mipsmt -#define cpu_has_mipsmt __isa_lt_and_ase(6, MIPS_ASE_MIPSMT) +#define cpu_has_mipsmt __isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT) #endif #ifndef cpu_has_vp @@ -568,6 +582,14 @@ # define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY) #endif +#ifndef cpu_has_ftlbparex +# define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX) +#endif + +#ifndef cpu_has_gsexcex +# define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX) +#endif + #ifdef CONFIG_SMP /* * Some systems share FTLB RAMs between threads within a core (siblings in |