diff options
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi index 7b4426e0a5a5..bb7b9b9f3f5f 100644 --- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi @@ -1,7 +1,7 @@ /* * B4420 Silicon/SoC Device Tree Source (pre include) * - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012 - 2015 Freescale Semiconductor, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -34,6 +34,8 @@ /dts-v1/; +/include/ "e6500_power_isa.dtsi" + / { compatible = "fsl,B4420"; #address-cells = <2>; @@ -49,11 +51,17 @@ serial2 = &serial2; serial3 = &serial3; pci0 = &pci0; + usb0 = &usb0; dma0 = &dma0; dma1 = &dma1; sdhc = &sdhc; - }; + fman0 = &fman0; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + }; cpus { #address-cells = <1>; @@ -62,12 +70,16 @@ cpu0: PowerPC,e6500@0 { device_type = "cpu"; reg = <0 1>; - next-level-cache = <&L2>; + clocks = <&clockgen 1 0>; + next-level-cache = <&L2_1>; + fsl,portid-mapping = <0x80000000>; }; cpu1: PowerPC,e6500@2 { device_type = "cpu"; reg = <2 3>; - next-level-cache = <&L2>; + clocks = <&clockgen 1 0>; + next-level-cache = <&L2_1>; + fsl,portid-mapping = <0x80000000>; }; }; }; |