diff options
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi index 7a2697d04549..6318962e8d14 100644 --- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi @@ -1,7 +1,7 @@ /* * P2041 Silicon/SoC Device Tree Source (pre include) * - * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2011 - 2015 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -72,6 +72,14 @@ rtic_c = &rtic_c; rtic_d = &rtic_d; sec_mon = &sec_mon; + + fman0 = &fman0; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + ethernet4 = &enet4; + ethernet5 = &enet5; }; cpus { @@ -81,7 +89,9 @@ cpu0: PowerPC,e500mc@0 { device_type = "cpu"; reg = <0>; + clocks = <&clockgen 1 0>; next-level-cache = <&L2_0>; + fsl,portid-mapping = <0x80000000>; L2_0: l2-cache { next-level-cache = <&cpc>; }; @@ -89,7 +99,9 @@ cpu1: PowerPC,e500mc@1 { device_type = "cpu"; reg = <1>; + clocks = <&clockgen 1 1>; next-level-cache = <&L2_1>; + fsl,portid-mapping = <0x40000000>; L2_1: l2-cache { next-level-cache = <&cpc>; }; @@ -97,7 +109,9 @@ cpu2: PowerPC,e500mc@2 { device_type = "cpu"; reg = <2>; + clocks = <&clockgen 1 2>; next-level-cache = <&L2_2>; + fsl,portid-mapping = <0x20000000>; L2_2: l2-cache { next-level-cache = <&cpc>; }; @@ -105,7 +119,9 @@ cpu3: PowerPC,e500mc@3 { device_type = "cpu"; reg = <3>; + clocks = <&clockgen 1 3>; next-level-cache = <&L2_3>; + fsl,portid-mapping = <0x10000000>; L2_3: l2-cache { next-level-cache = <&cpc>; }; |