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Diffstat (limited to 'arch/powerpc/kernel/head_8xx.S')
-rw-r--r--arch/powerpc/kernel/head_8xx.S72
1 files changed, 71 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1a9c99d3e5d8..c032fe8c2d26 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -329,6 +329,12 @@ InstructionTLBMiss:
mtspr SPRN_SPRG_SCRATCH2, r3
#endif
EXCEPTION_PROLOG_0
+#ifdef CONFIG_PPC_8xx_PERF_EVENT
+ lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha
+ lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
+ addi r11, r11, 1
+ stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
+#endif
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
@@ -429,6 +435,12 @@ InstructionTLBMiss:
DataStoreTLBMiss:
mtspr SPRN_SPRG_SCRATCH2, r3
EXCEPTION_PROLOG_0
+#ifdef CONFIG_PPC_8xx_PERF_EVENT
+ lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha
+ lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
+ addi r11, r11, 1
+ stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
+#endif
mfcr r3
/* If we are faulting a kernel address, we have to use the
@@ -561,6 +573,7 @@ InstructionTLBError:
andis. r10,r5,0x4000
beq+ 1f
tlbie r4
+itlbie:
/* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
1: EXC_XFER_LITE(0x400, handle_page_fault)
@@ -585,6 +598,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
andis. r10,r5,0x4000
beq+ 1f
tlbie r4
+dtlbie:
1: li r10,RPN_PATTERN
mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
/* 0x300 is DataAccess exception, needed by bad_page_fault() */
@@ -602,8 +616,43 @@ DARFixed:/* Return from dcbx instruction bug workaround */
* support of breakpoints and such. Someday I will get around to
* using them.
*/
- EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
+ . = 0x1c00
+DataBreakpoint:
+ EXCEPTION_PROLOG_0
+ mfcr r10
+ mfspr r11, SPRN_SRR0
+ cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l
+ cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l
+ beq- cr0, 11f
+ beq- cr7, 11f
+ EXCEPTION_PROLOG_1
+ EXCEPTION_PROLOG_2
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ mfspr r4,SPRN_BAR
+ stw r4,_DAR(r11)
+ mfspr r5,SPRN_DSISR
+ EXC_XFER_EE(0x1c00, do_break)
+11:
+ mtcr r10
+ EXCEPTION_EPILOG_0
+ rfi
+
+#ifdef CONFIG_PPC_8xx_PERF_EVENT
+ . = 0x1d00
+InstructionBreakpoint:
+ EXCEPTION_PROLOG_0
+ lis r10, (instruction_counter - PAGE_OFFSET)@ha
+ lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10)
+ addi r11, r11, -1
+ stw r11, (instruction_counter - PAGE_OFFSET)@l(r10)
+ lis r10, 0xffff
+ ori r10, r10, 0x01
+ mtspr SPRN_COUNTA, r10
+ EXCEPTION_EPILOG_0
+ rfi
+#else
EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
+#endif
EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
@@ -977,6 +1026,14 @@ initial_mmu:
lis r8, IDC_ENABLE@h
mtspr SPRN_DC_CST, r8
#endif
+ /* Disable debug mode entry on breakpoints */
+ mfspr r8, SPRN_DER
+#ifdef CONFIG_PPC_8xx_PERF_EVENT
+ rlwinm r8, r8, 0, ~0xc
+#else
+ rlwinm r8, r8, 0, ~0x8
+#endif
+ mtspr SPRN_DER, r8
blr
@@ -1010,3 +1067,16 @@ cpu6_errata_word:
.space 16
#endif
+#ifdef CONFIG_PPC_8xx_PERF_EVENT
+ .globl itlb_miss_counter
+itlb_miss_counter:
+ .space 4
+
+ .globl dtlb_miss_counter
+dtlb_miss_counter:
+ .space 4
+
+ .globl instruction_counter
+instruction_counter:
+ .space 4
+#endif