diff options
Diffstat (limited to 'arch/x86/include/asm/apic.h')
| -rw-r--r-- | arch/x86/include/asm/apic.h | 861 |
1 files changed, 387 insertions, 474 deletions
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index f8119b582c3c..a26e66d66444 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -1,21 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef _ASM_X86_APIC_H #define _ASM_X86_APIC_H #include <linux/cpumask.h> -#include <linux/pm.h> +#include <linux/static_call.h> #include <asm/alternative.h> #include <asm/cpufeature.h> -#include <asm/processor.h> #include <asm/apicdef.h> #include <linux/atomic.h> #include <asm/fixmap.h> #include <asm/mpspec.h> #include <asm/msr.h> -#include <asm/idle.h> +#include <asm/hardirq.h> +#include <asm/io.h> +#include <asm/posted_intr.h> #define ARCH_APICTIMER_STOPS_ON_C3 1 +/* Macros for apic_extnmi which controls external NMI masking */ +#define APIC_EXTNMI_BSP 0 /* Default */ +#define APIC_EXTNMI_ALL 1 +#define APIC_EXTNMI_NONE 2 + /* * Debugging macros */ @@ -24,46 +31,48 @@ #define APIC_DEBUG 2 /* - * Define the default level of output to be very little - * This can be turned up by using apic=verbose for more - * information and apic=debug for _lots_ of information. - * apic_verbosity is defined in apic.c + * Define the default level of output to be very little This can be turned + * up by using apic=verbose for more information and apic=debug for _lots_ + * of information. apic_verbosity is defined in apic.c */ -#define apic_printk(v, s, a...) do { \ - if ((v) <= apic_verbosity) \ - printk(s, ##a); \ - } while (0) - +#define apic_printk(v, s, a...) \ +do { \ + if ((v) <= apic_verbosity) \ + printk(s, ##a); \ +} while (0) + +#define apic_pr_verbose(s, a...) apic_printk(APIC_VERBOSE, KERN_INFO s, ##a) +#define apic_pr_debug(s, a...) apic_printk(APIC_DEBUG, KERN_DEBUG s, ##a) +#define apic_pr_debug_cont(s, a...) apic_printk(APIC_DEBUG, KERN_CONT s, ##a) +/* Unconditional debug prints for code which is guarded by apic_verbosity already */ +#define apic_dbg(s, a...) printk(KERN_DEBUG s, ##a) #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) -extern void generic_apic_probe(void); +extern void x86_32_probe_apic(void); #else -static inline void generic_apic_probe(void) -{ -} +static inline void x86_32_probe_apic(void) { } #endif +extern u32 cpuid_to_apicid[]; + +#define CPU_ACPIID_INVALID U32_MAX + #ifdef CONFIG_X86_LOCAL_APIC -extern unsigned int apic_verbosity; +extern int apic_verbosity; extern int local_apic_timer_c2_ok; -extern int disable_apic; -extern unsigned int lapic_timer_frequency; +extern bool apic_is_disabled; +extern unsigned int lapic_timer_period; -#ifdef CONFIG_SMP -extern void __inquire_remote_apic(int apicid); -#else /* CONFIG_SMP */ -static inline void __inquire_remote_apic(int apicid) -{ -} -#endif /* CONFIG_SMP */ - -static inline void default_inquire_remote_apic(int apicid) -{ - if (apic_verbosity >= APIC_DEBUG) - __inquire_remote_apic(apicid); -} +extern enum apic_intr_mode_id apic_intr_mode; +enum apic_intr_mode_id { + APIC_PIC, + APIC_VIRTUAL_WIRE, + APIC_VIRTUAL_WIRE_NO_CONFIG, + APIC_SYMMETRIC_IO, + APIC_SYMMETRIC_IO_NO_ROUTING +}; /* * With 82489DX we can't rely on apic feature bit @@ -75,7 +84,7 @@ static inline void default_inquire_remote_apic(int apicid) */ static inline bool apic_from_smp_config(void) { - return smp_found_config && !disable_apic; + return smp_found_config && !apic_is_disabled; } /* @@ -85,169 +94,65 @@ static inline bool apic_from_smp_config(void) #include <asm/paravirt.h> #endif -#ifdef CONFIG_X86_64 -extern int is_vsmp_box(void); -#else -static inline int is_vsmp_box(void) -{ - return 0; -} -#endif -extern void xapic_wait_icr_idle(void); -extern u32 safe_xapic_wait_icr_idle(void); -extern void xapic_icr_write(u32, u32); -extern int setup_profiling_timer(unsigned int); - static inline void native_apic_mem_write(u32 reg, u32 v) { volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); - alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, - ASM_OUTPUT2("=r" (v), "=m" (*addr)), - ASM_OUTPUT2("0" (v), "m" (*addr))); + alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP, + ASM_OUTPUT("=r" (v), "=m" (*addr)), + ASM_INPUT("0" (v), "m" (*addr))); } static inline u32 native_apic_mem_read(u32 reg) { - return *((volatile u32 *)(APIC_BASE + reg)); + return readl((void __iomem *)(APIC_BASE + reg)); } -extern void native_apic_wait_icr_idle(void); -extern u32 native_safe_apic_wait_icr_idle(void); -extern void native_apic_icr_write(u32 low, u32 id); -extern u64 native_apic_icr_read(void); - -extern int x2apic_mode; - -#ifdef CONFIG_X86_X2APIC -/* - * Make previous memory operations globally visible before - * sending the IPI through x2apic wrmsr. We need a serializing instruction or - * mfence for this. - */ -static inline void x2apic_wrmsr_fence(void) +static inline void native_apic_mem_eoi(void) { - asm volatile("mfence" : : : "memory"); + native_apic_mem_write(APIC_EOI, APIC_EOI_ACK); } -static inline void native_apic_msr_write(u32 reg, u32 v) -{ - if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || - reg == APIC_LVR) - return; - - wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); -} - -static inline void native_apic_msr_eoi_write(u32 reg, u32 v) -{ - wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); -} - -static inline u32 native_apic_msr_read(u32 reg) -{ - u64 msr; - - if (reg == APIC_DFR) - return -1; - - rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); - return (u32)msr; -} - -static inline void native_x2apic_wait_icr_idle(void) -{ - /* no need to wait for icr idle in x2apic */ - return; -} - -static inline u32 native_safe_x2apic_wait_icr_idle(void) -{ - /* no need to wait for icr idle in x2apic */ - return 0; -} - -static inline void native_x2apic_icr_write(u32 low, u32 id) -{ - wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); -} - -static inline u64 native_x2apic_icr_read(void) -{ - unsigned long val; - - rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); - return val; -} +extern void native_apic_icr_write(u32 low, u32 id); +extern u64 native_apic_icr_read(void); -extern int x2apic_phys; -extern int x2apic_preenabled; -extern void check_x2apic(void); -extern void enable_x2apic(void); -extern void x2apic_icr_write(u32 low, u32 id); -static inline int x2apic_enabled(void) +static inline bool apic_is_x2apic_enabled(void) { u64 msr; - if (!cpu_has_x2apic) - return 0; - - rdmsrl(MSR_IA32_APICBASE, msr); - if (msr & X2APIC_ENABLE) - return 1; - return 0; + if (rdmsrq_safe(MSR_IA32_APICBASE, &msr)) + return false; + return msr & X2APIC_ENABLE; } -#define x2apic_supported() (cpu_has_x2apic) -static inline void x2apic_force_phys(void) -{ - x2apic_phys = 1; -} -#else -static inline void disable_x2apic(void) -{ -} -static inline void check_x2apic(void) -{ -} -static inline void enable_x2apic(void) -{ -} -static inline int x2apic_enabled(void) -{ - return 0; -} -static inline void x2apic_force_phys(void) -{ -} - -#define nox2apic 0 -#define x2apic_preenabled 0 -#define x2apic_supported() 0 -#endif - extern void enable_IR_x2apic(void); -extern int get_physical_broadcast(void); - extern int lapic_get_maxlvt(void); extern void clear_local_APIC(void); -extern void connect_bsp_APIC(void); extern void disconnect_bsp_APIC(int virt_wire_setup); extern void disable_local_APIC(void); +extern void apic_soft_disable(void); extern void lapic_shutdown(void); -extern int verify_local_APIC(void); extern void sync_Arb_IDs(void); extern void init_bsp_APIC(void); -extern void setup_local_APIC(void); -extern void end_local_APIC_setup(void); -extern void bsp_end_local_APIC_setup(void); +extern void apic_intr_mode_select(void); +extern void apic_intr_mode_init(void); extern void init_apic_mappings(void); void register_lapic_address(unsigned long address); extern void setup_boot_APIC_clock(void); extern void setup_secondary_APIC_clock(void); -extern int APIC_init_uniprocessor(void); -extern int apic_force_enable(unsigned long addr); +extern void lapic_update_tsc_freq(void); + +#ifdef CONFIG_X86_64 +static inline bool apic_force_enable(unsigned long addr) +{ + return false; +} +#else +extern bool apic_force_enable(unsigned long addr); +#endif + +extern void apic_ap_setup(void); /* * On 32bit this is mach-xxx local @@ -262,6 +167,22 @@ static inline int apic_is_clustered_box(void) #endif extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); +extern void lapic_assign_system_vectors(void); +extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); +extern void lapic_update_legacy_vectors(void); +extern void lapic_online(void); +extern void lapic_offline(void); +extern bool apic_needs_pit(void); + +extern void apic_send_IPI_allbutself(unsigned int vector); + +extern void topology_register_apic(u32 apic_id, u32 acpi_id, bool present); +extern void topology_register_boot_apic(u32 apic_id); +extern int topology_hotplug_apic(u32 apic_id, u32 acpi_id); +extern void topology_hotunplug_apic(unsigned int cpu); +extern void topology_apply_cmdline_limits_early(void); +extern void topology_init_possible_cpus(void); +extern void topology_reset_possible_cpus_up(void); #else /* !CONFIG_X86_LOCAL_APIC */ static inline void lapic_shutdown(void) { } @@ -270,17 +191,79 @@ static inline void init_apic_mappings(void) { } static inline void disable_local_APIC(void) { } # define setup_boot_APIC_clock x86_init_noop # define setup_secondary_APIC_clock x86_init_noop +static inline void lapic_update_tsc_freq(void) { } +static inline void init_bsp_APIC(void) { } +static inline void apic_intr_mode_select(void) { } +static inline void apic_intr_mode_init(void) { } +static inline void lapic_assign_system_vectors(void) { } +static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } +static inline bool apic_needs_pit(void) { return true; } +static inline void topology_apply_cmdline_limits_early(void) { } +static inline void topology_init_possible_cpus(void) { } #endif /* !CONFIG_X86_LOCAL_APIC */ -#ifdef CONFIG_X86_64 -#define SET_APIC_ID(x) (apic->set_apic_id(x)) -#else +#ifdef CONFIG_X86_X2APIC +static inline void native_apic_msr_write(u32 reg, u32 v) +{ + if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || + reg == APIC_LVR) + return; -#endif + wrmsrq(APIC_BASE_MSR + (reg >> 4), v); +} + +static inline void native_apic_msr_eoi(void) +{ + native_wrmsrq(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK); +} + +static inline u32 native_apic_msr_read(u32 reg) +{ + u64 msr; + + if (reg == APIC_DFR) + return -1; + + rdmsrq(APIC_BASE_MSR + (reg >> 4), msr); + return (u32)msr; +} + +static inline void native_x2apic_icr_write(u32 low, u32 id) +{ + wrmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); +} + +static inline u64 native_x2apic_icr_read(void) +{ + unsigned long val; + + rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), val); + return val; +} + +extern int x2apic_mode; +extern int x2apic_phys; +extern void __init x2apic_set_max_apicid(u32 apicid); +extern void x2apic_setup(void); +static inline int x2apic_enabled(void) +{ + return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); +} + +#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) +#else /* !CONFIG_X86_X2APIC */ +static inline void x2apic_setup(void) { } +static inline int x2apic_enabled(void) { return 0; } +static inline u32 native_apic_msr_read(u32 reg) { BUG(); } +#define x2apic_mode (0) +#define x2apic_supported() (0) +#endif /* !CONFIG_X86_X2APIC */ +extern void __init check_x2apic(void); + +struct irq_data; /* * Copyright 2004 James Cleverdon, IBM. - * Subject to the GNU Public License, v.2 * * Generic APIC sub-arch data struct. * @@ -289,109 +272,73 @@ static inline void disable_local_APIC(void) { } * James Cleverdon. */ struct apic { - char *name; - - int (*probe)(void); - int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); - int (*apic_id_valid)(int apicid); - int (*apic_id_registered)(void); - - u32 irq_delivery_mode; - u32 irq_dest_mode; - - const struct cpumask *(*target_cpus)(void); - - int disable_esr; - - int dest_logical; - unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); - unsigned long (*check_apicid_present)(int apicid); - - void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, - const struct cpumask *mask); - void (*init_apic_ldr)(void); - - void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); - - void (*setup_apic_routing)(void); - int (*multi_timer_check)(int apic, int irq); - int (*cpu_present_to_apicid)(int mps_cpu); - void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); - void (*setup_portio_remap)(void); - int (*check_phys_apicid_present)(int phys_apicid); - void (*enable_apic_mode)(void); - int (*phys_pkg_id)(int cpuid_apic, int index_msb); - - /* - * When one of the next two hooks returns 1 the apic - * is switched to this. Essentially they are additional - * probe functions: - */ - int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); - - unsigned int (*get_apic_id)(unsigned long x); - unsigned long (*set_apic_id)(unsigned int id); - unsigned long apic_id_mask; - - int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, - const struct cpumask *andmask, - unsigned int *apicid); - - /* ipi */ - void (*send_IPI_mask)(const struct cpumask *mask, int vector); - void (*send_IPI_mask_allbutself)(const struct cpumask *mask, - int vector); - void (*send_IPI_allbutself)(int vector); - void (*send_IPI_all)(int vector); - void (*send_IPI_self)(int vector); + /* Hotpath functions first */ + void (*eoi)(void); + void (*native_eoi)(void); + void (*write)(u32 reg, u32 v); + u32 (*read)(u32 reg); + + /* IPI related functions */ + void (*wait_icr_idle)(void); + u32 (*safe_wait_icr_idle)(void); + + void (*send_IPI)(int cpu, int vector); + void (*send_IPI_mask)(const struct cpumask *mask, int vector); + void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); + void (*send_IPI_allbutself)(int vector); + void (*send_IPI_all)(int vector); + void (*send_IPI_self)(int vector); + + u32 disable_esr : 1, + dest_mode_logical : 1, + x2apic_set_max_apicid : 1, + nmi_to_offline_cpu : 1; + + u32 (*calc_dest_apicid)(unsigned int cpu); + + /* ICR related functions */ + u64 (*icr_read)(void); + void (*icr_write)(u32 low, u32 high); + + /* The limit of the APIC ID space. */ + u32 max_apic_id; + + /* Probe, setup and smpboot functions */ + int (*probe)(void); + void (*setup)(void); + void (*teardown)(void); + int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); + + void (*init_apic_ldr)(void); + u32 (*cpu_present_to_apicid)(int mps_cpu); + + u32 (*get_apic_id)(u32 id); /* wakeup_secondary_cpu */ - int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); - - int trampoline_phys_low; - int trampoline_phys_high; - - void (*wait_for_init_deassert)(atomic_t *deassert); - void (*smp_callin_clear_local_apic)(void); - void (*inquire_remote_apic)(int apicid); - - /* apic ops */ - u32 (*read)(u32 reg); - void (*write)(u32 reg, u32 v); - /* - * ->eoi_write() has the same signature as ->write(). - * - * Drivers can support both ->eoi_write() and ->write() by passing the same - * callback value. Kernel can override ->eoi_write() and fall back - * on write for EOI. - */ - void (*eoi_write)(u32 reg, u32 v); - u64 (*icr_read)(void); - void (*icr_write)(u32 low, u32 high); - void (*wait_icr_idle)(void); - u32 (*safe_wait_icr_idle)(void); - -#ifdef CONFIG_X86_32 - /* - * Called very early during boot from get_smp_config(). It should - * return the logical apicid. x86_[bios]_cpu_to_apicid is - * initialized before this function is called. - * - * If logical apicid can't be determined that early, the function - * may return BAD_APICID. Logical apicid will be configured after - * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity - * won't be applied properly during early boot in this case. - */ - int (*x86_32_early_logical_apicid)(int cpu); - - /* - * Optional method called from setup_local_APIC() after logical - * apicid is guaranteed to be known to initialize apicid -> node - * mapping if NUMA initialization hasn't done so already. Don't - * add new users. - */ - int (*x86_32_numa_cpu_node)(int cpu); -#endif + int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip, unsigned int cpu); + /* wakeup secondary CPU using 64-bit wakeup point */ + int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip, unsigned int cpu); + + void (*update_vector)(unsigned int cpu, unsigned int vector, bool set); + + char *name; +}; + +struct apic_override { + void (*eoi)(void); + void (*native_eoi)(void); + void (*write)(u32 reg, u32 v); + u32 (*read)(u32 reg); + void (*send_IPI)(int cpu, int vector); + void (*send_IPI_mask)(const struct cpumask *mask, int vector); + void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); + void (*send_IPI_allbutself)(int vector); + void (*send_IPI_all)(int vector); + void (*send_IPI_self)(int vector); + u64 (*icr_read)(void); + void (*icr_write)(u32 low, u32 high); + int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip, unsigned int cpu); + int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip, unsigned int cpu); }; /* @@ -405,19 +352,11 @@ extern struct apic *apic; * APIC drivers are probed based on how they are listed in the .apicdrivers * section. So the order is important and enforced by the ordering * of different apic driver files in the Makefile. - * - * For the files having two apic drivers, we use apic_drivers() - * to enforce the order with in them. */ #define apic_driver(sym) \ static const struct apic *__apicdrivers_##sym __used \ __aligned(sizeof(struct apic *)) \ - __section(.apicdrivers) = { &sym } - -#define apic_drivers(sym1, sym2) \ - static struct apic *__apicdrivers_##sym1##sym2[2] __used \ - __aligned(sizeof(struct apic *)) \ - __section(.apicdrivers) = { &sym1, &sym2 } + __section(".apicdrivers") = { &sym } extern struct apic *__apicdrivers[], *__apicdrivers_end[]; @@ -425,294 +364,268 @@ extern struct apic *__apicdrivers[], *__apicdrivers_end[]; * APIC functionality to boot other CPUs - only used on SMP: */ #ifdef CONFIG_SMP -extern atomic_t init_deasserted; -extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); +extern int lapic_can_unplug_cpu(void); #endif #ifdef CONFIG_X86_LOCAL_APIC +extern struct apic_override __x86_apic_override; -static inline u32 apic_read(u32 reg) -{ - return apic->read(reg); +void __init apic_setup_apic_calls(void); +void __init apic_install_driver(struct apic *driver); + +#define apic_update_callback(_callback, _fn) { \ + __x86_apic_override._callback = _fn; \ + apic->_callback = _fn; \ + static_call_update(apic_call_##_callback, _fn); \ + pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \ } -static inline void apic_write(u32 reg, u32 val) +#define DECLARE_APIC_CALL(__cb) \ + DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb) + +DECLARE_APIC_CALL(eoi); +DECLARE_APIC_CALL(native_eoi); +DECLARE_APIC_CALL(icr_read); +DECLARE_APIC_CALL(icr_write); +DECLARE_APIC_CALL(read); +DECLARE_APIC_CALL(send_IPI); +DECLARE_APIC_CALL(send_IPI_mask); +DECLARE_APIC_CALL(send_IPI_mask_allbutself); +DECLARE_APIC_CALL(send_IPI_allbutself); +DECLARE_APIC_CALL(send_IPI_all); +DECLARE_APIC_CALL(send_IPI_self); +DECLARE_APIC_CALL(wait_icr_idle); +DECLARE_APIC_CALL(wakeup_secondary_cpu); +DECLARE_APIC_CALL(wakeup_secondary_cpu_64); +DECLARE_APIC_CALL(write); + +static __always_inline u32 apic_read(u32 reg) { - apic->write(reg, val); + return static_call(apic_call_read)(reg); } -static inline void apic_eoi(void) +static __always_inline void apic_write(u32 reg, u32 val) { - apic->eoi_write(APIC_EOI, APIC_EOI_ACK); + static_call(apic_call_write)(reg, val); } -static inline u64 apic_icr_read(void) +static __always_inline void apic_eoi(void) { - return apic->icr_read(); + static_call(apic_call_eoi)(); } -static inline void apic_icr_write(u32 low, u32 high) +static __always_inline void apic_native_eoi(void) { - apic->icr_write(low, high); + static_call(apic_call_native_eoi)(); } -static inline void apic_wait_icr_idle(void) +static __always_inline u64 apic_icr_read(void) { - apic->wait_icr_idle(); + return static_call(apic_call_icr_read)(); } -static inline u32 safe_apic_wait_icr_idle(void) +static __always_inline void apic_icr_write(u32 low, u32 high) { - return apic->safe_wait_icr_idle(); + static_call(apic_call_icr_write)(low, high); } -extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); - -#else /* CONFIG_X86_LOCAL_APIC */ - -static inline u32 apic_read(u32 reg) { return 0; } -static inline void apic_write(u32 reg, u32 val) { } -static inline void apic_eoi(void) { } -static inline u64 apic_icr_read(void) { return 0; } -static inline void apic_icr_write(u32 low, u32 high) { } -static inline void apic_wait_icr_idle(void) { } -static inline u32 safe_apic_wait_icr_idle(void) { return 0; } -static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} - -#endif /* CONFIG_X86_LOCAL_APIC */ - -static inline void ack_APIC_irq(void) +static __always_inline void __apic_send_IPI(int cpu, int vector) { - /* - * ack_APIC_irq() actually gets compiled as a single instruction - * ... yummie. - */ - apic_eoi(); + static_call(apic_call_send_IPI)(cpu, vector); } -static inline unsigned default_get_apic_id(unsigned long x) +static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector) { - unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); - - if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) - return (x >> 24) & 0xFF; - else - return (x >> 24) & 0x0F; + static_call_mod(apic_call_send_IPI_mask)(mask, vector); } -/* - * Warm reset vector default position: - */ -#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 -#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 - -#ifdef CONFIG_X86_64 -extern int default_acpi_madt_oem_check(char *, char *); - -extern void apic_send_IPI_self(int vector); - -DECLARE_PER_CPU(int, x2apic_extra_bits); - -extern int default_cpu_present_to_apicid(int mps_cpu); -extern int default_check_phys_apicid_present(int phys_apicid); -#endif - -static inline void default_wait_for_init_deassert(atomic_t *deassert) +static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) { - while (!atomic_read(deassert)) - cpu_relax(); - return; + static_call(apic_call_send_IPI_mask_allbutself)(mask, vector); } -extern void generic_bigsmp_probe(void); - - -#ifdef CONFIG_X86_LOCAL_APIC - -#include <asm/smp.h> - -#define APIC_DFR_VALUE (APIC_DFR_FLAT) - -static inline const struct cpumask *default_target_cpus(void) +static __always_inline void __apic_send_IPI_allbutself(int vector) { -#ifdef CONFIG_SMP - return cpu_online_mask; -#else - return cpumask_of(0); -#endif + static_call(apic_call_send_IPI_allbutself)(vector); } -static inline const struct cpumask *online_target_cpus(void) +static __always_inline void __apic_send_IPI_all(int vector) { - return cpu_online_mask; + static_call(apic_call_send_IPI_all)(vector); } -DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); - +static __always_inline void __apic_send_IPI_self(int vector) +{ + static_call_mod(apic_call_send_IPI_self)(vector); +} -static inline unsigned int read_apic_id(void) +static __always_inline void apic_wait_icr_idle(void) { - unsigned int reg; + static_call_cond(apic_call_wait_icr_idle)(); +} - reg = apic_read(APIC_ID); +static __always_inline u32 safe_apic_wait_icr_idle(void) +{ + return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; +} - return apic->get_apic_id(reg); +static __always_inline bool apic_id_valid(u32 apic_id) +{ + return apic_id <= apic->max_apic_id; } -static inline int default_apic_id_valid(int apicid) +static __always_inline void apic_update_vector(unsigned int cpu, unsigned int vector, bool set) { - return (apicid < 255); + if (apic->update_vector) + apic->update_vector(cpu, vector, set); } -extern void default_setup_apic_routing(void); +#else /* CONFIG_X86_LOCAL_APIC */ -extern struct apic apic_noop; +static inline u32 apic_read(u32 reg) { return 0; } +static inline void apic_write(u32 reg, u32 val) { } +static inline void apic_eoi(void) { } +static inline u64 apic_icr_read(void) { return 0; } +static inline void apic_icr_write(u32 low, u32 high) { } +static inline void apic_wait_icr_idle(void) { } +static inline u32 safe_apic_wait_icr_idle(void) { return 0; } +static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } +static inline void apic_setup_apic_calls(void) { } +static inline void apic_update_vector(unsigned int cpu, unsigned int vector, bool set) { } -#ifdef CONFIG_X86_32 +#define apic_update_callback(_callback, _fn) do { } while (0) -static inline int noop_x86_32_early_logical_apicid(int cpu) -{ - return BAD_APICID; -} +#endif /* CONFIG_X86_LOCAL_APIC */ -/* - * Set up the logical destination ID. - * - * Intel recommends to set DFR, LDR and TPR before enabling - * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel - * document number 292116). So here it goes... - */ -extern void default_init_apic_ldr(void); +extern void apic_ack_irq(struct irq_data *data); + +#define APIC_VECTOR_TO_BIT_NUMBER(v) ((unsigned int)(v) % 32) +#define APIC_VECTOR_TO_REG_OFFSET(v) ((unsigned int)(v) / 32 * 0x10) -static inline int default_apic_id_registered(void) +static inline bool lapic_vector_set_in_irr(unsigned int vector) { - return physid_isset(read_apic_id(), phys_cpu_present_map); + u32 irr = apic_read(APIC_IRR + APIC_VECTOR_TO_REG_OFFSET(vector)); + + return !!(irr & (1U << APIC_VECTOR_TO_BIT_NUMBER(vector))); } -static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) +static inline bool is_vector_pending(unsigned int vector) { - return cpuid_apic >> index_msb; + return lapic_vector_set_in_irr(vector) || pi_pending_this_cpu(vector); } -#endif +#define MAX_APIC_VECTOR 256 +#define APIC_VECTORS_PER_REG 32 -static inline int -flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, - const struct cpumask *andmask, - unsigned int *apicid) -{ - unsigned long cpu_mask = cpumask_bits(cpumask)[0] & - cpumask_bits(andmask)[0] & - cpumask_bits(cpu_online_mask)[0] & - APIC_ALL_CPUS; - - if (likely(cpu_mask)) { - *apicid = (unsigned int)cpu_mask; - return 0; - } else { - return -EINVAL; - } -} +/* + * Vector states are maintained by APIC in 32-bit registers that are + * 16 bytes aligned. The status of each vector is kept in a single + * bit. + */ +static inline int apic_find_highest_vector(void *bitmap) +{ + int vec; + u32 *reg; -extern int -default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, - const struct cpumask *andmask, - unsigned int *apicid); + for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; vec >= 0; vec -= APIC_VECTORS_PER_REG) { + reg = bitmap + APIC_VECTOR_TO_REG_OFFSET(vec); + if (*reg) + return __fls(*reg) + vec; + } -static inline void -flat_vector_allocation_domain(int cpu, struct cpumask *retmask, - const struct cpumask *mask) -{ - /* Careful. Some cpus do not strictly honor the set of cpus - * specified in the interrupt destination when using lowest - * priority interrupt delivery mode. - * - * In particular there was a hyperthreading cpu observed to - * deliver interrupts to the wrong hyperthread when only one - * hyperthread was specified in the interrupt desitination. - */ - cpumask_clear(retmask); - cpumask_bits(retmask)[0] = APIC_ALL_CPUS; + return -1; } -static inline void -default_vector_allocation_domain(int cpu, struct cpumask *retmask, - const struct cpumask *mask) +static inline u32 apic_get_reg(void *regs, int reg) { - cpumask_copy(retmask, cpumask_of(cpu)); + return *((u32 *) (regs + reg)); } -static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) +static inline void apic_set_reg(void *regs, int reg, u32 val) { - return physid_isset(apicid, *map); + *((u32 *) (regs + reg)) = val; } -static inline unsigned long default_check_apicid_present(int bit) +static __always_inline u64 apic_get_reg64(void *regs, int reg) { - return physid_isset(bit, phys_cpu_present_map); + BUILD_BUG_ON(reg != APIC_ICR); + return *((u64 *) (regs + reg)); } -static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) +static __always_inline void apic_set_reg64(void *regs, int reg, u64 val) { - *retmap = *phys_map; + BUILD_BUG_ON(reg != APIC_ICR); + *((u64 *) (regs + reg)) = val; } -static inline int __default_cpu_present_to_apicid(int mps_cpu) +static inline void apic_clear_vector(int vec, void *bitmap) { - if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) - return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); - else - return BAD_APICID; + clear_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec)); } -static inline int -__default_check_phys_apicid_present(int phys_apicid) +static inline void apic_set_vector(int vec, void *bitmap) { - return physid_isset(phys_apicid, phys_cpu_present_map); + set_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec)); } -#ifdef CONFIG_X86_32 -static inline int default_cpu_present_to_apicid(int mps_cpu) +static inline int apic_test_vector(int vec, void *bitmap) { - return __default_cpu_present_to_apicid(mps_cpu); + return test_bit(APIC_VECTOR_TO_BIT_NUMBER(vec), bitmap + APIC_VECTOR_TO_REG_OFFSET(vec)); } -static inline int -default_check_phys_apicid_present(int phys_apicid) +/* + * Warm reset vector position: + */ +#define TRAMPOLINE_PHYS_LOW 0x467 +#define TRAMPOLINE_PHYS_HIGH 0x469 + +#ifdef CONFIG_X86_LOCAL_APIC + +#include <asm/smp.h> + +extern struct apic apic_noop; + +static inline u32 read_apic_id(void) { - return __default_check_phys_apicid_present(phys_apicid); + u32 reg = apic_read(APIC_ID); + + return apic->get_apic_id(reg); } + +#ifdef CONFIG_X86_64 +typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); +extern int default_acpi_madt_oem_check(char *, char *); +extern void x86_64_probe_apic(void); #else -extern int default_cpu_present_to_apicid(int mps_cpu); -extern int default_check_phys_apicid_present(int phys_apicid); +static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } +static inline void x86_64_probe_apic(void) { } #endif -#endif /* CONFIG_X86_LOCAL_APIC */ -extern void irq_enter(void); -extern void irq_exit(void); +extern u32 apic_default_calc_apicid(unsigned int cpu); +extern u32 apic_flat_calc_apicid(unsigned int cpu); -static inline void entering_irq(void) -{ - irq_enter(); - exit_idle(); -} +extern u32 default_cpu_present_to_apicid(int mps_cpu); -static inline void entering_ack_irq(void) -{ - ack_APIC_irq(); - entering_irq(); -} +void apic_send_nmi_to_offline_cpu(unsigned int cpu); -static inline void exiting_irq(void) -{ - irq_exit(); -} +#else /* CONFIG_X86_LOCAL_APIC */ -static inline void exiting_ack_irq(void) -{ - irq_exit(); - /* Ack only at the end to avoid potential reentry */ - ack_APIC_irq(); -} +static inline u32 read_apic_id(void) { return 0; } + +#endif /* !CONFIG_X86_LOCAL_APIC */ + +#ifdef CONFIG_SMP +void apic_smt_update(void); +#else +static inline void apic_smt_update(void) { } +#endif + +struct msi_msg; +struct irq_cfg; + +extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, + bool dmar); + +extern void ioapic_zap_locks(void); #endif /* _ASM_X86_APIC_H */ |