diff options
Diffstat (limited to 'arch/xtensa/include/asm/cacheasm.h')
| -rw-r--r-- | arch/xtensa/include/asm/cacheasm.h | 104 |
1 files changed, 71 insertions, 33 deletions
diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h index 60e18773ecb8..34545ecfdd6b 100644 --- a/arch/xtensa/include/asm/cacheasm.h +++ b/arch/xtensa/include/asm/cacheasm.h @@ -31,16 +31,32 @@ * */ - .macro __loop_cache_all ar at insn size line_width - movi \ar, 0 + .macro __loop_cache_unroll ar at insn size line_width max_immed + + .if (1 << (\line_width)) > (\max_immed) + .set _reps, 1 + .elseif (2 << (\line_width)) > (\max_immed) + .set _reps, 2 + .else + .set _reps, 4 + .endif + + __loopi \ar, \at, \size, (_reps << (\line_width)) + .set _index, 0 + .rep _reps + \insn \ar, _index << (\line_width) + .set _index, _index + 1 + .endr + __endla \ar, \at, _reps << (\line_width) + + .endm + + + .macro __loop_cache_all ar at insn size line_width max_immed - __loopi \ar, \at, \size, (4 << (\line_width)) - \insn \ar, 0 << (\line_width) - \insn \ar, 1 << (\line_width) - \insn \ar, 2 << (\line_width) - \insn \ar, 3 << (\line_width) - __endla \ar, \at, 4 << (\line_width) + movi \ar, 0 + __loop_cache_unroll \ar, \at, \insn, \size, \line_width, \max_immed .endm @@ -57,63 +73,69 @@ .endm - .macro __loop_cache_page ar at insn line_width + .macro __loop_cache_page ar at insn line_width max_immed - __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width) - \insn \ar, 0 << (\line_width) - \insn \ar, 1 << (\line_width) - \insn \ar, 2 << (\line_width) - \insn \ar, 3 << (\line_width) - __endla \ar, \at, 4 << (\line_width) + __loop_cache_unroll \ar, \at, \insn, PAGE_SIZE, \line_width, \max_immed .endm -#if XCHAL_DCACHE_LINE_LOCKABLE - .macro ___unlock_dcache_all ar at - __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH +#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE + __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \ + XCHAL_DCACHE_LINEWIDTH 240 +#endif .endm -#endif - -#if XCHAL_ICACHE_LINE_LOCKABLE .macro ___unlock_icache_all ar at - __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH +#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE + __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \ + XCHAL_ICACHE_LINEWIDTH 240 +#endif .endm -#endif + .macro ___flush_invalidate_dcache_all ar at - __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH +#if XCHAL_DCACHE_SIZE + __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \ + XCHAL_DCACHE_LINEWIDTH 240 +#endif .endm .macro ___flush_dcache_all ar at - __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH +#if XCHAL_DCACHE_SIZE + __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \ + XCHAL_DCACHE_LINEWIDTH 240 +#endif .endm .macro ___invalidate_dcache_all ar at - __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ - XCHAL_DCACHE_LINEWIDTH +#if XCHAL_DCACHE_SIZE + __loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \ + XCHAL_DCACHE_LINEWIDTH 1020 +#endif .endm .macro ___invalidate_icache_all ar at - __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ - XCHAL_ICACHE_LINEWIDTH +#if XCHAL_ICACHE_SIZE + __loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \ + XCHAL_ICACHE_LINEWIDTH 1020 +#endif .endm @@ -121,28 +143,36 @@ .macro ___flush_invalidate_dcache_range ar as at +#if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___flush_dcache_range ar as at +#if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___invalidate_dcache_range ar as at +#if XCHAL_DCACHE_SIZE __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH +#endif .endm .macro ___invalidate_icache_range ar as at +#if XCHAL_ICACHE_SIZE __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH +#endif .endm @@ -150,27 +180,35 @@ .macro ___flush_invalidate_dcache_page ar as - __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH +#if XCHAL_DCACHE_SIZE + __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020 +#endif .endm .macro ___flush_dcache_page ar as - __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH +#if XCHAL_DCACHE_SIZE + __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020 +#endif .endm .macro ___invalidate_dcache_page ar as - __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH +#if XCHAL_DCACHE_SIZE + __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020 +#endif .endm .macro ___invalidate_icache_page ar as - __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH +#if XCHAL_ICACHE_SIZE + __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020 +#endif .endm |