diff options
Diffstat (limited to 'arch/xtensa/mm/misc.S')
| -rw-r--r-- | arch/xtensa/mm/misc.S | 115 |
1 files changed, 47 insertions, 68 deletions
diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S index 11a01c3e9cea..ec36f73c4765 100644 --- a/arch/xtensa/mm/misc.S +++ b/arch/xtensa/mm/misc.S @@ -14,8 +14,8 @@ #include <linux/linkage.h> +#include <linux/pgtable.h> #include <asm/page.h> -#include <asm/pgtable.h> #include <asm/asmmacro.h> #include <asm/cacheasm.h> #include <asm/tlbflush.h> @@ -30,7 +30,7 @@ ENTRY(clear_page) - entry a1, 16 + abi_entry_default movi a3, 0 __loopi a2, a7, PAGE_SIZE, 32 @@ -44,9 +44,10 @@ ENTRY(clear_page) s32i a3, a2, 28 __endla a2, a7, 32 - retw + abi_ret_default ENDPROC(clear_page) +EXPORT_SYMBOL(clear_page) /* * copy_page and copy_user_page are the same for non-cache-aliased configs. @@ -57,7 +58,7 @@ ENDPROC(clear_page) ENTRY(copy_page) - entry a1, 16 + abi_entry_default __loopi a2, a4, PAGE_SIZE, 32 @@ -86,9 +87,10 @@ ENTRY(copy_page) __endl a2, a4 - retw + abi_ret_default ENDPROC(copy_page) +EXPORT_SYMBOL(copy_page) #ifdef CONFIG_MMU /* @@ -116,22 +118,15 @@ ENTRY(__tlbtemp_mapping_start) ENTRY(clear_page_alias) - entry a1, 32 - - /* Skip setting up a temporary DTLB if not aliased low page. */ + abi_entry_default movi a5, PAGE_OFFSET - movi a6, 0 - beqz a3, 1f - - /* Setup a temporary DTLB for the addr. */ - addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) mov a4, a2 wdtlb a6, a2 dsync -1: movi a3, 0 + movi a3, 0 __loopi a2, a7, PAGE_SIZE, 32 s32i a3, a2, 0 s32i a3, a2, 4 @@ -143,15 +138,12 @@ ENTRY(clear_page_alias) s32i a3, a2, 28 __endla a2, a7, 32 - bnez a6, 1f - retw - - /* We need to invalidate the temporary idtlb entry, if any. */ + /* We need to invalidate the temporary dtlb entry. */ -1: idtlb a4 + idtlb a4 dsync - retw + abi_ret_default ENDPROC(clear_page_alias) @@ -164,13 +156,7 @@ ENDPROC(clear_page_alias) ENTRY(copy_page_alias) - entry a1, 32 - - /* Skip setting up a temporary DTLB for destination if not aliased. */ - - movi a6, 0 - movi a7, 0 - beqz a4, 1f + abi_entry_default /* Setup a temporary DTLB for destination. */ @@ -178,10 +164,6 @@ ENTRY(copy_page_alias) wdtlb a6, a2 dsync - /* Skip setting up a temporary DTLB for source if not aliased. */ - -1: beqz a5, 1f - /* Setup a temporary DTLB for source. */ addi a7, a5, PAGE_KERNEL @@ -219,21 +201,15 @@ ENTRY(copy_page_alias) /* We need to invalidate any temporary mapping! */ - bnez a6, 1f - bnez a7, 2f - retw - -1: addi a2, a2, -PAGE_SIZE + addi a2, a2, -PAGE_SIZE idtlb a2 dsync - bnez a7, 2f - retw -2: addi a3, a3, -PAGE_SIZE+1 + addi a3, a3, -PAGE_SIZE+1 idtlb a3 dsync - retw + abi_ret_default ENDPROC(copy_page_alias) @@ -248,7 +224,7 @@ ENDPROC(copy_page_alias) ENTRY(__flush_invalidate_dcache_page_alias) - entry sp, 16 + abi_entry_default movi a7, 0 # required for exception handler addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) @@ -261,7 +237,7 @@ ENTRY(__flush_invalidate_dcache_page_alias) idtlb a4 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_page_alias) @@ -272,7 +248,7 @@ ENDPROC(__flush_invalidate_dcache_page_alias) ENTRY(__invalidate_dcache_page_alias) - entry sp, 16 + abi_entry_default movi a7, 0 # required for exception handler addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) @@ -285,7 +261,7 @@ ENTRY(__invalidate_dcache_page_alias) idtlb a4 dsync - retw + abi_ret_default ENDPROC(__invalidate_dcache_page_alias) #endif @@ -296,7 +272,7 @@ ENTRY(__tlbtemp_mapping_itlb) ENTRY(__invalidate_icache_page_alias) - entry sp, 16 + abi_entry_default addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE) mov a4, a2 @@ -307,7 +283,7 @@ ENTRY(__invalidate_icache_page_alias) iitlb a4 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_page_alias) @@ -325,12 +301,12 @@ ENTRY(__tlbtemp_mapping_end) ENTRY(__invalidate_icache_page) - entry sp, 16 + abi_entry_default ___invalidate_icache_page a2 a3 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_page) @@ -340,12 +316,12 @@ ENDPROC(__invalidate_icache_page) ENTRY(__invalidate_dcache_page) - entry sp, 16 + abi_entry_default ___invalidate_dcache_page a2 a3 dsync - retw + abi_ret_default ENDPROC(__invalidate_dcache_page) @@ -355,12 +331,12 @@ ENDPROC(__invalidate_dcache_page) ENTRY(__flush_invalidate_dcache_page) - entry sp, 16 + abi_entry_default ___flush_invalidate_dcache_page a2 a3 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_page) @@ -370,12 +346,12 @@ ENDPROC(__flush_invalidate_dcache_page) ENTRY(__flush_dcache_page) - entry sp, 16 + abi_entry_default ___flush_dcache_page a2 a3 dsync - retw + abi_ret_default ENDPROC(__flush_dcache_page) @@ -385,14 +361,15 @@ ENDPROC(__flush_dcache_page) ENTRY(__invalidate_icache_range) - entry sp, 16 + abi_entry_default ___invalidate_icache_range a2 a3 a4 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_range) +EXPORT_SYMBOL(__invalidate_icache_range) /* * void __flush_invalidate_dcache_range(ulong start, ulong size) @@ -400,12 +377,12 @@ ENDPROC(__invalidate_icache_range) ENTRY(__flush_invalidate_dcache_range) - entry sp, 16 + abi_entry_default ___flush_invalidate_dcache_range a2 a3 a4 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_range) @@ -415,14 +392,15 @@ ENDPROC(__flush_invalidate_dcache_range) ENTRY(__flush_dcache_range) - entry sp, 16 + abi_entry_default ___flush_dcache_range a2 a3 a4 dsync - retw + abi_ret_default ENDPROC(__flush_dcache_range) +EXPORT_SYMBOL(__flush_dcache_range) /* * void _invalidate_dcache_range(ulong start, ulong size) @@ -430,13 +408,14 @@ ENDPROC(__flush_dcache_range) ENTRY(__invalidate_dcache_range) - entry sp, 16 + abi_entry_default ___invalidate_dcache_range a2 a3 a4 - retw + abi_ret_default ENDPROC(__invalidate_dcache_range) +EXPORT_SYMBOL(__invalidate_dcache_range) /* * void _invalidate_icache_all(void) @@ -444,12 +423,12 @@ ENDPROC(__invalidate_dcache_range) ENTRY(__invalidate_icache_all) - entry sp, 16 + abi_entry_default ___invalidate_icache_all a2 a3 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_all) @@ -459,12 +438,12 @@ ENDPROC(__invalidate_icache_all) ENTRY(__flush_invalidate_dcache_all) - entry sp, 16 + abi_entry_default ___flush_invalidate_dcache_all a2 a3 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_all) @@ -474,11 +453,11 @@ ENDPROC(__flush_invalidate_dcache_all) ENTRY(__invalidate_dcache_all) - entry sp, 16 + abi_entry_default ___invalidate_dcache_all a2 a3 dsync - retw + abi_ret_default ENDPROC(__invalidate_dcache_all) |