diff options
Diffstat (limited to 'arch')
109 files changed, 856 insertions, 689 deletions
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index c475379199b1..8e9c98edc068 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -353,15 +353,15 @@ validate_group(struct perf_event *event) fake_pmu.used_mask = fake_used_mask; if (!validate_event(&fake_pmu, leader)) - return -ENOSPC; + return -EINVAL; list_for_each_entry(sibling, &leader->sibling_list, group_entry) { if (!validate_event(&fake_pmu, sibling)) - return -ENOSPC; + return -EINVAL; } if (!validate_event(&fake_pmu, event)) - return -ENOSPC; + return -EINVAL; return 0; } diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 66591fa53e05..ad930688358c 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -83,7 +83,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} * USB Device (Gadget) * -------------------------------------------------------------------- */ -#ifdef CONFIG_USB_GADGET_AT91 +#ifdef CONFIG_USB_AT91 static struct at91_udc_data udc_data; static struct resource udc_resources[] = { diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index b84a9f642f59..0d20677fbef0 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -195,9 +195,9 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), - CLKDEV_CON_DEV_ID("t3_clk", "atmel_tcb.1", &tc3_clk), - CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk), - CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk), + CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk), + CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), + CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), /* more usart lookup table for DT entries */ CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 25e3464fb07f..629fa9774972 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -84,7 +84,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} * USB Device (Gadget) * -------------------------------------------------------------------- */ -#ifdef CONFIG_USB_GADGET_AT91 +#ifdef CONFIG_USB_AT91 static struct at91_udc_data udc_data; static struct resource udc_resources[] = { diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index ae78f4d03b73..a178b58b0b9c 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -87,7 +87,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} * USB Device (Gadget) * -------------------------------------------------------------------- */ -#ifdef CONFIG_USB_GADGET_AT91 +#ifdef CONFIG_USB_AT91 static struct at91_udc_data udc_data; static struct resource udc_resources[] = { diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index ad017eb1f8df..d5fbac9ff4fa 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -92,7 +92,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} * USB Device (Gadget) * -------------------------------------------------------------------- */ -#ifdef CONFIG_USB_GADGET_AT91 +#ifdef CONFIG_USB_AT91 static struct at91_udc_data udc_data; static struct resource udc_resources[] = { diff --git a/arch/arm/mach-at91/include/mach/system_rev.h b/arch/arm/mach-at91/include/mach/system_rev.h index 8f4866045b41..ec164a4124c9 100644 --- a/arch/arm/mach-at91/include/mach/system_rev.h +++ b/arch/arm/mach-at91/include/mach/system_rev.h @@ -19,7 +19,7 @@ #define BOARD_HAVE_NAND_16BIT (1 << 31) static inline int board_have_nand_16bit(void) { - return system_rev & BOARD_HAVE_NAND_16BIT; + return (system_rev & BOARD_HAVE_NAND_16BIT) ? 1 : 0; } #endif /* __ARCH_SYSTEM_REV_H__ */ diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 1d7d24995226..6659a90dbcad 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -753,7 +753,7 @@ static struct snd_platform_data da850_evm_snd_data = { .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), .tdm_slots = 2, .serial_dir = da850_iis_serializer_direction, - .asp_chan_q = EVENTQ_1, + .asp_chan_q = EVENTQ_0, .version = MCASP_VERSION_2, .txnumevt = 1, .rxnumevt = 1, diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 1918ae711428..46e1f4173b97 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -107,7 +107,7 @@ static struct mtd_partition davinci_nand_partitions[] = { /* UBL (a few copies) plus U-Boot */ .name = "bootloader", .offset = 0, - .size = 28 * NAND_BLOCK_SIZE, + .size = 30 * NAND_BLOCK_SIZE, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, { /* U-Boot environment */ diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index e574d7f837a8..635bf7740157 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -564,7 +564,7 @@ static int setup_vpif_input_channel_mode(int mux_mode) int val; u32 value; - if (!vpif_vsclkdis_reg || !cpld_client) + if (!vpif_vidclkctl_reg || !cpld_client) return -ENXIO; val = i2c_smbus_read_byte(cpld_client); @@ -572,7 +572,7 @@ static int setup_vpif_input_channel_mode(int mux_mode) return val; spin_lock_irqsave(&vpif_reg_lock, flags); - value = __raw_readl(vpif_vsclkdis_reg); + value = __raw_readl(vpif_vidclkctl_reg); if (mux_mode) { val &= VPIF_INPUT_TWO_CHANNEL; value |= VIDCH1CLK; @@ -580,7 +580,7 @@ static int setup_vpif_input_channel_mode(int mux_mode) val |= VPIF_INPUT_ONE_CHANNEL; value &= ~VIDCH1CLK; } - __raw_writel(value, vpif_vsclkdis_reg); + __raw_writel(value, vpif_vidclkctl_reg); spin_unlock_irqrestore(&vpif_reg_lock, flags); err = i2c_smbus_write_byte(cpld_client, val); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 0b68ed534f8e..af27c130595f 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -161,7 +161,6 @@ static struct clk dsp_clk = { .name = "dsp", .parent = &pll1_sysclk1, .lpsc = DM646X_LPSC_C64X_CPU, - .flags = PSC_DSP, .usecount = 1, /* REVISIT how to disable? */ }; diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index fa59c097223d..8bc3fc256171 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -233,7 +233,7 @@ #define PTCMD 0x120 #define PTSTAT 0x128 #define PDSTAT 0x200 -#define PDCTL1 0x304 +#define PDCTL 0x300 #define MDSTAT 0x800 #define MDCTL 0xA00 @@ -244,7 +244,10 @@ #define PSC_STATE_ENABLE 3 #define MDSTAT_STATE_MASK 0x3f +#define PDSTAT_STATE_MASK 0x1f #define MDCTL_FORCE BIT(31) +#define PDCTL_NEXT BIT(1) +#define PDCTL_EPCGOOD BIT(8) #ifndef __ASSEMBLER__ diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 1fb6bdff38c1..d7e210f4b55c 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -52,7 +52,7 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) void davinci_psc_config(unsigned int domain, unsigned int ctlr, unsigned int id, bool enable, u32 flags) { - u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; + u32 epcpr, ptcmd, ptstat, pdstat, pdctl, mdstat, mdctl; void __iomem *psc_base; struct davinci_soc_info *soc_info = &davinci_soc_info; u32 next_state = PSC_STATE_ENABLE; @@ -79,11 +79,11 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr, mdctl |= MDCTL_FORCE; __raw_writel(mdctl, psc_base + MDCTL + 4 * id); - pdstat = __raw_readl(psc_base + PDSTAT); - if ((pdstat & 0x00000001) == 0) { - pdctl1 = __raw_readl(psc_base + PDCTL1); - pdctl1 |= 0x1; - __raw_writel(pdctl1, psc_base + PDCTL1); + pdstat = __raw_readl(psc_base + PDSTAT + 4 * domain); + if ((pdstat & PDSTAT_STATE_MASK) == 0) { + pdctl = __raw_readl(psc_base + PDCTL + 4 * domain); + pdctl |= PDCTL_NEXT; + __raw_writel(pdctl, psc_base + PDCTL + 4 * domain); ptcmd = 1 << domain; __raw_writel(ptcmd, psc_base + PTCMD); @@ -92,9 +92,9 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr, epcpr = __raw_readl(psc_base + EPCPR); } while ((((epcpr >> domain) & 1) == 0)); - pdctl1 = __raw_readl(psc_base + PDCTL1); - pdctl1 |= 0x100; - __raw_writel(pdctl1, psc_base + PDCTL1); + pdctl = __raw_readl(psc_base + PDCTL + 4 * domain); + pdctl |= PDCTL_EPCGOOD; + __raw_writel(pdctl, psc_base + PDCTL + 4 * domain); } else { ptcmd = 1 << domain; __raw_writel(ptcmd, psc_base + PTCMD); diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c index 00be4fc26dd7..98b8c83b09ab 100644 --- a/arch/arm/mach-dove/addr-map.c +++ b/arch/arm/mach-dove/addr-map.c @@ -14,6 +14,7 @@ #include <linux/io.h> #include <asm/mach/arch.h> #include <asm/setup.h> +#include <plat/addr-map.h> #include "common.h" /* @@ -34,98 +35,72 @@ #define ATTR_PCIE_MEM 0xe8 #define ATTR_SCRATCHPAD 0x0 -/* - * CPU Address Decode Windows registers - */ -#define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0) -#define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4) -#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8) -#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc) - -struct mbus_dram_target_info dove_mbus_dram_info; - static inline void __iomem *ddr_map_sc(int i) { return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); } -static int cpu_win_can_remap(int win) -{ - if (win < 4) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - u32 ctrl; - - base &= 0xffff0000; - ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; - - writel(base, WIN_BASE(win)); - writel(ctrl, WIN_CTRL(win)); - if (cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - writel(remap & 0xffff0000, WIN_REMAP_LO(win)); - writel(0, WIN_REMAP_HI(win)); - } -} - -void __init dove_setup_cpu_mbus(void) -{ - int i; - int cs; +/* + * Description of the windows needed by the platform code + */ +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 8, + .remappable_wins = 4, + .bridge_virt_base = BRIDGE_VIRT_BASE, +}; +static const struct __initdata orion_addr_map_info addr_map_info[] = { /* - * First, disable and clear windows. + * Windows for PCIe IO+MEM space. */ - for (i = 0; i < 8; i++) { - writel(0, WIN_BASE(i)); - writel(0, WIN_CTRL(i)); - if (cpu_win_can_remap(i)) { - writel(0, WIN_REMAP_LO(i)); - writel(0, WIN_REMAP_HI(i)); - } - } - + { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, + TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE + }, + { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, + TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE + }, + { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, + TARGET_PCIE0, ATTR_PCIE_MEM, -1 + }, + { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, + TARGET_PCIE1, ATTR_PCIE_MEM, -1 + }, /* - * Setup windows for PCIe IO+MEM space. + * Window for CESA engine. */ - setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, - TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE); - setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, - TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE); - setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, - TARGET_PCIE0, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, - TARGET_PCIE1, ATTR_PCIE_MEM, -1); - + { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, + TARGET_CESA, ATTR_CESA, -1 + }, /* - * Setup window for CESA engine. + * Window to the BootROM for Standby and Sleep Resume */ - setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, - TARGET_CESA, ATTR_CESA, -1); - + { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, + TARGET_BOOTROM, ATTR_BOOTROM, -1 + }, /* - * Setup the Window to the BootROM for Standby and Sleep Resume + * Window to the PMU Scratch Pad space */ - setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, - TARGET_BOOTROM, ATTR_BOOTROM, -1); + { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, + TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1 + }, + /* End marker */ + { -1, 0, 0, 0, 0, 0 } +}; + +void __init dove_setup_cpu_mbus(void) +{ + int i; + int cs; /* - * Setup the Window to the PMU Scratch Pad space + * Disable, clear and configure windows. */ - setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, - TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1); + orion_config_wins(&addr_map_cfg, addr_map_info); /* * Setup MBUS dram target info. */ - dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; for (i = 0, cs = 0; i < 2; i++) { u32 map = readl(ddr_map_sc(i)); @@ -136,7 +111,7 @@ void __init dove_setup_cpu_mbus(void) if (map & 1) { struct mbus_dram_window *w; - w = &dove_mbus_dram_info.cs[cs++]; + w = &orion_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0; /* CS address decoding done inside */ /* the DDR controller, no need to */ @@ -145,5 +120,5 @@ void __init dove_setup_cpu_mbus(void) w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); } } - dove_mbus_dram_info.num_cs = cs; + orion_mbus_dram_info.num_cs = cs; } diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index a9e0dae86a26..29ff0d076f0a 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -14,7 +14,6 @@ #include <linux/platform_device.h> #include <linux/pci.h> #include <linux/clk.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/gpio.h> #include <asm/page.h> @@ -30,6 +29,7 @@ #include <linux/irq.h> #include <plat/time.h> #include <plat/common.h> +#include <plat/addr-map.h> #include "common.h" static int get_tclk(void); @@ -71,8 +71,7 @@ void __init dove_map_io(void) ****************************************************************************/ void __init dove_ehci0_init(void) { - orion_ehci_init(&dove_mbus_dram_info, - DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); + orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); } /***************************************************************************** @@ -80,8 +79,7 @@ void __init dove_ehci0_init(void) ****************************************************************************/ void __init dove_ehci1_init(void) { - orion_ehci_1_init(&dove_mbus_dram_info, - DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); + orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); } /***************************************************************************** @@ -89,7 +87,7 @@ void __init dove_ehci1_init(void) ****************************************************************************/ void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge00_init(eth_data, &dove_mbus_dram_info, + orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 0, get_tclk()); } @@ -107,8 +105,7 @@ void __init dove_rtc_init(void) ****************************************************************************/ void __init dove_sata_init(struct mv_sata_platform_data *sata_data) { - orion_sata_init(sata_data, &dove_mbus_dram_info, - DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); + orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); } @@ -198,8 +195,7 @@ struct sys_timer dove_timer = { ****************************************************************************/ void __init dove_xor0_init(void) { - orion_xor0_init(&dove_mbus_dram_info, - DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, + orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); } diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h index 6a2046e44706..7322371d3908 100644 --- a/arch/arm/mach-dove/common.h +++ b/arch/arm/mach-dove/common.h @@ -15,7 +15,6 @@ struct mv643xx_eth_platform_data; struct mv_sata_platform_data; extern struct sys_timer dove_timer; -extern struct mbus_dram_target_info dove_mbus_dram_info; /* * Basic Dove init functions used early by machine-setup. diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c index aa2b3a09a51d..6c11a4df7178 100644 --- a/arch/arm/mach-dove/pcie.c +++ b/arch/arm/mach-dove/pcie.c @@ -10,7 +10,6 @@ #include <linux/kernel.h> #include <linux/pci.h> -#include <linux/mbus.h> #include <video/vga.h> #include <asm/mach/pci.h> #include <asm/mach/arch.h> @@ -19,6 +18,7 @@ #include <plat/pcie.h> #include <mach/irqs.h> #include <mach/bridge-regs.h> +#include <plat/addr-map.h> #include "common.h" struct pcie_port { @@ -50,7 +50,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) */ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - orion_pcie_setup(pp->base, &dove_mbus_dram_info); + orion_pcie_setup(pp->base); /* * IORESOURCE_IO diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 9cd860a27af5..8deb012189b5 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -37,14 +37,15 @@ static void __init imx6q_map_io(void) imx6q_clock_map_io(); } -static void __init imx6q_gpio_add_irq_domain(struct device_node *np, +static int __init imx6q_gpio_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { - static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS - - 32 * 7; /* imx6q gets 7 gpio ports */ + static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; + gpio_irq_base -= 32; irq_domain_add_simple(np, gpio_irq_base); - gpio_irq_base += 32; + + return 0; } static const struct of_device_id imx6q_irq_match[] __initconst = { diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c index 8d03bcef5182..e9a7180863d9 100644 --- a/arch/arm/mach-kirkwood/addr-map.c +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -13,12 +13,12 @@ #include <linux/mbus.h> #include <linux/io.h> #include <mach/hardware.h> +#include <plat/addr-map.h> #include "common.h" /* * Generic Address Decode Windows bit settings */ -#define TARGET_DDR 0 #define TARGET_DEV_BUS 1 #define TARGET_SRAM 3 #define TARGET_PCIE 4 @@ -36,118 +36,55 @@ #define ATTR_SRAM 0x01 /* - * Helpers to get DDR bank info + * Description of the windows needed by the platform code */ -#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) -#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) - -/* - * CPU Address Decode Windows registers - */ -#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) -#define WIN_CTRL_OFF 0x0000 -#define WIN_BASE_OFF 0x0004 -#define WIN_REMAP_LO_OFF 0x0008 -#define WIN_REMAP_HI_OFF 0x000c - - -struct mbus_dram_target_info kirkwood_mbus_dram_info; - -static int __init cpu_win_can_remap(int win) -{ - if (win < 4) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - void __iomem *addr = (void __iomem *)WIN_OFF(win); - u32 ctrl; - - base &= 0xffff0000; - ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; - - writel(base, addr + WIN_BASE_OFF); - writel(ctrl, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } -} - -void __init kirkwood_setup_cpu_mbus(void) -{ - void __iomem *addr; - int i; - int cs; +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 8, + .remappable_wins = 4, + .bridge_virt_base = BRIDGE_VIRT_BASE, +}; +static const struct __initdata orion_addr_map_info addr_map_info[] = { /* - * First, disable and clear windows. + * Windows for PCIe IO+MEM space. */ - for (i = 0; i < 8; i++) { - addr = (void __iomem *)WIN_OFF(i); - - writel(0, addr + WIN_BASE_OFF); - writel(0, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(i)) { - writel(0, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } - } - + { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE + }, + { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE + }, + { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, + TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE + }, + { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE + }, /* - * Setup windows for PCIe IO+MEM space. + * Window for NAND controller. */ - setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); - setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE); - setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, - TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE); - setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE); - + { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, + TARGET_DEV_BUS, ATTR_DEV_NAND, -1 + }, /* - * Setup window for NAND controller. + * Window for SRAM. */ - setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, - TARGET_DEV_BUS, ATTR_DEV_NAND, -1); + { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, + TARGET_SRAM, ATTR_SRAM, -1 + }, + /* End marker */ + { -1, 0, 0, 0, 0, 0 } +}; +void __init kirkwood_setup_cpu_mbus(void) +{ /* - * Setup window for SRAM. + * Disable, clear and configure windows. */ - setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, - TARGET_SRAM, ATTR_SRAM, -1); + orion_config_wins(&addr_map_cfg, addr_map_info); /* * Setup MBUS dram target info. */ - kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - addr = (void __iomem *)DDR_WINDOW_CPU_BASE; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(addr + DDR_BASE_CS_OFF(i)); - u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &kirkwood_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - kirkwood_mbus_dram_info.num_cs = cs; + orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE); } diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index f3248cfbe51d..10566d4052d2 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -12,7 +12,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/mtd/nand.h> #include <linux/dma-mapping.h> @@ -30,6 +29,7 @@ #include <plat/orion_nand.h> #include <plat/common.h> #include <plat/time.h> +#include <plat/addr-map.h> #include "common.h" /***************************************************************************** @@ -73,8 +73,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; void __init kirkwood_ehci_init(void) { kirkwood_clk_ctrl |= CGC_USB0; - orion_ehci_init(&kirkwood_mbus_dram_info, - USB_PHYS_BASE, IRQ_KIRKWOOD_USB); + orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB); } @@ -85,7 +84,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) { kirkwood_clk_ctrl |= CGC_GE0; - orion_ge00_init(eth_data, &kirkwood_mbus_dram_info, + orion_ge00_init(eth_data, GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk); } @@ -99,7 +98,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) kirkwood_clk_ctrl |= CGC_GE1; - orion_ge01_init(eth_data, &kirkwood_mbus_dram_info, + orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk); } @@ -178,8 +177,7 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) if (sata_data->n_ports > 1) kirkwood_clk_ctrl |= CGC_SATA1; - orion_sata_init(sata_data, &kirkwood_mbus_dram_info, - SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); + orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA); } @@ -221,7 +219,6 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) mvsdio_data->clock = 100000000; else mvsdio_data->clock = 200000000; - mvsdio_data->dram = &kirkwood_mbus_dram_info; kirkwood_clk_ctrl |= CGC_SDIO; kirkwood_sdio.dev.platform_data = mvsdio_data; platform_device_register(&kirkwood_sdio); @@ -285,8 +282,7 @@ static void __init kirkwood_xor0_init(void) { kirkwood_clk_ctrl |= CGC_XOR0; - orion_xor0_init(&kirkwood_mbus_dram_info, - XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, + orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE, IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); } @@ -364,7 +360,6 @@ static struct resource kirkwood_i2s_resources[] = { }; static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { - .dram = &kirkwood_mbus_dram_info, .burst = 128, }; @@ -430,6 +425,8 @@ static char * __init kirkwood_id(void) } else if (dev == MV88F6282_DEV_ID) { if (rev == MV88F6282_REV_A0) return "MV88F6282-Rev-A0"; + else if (rev == MV88F6282_REV_A1) + return "MV88F6282-Rev-A1"; else return "MV88F6282-Rev-Unsupported"; } else { diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index b9b0f0968a36..4756b945106b 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -30,7 +30,6 @@ void kirkwood_init(void); void kirkwood_init_early(void); void kirkwood_init_irq(void); -extern struct mbus_dram_target_info kirkwood_mbus_dram_info; void kirkwood_setup_cpu_mbus(void); void kirkwood_enable_pcie(void); diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index 010bdeb4ac5f..fede3d503efa 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -135,4 +135,5 @@ #define MV88F6282_DEV_ID 0x6282 #define MV88F6282_REV_A0 0 +#define MV88F6282_REV_A1 1 #endif diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index cc431fa22ccb..0c6ad63f10c7 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -10,7 +10,6 @@ #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mbus.h> #include <linux/io.h> #include <mach/hardware.h> #include <plat/mpp.h> diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h index ac787957e2d9..e8fda45c0736 100644 --- a/arch/arm/mach-kirkwood/mpp.h +++ b/arch/arm/mach-kirkwood/mpp.h @@ -102,6 +102,7 @@ #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 ) #define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) #define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) #define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c index 74b992d810ea..fb451bfe478b 100644 --- a/arch/arm/mach-kirkwood/pcie.c +++ b/arch/arm/mach-kirkwood/pcie.c @@ -11,12 +11,12 @@ #include <linux/kernel.h> #include <linux/pci.h> #include <linux/slab.h> -#include <linux/mbus.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> #include <mach/bridge-regs.h> +#include <plat/addr-map.h> #include "common.h" void kirkwood_enable_pcie(void) @@ -208,7 +208,7 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) */ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info); + orion_pcie_setup(pp->base); return 1; } diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c index 24030d0da6e3..0fb7a17df398 100644 --- a/arch/arm/mach-msm/devices-iommu.c +++ b/arch/arm/mach-msm/devices-iommu.c @@ -18,6 +18,7 @@ #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/bootmem.h> +#include <linux/module.h> #include <mach/irqs.h> #include <mach/iommu.h> diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index 311d5b0e9bc7..62b53d710efd 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -12,12 +12,12 @@ #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> +#include <plat/addr-map.h> #include "common.h" /* * Generic Address Decode Windows bit settings */ -#define TARGET_DDR 0 #define TARGET_DEV_BUS 1 #define TARGET_PCIE0 4 #define TARGET_PCIE1 8 @@ -32,23 +32,10 @@ #define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) /* - * Helpers to get DDR bank info - */ -#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) -#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) - -/* * CPU Address Decode Windows registers */ #define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) #define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) -#define WIN_CTRL_OFF 0x0000 -#define WIN_BASE_OFF 0x0004 -#define WIN_REMAP_LO_OFF 0x0008 -#define WIN_REMAP_HI_OFF 0x000c - - -struct mbus_dram_target_info mv78xx0_mbus_dram_info; static void __init __iomem *win_cfg_base(int win) { @@ -63,94 +50,43 @@ static void __init __iomem *win_cfg_base(int win) return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); } -static int __init cpu_win_can_remap(int win) -{ - if (win < 8) - return 1; - - return 0; -} - -static void __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - void __iomem *addr = win_cfg_base(win); - u32 ctrl; - - base &= 0xffff0000; - ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; - - writel(base, addr + WIN_BASE_OFF); - writel(ctrl, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } -} +/* + * Description of the windows needed by the platform code + */ +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 14, + .remappable_wins = 8, + .win_cfg_base = win_cfg_base, +}; void __init mv78xx0_setup_cpu_mbus(void) { - void __iomem *addr; - int i; - int cs; - /* - * First, disable and clear windows. + * Disable, clear and configure windows. */ - for (i = 0; i < 14; i++) { - addr = win_cfg_base(i); - - writel(0, addr + WIN_BASE_OFF); - writel(0, addr + WIN_CTRL_OFF); - if (cpu_win_can_remap(i)) { - writel(0, addr + WIN_REMAP_LO_OFF); - writel(0, addr + WIN_REMAP_HI_OFF); - } - } + orion_config_wins(&addr_map_cfg, NULL); /* * Setup MBUS dram target info. */ - mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - if (mv78xx0_core_index() == 0) - addr = (void __iomem *)DDR_WINDOW_CPU0_BASE; + orion_setup_cpu_mbus_target(&addr_map_cfg, + DDR_WINDOW_CPU0_BASE); else - addr = (void __iomem *)DDR_WINDOW_CPU1_BASE; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(addr + DDR_BASE_CS_OFF(i)); - u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &mv78xx0_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - mv78xx0_mbus_dram_info.num_cs = cs; + orion_setup_cpu_mbus_target(&addr_map_cfg, + DDR_WINDOW_CPU1_BASE); } void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min) { - setup_cpu_win(window, base, size, TARGET_PCIE(maj), - ATTR_PCIE_IO(min), -1); + orion_setup_cpu_win(&addr_map_cfg, window, base, size, + TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1); } void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, int maj, int min) { - setup_cpu_win(window, base, size, TARGET_PCIE(maj), - ATTR_PCIE_MEM(min), -1); + orion_setup_cpu_win(&addr_map_cfg, window, base, size, + TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 23d3980ef59d..534ce204e8b9 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -12,7 +12,6 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/ethtool.h> #include <asm/mach/map.h> @@ -23,6 +22,7 @@ #include <plat/orion_nand.h> #include <plat/time.h> #include <plat/common.h> +#include <plat/addr-map.h> #include "common.h" static int get_tclk(void); @@ -169,8 +169,7 @@ void __init mv78xx0_map_io(void) ****************************************************************************/ void __init mv78xx0_ehci0_init(void) { - orion_ehci_init(&mv78xx0_mbus_dram_info, - USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); + orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); } @@ -179,8 +178,7 @@ void __init mv78xx0_ehci0_init(void) ****************************************************************************/ void __init mv78xx0_ehci1_init(void) { - orion_ehci_1_init(&mv78xx0_mbus_dram_info, - USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); + orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); } @@ -189,8 +187,7 @@ void __init mv78xx0_ehci1_init(void) ****************************************************************************/ void __init mv78xx0_ehci2_init(void) { - orion_ehci_2_init(&mv78xx0_mbus_dram_info, - USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); + orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); } @@ -199,7 +196,7 @@ void __init mv78xx0_ehci2_init(void) ****************************************************************************/ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge00_init(eth_data, GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, IRQ_MV78XX0_GE_ERR, get_tclk()); } @@ -210,7 +207,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) ****************************************************************************/ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, NO_IRQ, get_tclk()); } @@ -234,7 +231,7 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge10_init(eth_data, GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, NO_IRQ, get_tclk()); } @@ -258,7 +255,7 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info, + orion_ge11_init(eth_data, GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, NO_IRQ, get_tclk()); } @@ -277,8 +274,7 @@ void __init mv78xx0_i2c_init(void) ****************************************************************************/ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) { - orion_sata_init(sata_data, &mv78xx0_mbus_dram_info, - SATA_PHYS_BASE, IRQ_MV78XX0_SATA); + orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA); } diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h index 632e63d65e7a..f2ca59c75c6f 100644 --- a/arch/arm/mach-mv78xx0/common.h +++ b/arch/arm/mach-mv78xx0/common.h @@ -23,7 +23,6 @@ void mv78xx0_init(void); void mv78xx0_init_early(void); void mv78xx0_init_irq(void); -extern struct mbus_dram_target_info mv78xx0_mbus_dram_info; void mv78xx0_setup_cpu_mbus(void); void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min); diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index cf4e494d44bf..df50342179e2 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -10,7 +10,6 @@ #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mbus.h> #include <linux/io.h> #include <plat/mpp.h> #include <mach/hardware.h> diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index c51af1cac300..12fcb108b0e1 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -10,11 +10,11 @@ #include <linux/kernel.h> #include <linux/pci.h> -#include <linux/mbus.h> #include <video/vga.h> #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <plat/addr-map.h> #include "common.h" struct pcie_port { @@ -153,7 +153,7 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) * Generic PCIe unit setup. */ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info); + orion_pcie_setup(pp->base); sys->resource[0] = &pp->res[0]; sys->resource[1] = &pp->res[1]; diff --git a/arch/arm/mach-mx5/imx51-dt.c b/arch/arm/mach-mx5/imx51-dt.c index ccc61585659b..596edd967dbf 100644 --- a/arch/arm/mach-mx5/imx51-dt.c +++ b/arch/arm/mach-mx5/imx51-dt.c @@ -44,20 +44,22 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = { { /* sentinel */ } }; -static void __init imx51_tzic_add_irq_domain(struct device_node *np, +static int __init imx51_tzic_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { irq_domain_add_simple(np, 0); + return 0; } -static void __init imx51_gpio_add_irq_domain(struct device_node *np, +static int __init imx51_gpio_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { - static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS - - 32 * 4; /* imx51 gets 4 gpio ports */ + static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; + gpio_irq_base -= 32; irq_domain_add_simple(np, gpio_irq_base); - gpio_irq_base += 32; + + return 0; } static const struct of_device_id imx51_irq_match[] __initconst = { diff --git a/arch/arm/mach-mx5/imx53-dt.c b/arch/arm/mach-mx5/imx53-dt.c index ccaa0b81b768..85bfd5ff21b0 100644 --- a/arch/arm/mach-mx5/imx53-dt.c +++ b/arch/arm/mach-mx5/imx53-dt.c @@ -48,20 +48,22 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = { { /* sentinel */ } }; -static void __init imx53_tzic_add_irq_domain(struct device_node *np, +static int __init imx53_tzic_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { irq_domain_add_simple(np, 0); + return 0; } -static void __init imx53_gpio_add_irq_domain(struct device_node *np, +static int __init imx53_gpio_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { - static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS - - 32 * 7; /* imx53 gets 7 gpio ports */ + static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; + gpio_irq_base -= 32; irq_domain_add_simple(np, gpio_irq_base); - gpio_irq_base += 32; + + return 0; } static const struct of_device_id imx53_irq_match[] __initconst = { diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h index 75d86118b76a..30c7990f3c01 100644 --- a/arch/arm/mach-mxs/include/mach/mx28.h +++ b/arch/arm/mach-mxs/include/mach/mx28.h @@ -104,8 +104,8 @@ #define MX28_INT_CAN1 9 #define MX28_INT_LRADC_TOUCH 10 #define MX28_INT_HSADC 13 -#define MX28_INT_IRADC_THRESH0 14 -#define MX28_INT_IRADC_THRESH1 15 +#define MX28_INT_LRADC_THRESH0 14 +#define MX28_INT_LRADC_THRESH1 15 #define MX28_INT_LRADC_CH0 16 #define MX28_INT_LRADC_CH1 17 #define MX28_INT_LRADC_CH2 18 diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h index 0d2d2b470998..bde5f6634747 100644 --- a/arch/arm/mach-mxs/include/mach/mxs.h +++ b/arch/arm/mach-mxs/include/mach/mxs.h @@ -30,6 +30,7 @@ */ #define cpu_is_mx23() ( \ machine_is_mx23evk() || \ + machine_is_stmp378x() || \ 0) #define cpu_is_mx28() ( \ machine_is_mx28evk() || \ diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c index 3b1681e4f49a..6b00577b7025 100644 --- a/arch/arm/mach-mxs/mach-m28evk.c +++ b/arch/arm/mach-mxs/mach-m28evk.c @@ -361,6 +361,6 @@ static struct sys_timer m28evk_timer = { MACHINE_START(M28EVK, "DENX M28 EVK") .map_io = mx28_map_io, .init_irq = mx28_init_irq, - .init_machine = m28evk_init, .timer = &m28evk_timer, + .init_machine = m28evk_init, MACHINE_END diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c index 177e53123a02..6834dea38c04 100644 --- a/arch/arm/mach-mxs/mach-stmp378x_devb.c +++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c @@ -115,6 +115,6 @@ static struct sys_timer stmp378x_dvb_timer = { MACHINE_START(STMP378X, "STMP378X") .map_io = mx23_map_io, .init_irq = mx23_init_irq, - .init_machine = stmp378x_dvb_init, .timer = &stmp378x_dvb_timer, + .init_machine = stmp378x_dvb_init, MACHINE_END diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c index 0fcff47009cf..9a7b08b2a925 100644 --- a/arch/arm/mach-mxs/module-tx28.c +++ b/arch/arm/mach-mxs/module-tx28.c @@ -66,11 +66,11 @@ static const iomux_cfg_t tx28_fec1_pads[] __initconst = { MX28_PAD_ENET0_CRS__ENET1_RX_EN, }; -static struct fec_platform_data tx28_fec0_data = { +static const struct fec_platform_data tx28_fec0_data __initconst = { .phy = PHY_INTERFACE_MODE_RMII, }; -static struct fec_platform_data tx28_fec1_data = { +static const struct fec_platform_data tx28_fec1_data __initconst = { .phy = PHY_INTERFACE_MODE_RMII, }; diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 5ceafdccc456..3638e5c12b7e 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -14,8 +14,8 @@ #include <linux/init.h> #include <linux/mbus.h> #include <linux/io.h> -#include <linux/errno.h> #include <mach/hardware.h> +#include <plat/addr-map.h> #include "common.h" /* @@ -41,7 +41,6 @@ /* * Generic Address Decode Windows bit settings */ -#define TARGET_DDR 0 #define TARGET_DEV_BUS 1 #define TARGET_PCI 3 #define TARGET_PCIE 4 @@ -57,27 +56,10 @@ #define ATTR_DEV_BOOT 0xf #define ATTR_SRAM 0x0 -/* - * Helpers to get DDR bank info - */ -#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) -#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3)) -#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3)) - -/* - * CPU Address Decode Windows registers - */ -#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) -#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) -#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) -#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) -#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) - - -struct mbus_dram_target_info orion5x_mbus_dram_info; static int __initdata win_alloc_count; -static int __init orion5x_cpu_win_can_remap(int win) +static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, + const int win) { u32 dev, rev; @@ -91,116 +73,82 @@ static int __init orion5x_cpu_win_can_remap(int win) return 0; } -static int __init setup_cpu_win(int win, u32 base, u32 size, - u8 target, u8 attr, int remap) -{ - if (win >= 8) { - printk(KERN_ERR "setup_cpu_win: trying to allocate " - "window %d\n", win); - return -ENOSPC; - } - - writel(base & 0xffff0000, CPU_WIN_BASE(win)); - writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1, - CPU_WIN_CTRL(win)); - - if (orion5x_cpu_win_can_remap(win)) { - if (remap < 0) - remap = base; - - writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); - writel(0, CPU_WIN_REMAP_HI(win)); - } - return 0; -} - -void __init orion5x_setup_cpu_mbus_bridge(void) -{ - int i; - int cs; +/* + * Description of the windows needed by the platform code + */ +static struct __initdata orion_addr_map_cfg addr_map_cfg = { + .num_wins = 8, + .cpu_win_can_remap = cpu_win_can_remap, + .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE, +}; +static const struct __initdata orion_addr_map_info addr_map_info[] = { /* - * First, disable and clear windows. + * Setup windows for PCI+PCIe IO+MEM space. */ - for (i = 0; i < 8; i++) { - writel(0, CPU_WIN_BASE(i)); - writel(0, CPU_WIN_CTRL(i)); - if (orion5x_cpu_win_can_remap(i)) { - writel(0, CPU_WIN_REMAP_LO(i)); - writel(0, CPU_WIN_REMAP_HI(i)); - } - } + { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE + }, + { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, + TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE + }, + { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE_MEM, -1 + }, + { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, + TARGET_PCI, ATTR_PCI_MEM, -1 + }, + /* End marker */ + { -1, 0, 0, 0, 0, 0 } +}; +void __init orion5x_setup_cpu_mbus_bridge(void) +{ /* - * Setup windows for PCI+PCIe IO+MEM space. + * Disable, clear and configure windows. */ - setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, - TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); - setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, - TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); - setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, - TARGET_PCIE, ATTR_PCIE_MEM, -1); - setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, - TARGET_PCI, ATTR_PCI_MEM, -1); + orion_config_wins(&addr_map_cfg, addr_map_info); win_alloc_count = 4; /* * Setup MBUS dram target info. */ - orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(DDR_BASE_CS(i)); - u32 size = readl(DDR_SIZE_CS(i)); - - /* - * Chip select enabled? - */ - if (size & 1) { - struct mbus_dram_window *w; - - w = &orion5x_mbus_dram_info.cs[cs++]; - w->cs_index = i; - w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xffff0000; - w->size = (size | 0x0000ffff) + 1; - } - } - orion5x_mbus_dram_info.num_cs = cs; + orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE); } void __init orion5x_setup_dev_boot_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); } void __init orion5x_setup_dev0_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS0, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS0, -1); } void __init orion5x_setup_dev1_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS1, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS1, -1); } void __init orion5x_setup_dev2_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_DEV_BUS, ATTR_DEV_CS2, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS2, -1); } void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) { - setup_cpu_win(win_alloc_count++, base, size, - TARGET_PCIE, ATTR_PCIE_WA, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size, + TARGET_PCIE, ATTR_PCIE_WA, -1); } -int __init orion5x_setup_sram_win(void) +void __init orion5x_setup_sram_win(void) { - return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE, - ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); + orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, + ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE, + TARGET_SRAM, ATTR_SRAM, -1); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 22ace0bf2f92..79ef693d2c03 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -15,7 +15,6 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/mv643xx_i2c.h> #include <linux/ata_platform.h> #include <net/dsa.h> @@ -31,6 +30,7 @@ #include <plat/orion_nand.h> #include <plat/time.h> #include <plat/common.h> +#include <plat/addr-map.h> #include "common.h" /***************************************************************************** @@ -71,8 +71,7 @@ void __init orion5x_map_io(void) ****************************************************************************/ void __init orion5x_ehci0_init(void) { - orion_ehci_init(&orion5x_mbus_dram_info, - ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); + orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); } @@ -81,8 +80,7 @@ void __init orion5x_ehci0_init(void) ****************************************************************************/ void __init orion5x_ehci1_init(void) { - orion_ehci_1_init(&orion5x_mbus_dram_info, - ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); + orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); } @@ -91,7 +89,7 @@ void __init orion5x_ehci1_init(void) ****************************************************************************/ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) { - orion_ge00_init(eth_data, &orion5x_mbus_dram_info, + orion_ge00_init(eth_data, ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, IRQ_ORION5X_ETH_ERR, orion5x_tclk); } @@ -121,8 +119,7 @@ void __init orion5x_i2c_init(void) ****************************************************************************/ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) { - orion_sata_init(sata_data, &orion5x_mbus_dram_info, - ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); + orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); } @@ -158,8 +155,7 @@ void __init orion5x_uart1_init(void) ****************************************************************************/ void __init orion5x_xor_init(void) { - orion_xor0_init(&orion5x_mbus_dram_info, - ORION5X_XOR_PHYS_BASE, + orion_xor0_init(ORION5X_XOR_PHYS_BASE, ORION5X_XOR_PHYS_BASE + 0x200, IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); } @@ -169,12 +165,7 @@ void __init orion5x_xor_init(void) ****************************************************************************/ static void __init orion5x_crypto_init(void) { - int ret; - - ret = orion5x_setup_sram_win(); - if (ret) - return; - + orion5x_setup_sram_win(); orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, SZ_8K, IRQ_ORION5X_CESA); } diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index 909489f4d23e..889d80c7a151 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -20,14 +20,13 @@ extern struct sys_timer orion5x_timer; * functions to map its interfaces and by the machine-setup to map its on- * board devices. Details in /mach-orion/addr-map.c */ -extern struct mbus_dram_target_info orion5x_mbus_dram_info; void orion5x_setup_cpu_mbus_bridge(void); void orion5x_setup_dev_boot_win(u32 base, u32 size); void orion5x_setup_dev0_win(u32 base, u32 size); void orion5x_setup_dev1_win(u32 base, u32 size); void orion5x_setup_dev2_win(u32 base, u32 size); void orion5x_setup_pcie_wa_win(u32 base, u32 size); -int orion5x_setup_sram_win(void); +void orion5x_setup_sram_win(void); void orion5x_ehci0_init(void); void orion5x_ehci1_init(void); diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 0a28bbc76891..2745f5d95b3f 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -69,7 +69,7 @@ ******************************************************************************/ #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) - +#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE | 0x1500) #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index b6ddd7a5db6a..5b70026f478c 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -10,7 +10,6 @@ #include <linux/kernel.h> #include <linux/init.h> -#include <linux/mbus.h> #include <linux/io.h> #include <mach/hardware.h> #include <plat/mpp.h> diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index bc4a920e26ee..a494c470e3e4 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -18,6 +18,7 @@ #include <asm/irq.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <plat/addr-map.h> #include "common.h" /***************************************************************************** @@ -145,7 +146,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * Generic PCIe unit setup. */ - orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); + orion_pcie_setup(PCIE_BASE); /* * Check whether to apply Orion-1/Orion-NAS PCIe config @@ -477,7 +478,7 @@ static int __init pci_setup(struct pci_sys_data *sys) /* * Point PCI unit MBUS decode windows to DRAM space. */ - orion5x_setup_pci_wins(&orion5x_mbus_dram_info); + orion5x_setup_pci_wins(&orion_mbus_dram_info); /* * Master + Slave enable diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c index cb53160f6c5d..26ebb57719df 100644 --- a/arch/arm/mach-prima2/pm.c +++ b/arch/arm/mach-prima2/pm.c @@ -9,6 +9,7 @@ #include <linux/kernel.h> #include <linux/suspend.h> #include <linux/slab.h> +#include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_device.h> diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c index ef555c041962..a12b689a8702 100644 --- a/arch/arm/mach-prima2/prima2.c +++ b/arch/arm/mach-prima2/prima2.c @@ -8,6 +8,7 @@ #include <linux/init.h> #include <linux/kernel.h> +#include <asm/sizes.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <linux/of.h> diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c index 5e6b42089eb4..3341fd118723 100644 --- a/arch/arm/mach-s3c64xx/dev-spi.c +++ b/arch/arm/mach-s3c64xx/dev-spi.c @@ -10,6 +10,7 @@ #include <linux/kernel.h> #include <linux/string.h> +#include <linux/export.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/gpio.h> diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c index 7a3bc32df425..51c00f2453c6 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c @@ -70,7 +70,7 @@ void __init s3c6400_init_irq(void) s3c64xx_init_irq(~0 & ~(0xf << 5), ~0); } -struct sysdev_class s3c6400_sysclass = { +static struct sysdev_class s3c6400_sysclass = { .name = "s3c6400-core", }; diff --git a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c index 83d2afb79e9f..2cf80026c58d 100644 --- a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c +++ b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c @@ -20,7 +20,7 @@ #include <plat/fb.h> #include <plat/gpio-cfg.h> -extern void s3c64xx_fb_gpio_setup_24bpp(void) +void s3c64xx_fb_gpio_setup_24bpp(void) { s3c_gpio_cfgrange_nopull(S3C64XX_GPI(0), 16, S3C_GPIO_SFN(2)); s3c_gpio_cfgrange_nopull(S3C64XX_GPJ(0), 12, S3C_GPIO_SFN(2)); diff --git a/arch/arm/mach-sa1100/Makefile.boot b/arch/arm/mach-sa1100/Makefile.boot index 5a616f6e5612..f7951aa04562 100644 --- a/arch/arm/mach-sa1100/Makefile.boot +++ b/arch/arm/mach-sa1100/Makefile.boot @@ -1,5 +1,5 @@ -ifeq ($(CONFIG_ARCH_SA1100),y) - zreladdr-$(CONFIG_SA1111) += 0xc0208000 +ifeq ($(CONFIG_SA1111),y) + zreladdr-y += 0xc0208000 else zreladdr-y += 0xc0008000 endif diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile index 95a5fc53b6db..c20ce0f5ce33 100644 --- a/arch/arm/plat-orion/Makefile +++ b/arch/arm/plat-orion/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o pcie.o time.o common.o mpp.o +obj-y := irq.o pcie.o time.o common.o mpp.o addr-map.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c new file mode 100644 index 000000000000..367ca89ac403 --- /dev/null +++ b/arch/arm/plat-orion/addr-map.c @@ -0,0 +1,174 @@ +/* + * arch/arm/plat-orion/addr-map.c + * + * Address map functions for Marvell Orion based SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <plat/addr-map.h> + +struct mbus_dram_target_info orion_mbus_dram_info; + +const struct mbus_dram_target_info *mv_mbus_dram_info(void) +{ + return &orion_mbus_dram_info; +} +EXPORT_SYMBOL_GPL(mv_mbus_dram_info); + +/* + * DDR target is the same on all Orion platforms. + */ +#define TARGET_DDR 0 + +/* + * Helpers to get DDR bank info + */ +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) + +/* + * CPU Address Decode Windows registers + */ +#define WIN_CTRL_OFF 0x0000 +#define WIN_BASE_OFF 0x0004 +#define WIN_REMAP_LO_OFF 0x0008 +#define WIN_REMAP_HI_OFF 0x000c + +/* + * Default implementation + */ +static void __init __iomem * +orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) +{ + return (void __iomem *)(cfg->bridge_virt_base + (win << 4)); +} + +/* + * Default implementation + */ +static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, + const int win) +{ + if (win < cfg->remappable_wins) + return 1; + + return 0; +} + +void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, + const int win, const u32 base, + const u32 size, const u8 target, + const u8 attr, const int remap) +{ + void __iomem *addr = cfg->win_cfg_base(cfg, win); + u32 ctrl, base_high, remap_addr; + + if (win >= cfg->num_wins) { + printk(KERN_ERR "setup_cpu_win: trying to allocate window " + "%d when only %d allowed\n", win, cfg->num_wins); + } + + base_high = base & 0xffff0000; + ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; + + writel(base_high, addr + WIN_BASE_OFF); + writel(ctrl, addr + WIN_CTRL_OFF); + if (cfg->cpu_win_can_remap(cfg, win)) { + if (remap < 0) + remap_addr = base; + else + remap_addr = remap; + writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } +} + +/* + * Configure a number of windows. + */ +static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg, + const struct orion_addr_map_info *info) +{ + while (info->win != -1) { + orion_setup_cpu_win(cfg, info->win, info->base, info->size, + info->target, info->attr, info->remap); + info++; + } +} + +static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg) +{ + void __iomem *addr; + int i; + + for (i = 0; i < cfg->num_wins; i++) { + addr = cfg->win_cfg_base(cfg, i); + + writel(0, addr + WIN_BASE_OFF); + writel(0, addr + WIN_CTRL_OFF); + if (cfg->cpu_win_can_remap(cfg, i)) { + writel(0, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } + } +} + +/* + * Disable, clear and configure windows. + */ +void __init orion_config_wins(struct orion_addr_map_cfg * cfg, + const struct orion_addr_map_info *info) +{ + if (!cfg->cpu_win_can_remap) + cfg->cpu_win_can_remap = orion_cpu_win_can_remap; + + if (!cfg->win_cfg_base) + cfg->win_cfg_base = orion_win_cfg_base; + + orion_disable_wins(cfg); + + if (info) + orion_setup_cpu_wins(cfg, info); +} + +/* + * Setup MBUS dram target info. + */ +void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, + const u32 ddr_window_cpu_base) +{ + void __iomem *addr; + int i; + int cs; + + orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + addr = (void __iomem *)ddr_window_cpu_base; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(addr + DDR_BASE_CS_OFF(i)); + u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); + + /* + * Chip select enabled? + */ + if (size & 1) { + struct mbus_dram_window *w; + + w = &orion_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); + w->base = base & 0xffff0000; + w->size = (size | 0x0000ffff) + 1; + } + } + orion_mbus_dram_info.num_cs = cs; +} diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 9e5451b3c8e3..e5a2fde29b19 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -13,7 +13,6 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/serial_8250.h> -#include <linux/mbus.h> #include <linux/ata_platform.h> #include <linux/mv643xx_eth.h> #include <linux/mv643xx_i2c.h> @@ -203,13 +202,12 @@ void __init orion_rtc_init(unsigned long mapbase, ****************************************************************************/ static __init void ge_complete( struct mv643xx_eth_shared_platform_data *orion_ge_shared_data, - struct mbus_dram_target_info *mbus_dram_info, int tclk, + int tclk, struct resource *orion_ge_resource, unsigned long irq, struct platform_device *orion_ge_shared, struct mv643xx_eth_platform_data *eth_data, struct platform_device *orion_ge) { - orion_ge_shared_data->dram = mbus_dram_info; orion_ge_shared_data->t_clk = tclk; orion_ge_resource->start = irq; orion_ge_resource->end = irq; @@ -259,7 +257,6 @@ static struct platform_device orion_ge00 = { }; void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -267,7 +264,7 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge00_shared_data, tclk, orion_ge00_resources, irq, &orion_ge00_shared, eth_data, &orion_ge00); } @@ -313,7 +310,6 @@ static struct platform_device orion_ge01 = { }; void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -321,7 +317,7 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge01_shared_data, tclk, orion_ge01_resources, irq, &orion_ge01_shared, eth_data, &orion_ge01); } @@ -367,7 +363,6 @@ static struct platform_device orion_ge10 = { }; void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -375,7 +370,7 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge10_shared, orion_ge10_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge10_shared_data, tclk, orion_ge10_resources, irq, &orion_ge10_shared, eth_data, &orion_ge10); } @@ -421,7 +416,6 @@ static struct platform_device orion_ge11 = { }; void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -429,7 +423,7 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, { fill_resources(&orion_ge11_shared, orion_ge11_shared_resources, mapbase + 0x2000, SZ_16K - 1, irq_err); - ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk, + ge_complete(&orion_ge11_shared_data, tclk, orion_ge11_resources, irq, &orion_ge11_shared, eth_data, &orion_ge11); } @@ -592,8 +586,6 @@ void __init orion_wdt_init(unsigned long tclk) /***************************************************************************** * XOR ****************************************************************************/ -static struct mv_xor_platform_shared_data orion_xor_shared_data; - static u64 orion_xor_dmamask = DMA_BIT_MASK(32); void __init orion_xor_init_channels( @@ -632,9 +624,6 @@ static struct resource orion_xor0_shared_resources[] = { static struct platform_device orion_xor0_shared = { .name = MV_XOR_SHARED_NAME, .id = 0, - .dev = { - .platform_data = &orion_xor_shared_data, - }, .num_resources = ARRAY_SIZE(orion_xor0_shared_resources), .resource = orion_xor0_shared_resources, }; @@ -687,14 +676,11 @@ static struct platform_device orion_xor01_channel = { }, }; -void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase_low, +void __init orion_xor0_init(unsigned long mapbase_low, unsigned long mapbase_high, unsigned long irq_0, unsigned long irq_1) { - orion_xor_shared_data.dram = mbus_dram_info; - orion_xor0_shared_resources[0].start = mapbase_low; orion_xor0_shared_resources[0].end = mapbase_low + 0xff; orion_xor0_shared_resources[1].start = mapbase_high; @@ -727,9 +713,6 @@ static struct resource orion_xor1_shared_resources[] = { static struct platform_device orion_xor1_shared = { .name = MV_XOR_SHARED_NAME, .id = 1, - .dev = { - .platform_data = &orion_xor_shared_data, - }, .num_resources = ARRAY_SIZE(orion_xor1_shared_resources), .resource = orion_xor1_shared_resources, }; @@ -828,11 +811,9 @@ static struct platform_device orion_ehci = { }, }; -void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_init(unsigned long mapbase, unsigned long irq) { - orion_ehci_data.dram = mbus_dram_info; fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, irq); @@ -854,11 +835,9 @@ static struct platform_device orion_ehci_1 = { }, }; -void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_1_init(unsigned long mapbase, unsigned long irq) { - orion_ehci_data.dram = mbus_dram_info; fill_resources(&orion_ehci_1, orion_ehci_1_resources, mapbase, SZ_4K - 1, irq); @@ -880,11 +859,9 @@ static struct platform_device orion_ehci_2 = { }, }; -void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_2_init(unsigned long mapbase, unsigned long irq) { - orion_ehci_data.dram = mbus_dram_info; fill_resources(&orion_ehci_2, orion_ehci_2_resources, mapbase, SZ_4K - 1, irq); @@ -911,11 +888,9 @@ static struct platform_device orion_sata = { }; void __init orion_sata_init(struct mv_sata_platform_data *sata_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq) { - sata_data->dram = mbus_dram_info; orion_sata.dev.platform_data = sata_data; fill_resources(&orion_sata, orion_sata_resources, mapbase, 0x5000 - 1, irq); diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h new file mode 100644 index 000000000000..fd556f77562c --- /dev/null +++ b/arch/arm/plat-orion/include/plat/addr-map.h @@ -0,0 +1,53 @@ +/* + * arch/arm/plat-orion/include/plat/addr-map.h + * + * Marvell Orion SoC address map handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_ADDR_MAP_H +#define __PLAT_ADDR_MAP_H + +extern struct mbus_dram_target_info orion_mbus_dram_info; + +struct orion_addr_map_cfg { + const int num_wins; /* Total number of windows */ + const int remappable_wins; + const u32 bridge_virt_base; + + /* If NULL, the default cpu_win_can_remap will be used, using + the value in remappable_wins */ + int (*cpu_win_can_remap) (const struct orion_addr_map_cfg *cfg, + const int win); + /* If NULL, the default win_cfg_base will be used, using the + value in bridge_virt_base */ + void __iomem *(*win_cfg_base) (const struct orion_addr_map_cfg *cfg, + const int win); +}; + +/* + * Information needed to setup one address mapping. + */ +struct orion_addr_map_info { + const int win; + const u32 base; + const u32 size; + const u8 target; + const u8 attr; + const int remap; +}; + +void __init orion_config_wins(struct orion_addr_map_cfg *cfg, + const struct orion_addr_map_info *info); + +void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, + const int win, const u32 base, + const u32 size, const u8 target, + const u8 attr, const int remap); + +void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, + const u32 ddr_window_cpu_base); +#endif diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h index 9cf1f781329b..885f8abd927b 100644 --- a/arch/arm/plat-orion/include/plat/audio.h +++ b/arch/arm/plat-orion/include/plat/audio.h @@ -1,11 +1,8 @@ #ifndef __PLAT_AUDIO_H #define __PLAT_AUDIO_H -#include <linux/mbus.h> - struct kirkwood_asoc_platform_data { u32 tclk; - struct mbus_dram_target_info *dram; int burst; }; #endif diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index a63c357e2ab1..0fe08d77e835 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -37,28 +37,24 @@ void __init orion_rtc_init(unsigned long mapbase, unsigned long irq); void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, int tclk); void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, int tclk); void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, int tclk); void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq, unsigned long irq_err, @@ -82,8 +78,7 @@ void __init orion_spi_1_init(unsigned long mapbase, void __init orion_wdt_init(unsigned long tclk); -void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase_low, +void __init orion_xor0_init(unsigned long mapbase_low, unsigned long mapbase_high, unsigned long irq_0, unsigned long irq_1); @@ -93,20 +88,16 @@ void __init orion_xor1_init(unsigned long mapbase_low, unsigned long irq_0, unsigned long irq_1); -void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_init(unsigned long mapbase, unsigned long irq); -void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_1_init(unsigned long mapbase, unsigned long irq); -void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, - unsigned long mapbase, +void __init orion_ehci_2_init(unsigned long mapbase, unsigned long irq); void __init orion_sata_init(struct mv_sata_platform_data *sata_data, - struct mbus_dram_target_info *mbus_dram_info, unsigned long mapbase, unsigned long irq); diff --git a/arch/arm/plat-orion/include/plat/ehci-orion.h b/arch/arm/plat-orion/include/plat/ehci-orion.h index 4ec668e77460..6fc78e430420 100644 --- a/arch/arm/plat-orion/include/plat/ehci-orion.h +++ b/arch/arm/plat-orion/include/plat/ehci-orion.h @@ -19,7 +19,6 @@ enum orion_ehci_phy_ver { }; struct orion_ehci_data { - struct mbus_dram_target_info *dram; enum orion_ehci_phy_ver phy_version; }; diff --git a/arch/arm/plat-orion/include/plat/mv_xor.h b/arch/arm/plat-orion/include/plat/mv_xor.h index bd5f3bdb4ae3..2ba1f7d76eef 100644 --- a/arch/arm/plat-orion/include/plat/mv_xor.h +++ b/arch/arm/plat-orion/include/plat/mv_xor.h @@ -13,12 +13,6 @@ #define MV_XOR_SHARED_NAME "mv_xor_shared" #define MV_XOR_NAME "mv_xor" -struct mbus_dram_target_info; - -struct mv_xor_platform_shared_data { - struct mbus_dram_target_info *dram; -}; - struct mv_xor_platform_data { struct platform_device *shared; int hw_id; diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/arch/arm/plat-orion/include/plat/mvsdio.h index 14ca88676002..1190efedcb94 100644 --- a/arch/arm/plat-orion/include/plat/mvsdio.h +++ b/arch/arm/plat-orion/include/plat/mvsdio.h @@ -12,7 +12,6 @@ #include <linux/mbus.h> struct mvsdio_platform_data { - struct mbus_dram_target_info *dram; unsigned int clock; int gpio_card_detect; int gpio_write_protect; diff --git a/arch/arm/plat-orion/include/plat/pcie.h b/arch/arm/plat-orion/include/plat/pcie.h index cc99163e73fd..fe5b9e862747 100644 --- a/arch/arm/plat-orion/include/plat/pcie.h +++ b/arch/arm/plat-orion/include/plat/pcie.h @@ -20,8 +20,7 @@ int orion_pcie_x4_mode(void __iomem *base); int orion_pcie_get_local_bus_nr(void __iomem *base); void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); void orion_pcie_reset(void __iomem *base); -void orion_pcie_setup(void __iomem *base, - struct mbus_dram_target_info *dram); +void orion_pcie_setup(void __iomem *base); int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val); int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index af2d733c50b5..86dbb5bdb172 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -13,6 +13,7 @@ #include <linux/mbus.h> #include <asm/mach/pci.h> #include <plat/pcie.h> +#include <plat/addr-map.h> #include <linux/delay.h> /* @@ -175,8 +176,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base, writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); } -void __init orion_pcie_setup(void __iomem *base, - struct mbus_dram_target_info *dram) +void __init orion_pcie_setup(void __iomem *base) { u16 cmd; u32 mask; @@ -184,7 +184,7 @@ void __init orion_pcie_setup(void __iomem *base, /* * Point PCIe unit MBUS decode windows to DRAM space. */ - orion_pcie_setup_wins(base, dram); + orion_pcie_setup_wins(base, &orion_mbus_dram_info); /* * Master + slave enable. diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h index 43f984e93970..303192fc9260 100644 --- a/arch/m68k/include/asm/unistd.h +++ b/arch/m68k/include/asm/unistd.h @@ -350,10 +350,12 @@ #define __NR_clock_adjtime 342 #define __NR_syncfs 343 #define __NR_setns 344 +#define __NR_process_vm_readv 345 +#define __NR_process_vm_writev 346 #ifdef __KERNEL__ -#define NR_syscalls 345 +#define NR_syscalls 347 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/arch/m68k/kernel/syscalltable.S b/arch/m68k/kernel/syscalltable.S index c468f2edaa85..ce827b376110 100644 --- a/arch/m68k/kernel/syscalltable.S +++ b/arch/m68k/kernel/syscalltable.S @@ -365,4 +365,6 @@ ENTRY(sys_call_table) .long sys_clock_adjtime .long sys_syncfs .long sys_setns + .long sys_process_vm_readv /* 345 */ + .long sys_process_vm_writev diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 4f2971bcf8e5..315fc0b250f8 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -623,7 +623,7 @@ static int mipspmu_event_init(struct perf_event *event) if (!atomic_inc_not_zero(&active_events)) { if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) { atomic_dec(&active_events); - return -ENOSPC; + return -EINVAL; } mutex_lock(&pmu_reserve_mutex); @@ -732,15 +732,15 @@ static int validate_group(struct perf_event *event) memset(&fake_cpuc, 0, sizeof(fake_cpuc)); if (!validate_event(&fake_cpuc, leader)) - return -ENOSPC; + return -EINVAL; list_for_each_entry(sibling, &leader->sibling_list, group_entry) { if (!validate_event(&fake_cpuc, sibling)) - return -ENOSPC; + return -EINVAL; } if (!validate_event(&fake_cpuc, event)) - return -ENOSPC; + return -EINVAL; return 0; } diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index 524d23b8610c..4f289ff0b7fe 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -599,10 +599,10 @@ static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste) skey = page_get_storage_key(address); bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); /* Clear page changed & referenced bit in the storage key */ - if (bits) { - skey ^= bits; - page_set_storage_key(address, skey, 1); - } + if (bits & _PAGE_CHANGED) + page_set_storage_key(address, skey ^ bits, 1); + else if (bits) + page_reset_referenced(address); /* Transfer page changed & referenced bit to guest bits in pgste */ pgste_val(pgste) |= bits << 48; /* RCP_GR_BIT & RCP_GC_BIT */ /* Get host changed & referenced bits from pgste */ diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c index 450931a45b68..573bc29551ef 100644 --- a/arch/s390/kernel/ptrace.c +++ b/arch/s390/kernel/ptrace.c @@ -296,13 +296,6 @@ static int __poke_user(struct task_struct *child, addr_t addr, addr_t data) ((data & PSW_MASK_EA) && !(data & PSW_MASK_BA)))) /* Invalid psw mask. */ return -EINVAL; - if (addr == (addr_t) &dummy->regs.psw.addr) - /* - * The debugger changed the instruction address, - * reset system call restart, see signal.c:do_signal - */ - task_thread_info(child)->system_call = 0; - *(addr_t *)((addr_t) &task_pt_regs(child)->psw + addr) = data; } else if (addr < (addr_t) (&dummy->regs.orig_gpr2)) { @@ -614,11 +607,6 @@ static int __poke_user_compat(struct task_struct *child, /* Transfer 31 bit amode bit to psw mask. */ regs->psw.mask = (regs->psw.mask & ~PSW_MASK_BA) | (__u64)(tmp & PSW32_ADDR_AMODE); - /* - * The debugger changed the instruction address, - * reset system call restart, see signal.c:do_signal - */ - task_thread_info(child)->system_call = 0; } else { /* gpr 0-15 */ *(__u32*)((addr_t) ®s->psw + addr*2 + 4) = tmp; @@ -905,6 +893,14 @@ static int s390_last_break_get(struct task_struct *target, return 0; } +static int s390_last_break_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + return 0; +} + #endif static int s390_system_call_get(struct task_struct *target, @@ -951,6 +947,7 @@ static const struct user_regset s390_regsets[] = { .size = sizeof(long), .align = sizeof(long), .get = s390_last_break_get, + .set = s390_last_break_set, }, #endif [REGSET_SYSTEM_CALL] = { @@ -1116,6 +1113,14 @@ static int s390_compat_last_break_get(struct task_struct *target, return 0; } +static int s390_compat_last_break_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + return 0; +} + static const struct user_regset s390_compat_regsets[] = { [REGSET_GENERAL] = { .core_note_type = NT_PRSTATUS, @@ -1139,6 +1144,7 @@ static const struct user_regset s390_compat_regsets[] = { .size = sizeof(long), .align = sizeof(long), .get = s390_compat_last_break_get, + .set = s390_compat_last_break_set, }, [REGSET_SYSTEM_CALL] = { .core_note_type = NT_S390_SYSTEM_CALL, diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index e58a462949b1..e54c4ff8abaa 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -579,7 +579,7 @@ static unsigned long __init find_crash_base(unsigned long crash_size, *msg = "first memory chunk must be at least crashkernel size"; return 0; } - if (is_kdump_kernel() && (crash_size == OLDMEM_SIZE)) + if (OLDMEM_BASE && crash_size == OLDMEM_SIZE) return OLDMEM_BASE; for (i = MEMORY_CHUNKS - 1; i >= 0; i--) { diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c index 05a85bc14c98..7f6f9f354545 100644 --- a/arch/s390/kernel/signal.c +++ b/arch/s390/kernel/signal.c @@ -460,9 +460,9 @@ void do_signal(struct pt_regs *regs) regs->svc_code >> 16); break; } - /* No longer in a system call */ - clear_thread_flag(TIF_SYSCALL); } + /* No longer in a system call */ + clear_thread_flag(TIF_SYSCALL); if ((is_compat_task() ? handle_signal32(signr, &ka, &info, oldset, regs) : @@ -486,6 +486,7 @@ void do_signal(struct pt_regs *regs) } /* No handlers present - check for system call restart */ + clear_thread_flag(TIF_SYSCALL); if (current_thread_info()->system_call) { regs->svc_code = current_thread_info()->system_call; switch (regs->gprs[2]) { @@ -500,9 +501,6 @@ void do_signal(struct pt_regs *regs) regs->gprs[2] = regs->orig_gpr2; set_thread_flag(TIF_SYSCALL); break; - default: - clear_thread_flag(TIF_SYSCALL); - break; } } diff --git a/arch/tile/include/asm/irq.h b/arch/tile/include/asm/irq.h index 94e9a511de84..f80f8ceabc67 100644 --- a/arch/tile/include/asm/irq.h +++ b/arch/tile/include/asm/irq.h @@ -74,16 +74,6 @@ enum { */ void tile_irq_activate(unsigned int irq, int tile_irq_type); -/* - * For onboard, non-PCI (e.g. TILE_IRQ_PERCPU) devices, drivers know - * how to use enable/disable_percpu_irq() to manage interrupts on each - * core. We can't use the generic enable/disable_irq() because they - * use a single reference count per irq, rather than per cpu per irq. - */ -void enable_percpu_irq(unsigned int irq); -void disable_percpu_irq(unsigned int irq); - - void setup_irq_regs(void); #endif /* _ASM_TILE_IRQ_H */ diff --git a/arch/tile/kernel/irq.c b/arch/tile/kernel/irq.c index aa0134db2dd6..02e628065012 100644 --- a/arch/tile/kernel/irq.c +++ b/arch/tile/kernel/irq.c @@ -152,14 +152,13 @@ void tile_dev_intr(struct pt_regs *regs, int intnum) * Remove an irq from the disabled mask. If we're in an interrupt * context, defer enabling the HW interrupt until we leave. */ -void enable_percpu_irq(unsigned int irq) +static void tile_irq_chip_enable(struct irq_data *d) { - get_cpu_var(irq_disable_mask) &= ~(1UL << irq); + get_cpu_var(irq_disable_mask) &= ~(1UL << d->irq); if (__get_cpu_var(irq_depth) == 0) - unmask_irqs(1UL << irq); + unmask_irqs(1UL << d->irq); put_cpu_var(irq_disable_mask); } -EXPORT_SYMBOL(enable_percpu_irq); /* * Add an irq to the disabled mask. We disable the HW interrupt @@ -167,13 +166,12 @@ EXPORT_SYMBOL(enable_percpu_irq); * in an interrupt context, the return path is careful to avoid * unmasking a newly disabled interrupt. */ -void disable_percpu_irq(unsigned int irq) +static void tile_irq_chip_disable(struct irq_data *d) { - get_cpu_var(irq_disable_mask) |= (1UL << irq); - mask_irqs(1UL << irq); + get_cpu_var(irq_disable_mask) |= (1UL << d->irq); + mask_irqs(1UL << d->irq); put_cpu_var(irq_disable_mask); } -EXPORT_SYMBOL(disable_percpu_irq); /* Mask an interrupt. */ static void tile_irq_chip_mask(struct irq_data *d) @@ -209,6 +207,8 @@ static void tile_irq_chip_eoi(struct irq_data *d) static struct irq_chip tile_irq_chip = { .name = "tile_irq_chip", + .irq_enable = tile_irq_chip_enable, + .irq_disable = tile_irq_chip_disable, .irq_ack = tile_irq_chip_ack, .irq_eoi = tile_irq_chip_eoi, .irq_mask = tile_irq_chip_mask, diff --git a/arch/tile/kernel/pci-dma.c b/arch/tile/kernel/pci-dma.c index 658f2ce426a4..b3ed19f8779c 100644 --- a/arch/tile/kernel/pci-dma.c +++ b/arch/tile/kernel/pci-dma.c @@ -15,6 +15,7 @@ #include <linux/mm.h> #include <linux/dma-mapping.h> #include <linux/vmalloc.h> +#include <linux/export.h> #include <asm/tlbflush.h> #include <asm/homecache.h> diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c index 2a8014cb1ff5..9d610d3fb11e 100644 --- a/arch/tile/kernel/pci.c +++ b/arch/tile/kernel/pci.c @@ -24,6 +24,7 @@ #include <linux/irq.h> #include <linux/io.h> #include <linux/uaccess.h> +#include <linux/export.h> #include <asm/processor.h> #include <asm/sections.h> diff --git a/arch/tile/kernel/sysfs.c b/arch/tile/kernel/sysfs.c index b671a86f4515..602908268093 100644 --- a/arch/tile/kernel/sysfs.c +++ b/arch/tile/kernel/sysfs.c @@ -18,6 +18,7 @@ #include <linux/cpu.h> #include <linux/slab.h> #include <linux/smp.h> +#include <linux/stat.h> #include <hv/hypervisor.h> /* Return a string queried from the hypervisor, truncated to page size. */ diff --git a/arch/tile/lib/exports.c b/arch/tile/lib/exports.c index a87d2a859ba9..2a81d32de0da 100644 --- a/arch/tile/lib/exports.c +++ b/arch/tile/lib/exports.c @@ -39,6 +39,9 @@ EXPORT_SYMBOL(finv_user_asm); EXPORT_SYMBOL(current_text_addr); EXPORT_SYMBOL(dump_stack); +/* arch/tile/kernel/head.S */ +EXPORT_SYMBOL(empty_zero_page); + /* arch/tile/lib/, various memcpy files */ EXPORT_SYMBOL(memcpy); EXPORT_SYMBOL(__copy_to_user_inatomic); diff --git a/arch/tile/mm/homecache.c b/arch/tile/mm/homecache.c index cbe6f4f9eca3..1cc6ae477c98 100644 --- a/arch/tile/mm/homecache.c +++ b/arch/tile/mm/homecache.c @@ -449,9 +449,12 @@ void homecache_free_pages(unsigned long addr, unsigned int order) VM_BUG_ON(!virt_addr_valid((void *)addr)); page = virt_to_page((void *)addr); if (put_page_testzero(page)) { - int pages = (1 << order); homecache_change_page_home(page, order, initial_page_home()); - while (pages--) - __free_page(page++); + if (order == 0) { + free_hot_cold_page(page, 0); + } else { + init_page_count(page); + __free_pages(page, order); + } } } diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index cb9a1044a771..efb42949cc09 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -390,7 +390,7 @@ config X86_INTEL_CE This option compiles in support for the CE4100 SOC for settop boxes and media devices. -config X86_INTEL_MID +config X86_WANT_INTEL_MID bool "Intel MID platform support" depends on X86_32 depends on X86_EXTENDED_PLATFORM @@ -399,7 +399,10 @@ config X86_INTEL_MID systems which do not have the PCI legacy interfaces (Moorestown, Medfield). If you are building for a PC class system say N here. -if X86_INTEL_MID +if X86_WANT_INTEL_MID + +config X86_INTEL_MID + bool config X86_MRST bool "Moorestown MID platform" @@ -411,6 +414,7 @@ config X86_MRST select SPI select INTEL_SCU_IPC select X86_PLATFORM_DEVICES + select X86_INTEL_MID ---help--- Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin Internet Device(MID) platform. Moorestown consists of two chips: diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h index 908b96957d88..c9547033e38e 100644 --- a/arch/x86/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h @@ -53,6 +53,13 @@ */ #define E820_RESERVED_KERN 128 +/* + * Address ranges that need to be mapped by the kernel direct + * mapping. This is used to make sure regions such as + * EFI_RUNTIME_SERVICES_DATA are directly mapped. See setup_arch(). + */ +#define E820_RESERVED_EFI 129 + #ifndef __ASSEMBLY__ #include <linux/types.h> struct e820entry { @@ -115,6 +122,7 @@ static inline void early_memtest(unsigned long start, unsigned long end) } #endif +extern unsigned long e820_end_pfn(unsigned long limit_pfn, unsigned type); extern unsigned long e820_end_of_ram_pfn(void); extern unsigned long e820_end_of_low_ram_pfn(void); extern u64 early_reserve_e820(u64 startt, u64 sizet, u64 align); diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h index 7093e4a6a0bc..b8d8bfcd44a9 100644 --- a/arch/x86/include/asm/efi.h +++ b/arch/x86/include/asm/efi.h @@ -33,8 +33,6 @@ extern unsigned long asmlinkage efi_call_phys(void *, ...); #define efi_call_virt6(f, a1, a2, a3, a4, a5, a6) \ efi_call_virt(f, a1, a2, a3, a4, a5, a6) -#define efi_ioremap(addr, size, type) ioremap_cache(addr, size) - #else /* !CONFIG_X86_32 */ extern u64 efi_call0(void *fp); @@ -84,9 +82,6 @@ extern u64 efi_call6(void *fp, u64 arg1, u64 arg2, u64 arg3, efi_call6((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2), \ (u64)(a3), (u64)(a4), (u64)(a5), (u64)(a6)) -extern void __iomem *efi_ioremap(unsigned long addr, unsigned long size, - u32 type); - #endif /* CONFIG_X86_32 */ extern int add_efi_memmap; diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h index 4420993acc47..925b605eb5c6 100644 --- a/arch/x86/include/asm/intel_scu_ipc.h +++ b/arch/x86/include/asm/intel_scu_ipc.h @@ -3,11 +3,15 @@ #include <linux/notifier.h> -#define IPCMSG_VRTC 0xFA /* Set vRTC device */ - -/* Command id associated with message IPCMSG_VRTC */ -#define IPC_CMD_VRTC_SETTIME 1 /* Set time */ -#define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */ +#define IPCMSG_WARM_RESET 0xF0 +#define IPCMSG_COLD_RESET 0xF1 +#define IPCMSG_SOFT_RESET 0xF2 +#define IPCMSG_COLD_BOOT 0xF3 + +#define IPCMSG_VRTC 0xFA /* Set vRTC device */ + /* Command id associated with message IPCMSG_VRTC */ + #define IPC_CMD_VRTC_SETTIME 1 /* Set time */ + #define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */ /* Read single register */ int intel_scu_ipc_ioread8(u16 addr, u8 *data); diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h index e6283129c821..93f79094c224 100644 --- a/arch/x86/include/asm/mrst.h +++ b/arch/x86/include/asm/mrst.h @@ -31,11 +31,20 @@ enum mrst_cpu_type { }; extern enum mrst_cpu_type __mrst_cpu_chip; + +#ifdef CONFIG_X86_INTEL_MID + static inline enum mrst_cpu_type mrst_identify_cpu(void) { return __mrst_cpu_chip; } +#else /* !CONFIG_X86_INTEL_MID */ + +#define mrst_identify_cpu() (0) + +#endif /* !CONFIG_X86_INTEL_MID */ + enum mrst_timer_options { MRST_TIMER_DEFAULT, MRST_TIMER_APBT_ONLY, diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 084ef95274cd..95203d40ffdd 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -169,7 +169,14 @@ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) return native_write_msr_safe(msr, low, high); } -/* rdmsr with exception handling */ +/* + * rdmsr with exception handling. + * + * Please note that the exception handling works only after we've + * switched to the "smart" #GP handler in trap_init() which knows about + * exception tables - using this macro earlier than that causes machine + * hangs on boxes which do not implement the @msr in the first argument. + */ #define rdmsr_safe(msr, p1, p2) \ ({ \ int __err; \ diff --git a/arch/x86/include/asm/system.h b/arch/x86/include/asm/system.h index c2ff2a1d845e..2d2f01ce6dcb 100644 --- a/arch/x86/include/asm/system.h +++ b/arch/x86/include/asm/system.h @@ -401,6 +401,7 @@ extern unsigned long arch_align_stack(unsigned long sp); extern void free_init_pages(char *what, unsigned long begin, unsigned long end); void default_idle(void); +bool set_pm_idle_to_default(void); void stop_this_cpu(void *dummy); diff --git a/arch/x86/include/asm/timer.h b/arch/x86/include/asm/timer.h index fa7b9176b76c..431793e5d484 100644 --- a/arch/x86/include/asm/timer.h +++ b/arch/x86/include/asm/timer.h @@ -32,6 +32,22 @@ extern int no_timer_check; * (mathieu.desnoyers@polymtl.ca) * * -johnstul@us.ibm.com "math is hard, lets go shopping!" + * + * In: + * + * ns = cycles * cyc2ns_scale / SC + * + * Although we may still have enough bits to store the value of ns, + * in some cases, we may not have enough bits to store cycles * cyc2ns_scale, + * leading to an incorrect result. + * + * To avoid this, we can decompose 'cycles' into quotient and remainder + * of division by SC. Then, + * + * ns = (quot * SC + rem) * cyc2ns_scale / SC + * = quot * cyc2ns_scale + (rem * cyc2ns_scale) / SC + * + * - sqazi@google.com */ DECLARE_PER_CPU(unsigned long, cyc2ns); @@ -41,9 +57,14 @@ DECLARE_PER_CPU(unsigned long long, cyc2ns_offset); static inline unsigned long long __cycles_2_ns(unsigned long long cyc) { + unsigned long long quot; + unsigned long long rem; int cpu = smp_processor_id(); unsigned long long ns = per_cpu(cyc2ns_offset, cpu); - ns += cyc * per_cpu(cyc2ns, cpu) >> CYC2NS_SCALE_FACTOR; + quot = (cyc >> CYC2NS_SCALE_FACTOR); + rem = cyc & ((1ULL << CYC2NS_SCALE_FACTOR) - 1); + ns += quot * per_cpu(cyc2ns, cpu) + + ((rem * per_cpu(cyc2ns, cpu)) >> CYC2NS_SCALE_FACTOR); return ns; } diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h index 10474fb1185d..cf1d73643f60 100644 --- a/arch/x86/include/asm/uv/uv_mmrs.h +++ b/arch/x86/include/asm/uv/uv_mmrs.h @@ -57,6 +57,7 @@ #define UV1_HUB_PART_NUMBER 0x88a5 #define UV2_HUB_PART_NUMBER 0x8eb8 +#define UV2_HUB_PART_NUMBER_X 0x1111 /* Compat: if this #define is present, UV headers support UV2 */ #define UV2_HUB_IS_SUPPORTED 1 diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index 62ae3001ae02..9d59bbacd4e3 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -93,6 +93,8 @@ static int __init early_get_pnodeid(void) if (node_id.s.part_number == UV2_HUB_PART_NUMBER) uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; + if (node_id.s.part_number == UV2_HUB_PART_NUMBER_X) + uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; uv_hub_info->hub_revision = uv_min_hub_revision_id; pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index c7e46cb35327..0bab2b18bb20 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -442,8 +442,6 @@ static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c) static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) { - u32 dummy; - early_init_amd_mc(c); /* @@ -473,12 +471,12 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_EXTD_APICID); } #endif - - rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); } static void __cpuinit init_amd(struct cpuinfo_x86 *c) { + u32 dummy; + #ifdef CONFIG_SMP unsigned long long value; @@ -657,6 +655,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask); } } + + rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); } #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index a71efcdbb092..97b26356e9ee 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -547,6 +547,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base, if (tmp != mask_lo) { printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n"); + add_taint(TAINT_FIRMWARE_WORKAROUND); mask_lo = tmp; } } @@ -693,6 +694,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock) /* Disable MTRRs, and set the default type to uncached */ mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); + wbinvd(); } static void post_set(void) __releases(set_atomicity_lock) diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 640891014b2a..2bda212a0010 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -312,12 +312,8 @@ int x86_setup_perfctr(struct perf_event *event) return -EOPNOTSUPP; } - /* - * Do not allow config1 (extended registers) to propagate, - * there's no sane user-space generalization yet: - */ if (attr->type == PERF_TYPE_RAW) - return 0; + return x86_pmu_extra_regs(event->attr.config, event); if (attr->type == PERF_TYPE_HW_CACHE) return set_ext_hw_attr(hwc, event); @@ -588,7 +584,7 @@ done: x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); } } - return num ? -ENOSPC : 0; + return num ? -EINVAL : 0; } /* @@ -607,7 +603,7 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, if (is_x86_event(leader)) { if (n >= max_count) - return -ENOSPC; + return -EINVAL; cpuc->event_list[n] = leader; n++; } @@ -620,7 +616,7 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, continue; if (n >= max_count) - return -ENOSPC; + return -EINVAL; cpuc->event_list[n] = event; n++; @@ -1316,7 +1312,7 @@ static int validate_event(struct perf_event *event) c = x86_pmu.get_event_constraints(fake_cpuc, event); if (!c || !c->weight) - ret = -ENOSPC; + ret = -EINVAL; if (x86_pmu.put_event_constraints) x86_pmu.put_event_constraints(fake_cpuc, event); @@ -1341,7 +1337,7 @@ static int validate_group(struct perf_event *event) { struct perf_event *leader = event->group_leader; struct cpu_hw_events *fake_cpuc; - int ret = -ENOSPC, n; + int ret = -EINVAL, n; fake_cpuc = allocate_fake_cpuc(); if (IS_ERR(fake_cpuc)) diff --git a/arch/x86/kernel/cpu/perf_event_amd_ibs.c b/arch/x86/kernel/cpu/perf_event_amd_ibs.c index ab6343d21825..3b8a2d30d14e 100644 --- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c +++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c @@ -199,8 +199,7 @@ static int force_ibs_eilvt_setup(void) goto out; } - pr_err(FW_BUG "using offset %d for IBS interrupts\n", offset); - pr_err(FW_BUG "workaround enabled for IBS LVT offset\n"); + pr_info("IBS: LVT offset %d assigned\n", offset); return 0; out: @@ -265,19 +264,23 @@ perf_ibs_cpu_notifier(struct notifier_block *self, unsigned long action, void *h static __init int amd_ibs_init(void) { u32 caps; - int ret; + int ret = -EINVAL; caps = __get_ibs_caps(); if (!caps) return -ENODEV; /* ibs not supported by the cpu */ - if (!ibs_eilvt_valid()) { - ret = force_ibs_eilvt_setup(); - if (ret) { - pr_err("Failed to setup IBS, %d\n", ret); - return ret; - } - } + /* + * Force LVT offset assignment for family 10h: The offsets are + * not assigned by the BIOS for this family, so the OS is + * responsible for doing it. If the OS assignment fails, fall + * back to BIOS settings and try to setup this. + */ + if (boot_cpu_data.x86 == 0x10) + force_ibs_eilvt_setup(); + + if (!ibs_eilvt_valid()) + goto out; get_online_cpus(); ibs_caps = caps; @@ -287,7 +290,11 @@ static __init int amd_ibs_init(void) smp_call_function(setup_APIC_ibs, NULL, 1); put_online_cpus(); - return perf_event_ibs_init(); + ret = perf_event_ibs_init(); +out: + if (ret) + pr_err("Failed to setup IBS, %d\n", ret); + return ret; } /* Since we need the pci subsystem to init ibs we can't do this earlier: */ diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 2be5ebe99872..8d601b18bf9f 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -1545,6 +1545,13 @@ static void intel_clovertown_quirks(void) x86_pmu.pebs_constraints = NULL; } +static void intel_sandybridge_quirks(void) +{ + printk(KERN_WARNING "PEBS disabled due to CPU errata.\n"); + x86_pmu.pebs = 0; + x86_pmu.pebs_constraints = NULL; +} + __init int intel_pmu_init(void) { union cpuid10_edx edx; @@ -1694,6 +1701,7 @@ __init int intel_pmu_init(void) break; case 42: /* SandyBridge */ + x86_pmu.quirks = intel_sandybridge_quirks; case 45: /* SandyBridge, "Romely-EP" */ memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids)); diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index c0d238f49db8..73da6b64f5b7 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c @@ -493,6 +493,7 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs) unsigned long from = cpuc->lbr_entries[0].from; unsigned long old_to, to = cpuc->lbr_entries[0].to; unsigned long ip = regs->ip; + int is_64bit = 0; /* * We don't need to fixup if the PEBS assist is fault like @@ -544,7 +545,10 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs) } else kaddr = (void *)to; - kernel_insn_init(&insn, kaddr); +#ifdef CONFIG_X86_64 + is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32); +#endif + insn_init(&insn, kaddr, is_64bit); insn_get_length(&insn); to += insn.length; } while (to < ip); diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c index 492bf1358a7c..ef484d9d0a25 100644 --- a/arch/x86/kernel/cpu/perf_event_p4.c +++ b/arch/x86/kernel/cpu/perf_event_p4.c @@ -1268,7 +1268,7 @@ reserve: } done: - return num ? -ENOSPC : 0; + return num ? -EINVAL : 0; } static __initconst const struct x86_pmu p4_pmu = { diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index 303a0e48f076..65ffd110a81b 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -135,6 +135,7 @@ static void __init e820_print_type(u32 type) printk(KERN_CONT "(usable)"); break; case E820_RESERVED: + case E820_RESERVED_EFI: printk(KERN_CONT "(reserved)"); break; case E820_ACPI: @@ -783,7 +784,7 @@ u64 __init early_reserve_e820(u64 startt, u64 sizet, u64 align) /* * Find the highest page frame number we have available */ -static unsigned long __init e820_end_pfn(unsigned long limit_pfn, unsigned type) +unsigned long __init e820_end_pfn(unsigned long limit_pfn, unsigned type) { int i; unsigned long last_pfn = 0; diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index b946a9eac7d9..1bb0bf4d92cd 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -1049,6 +1049,14 @@ int hpet_rtc_timer_init(void) } EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); +static void hpet_disable_rtc_channel(void) +{ + unsigned long cfg; + cfg = hpet_readl(HPET_T1_CFG); + cfg &= ~HPET_TN_ENABLE; + hpet_writel(cfg, HPET_T1_CFG); +} + /* * The functions below are called from rtc driver. * Return 0 if HPET is not being used. @@ -1060,6 +1068,9 @@ int hpet_mask_rtc_irq_bit(unsigned long bit_mask) return 0; hpet_rtc_flags &= ~bit_mask; + if (unlikely(!hpet_rtc_flags)) + hpet_disable_rtc_channel(); + return 1; } EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); @@ -1125,15 +1136,11 @@ EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); static void hpet_rtc_timer_reinit(void) { - unsigned int cfg, delta; + unsigned int delta; int lost_ints = -1; - if (unlikely(!hpet_rtc_flags)) { - cfg = hpet_readl(HPET_T1_CFG); - cfg &= ~HPET_TN_ENABLE; - hpet_writel(cfg, HPET_T1_CFG); - return; - } + if (unlikely(!hpet_rtc_flags)) + hpet_disable_rtc_channel(); if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) delta = hpet_default_delta; diff --git a/arch/x86/kernel/irq_64.c b/arch/x86/kernel/irq_64.c index acf8fbf8fbda..69bca468c47a 100644 --- a/arch/x86/kernel/irq_64.c +++ b/arch/x86/kernel/irq_64.c @@ -38,6 +38,9 @@ static inline void stack_overflow_check(struct pt_regs *regs) #ifdef CONFIG_DEBUG_STACKOVERFLOW u64 curbase = (u64)task_stack_page(current); + if (user_mode_vm(regs)) + return; + WARN_ONCE(regs->sp >= curbase && regs->sp <= curbase + THREAD_SIZE && regs->sp < curbase + sizeof(struct thread_info) + diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index f2d2a664e797..9d46f5e43b51 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -256,7 +256,7 @@ static int __init microcode_dev_init(void) return 0; } -static void microcode_dev_exit(void) +static void __exit microcode_dev_exit(void) { misc_deregister(µcode_dev); } @@ -519,10 +519,8 @@ static int __init microcode_init(void) microcode_pdev = platform_device_register_simple("microcode", -1, NULL, 0); - if (IS_ERR(microcode_pdev)) { - microcode_dev_exit(); + if (IS_ERR(microcode_pdev)) return PTR_ERR(microcode_pdev); - } get_online_cpus(); mutex_lock(µcode_mutex); @@ -532,14 +530,12 @@ static int __init microcode_init(void) mutex_unlock(µcode_mutex); put_online_cpus(); - if (error) { - platform_device_unregister(microcode_pdev); - return error; - } + if (error) + goto out_pdev; error = microcode_dev_init(); if (error) - return error; + goto out_sysdev_driver; register_syscore_ops(&mc_syscore_ops); register_hotcpu_notifier(&mc_cpu_notifier); @@ -548,6 +544,20 @@ static int __init microcode_init(void) " <tigran@aivazian.fsnet.co.uk>, Peter Oruba\n"); return 0; + +out_sysdev_driver: + get_online_cpus(); + mutex_lock(µcode_mutex); + + sysdev_driver_unregister(&cpu_sysdev_class, &mc_sysdev_driver); + + mutex_unlock(µcode_mutex); + put_online_cpus(); + +out_pdev: + platform_device_unregister(microcode_pdev); + return error; + } module_init(microcode_init); diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index 9103b89c145a..0741b062a304 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -95,8 +95,8 @@ static void __init MP_bus_info(struct mpc_bus *m) } #endif + set_bit(m->busid, mp_bus_not_pci); if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { - set_bit(m->busid, mp_bus_not_pci); #if defined(CONFIG_EISA) || defined(CONFIG_MCA) mp_bus_id_to_type[m->busid] = MP_BUS_ISA; #endif diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index b9b3b1a51643..ee5d4fbd53b4 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -403,6 +403,14 @@ void default_idle(void) EXPORT_SYMBOL(default_idle); #endif +bool set_pm_idle_to_default(void) +{ + bool ret = !!pm_idle; + + pm_idle = default_idle; + + return ret; +} void stop_this_cpu(void *dummy) { local_irq_disable(); diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c index b78643d0f9a5..03920a15a632 100644 --- a/arch/x86/kernel/quirks.c +++ b/arch/x86/kernel/quirks.c @@ -553,4 +553,17 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC, quirk_amd_nb_node); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_LINK, quirk_amd_nb_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F0, + quirk_amd_nb_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F1, + quirk_amd_nb_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F2, + quirk_amd_nb_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3, + quirk_amd_nb_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4, + quirk_amd_nb_node); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5, + quirk_amd_nb_node); + #endif diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index e334be1182b9..37a458b521a6 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -124,7 +124,7 @@ __setup("reboot=", reboot_setup); */ /* - * Some machines require the "reboot=b" commandline option, + * Some machines require the "reboot=b" or "reboot=k" commandline options, * this quirk makes that automatic. */ static int __init set_bios_reboot(const struct dmi_system_id *d) @@ -136,6 +136,15 @@ static int __init set_bios_reboot(const struct dmi_system_id *d) return 0; } +static int __init set_kbd_reboot(const struct dmi_system_id *d) +{ + if (reboot_type != BOOT_KBD) { + reboot_type = BOOT_KBD; + printk(KERN_INFO "%s series board detected. Selecting KBD-method for reboot.\n", d->ident); + } + return 0; +} + static struct dmi_system_id __initdata reboot_dmi_table[] = { { /* Handle problems with rebooting on Dell E520's */ .callback = set_bios_reboot, @@ -295,7 +304,7 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = { }, }, { /* Handle reboot issue on Acer Aspire one */ - .callback = set_bios_reboot, + .callback = set_kbd_reboot, .ident = "Acer Aspire One A110", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Acer"), @@ -443,6 +452,14 @@ static struct dmi_system_id __initdata pci_reboot_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "Latitude E6420"), }, }, + { /* Handle problems with rebooting on the OptiPlex 990. */ + .callback = set_pci_reboot, + .ident = "Dell OptiPlex 990", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 990"), + }, + }, { } }; diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c index 348ce016a835..af6db6ec5b2a 100644 --- a/arch/x86/kernel/rtc.c +++ b/arch/x86/kernel/rtc.c @@ -12,6 +12,7 @@ #include <asm/vsyscall.h> #include <asm/x86_init.h> #include <asm/time.h> +#include <asm/mrst.h> #ifdef CONFIG_X86_32 /* @@ -242,6 +243,10 @@ static __init int add_rtc_cmos(void) if (of_have_populated_dt()) return 0; + /* Intel MID platforms don't have ioport rtc */ + if (mrst_identify_cpu()) + return -ENODEV; + platform_device_register(&rtc_device); dev_info(&rtc_device.dev, "registered platform RTC device (no PNP device found)\n"); diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index cf0ef986cb6d..9a9e40fb091c 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -691,6 +691,8 @@ early_param("reservelow", parse_reservelow); void __init setup_arch(char **cmdline_p) { + unsigned long end_pfn; + #ifdef CONFIG_X86_32 memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data)); visws_early_detect(); @@ -932,7 +934,24 @@ void __init setup_arch(char **cmdline_p) init_gbpages(); /* max_pfn_mapped is updated here */ - max_low_pfn_mapped = init_memory_mapping(0, max_low_pfn<<PAGE_SHIFT); + end_pfn = max_low_pfn; + +#ifdef CONFIG_X86_64 + /* + * There may be regions after the last E820_RAM region that we + * want to include in the kernel direct mapping, such as + * EFI_RUNTIME_SERVICES_DATA. + */ + if (efi_enabled) { + unsigned long efi_end; + + efi_end = e820_end_pfn(MAXMEM>>PAGE_SHIFT, E820_RESERVED_EFI); + if (efi_end > max_low_pfn) + end_pfn = efi_end; + } +#endif + + max_low_pfn_mapped = init_memory_mapping(0, end_pfn << PAGE_SHIFT); max_pfn_mapped = max_low_pfn_mapped; #ifdef CONFIG_X86_64 diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c index ea305856151c..dd74e46828c0 100644 --- a/arch/x86/mm/gup.c +++ b/arch/x86/mm/gup.c @@ -201,6 +201,8 @@ static noinline int gup_huge_pud(pud_t pud, unsigned long addr, do { VM_BUG_ON(compound_head(page) != head); pages[*nr] = page; + if (PageTail(page)) + get_huge_page_tail(page); (*nr)++; page++; refs++; diff --git a/arch/x86/mm/highmem_32.c b/arch/x86/mm/highmem_32.c index b49962662101..f4f29b19fac5 100644 --- a/arch/x86/mm/highmem_32.c +++ b/arch/x86/mm/highmem_32.c @@ -45,6 +45,7 @@ void *kmap_atomic_prot(struct page *page, pgprot_t prot) vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); BUG_ON(!pte_none(*(kmap_pte-idx))); set_pte(kmap_pte-idx, mk_pte(page, prot)); + arch_flush_lazy_mmu_mode(); return (void *)vaddr; } @@ -88,6 +89,7 @@ void __kunmap_atomic(void *kvaddr) */ kpte_clear_flush(kmap_pte-idx, vaddr); kmap_atomic_idx_pop(); + arch_flush_lazy_mmu_mode(); } #ifdef CONFIG_DEBUG_HIGHMEM else { diff --git a/arch/x86/oprofile/init.c b/arch/x86/oprofile/init.c index cdfe4c54deca..f148cf652678 100644 --- a/arch/x86/oprofile/init.c +++ b/arch/x86/oprofile/init.c @@ -21,6 +21,7 @@ extern int op_nmi_timer_init(struct oprofile_operations *ops); extern void op_nmi_exit(void); extern void x86_backtrace(struct pt_regs * const regs, unsigned int depth); +static int nmi_timer; int __init oprofile_arch_init(struct oprofile_operations *ops) { @@ -31,8 +32,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) #ifdef CONFIG_X86_LOCAL_APIC ret = op_nmi_init(ops); #endif + nmi_timer = (ret != 0); #ifdef CONFIG_X86_IO_APIC - if (ret < 0) + if (nmi_timer) ret = op_nmi_timer_init(ops); #endif ops->backtrace = x86_backtrace; @@ -44,6 +46,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) void oprofile_arch_exit(void) { #ifdef CONFIG_X86_LOCAL_APIC - op_nmi_exit(); + if (!nmi_timer) + op_nmi_exit(); #endif } diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c index 37718f0f053d..c9718a16be15 100644 --- a/arch/x86/platform/efi/efi.c +++ b/arch/x86/platform/efi/efi.c @@ -323,10 +323,13 @@ static void __init do_add_efi_memmap(void) case EFI_UNUSABLE_MEMORY: e820_type = E820_UNUSABLE; break; + case EFI_RUNTIME_SERVICES_DATA: + e820_type = E820_RESERVED_EFI; + break; default: /* * EFI_RESERVED_TYPE EFI_RUNTIME_SERVICES_CODE - * EFI_RUNTIME_SERVICES_DATA EFI_MEMORY_MAPPED_IO + * EFI_MEMORY_MAPPED_IO * EFI_MEMORY_MAPPED_IO_PORT_SPACE EFI_PAL_CODE */ e820_type = E820_RESERVED; @@ -671,10 +674,21 @@ void __init efi_enter_virtual_mode(void) end_pfn = PFN_UP(end); if (end_pfn <= max_low_pfn_mapped || (end_pfn > (1UL << (32 - PAGE_SHIFT)) - && end_pfn <= max_pfn_mapped)) + && end_pfn <= max_pfn_mapped)) { va = __va(md->phys_addr); - else - va = efi_ioremap(md->phys_addr, size, md->type); + + if (!(md->attribute & EFI_MEMORY_WB)) { + addr = (u64) (unsigned long)va; + npages = md->num_pages; + memrange_efi_to_native(&addr, &npages); + set_memory_uc(addr, npages); + } + } else { + if (!(md->attribute & EFI_MEMORY_WB)) + va = ioremap_nocache(md->phys_addr, size); + else + va = ioremap_cache(md->phys_addr, size); + } md->virt_addr = (u64) (unsigned long) va; @@ -684,13 +698,6 @@ void __init efi_enter_virtual_mode(void) continue; } - if (!(md->attribute & EFI_MEMORY_WB)) { - addr = md->virt_addr; - npages = md->num_pages; - memrange_efi_to_native(&addr, &npages); - set_memory_uc(addr, npages); - } - systab = (u64) (unsigned long) efi_phys.systab; if (md->phys_addr <= systab && systab < end) { systab += md->virt_addr - md->phys_addr; diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c index ac3aa54e2654..312250c6b2de 100644 --- a/arch/x86/platform/efi/efi_64.c +++ b/arch/x86/platform/efi/efi_64.c @@ -80,20 +80,3 @@ void __init efi_call_phys_epilog(void) local_irq_restore(efi_flags); early_code_mapping_set_exec(0); } - -void __iomem *__init efi_ioremap(unsigned long phys_addr, unsigned long size, - u32 type) -{ - unsigned long last_map_pfn; - - if (type == EFI_MEMORY_MAPPED_IO) - return ioremap(phys_addr, size); - - last_map_pfn = init_memory_mapping(phys_addr, phys_addr + size); - if ((last_map_pfn << PAGE_SHIFT) < phys_addr + size) { - unsigned long top = last_map_pfn << PAGE_SHIFT; - efi_ioremap(top, size - (top - phys_addr), type); - } - - return (void __iomem *)__va(phys_addr); -} diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c index b1489a06a49d..ad4ec1cb097e 100644 --- a/arch/x86/platform/mrst/mrst.c +++ b/arch/x86/platform/mrst/mrst.c @@ -76,6 +76,20 @@ struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX]; EXPORT_SYMBOL_GPL(sfi_mrtc_array); int sfi_mrtc_num; +static void mrst_power_off(void) +{ + if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) + intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 1); +} + +static void mrst_reboot(void) +{ + if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) + intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0); + else + intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0); +} + /* parse all the mtimer info to a static mtimer array */ static int __init sfi_parse_mtmr(struct sfi_table_header *table) { @@ -265,17 +279,6 @@ static int mrst_i8042_detect(void) return 0; } -/* Reboot and power off are handled by the SCU on a MID device */ -static void mrst_power_off(void) -{ - intel_scu_ipc_simple_command(0xf1, 1); -} - -static void mrst_reboot(void) -{ - intel_scu_ipc_simple_command(0xf1, 0); -} - /* * Moorestown does not have external NMI source nor port 0x61 to report * NMI status. The possible NMI sources are from pmu as a result of NMI @@ -484,6 +487,46 @@ static void __init *max7315_platform_data(void *info) return max7315; } +static void *tca6416_platform_data(void *info) +{ + static struct pca953x_platform_data tca6416; + struct i2c_board_info *i2c_info = info; + int gpio_base, intr; + char base_pin_name[SFI_NAME_LEN + 1]; + char intr_pin_name[SFI_NAME_LEN + 1]; + + strcpy(i2c_info->type, "tca6416"); + strcpy(base_pin_name, "tca6416_base"); + strcpy(intr_pin_name, "tca6416_int"); + + gpio_base = get_gpio_by_name(base_pin_name); + intr = get_gpio_by_name(intr_pin_name); + + if (gpio_base == -1) + return NULL; + tca6416.gpio_base = gpio_base; + if (intr != -1) { + i2c_info->irq = intr + MRST_IRQ_OFFSET; + tca6416.irq_base = gpio_base + MRST_IRQ_OFFSET; + } else { + i2c_info->irq = -1; + tca6416.irq_base = -1; + } + return &tca6416; +} + +static void *mpu3050_platform_data(void *info) +{ + struct i2c_board_info *i2c_info = info; + int intr = get_gpio_by_name("mpu3050_int"); + + if (intr == -1) + return NULL; + + i2c_info->irq = intr + MRST_IRQ_OFFSET; + return NULL; +} + static void __init *emc1403_platform_data(void *info) { static short intr2nd_pdata; @@ -646,12 +689,15 @@ static void *msic_ocd_platform_data(void *info) static const struct devs_id __initconst device_ids[] = { {"bma023", SFI_DEV_TYPE_I2C, 1, &no_platform_data}, {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data}, + {"pmic_gpio", SFI_DEV_TYPE_IPC, 1, &pmic_gpio_platform_data}, {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data}, {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data}, {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data}, + {"tca6416", SFI_DEV_TYPE_I2C, 1, &tca6416_platform_data}, {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data}, {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data}, {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data}, + {"mpu3050", SFI_DEV_TYPE_I2C, 1, &mpu3050_platform_data}, /* MSIC subdevices */ {"msic_battery", SFI_DEV_TYPE_IPC, 1, &msic_battery_platform_data}, diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index 38d0af4fefec..1093f80c162d 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c @@ -410,6 +410,6 @@ void __init xen_arch_setup(void) #endif disable_cpuidle(); boot_option_idle_override = IDLE_HALT; - + WARN_ON(set_pm_idle_to_default()); fiddle_vdso(); } |