diff options
Diffstat (limited to 'drivers/clk/clk-sp7021.c')
| -rw-r--r-- | drivers/clk/clk-sp7021.c | 61 |
1 files changed, 28 insertions, 33 deletions
diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c index 11d22043ddd7..36528a71a2e6 100644 --- a/drivers/clk/clk-sp7021.c +++ b/drivers/clk/clk-sp7021.c @@ -7,6 +7,7 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/bitfield.h> +#include <linux/hw_bitfield.h> #include <linux/slab.h> #include <linux/io.h> #include <linux/err.h> @@ -14,7 +15,7 @@ #include <dt-bindings/clock/sunplus,sp7021-clkc.h> -/* speical div_width values for PLLTV/PLLA */ +/* special div_width values for PLLTV/PLLA */ #define DIV_TV 33 #define DIV_A 34 @@ -38,13 +39,6 @@ enum { #define MASK_DIVN GENMASK(7, 0) #define MASK_DIVM GENMASK(14, 8) -/* HIWORD_MASK FIELD_PREP */ -#define HWM_FIELD_PREP(mask, value) \ -({ \ - u64 _m = mask; \ - (_m << 16) | FIELD_PREP(_m, value); \ -}) - struct sp_pll { struct clk_hw hw; void __iomem *reg; @@ -313,15 +307,15 @@ static int plltv_set_rate(struct sp_pll *clk) u32 r0, r1, r2; r0 = BIT(clk->bp_bit + 16); - r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]); - r0 |= HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]); - r0 |= HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]); - r0 |= HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]); + r0 |= FIELD_PREP_WM16(MASK_SEL_FRA, clk->p[SEL_FRA]); + r0 |= FIELD_PREP_WM16(MASK_SDM_MOD, clk->p[SDM_MOD]); + r0 |= FIELD_PREP_WM16(MASK_PH_SEL, clk->p[PH_SEL]); + r0 |= FIELD_PREP_WM16(MASK_NFRA, clk->p[NFRA]); - r1 = HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]); + r1 = FIELD_PREP_WM16(MASK_DIVR, clk->p[DIVR]); - r2 = HWM_FIELD_PREP(MASK_DIVN, clk->p[DIVN] - 1); - r2 |= HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1); + r2 = FIELD_PREP_WM16(MASK_DIVN, clk->p[DIVN] - 1); + r2 |= FIELD_PREP_WM16(MASK_DIVM, clk->p[DIVM] - 1); spin_lock_irqsave(&clk->lock, flags); writel(r0, clk->reg); @@ -412,25 +406,27 @@ static long sp_pll_calc_div(struct sp_pll *clk, unsigned long rate) return fbdiv; } -static long sp_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int sp_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct sp_pll *clk = to_sp_pll(hw); long ret; - if (rate == *prate) { - ret = *prate; /* bypass */ + if (req->rate == req->best_parent_rate) { + ret = req->best_parent_rate; /* bypass */ } else if (clk->div_width == DIV_A) { - ret = plla_round_rate(clk, rate); + ret = plla_round_rate(clk, req->rate); } else if (clk->div_width == DIV_TV) { - ret = plltv_div(clk, rate); + ret = plltv_div(clk, req->rate); if (ret < 0) - ret = *prate; + ret = req->best_parent_rate; } else { - ret = sp_pll_calc_div(clk, rate) * clk->brate; + ret = sp_pll_calc_div(clk, req->rate) * clk->brate; } - return ret; + req->rate = ret; + + return 0; } static unsigned long sp_pll_recalc_rate(struct clk_hw *hw, @@ -535,7 +531,7 @@ static const struct clk_ops sp_pll_ops = { .enable = sp_pll_enable, .disable = sp_pll_disable, .is_enabled = sp_pll_is_enabled, - .round_rate = sp_pll_round_rate, + .determine_rate = sp_pll_determine_rate, .recalc_rate = sp_pll_recalc_rate, .set_rate = sp_pll_set_rate }; @@ -604,14 +600,14 @@ static int sp7021_clk_probe(struct platform_device *pdev) int i; clk_base = devm_platform_ioremap_resource(pdev, 0); - if (!clk_base) - return -ENXIO; + if (IS_ERR(clk_base)) + return PTR_ERR(clk_base); pll_base = devm_platform_ioremap_resource(pdev, 1); - if (!pll_base) - return -ENXIO; + if (IS_ERR(pll_base)) + return PTR_ERR(pll_base); sys_base = devm_platform_ioremap_resource(pdev, 2); - if (!sys_base) - return -ENXIO; + if (IS_ERR(sys_base)) + return PTR_ERR(sys_base); /* enable default clks */ for (i = 0; i < ARRAY_SIZE(sp_clken); i++) @@ -621,6 +617,7 @@ static int sp7021_clk_probe(struct platform_device *pdev) GFP_KERNEL); if (!clk_data) return -ENOMEM; + clk_data->num = CLK_MAX; hws = clk_data->hws; pd_ext.index = 0; @@ -688,8 +685,6 @@ static int sp7021_clk_probe(struct platform_device *pdev) return PTR_ERR(hws[i]); } - clk_data->num = CLK_MAX; - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); } |