1 files changed, 65 insertions, 26 deletions

diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c
index 7e9134b205ab..6ca53a960eb7 100644
--- a/drivers/clk/imx/clk-pfdv2.c
+++ b/drivers/clk/imx/clk-pfdv2.c
@@ -9,6 +9,7 @@
 
 #include <linux/clk-provider.h>
 #include <linux/err.h>
+#include <linux/io.h>
 #include <linux/iopoll.h>
 #include <linux/slab.h>
 
@@ -16,7 +17,7 @@
 
 /**
  * struct clk_pfdv2 - IMX PFD clock
- * @clk_hw:	clock source
+ * @hw:		clock source
  * @reg:	PFD register address
  * @gate_bit:	Gate bit offset
  * @vld_bit:	Valid bit offset
@@ -43,7 +44,7 @@ static int clk_pfdv2_wait(struct clk_pfdv2 *pfd)
 {
 	u32 val;
 
-	return readl_poll_timeout(pfd->reg, val, val & pfd->vld_bit,
+	return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit),
 				  0, LOCK_TIMEOUT_US);
 }
 
@@ -55,7 +56,7 @@ static int clk_pfdv2_enable(struct clk_hw *hw)
 
 	spin_lock_irqsave(&pfd_lock, flags);
 	val = readl_relaxed(pfd->reg);
-	val &= ~pfd->gate_bit;
+	val &= ~(1 << pfd->gate_bit);
 	writel_relaxed(val, pfd->reg);
 	spin_unlock_irqrestore(&pfd_lock, flags);
 
@@ -70,7 +71,7 @@ static void clk_pfdv2_disable(struct clk_hw *hw)
 
 	spin_lock_irqsave(&pfd_lock, flags);
 	val = readl_relaxed(pfd->reg);
-	val |= pfd->gate_bit;
+	val |= (1 << pfd->gate_bit);
 	writel_relaxed(val, pfd->reg);
 	spin_unlock_irqrestore(&pfd_lock, flags);
 }
@@ -97,33 +98,52 @@ static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
 	return tmp;
 }
 
-static long clk_pfdv2_round_rate(struct clk_hw *hw, unsigned long rate,
-				 unsigned long *prate)
+static int clk_pfdv2_determine_rate(struct clk_hw *hw,
+				    struct clk_rate_request *req)
 {
-	u64 tmp = *prate;
+	unsigned long parent_rates[] = {
+					480000000,
+					528000000,
+					req->best_parent_rate
+				       };
+	unsigned long best_rate = -1UL, rate = req->rate;
+	unsigned long best_parent_rate = req->best_parent_rate;
+	u64 tmp;
 	u8 frac;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(parent_rates); i++) {
+		tmp = parent_rates[i];
+		tmp = tmp * 18 + rate / 2;
+		do_div(tmp, rate);
+		frac = tmp;
+
+		if (frac < 12)
+			frac = 12;
+		else if (frac > 35)
+			frac = 35;
+
+		tmp = parent_rates[i];
+		tmp *= 18;
+		do_div(tmp, frac);
+
+		if (abs(tmp - req->rate) < abs(best_rate - req->rate)) {
+			best_rate = tmp;
+			best_parent_rate = parent_rates[i];
+		}
+	}
 
-	tmp = tmp * 18 + rate / 2;
-	do_div(tmp, rate);
-	frac = tmp;
-
-	if (frac < 12)
-		frac = 12;
-	else if (frac > 35)
-		frac = 35;
-
-	tmp = *prate;
-	tmp *= 18;
-	do_div(tmp, frac);
+	req->best_parent_rate = best_parent_rate;
+	req->rate = best_rate;
 
-	return tmp;
+	return 0;
 }
 
 static int clk_pfdv2_is_enabled(struct clk_hw *hw)
 {
 	struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
 
-	if (readl_relaxed(pfd->reg) & pfd->gate_bit)
+	if (readl_relaxed(pfd->reg) & (1 << pfd->gate_bit))
 		return 0;
 
 	return 1;
@@ -138,6 +158,21 @@ static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
 	u32 val;
 	u8 frac;
 
+	if (!rate)
+		return -EINVAL;
+
+	/*
+	 * PFD can NOT change rate without gating.
+	 * as the PFDs may enabled in HW by default but no
+	 * consumer used it, the enable count is '0', so the
+	 * 'SET_RATE_GATE' can NOT help on blocking the set_rate
+	 * ops especially for 'assigned-clock-xxx'. In order
+	 * to simplify the case, just disable the PFD if it is
+	 * enabled in HW but not in SW.
+	 */
+	if (clk_pfdv2_is_enabled(hw))
+		clk_pfdv2_disable(hw);
+
 	tmp = tmp * 18 + rate / 2;
 	do_div(tmp, rate);
 	frac = tmp;
@@ -160,13 +195,13 @@ static const struct clk_ops clk_pfdv2_ops = {
 	.enable		= clk_pfdv2_enable,
 	.disable	= clk_pfdv2_disable,
 	.recalc_rate	= clk_pfdv2_recalc_rate,
-	.round_rate	= clk_pfdv2_round_rate,
+	.determine_rate	= clk_pfdv2_determine_rate,
 	.set_rate	= clk_pfdv2_set_rate,
 	.is_enabled     = clk_pfdv2_is_enabled,
 };
 
-struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
-			     void __iomem *reg, u8 idx)
+struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name,
+			     const char *parent_name, void __iomem *reg, u8 idx)
 {
 	struct clk_init_data init;
 	struct clk_pfdv2 *pfd;
@@ -180,7 +215,7 @@ struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
 		return ERR_PTR(-ENOMEM);
 
 	pfd->reg = reg;
-	pfd->gate_bit = 1 << ((idx + 1) * 8 - 1);
+	pfd->gate_bit = (idx + 1) * 8 - 1;
 	pfd->vld_bit = pfd->gate_bit - 1;
 	pfd->frac_off = idx * 8;
 
@@ -188,7 +223,10 @@ struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
 	init.ops = &clk_pfdv2_ops;
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
-	init.flags = CLK_SET_RATE_GATE;
+	if (type == IMX_PFDV2_IMX7ULP)
+		init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT;
+	else
+		init.flags = CLK_SET_RATE_GATE;
 
 	pfd->hw.init = &init;
 
@@ -201,3 +239,4 @@ struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
 
 	return hw;
 }
+EXPORT_SYMBOL_GPL(imx_clk_hw_pfdv2);