diff options
Diffstat (limited to 'drivers/clk/imx/clk-pllv4.c')
| -rw-r--r-- | drivers/clk/imx/clk-pllv4.c | 71 |
1 files changed, 52 insertions, 19 deletions
diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c index 6e7e34571fc8..01d05b5d5438 100644 --- a/drivers/clk/imx/clk-pllv4.c +++ b/drivers/clk/imx/clk-pllv4.c @@ -44,11 +44,15 @@ struct clk_pllv4 { u32 cfg_offset; u32 num_offset; u32 denom_offset; + bool use_mult_range; }; /* Valid PLL MULT Table */ static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16}; +/* Valid PLL MULT range, (max, min) */ +static const int pllv4_mult_range[] = {54, 27}; + #define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw) #define LOCK_TIMEOUT_US USEC_PER_MSEC @@ -91,33 +95,48 @@ static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw, return (parent_rate * mult) + (u32)temp64; } -static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_pllv4_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - unsigned long parent_rate = *prate; + struct clk_pllv4 *pll = to_clk_pllv4(hw); + unsigned long parent_rate = req->best_parent_rate; unsigned long round_rate, i; u32 mfn, mfd = DEFAULT_MFD; bool found = false; u64 temp64; - - for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) { - round_rate = parent_rate * pllv4_mult_table[i]; - if (rate >= round_rate) { + u32 mult; + + if (pll->use_mult_range) { + temp64 = (u64) req->rate; + do_div(temp64, parent_rate); + mult = temp64; + if (mult >= pllv4_mult_range[1] && + mult <= pllv4_mult_range[0]) { + round_rate = parent_rate * mult; found = true; - break; + } + } else { + for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) { + round_rate = parent_rate * pllv4_mult_table[i]; + if (req->rate >= round_rate) { + found = true; + break; + } } } if (!found) { pr_warn("%s: unable to round rate %lu, parent rate %lu\n", - clk_hw_get_name(hw), rate, parent_rate); + clk_hw_get_name(hw), req->rate, parent_rate); + req->rate = 0; + return 0; } if (parent_rate <= MAX_MFD) mfd = parent_rate; - temp64 = (u64)(rate - round_rate); + temp64 = (u64)(req->rate - round_rate); temp64 *= mfd; do_div(temp64, parent_rate); mfn = temp64; @@ -128,24 +147,35 @@ static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate, * pair of mfn/mfd, we simply return the round_rate without using * the frac part. */ - if (mfn >= mfd) - return round_rate; + if (mfn >= mfd) { + req->rate = round_rate; + + return 0; + } temp64 = (u64)parent_rate; temp64 *= mfn; do_div(temp64, mfd); - return round_rate + (u32)temp64; + req->rate = round_rate + (u32)temp64; + + return 0; } -static bool clk_pllv4_is_valid_mult(unsigned int mult) +static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int mult) { int i; /* check if mult is in valid MULT table */ - for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) { - if (pllv4_mult_table[i] == mult) + if (pll->use_mult_range) { + if (mult >= pllv4_mult_range[1] && + mult <= pllv4_mult_range[0]) return true; + } else { + for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) { + if (pllv4_mult_table[i] == mult) + return true; + } } return false; @@ -160,7 +190,7 @@ static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate, mult = rate / parent_rate; - if (!clk_pllv4_is_valid_mult(mult)) + if (!clk_pllv4_is_valid_mult(pll, mult)) return -EINVAL; if (parent_rate <= MAX_MFD) @@ -206,7 +236,7 @@ static void clk_pllv4_unprepare(struct clk_hw *hw) static const struct clk_ops clk_pllv4_ops = { .recalc_rate = clk_pllv4_recalc_rate, - .round_rate = clk_pllv4_round_rate, + .determine_rate = clk_pllv4_determine_rate, .set_rate = clk_pllv4_set_rate, .prepare = clk_pllv4_prepare, .unprepare = clk_pllv4_unprepare, @@ -227,10 +257,13 @@ struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name, pll->base = base; - if (type == IMX_PLLV4_IMX8ULP) { + if (type == IMX_PLLV4_IMX8ULP || + type == IMX_PLLV4_IMX8ULP_1GHZ) { pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET; pll->num_offset = IMX8ULP_PLL_NUM_OFFSET; pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET; + if (type == IMX_PLLV4_IMX8ULP_1GHZ) + pll->use_mult_range = true; } else { pll->cfg_offset = PLL_CFG_OFFSET; pll->num_offset = PLL_NUM_OFFSET; |