diff options
Diffstat (limited to 'drivers/clk/ingenic/cgu.h')
| -rw-r--r-- | drivers/clk/ingenic/cgu.h | 63 |
1 files changed, 41 insertions, 22 deletions
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 09700b2c555d..0d417d69dab7 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -1,30 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Ingenic SoC CGU driver * * Copyright (c) 2013-2015 Imagination Technologies - * Author: Paul Burton <paul.burton@imgtec.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Author: Paul Burton <paul.burton@mips.com> */ #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ #define __DRIVERS_CLK_INGENIC_CGU_H__ #include <linux/bitops.h> +#include <linux/clk-provider.h> #include <linux/of.h> #include <linux/spinlock.h> /** * struct ingenic_cgu_pll_info - information about a PLL * @reg: the offset of the PLL's control register within the CGU + * @rate_multiplier: the multiplier needed by pll rate calculation * @m_shift: the number of bits to shift the multiplier value by (ie. the * index of the lowest bit of the multiplier value in the PLL's * control register) @@ -40,24 +33,38 @@ * @od_shift: the number of bits to shift the post-VCO divider value by (ie. * the index of the lowest bit of the post-VCO divider value in * the PLL's control register) - * @od_bits: the size of the post-VCO divider field in bits + * @od_bits: the size of the post-VCO divider field in bits, or 0 if no + * OD field exists (then the OD is fixed to 1) * @od_max: the maximum post-VCO divider value * @od_encoding: a pointer to an array mapping post-VCO divider values to * their encoded values in the PLL control register, or -1 for * unsupported values - * @bypass_bit: the index of the bypass bit in the PLL control register - * @enable_bit: the index of the enable bit in the PLL control register - * @stable_bit: the index of the stable bit in the PLL control register + * @bypass_reg: the offset of the bypass control register within the CGU + * @bypass_bit: the index of the bypass bit in the PLL control register, or + * -1 if there is no bypass bit + * @enable_bit: the index of the enable bit in the PLL control register, or + * -1 if there is no enable bit (ie, the PLL is always on) + * @stable_bit: the index of the stable bit in the PLL control register, or + * -1 if there is no stable bit + * @set_rate_hook: hook called immediately after updating the CGU register, + * before releasing the spinlock */ struct ingenic_cgu_pll_info { unsigned reg; + unsigned rate_multiplier; const s8 *od_encoding; u8 m_shift, m_bits, m_offset; u8 n_shift, n_bits, n_offset; u8 od_shift, od_bits, od_max; - u8 bypass_bit; - u8 enable_bit; - u8 stable_bit; + unsigned bypass_reg; + s8 bypass_bit; + s8 enable_bit; + s8 stable_bit; + void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate, + unsigned int *m, unsigned int *n, unsigned int *od); + void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate); }; /** @@ -78,7 +85,7 @@ struct ingenic_cgu_mux_info { * @reg: offset of the divider control register within the CGU * @shift: number of bits to left shift the divide value by (ie. the index of * the lowest bit of the divide value within its control register) - * @div: number of bits to divide the divider value by (i.e. if the + * @div: number to divide the divider value by (i.e. if the * effective divider value is the value written to the register * multiplied by some constant) * @bits: the size of the divide value in bits @@ -86,6 +93,9 @@ struct ingenic_cgu_mux_info { * isn't one * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one + * @bypass_mask: mask of parent clocks for which the divider does not apply + * @div_table: optional table to map the value read from the register to the + * actual divider value */ struct ingenic_cgu_div_info { unsigned reg; @@ -95,6 +105,8 @@ struct ingenic_cgu_div_info { s8 ce_bit; s8 busy_bit; s8 stop_bit; + u8 bypass_mask; + const u8 *div_table; }; /** @@ -109,10 +121,14 @@ struct ingenic_cgu_fixdiv_info { * struct ingenic_cgu_gate_info - information about a clock gate * @reg: offset of the gate control register within the CGU * @bit: offset of the bit in the register that controls the gate + * @clear_to_gate: if set, the clock is gated when the bit is cleared + * @delay_us: delay in microseconds after which the clock is considered stable */ struct ingenic_cgu_gate_info { unsigned reg; u8 bit; + bool clear_to_gate; + u16 delay_us; }; /** @@ -120,13 +136,14 @@ struct ingenic_cgu_gate_info { * @clk_ops: custom clock operation callbacks */ struct ingenic_cgu_custom_info { - struct clk_ops *clk_ops; + const struct clk_ops *clk_ops; }; /** * struct ingenic_cgu_clk_info - information about a clock * @name: name of the clock * @type: a bitmask formed from CGU_CLK_* values + * @flags: common clock flags to set on this clock * @parents: an array of the indices of potential parents of this clock * within the clock_info array of the CGU, or -1 in entries * which correspond to no valid parent @@ -152,6 +169,8 @@ struct ingenic_cgu_clk_info { CGU_CLK_CUSTOM = BIT(7), } type; + unsigned long flags; + int parents[4]; union { @@ -188,7 +207,7 @@ struct ingenic_cgu { /** * struct ingenic_clk - private data for a clock - * @hw: see Documentation/clk.txt + * @hw: see Documentation/driver-api/clk.rst * @cgu: a pointer to the CGU data * @idx: the index of this clock in cgu->clock_info */ @@ -220,7 +239,7 @@ ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, * * Register the clocks described by the CGU with the common clock framework. * - * Return: 0 on success or -errno if unsuccesful. + * Return: 0 on success or -errno if unsuccessful. */ int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); |