diff options
Diffstat (limited to 'drivers/clk/meson/clk-cpu-dyndiv.c')
| -rw-r--r-- | drivers/clk/meson/clk-cpu-dyndiv.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu-dyndiv.c index 36976927fe82..83aedbfd2891 100644 --- a/drivers/clk/meson/clk-cpu-dyndiv.c +++ b/drivers/clk/meson/clk-cpu-dyndiv.c @@ -27,14 +27,13 @@ static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw, NULL, 0, data->div.width); } -static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *prate) +static int meson_clk_cpu_dyndiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk); - return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0); + return divider_determine_rate(hw, req, NULL, data->div.width, 0); } static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, @@ -62,12 +61,14 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate, }; const struct clk_ops meson_clk_cpu_dyndiv_ops = { + .init = clk_regmap_init, .recalc_rate = meson_clk_cpu_dyndiv_recalc_rate, - .round_rate = meson_clk_cpu_dyndiv_round_rate, + .determine_rate = meson_clk_cpu_dyndiv_determine_rate, .set_rate = meson_clk_cpu_dyndiv_set_rate, }; -EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops); +EXPORT_SYMBOL_NS_GPL(meson_clk_cpu_dyndiv_ops, "CLK_MESON"); MODULE_DESCRIPTION("Amlogic CPU Dynamic Clock divider"); MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); -MODULE_LICENSE("GPL v2"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); |