diff options
Diffstat (limited to 'drivers/clk/meson/meson8b.c')
| -rw-r--r-- | drivers/clk/meson/meson8b.c | 2295 |
1 files changed, 1104 insertions, 1191 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index a844d35b553a..95d0b9cbd904 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -16,12 +16,79 @@ #include <linux/slab.h> #include <linux/regmap.h> -#include "meson8b.h" #include "clk-regmap.h" +#include "meson-clkc-utils.h" #include "clk-pll.h" #include "clk-mpll.h" -static DEFINE_SPINLOCK(meson_clk_lock); +#include <dt-bindings/clock/meson8b-clkc.h> +#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> + +/* + * Clock controller register offsets + * + * Register offsets from the HardKernel[0] data sheet must be multiplied + * by 4 before adding them to the base address to get the right value + * + * [0] https://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf + */ +#define HHI_GP_PLL_CNTL 0x40 +#define HHI_GP_PLL_CNTL2 0x44 +#define HHI_GP_PLL_CNTL3 0x48 +#define HHI_GP_PLL_CNTL4 0x4C +#define HHI_GP_PLL_CNTL5 0x50 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12c +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_AO 0x154 +#define HHI_SYS_CPU_CLK_CNTL1 0x15c +#define HHI_VID_CLK_DIV 0x164 +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_AUD_CLK_CNTL 0x178 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_AUD_CLK_CNTL2 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_VID_DIVIDER_CNTL 0x198 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_MALI_CLK_CNTL 0x1b0 +#define HHI_VPU_CLK_CNTL 0x1bc +#define HHI_HDMI_CLK_CNTL 0x1cc +#define HHI_VDEC_CLK_CNTL 0x1e0 +#define HHI_VDEC2_CLK_CNTL 0x1e4 +#define HHI_VDEC3_CLK_CNTL 0x1e8 +#define HHI_NAND_CLK_CNTL 0x25c +#define HHI_MPLL_CNTL 0x280 +#define HHI_SYS_PLL_CNTL 0x300 +#define HHI_VID_PLL_CNTL 0x320 +#define HHI_VID_PLL_CNTL2 0x324 +#define HHI_VID_PLL_CNTL3 0x328 +#define HHI_VID_PLL_CNTL4 0x32c +#define HHI_VID_PLL_CNTL5 0x330 +#define HHI_VID_PLL_CNTL6 0x334 +#define HHI_VID2_PLL_CNTL 0x380 +#define HHI_VID2_PLL_CNTL2 0x384 +#define HHI_VID2_PLL_CNTL3 0x388 +#define HHI_VID2_PLL_CNTL4 0x38c +#define HHI_VID2_PLL_CNTL5 0x390 +#define HHI_VID2_PLL_CNTL6 0x394 + +/* + * MPLL register offeset taken from the S905 datasheet. Vendor kernel source + * confirm these are the same for the S805. + */ +#define HHI_MPLL_CNTL 0x280 +#define HHI_MPLL_CNTL2 0x284 +#define HHI_MPLL_CNTL3 0x288 +#define HHI_MPLL_CNTL4 0x28c +#define HHI_MPLL_CNTL5 0x290 +#define HHI_MPLL_CNTL6 0x294 +#define HHI_MPLL_CNTL7 0x298 +#define HHI_MPLL_CNTL8 0x29c +#define HHI_MPLL_CNTL9 0x2a0 +#define HHI_MPLL_CNTL10 0x2a4 struct meson8b_clk_reset { struct reset_controller_dev reset; @@ -118,6 +185,56 @@ static struct clk_regmap meson8b_fixed_pll = { }, }; +static struct clk_fixed_factor hdmi_pll_dco_in = { + .mult = 2, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "hdmi_pll_dco_in", + .ops = &clk_fixed_factor_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + .index = -1, + }, + .num_parents = 1, + }, +}; + +/* + * Taken from the vendor driver for the 2970/2975MHz (both only differ in the + * FRAC part in HHI_VID_PLL_CNTL2) where these values are identical for Meson8, + * Meson8b and Meson8m2. This doubles the input (or output - it's not clear + * which one but the result is the same) clock. The vendor driver additionally + * has the following comment about: "optimise HPLL VCO 2.97GHz performance". + */ +static const struct reg_sequence meson8b_hdmi_pll_init_regs[] = { + { .reg = HHI_VID_PLL_CNTL2, .def = 0x69c84000 }, + { .reg = HHI_VID_PLL_CNTL3, .def = 0x8a46c023 }, + { .reg = HHI_VID_PLL_CNTL4, .def = 0x4123b100 }, + { .reg = HHI_VID_PLL_CNTL5, .def = 0x00012385 }, + { .reg = HHI_VID2_PLL_CNTL2, .def = 0x0430a800 }, +}; + +static const struct pll_params_table meson8b_hdmi_pll_params_table[] = { + PLL_PARAMS(40, 1), + PLL_PARAMS(42, 1), + PLL_PARAMS(44, 1), + PLL_PARAMS(45, 1), + PLL_PARAMS(49, 1), + PLL_PARAMS(52, 1), + PLL_PARAMS(54, 1), + PLL_PARAMS(56, 1), + PLL_PARAMS(59, 1), + PLL_PARAMS(60, 1), + PLL_PARAMS(61, 1), + PLL_PARAMS(62, 1), + PLL_PARAMS(64, 1), + PLL_PARAMS(66, 1), + PLL_PARAMS(68, 1), + PLL_PARAMS(71, 1), + PLL_PARAMS(82, 1), + { /* sentinel */ } +}; + static struct clk_regmap meson8b_hdmi_pll_dco = { .data = &(struct meson_clk_pll_data){ .en = { @@ -150,15 +267,16 @@ static struct clk_regmap meson8b_hdmi_pll_dco = { .shift = 29, .width = 1, }, + .table = meson8b_hdmi_pll_params_table, + .init_regs = meson8b_hdmi_pll_init_regs, + .init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs), }, .hw.init = &(struct clk_init_data){ /* sometimes also called "HPLL" or "HPLL PLL" */ .name = "hdmi_pll_dco", - .ops = &meson_clk_pll_ro_ops, - .parent_data = &(const struct clk_parent_data) { - .fw_name = "xtal", - .name = "xtal", - .index = -1, + .ops = &meson_clk_pll_ops, + .parent_hws = (const struct clk_hw *[]) { + &hdmi_pll_dco_in.hw }, .num_parents = 1, }, @@ -173,7 +291,7 @@ static struct clk_regmap meson8b_hdmi_pll_lvds_out = { }, .hw.init = &(struct clk_init_data){ .name = "hdmi_pll_lvds_out", - .ops = &clk_regmap_divider_ro_ops, + .ops = &clk_regmap_divider_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_hdmi_pll_dco.hw }, @@ -191,7 +309,7 @@ static struct clk_regmap meson8b_hdmi_pll_hdmi_out = { }, .hw.init = &(struct clk_init_data){ .name = "hdmi_pll_hdmi_out", - .ops = &clk_regmap_divider_ro_ops, + .ops = &clk_regmap_divider_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_hdmi_pll_dco.hw }, @@ -437,7 +555,6 @@ static struct clk_regmap meson8b_mpll0_div = { .shift = 25, .width = 1, }, - .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ .name = "mpll0_div", @@ -482,7 +599,6 @@ static struct clk_regmap meson8b_mpll1_div = { .shift = 16, .width = 9, }, - .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ .name = "mpll1_div", @@ -527,7 +643,6 @@ static struct clk_regmap meson8b_mpll2_div = { .shift = 16, .width = 9, }, - .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ .name = "mpll2_div", @@ -555,16 +670,17 @@ static struct clk_regmap meson8b_mpll2 = { }, }; -static u32 mux_table_clk81[] = { 6, 5, 7 }; -static struct clk_regmap meson8b_mpeg_clk_sel = { +/* clk81 is often referred as "mpeg_clk" */ +static u32 meson8b_clk81_parents_val_table[] = { 6, 5, 7 }; +static struct clk_regmap meson8b_clk81_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_MPEG_CLK_CNTL, .mask = 0x7, .shift = 12, - .table = mux_table_clk81, + .table = meson8b_clk81_parents_val_table, }, .hw.init = &(struct clk_init_data){ - .name = "mpeg_clk_sel", + .name = "clk81_sel", .ops = &clk_regmap_mux_ro_ops, /* * FIXME bits 14:12 selects from 8 possible parents: @@ -580,17 +696,17 @@ static struct clk_regmap meson8b_mpeg_clk_sel = { }, }; -static struct clk_regmap meson8b_mpeg_clk_div = { +static struct clk_regmap meson8b_clk81_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_MPEG_CLK_CNTL, .shift = 0, .width = 7, }, .hw.init = &(struct clk_init_data){ - .name = "mpeg_clk_div", + .name = "clk81_div", .ops = &clk_regmap_divider_ro_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_mpeg_clk_sel.hw + &meson8b_clk81_sel.hw }, .num_parents = 1, }, @@ -605,7 +721,7 @@ static struct clk_regmap meson8b_clk81 = { .name = "clk81", .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_mpeg_clk_div.hw + &meson8b_clk81_div.hw }, .num_parents = 1, .flags = CLK_IS_CRITICAL, @@ -659,7 +775,7 @@ static struct clk_fixed_factor meson8b_cpu_in_div3 = { }, }; -static const struct clk_div_table cpu_scale_table[] = { +static const struct clk_div_table meson8b_cpu_scale_div_table[] = { { .val = 1, .div = 4 }, { .val = 2, .div = 6 }, { .val = 3, .div = 8 }, @@ -676,7 +792,7 @@ static struct clk_regmap meson8b_cpu_scale_div = { .offset = HHI_SYS_CPU_CLK_CNTL1, .shift = 20, .width = 10, - .table = cpu_scale_table, + .table = meson8b_cpu_scale_div_table, .flags = CLK_DIVIDER_ALLOW_ZERO, }, .hw.init = &(struct clk_init_data){ @@ -690,13 +806,13 @@ static struct clk_regmap meson8b_cpu_scale_div = { }, }; -static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 }; +static u32 meson8b_cpu_scale_out_parents_val_table[] = { 0, 1, 3 }; static struct clk_regmap meson8b_cpu_scale_out_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_SYS_CPU_CLK_CNTL0, .mask = 0x3, .shift = 2, - .table = mux_table_cpu_scale_out_sel, + .table = meson8b_cpu_scale_out_parents_val_table, }, .hw.init = &(struct clk_init_data){ .name = "cpu_scale_out_sel", @@ -778,13 +894,13 @@ static struct clk_regmap meson8b_nand_clk_div = { }, }; -static struct clk_regmap meson8b_nand_clk_gate = { +static struct clk_regmap meson8b_nand_clk = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_NAND_CLK_CNTL, .bit_idx = 8, }, .hw.init = &(struct clk_init_data){ - .name = "nand_clk_gate", + .name = "nand_clk", .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_nand_clk_div.hw @@ -885,160 +1001,154 @@ static struct clk_fixed_factor meson8b_cpu_clk_div8 = { }, }; -static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 }; -static struct clk_regmap meson8b_apb_clk_sel = { +static u32 meson8b_cpu_if_parents_val_table[] = { 1, 2, 3, 4, 5, 6, 7 }; +static const struct clk_hw *meson8b_cpu_if_parents[] = { + &meson8b_cpu_clk_div2.hw, + &meson8b_cpu_clk_div3.hw, + &meson8b_cpu_clk_div4.hw, + &meson8b_cpu_clk_div5.hw, + &meson8b_cpu_clk_div6.hw, + &meson8b_cpu_clk_div7.hw, + &meson8b_cpu_clk_div8.hw, +}; + +static struct clk_regmap meson8b_apb_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .mask = 0x7, .shift = 3, - .table = mux_table_apb, + .table = meson8b_cpu_if_parents_val_table, }, .hw.init = &(struct clk_init_data){ - .name = "apb_clk_sel", + .name = "apb_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cpu_clk_div2.hw, - &meson8b_cpu_clk_div3.hw, - &meson8b_cpu_clk_div4.hw, - &meson8b_cpu_clk_div5.hw, - &meson8b_cpu_clk_div6.hw, - &meson8b_cpu_clk_div7.hw, - &meson8b_cpu_clk_div8.hw, - }, - .num_parents = 7, + .parent_hws = meson8b_cpu_if_parents, + .num_parents = ARRAY_SIZE(meson8b_cpu_if_parents), }, }; -static struct clk_regmap meson8b_apb_clk_gate = { +static struct clk_regmap meson8b_apb = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 16, .flags = CLK_GATE_SET_TO_DISABLE, }, .hw.init = &(struct clk_init_data){ - .name = "apb_clk_dis", + .name = "apb", .ops = &clk_regmap_gate_ro_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_apb_clk_sel.hw + &meson8b_apb_sel.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, }, }; -static struct clk_regmap meson8b_periph_clk_sel = { +static struct clk_regmap meson8b_periph_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .mask = 0x7, .shift = 6, }, .hw.init = &(struct clk_init_data){ - .name = "periph_clk_sel", + .name = "periph_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cpu_clk_div2.hw, - &meson8b_cpu_clk_div3.hw, - &meson8b_cpu_clk_div4.hw, - &meson8b_cpu_clk_div5.hw, - &meson8b_cpu_clk_div6.hw, - &meson8b_cpu_clk_div7.hw, - &meson8b_cpu_clk_div8.hw, - }, - .num_parents = 7, + .parent_hws = meson8b_cpu_if_parents, + .num_parents = ARRAY_SIZE(meson8b_cpu_if_parents), }, }; -static struct clk_regmap meson8b_periph_clk_gate = { +static struct clk_regmap meson8b_periph = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 17, .flags = CLK_GATE_SET_TO_DISABLE, }, .hw.init = &(struct clk_init_data){ - .name = "periph_clk_dis", + .name = "periph", .ops = &clk_regmap_gate_ro_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_periph_clk_sel.hw + &meson8b_periph_sel.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, }, }; -static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 }; -static struct clk_regmap meson8b_axi_clk_sel = { +static struct clk_regmap meson8b_axi_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .mask = 0x7, .shift = 9, - .table = mux_table_axi, + .table = meson8b_cpu_if_parents_val_table, }, .hw.init = &(struct clk_init_data){ - .name = "axi_clk_sel", + .name = "axi_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cpu_clk_div2.hw, - &meson8b_cpu_clk_div3.hw, - &meson8b_cpu_clk_div4.hw, - &meson8b_cpu_clk_div5.hw, - &meson8b_cpu_clk_div6.hw, - &meson8b_cpu_clk_div7.hw, - &meson8b_cpu_clk_div8.hw, - }, - .num_parents = 7, + .parent_hws = meson8b_cpu_if_parents, + .num_parents = ARRAY_SIZE(meson8b_cpu_if_parents), }, }; -static struct clk_regmap meson8b_axi_clk_gate = { +static struct clk_regmap meson8b_axi = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 18, .flags = CLK_GATE_SET_TO_DISABLE, }, .hw.init = &(struct clk_init_data){ - .name = "axi_clk_dis", + .name = "axi", .ops = &clk_regmap_gate_ro_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_axi_clk_sel.hw + &meson8b_axi_sel.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, }, }; -static struct clk_regmap meson8b_l2_dram_clk_sel = { +static struct clk_regmap meson8b_l2_dram_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .mask = 0x7, .shift = 12, }, .hw.init = &(struct clk_init_data){ - .name = "l2_dram_clk_sel", + .name = "l2_dram_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cpu_clk_div2.hw, - &meson8b_cpu_clk_div3.hw, - &meson8b_cpu_clk_div4.hw, - &meson8b_cpu_clk_div5.hw, - &meson8b_cpu_clk_div6.hw, - &meson8b_cpu_clk_div7.hw, - &meson8b_cpu_clk_div8.hw, - }, - .num_parents = 7, + .parent_hws = meson8b_cpu_if_parents, + .num_parents = ARRAY_SIZE(meson8b_cpu_if_parents), }, }; -static struct clk_regmap meson8b_l2_dram_clk_gate = { +static struct clk_regmap meson8b_l2_dram = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 19, .flags = CLK_GATE_SET_TO_DISABLE, }, .hw.init = &(struct clk_init_data){ - .name = "l2_dram_clk_dis", + .name = "l2_dram", .ops = &clk_regmap_gate_ro_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_l2_dram_clk_sel.hw + &meson8b_l2_dram_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* also called LVDS_CLK_EN */ +static struct clk_regmap meson8b_vid_pll_lvds_en = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VID_DIVIDER_CNTL, + .bit_idx = 11, + }, + .hw.init = &(struct clk_init_data){ + .name = "vid_pll_lvds_en", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &meson8b_hdmi_pll_lvds_out.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1053,7 +1163,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { }, .hw.init = &(struct clk_init_data){ .name = "vid_pll_in_sel", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, /* * TODO: depending on the SoC there is also a second parent: * Meson8: unknown @@ -1061,7 +1171,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { * Meson8m2: vid2_pll */ .parent_hws = (const struct clk_hw *[]) { - &meson8b_hdmi_pll_lvds_out.hw + &meson8b_vid_pll_lvds_en.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1075,7 +1185,7 @@ static struct clk_regmap meson8b_vid_pll_in_en = { }, .hw.init = &(struct clk_init_data){ .name = "vid_pll_in_en", - .ops = &clk_regmap_gate_ro_ops, + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vid_pll_in_sel.hw }, @@ -1092,7 +1202,7 @@ static struct clk_regmap meson8b_vid_pll_pre_div = { }, .hw.init = &(struct clk_init_data){ .name = "vid_pll_pre_div", - .ops = &clk_regmap_divider_ro_ops, + .ops = &clk_regmap_divider_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vid_pll_in_en.hw }, @@ -1109,7 +1219,7 @@ static struct clk_regmap meson8b_vid_pll_post_div = { }, .hw.init = &(struct clk_init_data){ .name = "vid_pll_post_div", - .ops = &clk_regmap_divider_ro_ops, + .ops = &clk_regmap_divider_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vid_pll_pre_div.hw }, @@ -1126,7 +1236,7 @@ static struct clk_regmap meson8b_vid_pll = { }, .hw.init = &(struct clk_init_data){ .name = "vid_pll", - .ops = &clk_regmap_mux_ro_ops, + .ops = &clk_regmap_mux_ops, /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */ .parent_hws = (const struct clk_hw *[]) { &meson8b_vid_pll_pre_div.hw, @@ -1145,7 +1255,7 @@ static struct clk_regmap meson8b_vid_pll_final_div = { }, .hw.init = &(struct clk_init_data){ .name = "vid_pll_final_div", - .ops = &clk_regmap_divider_ro_ops, + .ops = &clk_regmap_divider_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vid_pll.hw }, @@ -1154,7 +1264,7 @@ static struct clk_regmap meson8b_vid_pll_final_div = { }, }; -static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { +static const struct clk_hw *meson8b_vclk_parents[] = { &meson8b_vid_pll_final_div.hw, &meson8b_fclk_div4.hw, &meson8b_fclk_div3.hw, @@ -1172,10 +1282,10 @@ static struct clk_regmap meson8b_vclk_in_sel = { }, .hw.init = &(struct clk_init_data){ .name = "vclk_in_sel", - .ops = &clk_regmap_mux_ro_ops, - .parent_hws = meson8b_vclk_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_mux_ops, + .parent_hws = meson8b_vclk_parents, + .num_parents = ARRAY_SIZE(meson8b_vclk_parents), + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, }; @@ -1186,7 +1296,7 @@ static struct clk_regmap meson8b_vclk_in_en = { }, .hw.init = &(struct clk_init_data){ .name = "vclk_in_en", - .ops = &clk_regmap_gate_ro_ops, + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk_in_sel.hw }, @@ -1202,7 +1312,7 @@ static struct clk_regmap meson8b_vclk_en = { }, .hw.init = &(struct clk_init_data){ .name = "vclk_en", - .ops = &clk_regmap_gate_ro_ops, + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk_in_en.hw }, @@ -1211,14 +1321,14 @@ static struct clk_regmap meson8b_vclk_en = { }, }; -static struct clk_regmap meson8b_vclk_div1_gate = { +static struct clk_regmap meson8b_vclk_div1 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VID_CLK_CNTL, .bit_idx = 0, }, .hw.init = &(struct clk_init_data){ - .name = "vclk_div1_en", - .ops = &clk_regmap_gate_ro_ops, + .name = "vclk_div1", + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk_en.hw }, @@ -1231,7 +1341,7 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ - .name = "vclk_div2", + .name = "vclk_div2_div", .ops = &clk_fixed_factor_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk_en.hw @@ -1241,14 +1351,14 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = { } }; -static struct clk_regmap meson8b_vclk_div2_div_gate = { +static struct clk_regmap meson8b_vclk_div2 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VID_CLK_CNTL, .bit_idx = 1, }, .hw.init = &(struct clk_init_data){ - .name = "vclk_div2_en", - .ops = &clk_regmap_gate_ro_ops, + .name = "vclk_div2", + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk_div2_div.hw }, @@ -1261,7 +1371,7 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = { .mult = 1, .div = 4, .hw.init = &(struct clk_init_data){ - .name = "vclk_div4", + .name = "vclk_div4_div", .ops = &clk_fixed_factor_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk_en.hw @@ -1271,14 +1381,14 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = { } }; -static struct clk_regmap meson8b_vclk_div4_div_gate = { +static struct clk_regmap meson8b_vclk_div4 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VID_CLK_CNTL, .bit_idx = 2, }, .hw.init = &(struct clk_init_data){ - .name = "vclk_div4_en", - .ops = &clk_regmap_gate_ro_ops, + .name = "vclk_div4", + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk_div4_div.hw }, @@ -1291,7 +1401,7 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = { .mult = 1, .div = 6, .hw.init = &(struct clk_init_data){ - .name = "vclk_div6", + .name = "vclk_div6_div", .ops = &clk_fixed_factor_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk_en.hw @@ -1301,14 +1411,14 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = { } }; -static struct clk_regmap meson8b_vclk_div6_div_gate = { +static struct clk_regmap meson8b_vclk_div6 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VID_CLK_CNTL, .bit_idx = 3, }, .hw.init = &(struct clk_init_data){ - .name = "vclk_div6_en", - .ops = &clk_regmap_gate_ro_ops, + .name = "vclk_div6", + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk_div6_div.hw }, @@ -1321,7 +1431,7 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = { .mult = 1, .div = 12, .hw.init = &(struct clk_init_data){ - .name = "vclk_div12", + .name = "vclk_div12_div", .ops = &clk_fixed_factor_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk_en.hw @@ -1331,14 +1441,14 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = { } }; -static struct clk_regmap meson8b_vclk_div12_div_gate = { +static struct clk_regmap meson8b_vclk_div12 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VID_CLK_CNTL, .bit_idx = 4, }, .hw.init = &(struct clk_init_data){ - .name = "vclk_div12_en", - .ops = &clk_regmap_gate_ro_ops, + .name = "vclk_div12", + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk_div12_div.hw }, @@ -1355,21 +1465,21 @@ static struct clk_regmap meson8b_vclk2_in_sel = { }, .hw.init = &(struct clk_init_data){ .name = "vclk2_in_sel", - .ops = &clk_regmap_mux_ro_ops, - .parent_hws = meson8b_vclk_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_mux_ops, + .parent_hws = meson8b_vclk_parents, + .num_parents = ARRAY_SIZE(meson8b_vclk_parents), + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, }; -static struct clk_regmap meson8b_vclk2_clk_in_en = { +static struct clk_regmap meson8b_vclk2_in_en = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VIID_CLK_DIV, .bit_idx = 16, }, .hw.init = &(struct clk_init_data){ .name = "vclk2_in_en", - .ops = &clk_regmap_gate_ro_ops, + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk2_in_sel.hw }, @@ -1378,32 +1488,32 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = { }, }; -static struct clk_regmap meson8b_vclk2_clk_en = { +static struct clk_regmap meson8b_vclk2_en = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VIID_CLK_DIV, .bit_idx = 19, }, .hw.init = &(struct clk_init_data){ .name = "vclk2_en", - .ops = &clk_regmap_gate_ro_ops, + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_clk_in_en.hw + &meson8b_vclk2_in_en.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, }, }; -static struct clk_regmap meson8b_vclk2_div1_gate = { +static struct clk_regmap meson8b_vclk2_div1 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VIID_CLK_DIV, .bit_idx = 0, }, .hw.init = &(struct clk_init_data){ - .name = "vclk2_div1_en", - .ops = &clk_regmap_gate_ro_ops, + .name = "vclk2_div1", + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw + &meson8b_vclk2_en.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1414,24 +1524,24 @@ static struct clk_fixed_factor meson8b_vclk2_div2_div = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ - .name = "vclk2_div2", + .name = "vclk2_div2_div", .ops = &clk_fixed_factor_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw + &meson8b_vclk2_en.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, } }; -static struct clk_regmap meson8b_vclk2_div2_div_gate = { +static struct clk_regmap meson8b_vclk2_div2 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VIID_CLK_DIV, .bit_idx = 1, }, .hw.init = &(struct clk_init_data){ - .name = "vclk2_div2_en", - .ops = &clk_regmap_gate_ro_ops, + .name = "vclk2_div2", + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk2_div2_div.hw }, @@ -1444,24 +1554,24 @@ static struct clk_fixed_factor meson8b_vclk2_div4_div = { .mult = 1, .div = 4, .hw.init = &(struct clk_init_data){ - .name = "vclk2_div4", + .name = "vclk2_div4_div", .ops = &clk_fixed_factor_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw + &meson8b_vclk2_en.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, } }; -static struct clk_regmap meson8b_vclk2_div4_div_gate = { +static struct clk_regmap meson8b_vclk2_div4 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VIID_CLK_DIV, .bit_idx = 2, }, .hw.init = &(struct clk_init_data){ - .name = "vclk2_div4_en", - .ops = &clk_regmap_gate_ro_ops, + .name = "vclk2_div4", + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk2_div4_div.hw }, @@ -1474,24 +1584,24 @@ static struct clk_fixed_factor meson8b_vclk2_div6_div = { .mult = 1, .div = 6, .hw.init = &(struct clk_init_data){ - .name = "vclk2_div6", + .name = "vclk2_div6_div", .ops = &clk_fixed_factor_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw + &meson8b_vclk2_en.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, } }; -static struct clk_regmap meson8b_vclk2_div6_div_gate = { +static struct clk_regmap meson8b_vclk2_div6 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VIID_CLK_DIV, .bit_idx = 3, }, .hw.init = &(struct clk_init_data){ - .name = "vclk2_div6_en", - .ops = &clk_regmap_gate_ro_ops, + .name = "vclk2_div6", + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk2_div6_div.hw }, @@ -1504,24 +1614,24 @@ static struct clk_fixed_factor meson8b_vclk2_div12_div = { .mult = 1, .div = 12, .hw.init = &(struct clk_init_data){ - .name = "vclk2_div12", + .name = "vclk2_div12_div", .ops = &clk_fixed_factor_ops, .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw + &meson8b_vclk2_en.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, } }; -static struct clk_regmap meson8b_vclk2_div12_div_gate = { +static struct clk_regmap meson8b_vclk2_div12 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VIID_CLK_DIV, .bit_idx = 4, }, .hw.init = &(struct clk_init_data){ - .name = "vclk2_div12_en", - .ops = &clk_regmap_gate_ro_ops, + .name = "vclk2_div12", + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_vclk2_div12_div.hw }, @@ -1530,12 +1640,12 @@ static struct clk_regmap meson8b_vclk2_div12_div_gate = { }, }; -static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = { - &meson8b_vclk_div1_gate.hw, - &meson8b_vclk_div2_div_gate.hw, - &meson8b_vclk_div4_div_gate.hw, - &meson8b_vclk_div6_div_gate.hw, - &meson8b_vclk_div12_div_gate.hw, +static const struct clk_hw *meson8b_vclk_enc_parents[] = { + &meson8b_vclk_div1.hw, + &meson8b_vclk_div2.hw, + &meson8b_vclk_div4.hw, + &meson8b_vclk_div6.hw, + &meson8b_vclk_div12.hw, }; static struct clk_regmap meson8b_cts_enct_sel = { @@ -1546,9 +1656,9 @@ static struct clk_regmap meson8b_cts_enct_sel = { }, .hw.init = &(struct clk_init_data){ .name = "cts_enct_sel", - .ops = &clk_regmap_mux_ro_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), + .ops = &clk_regmap_mux_ops, + .parent_hws = meson8b_vclk_enc_parents, + .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -1560,7 +1670,7 @@ static struct clk_regmap meson8b_cts_enct = { }, .hw.init = &(struct clk_init_data){ .name = "cts_enct", - .ops = &clk_regmap_gate_ro_ops, + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_cts_enct_sel.hw }, @@ -1577,9 +1687,9 @@ static struct clk_regmap meson8b_cts_encp_sel = { }, .hw.init = &(struct clk_init_data){ .name = "cts_encp_sel", - .ops = &clk_regmap_mux_ro_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), + .ops = &clk_regmap_mux_ops, + .parent_hws = meson8b_vclk_enc_parents, + .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -1591,7 +1701,7 @@ static struct clk_regmap meson8b_cts_encp = { }, .hw.init = &(struct clk_init_data){ .name = "cts_encp", - .ops = &clk_regmap_gate_ro_ops, + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_cts_encp_sel.hw }, @@ -1608,9 +1718,9 @@ static struct clk_regmap meson8b_cts_enci_sel = { }, .hw.init = &(struct clk_init_data){ .name = "cts_enci_sel", - .ops = &clk_regmap_mux_ro_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), + .ops = &clk_regmap_mux_ops, + .parent_hws = meson8b_vclk_enc_parents, + .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -1622,7 +1732,7 @@ static struct clk_regmap meson8b_cts_enci = { }, .hw.init = &(struct clk_init_data){ .name = "cts_enci", - .ops = &clk_regmap_gate_ro_ops, + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_cts_enci_sel.hw }, @@ -1639,9 +1749,9 @@ static struct clk_regmap meson8b_hdmi_tx_pixel_sel = { }, .hw.init = &(struct clk_init_data){ .name = "hdmi_tx_pixel_sel", - .ops = &clk_regmap_mux_ro_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), + .ops = &clk_regmap_mux_ops, + .parent_hws = meson8b_vclk_enc_parents, + .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -1653,7 +1763,7 @@ static struct clk_regmap meson8b_hdmi_tx_pixel = { }, .hw.init = &(struct clk_init_data){ .name = "hdmi_tx_pixel", - .ops = &clk_regmap_gate_ro_ops, + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_hdmi_tx_pixel_sel.hw }, @@ -1662,14 +1772,6 @@ static struct clk_regmap meson8b_hdmi_tx_pixel = { }, }; -static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = { - &meson8b_vclk2_div1_gate.hw, - &meson8b_vclk2_div2_div_gate.hw, - &meson8b_vclk2_div4_div_gate.hw, - &meson8b_vclk2_div6_div_gate.hw, - &meson8b_vclk2_div12_div_gate.hw, -}; - static struct clk_regmap meson8b_cts_encl_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_VIID_CLK_DIV, @@ -1678,9 +1780,9 @@ static struct clk_regmap meson8b_cts_encl_sel = { }, .hw.init = &(struct clk_init_data){ .name = "cts_encl_sel", - .ops = &clk_regmap_mux_ro_ops, - .parent_hws = meson8b_vclk2_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws), + .ops = &clk_regmap_mux_ops, + .parent_hws = meson8b_vclk_enc_parents, + .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -1692,7 +1794,7 @@ static struct clk_regmap meson8b_cts_encl = { }, .hw.init = &(struct clk_init_data){ .name = "cts_encl", - .ops = &clk_regmap_gate_ro_ops, + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_cts_encl_sel.hw }, @@ -1709,9 +1811,9 @@ static struct clk_regmap meson8b_cts_vdac0_sel = { }, .hw.init = &(struct clk_init_data){ .name = "cts_vdac0_sel", - .ops = &clk_regmap_mux_ro_ops, - .parent_hws = meson8b_vclk2_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws), + .ops = &clk_regmap_mux_ops, + .parent_hws = meson8b_vclk_enc_parents, + .num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -1723,7 +1825,7 @@ static struct clk_regmap meson8b_cts_vdac0 = { }, .hw.init = &(struct clk_init_data){ .name = "cts_vdac0", - .ops = &clk_regmap_gate_ro_ops, + .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &meson8b_cts_vdac0_sel.hw }, @@ -1794,7 +1896,8 @@ static struct clk_regmap meson8b_hdmi_sys = { * CLK_SET_RATE_GATE is set. * Meson8 only has mali_0 and no glitch-free mux. */ -static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = { +static u32 meson8b_mali_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 }; +static const struct clk_parent_data meson8b_mali_parents[] = { { .fw_name = "xtal", .name = "xtal", .index = -1, }, { .hw = &meson8b_mpll2.hw, }, { .hw = &meson8b_mpll1.hw, }, @@ -1804,20 +1907,18 @@ static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = { { .hw = &meson8b_fclk_div5.hw, }, }; -static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 }; - static struct clk_regmap meson8b_mali_0_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_MALI_CLK_CNTL, .mask = 0x7, .shift = 9, - .table = meson8b_mali_0_1_mux_table, + .table = meson8b_mali_parents_val_table, }, .hw.init = &(struct clk_init_data){ .name = "mali_0_sel", .ops = &clk_regmap_mux_ops, - .parent_data = meson8b_mali_0_1_parent_data, - .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data), + .parent_data = meson8b_mali_parents, + .num_parents = ARRAY_SIZE(meson8b_mali_parents), /* * Don't propagate rate changes up because the only changeable * parents are mpll1 and mpll2 but we need those for audio and @@ -1866,13 +1967,13 @@ static struct clk_regmap meson8b_mali_1_sel = { .offset = HHI_MALI_CLK_CNTL, .mask = 0x7, .shift = 25, - .table = meson8b_mali_0_1_mux_table, + .table = meson8b_mali_parents_val_table, }, .hw.init = &(struct clk_init_data){ .name = "mali_1_sel", .ops = &clk_regmap_mux_ops, - .parent_data = meson8b_mali_0_1_parent_data, - .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data), + .parent_data = meson8b_mali_parents, + .num_parents = ARRAY_SIZE(meson8b_mali_parents), /* * Don't propagate rate changes up because the only changeable * parents are mpll1 and mpll2 but we need those for audio and @@ -2007,20 +2108,13 @@ static struct clk_regmap meson8m2_gp_pll = { }, }; -static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = { +static const struct clk_hw *meson8b_vpu_parents[] = { &meson8b_fclk_div4.hw, &meson8b_fclk_div3.hw, &meson8b_fclk_div5.hw, &meson8b_fclk_div7.hw, }; -static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = { - &meson8b_fclk_div4.hw, - &meson8b_fclk_div3.hw, - &meson8b_fclk_div5.hw, - &meson8m2_gp_pll.hw, -}; - static struct clk_regmap meson8b_vpu_0_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_VPU_CLK_CNTL, @@ -2030,12 +2124,19 @@ static struct clk_regmap meson8b_vpu_0_sel = { .hw.init = &(struct clk_init_data){ .name = "vpu_0_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vpu_0_1_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws), + .parent_hws = meson8b_vpu_parents, + .num_parents = ARRAY_SIZE(meson8b_vpu_parents), .flags = CLK_SET_RATE_PARENT, }, }; +static const struct clk_hw *mmeson8m2_vpu_parents[] = { + &meson8b_fclk_div4.hw, + &meson8b_fclk_div3.hw, + &meson8b_fclk_div5.hw, + &meson8m2_gp_pll.hw, +}; + static struct clk_regmap meson8m2_vpu_0_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_VPU_CLK_CNTL, @@ -2045,8 +2146,8 @@ static struct clk_regmap meson8m2_vpu_0_sel = { .hw.init = &(struct clk_init_data){ .name = "vpu_0_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = mmeson8m2_vpu_0_1_parent_hws, - .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws), + .parent_hws = mmeson8m2_vpu_parents, + .num_parents = ARRAY_SIZE(mmeson8m2_vpu_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -2101,8 +2202,8 @@ static struct clk_regmap meson8b_vpu_1_sel = { .hw.init = &(struct clk_init_data){ .name = "vpu_1_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vpu_0_1_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws), + .parent_hws = meson8b_vpu_parents, + .num_parents = ARRAY_SIZE(meson8b_vpu_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -2116,8 +2217,8 @@ static struct clk_regmap meson8m2_vpu_1_sel = { .hw.init = &(struct clk_init_data){ .name = "vpu_1_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = mmeson8m2_vpu_0_1_parent_hws, - .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws), + .parent_hws = mmeson8m2_vpu_parents, + .num_parents = ARRAY_SIZE(mmeson8m2_vpu_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -2164,7 +2265,7 @@ static struct clk_regmap meson8b_vpu_1 = { }; /* - * The VPU clock has two two identical clock trees (vpu_0 and vpu_1) + * The VPU clock has two identical clock trees (vpu_0 and vpu_1) * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can * actually manage this glitch-free mux because it does top-to-bottom * updates the each clock tree and switches to the "inactive" one when @@ -2189,7 +2290,7 @@ static struct clk_regmap meson8b_vpu = { }, }; -static const struct clk_hw *meson8b_vdec_parent_hws[] = { +static const struct clk_hw *meson8b_vdec_parents[] = { &meson8b_fclk_div4.hw, &meson8b_fclk_div3.hw, &meson8b_fclk_div5.hw, @@ -2208,8 +2309,8 @@ static struct clk_regmap meson8b_vdec_1_sel = { .hw.init = &(struct clk_init_data){ .name = "vdec_1_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vdec_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws), + .parent_hws = meson8b_vdec_parents, + .num_parents = ARRAY_SIZE(meson8b_vdec_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -2311,8 +2412,8 @@ static struct clk_regmap meson8b_vdec_hcodec_sel = { .hw.init = &(struct clk_init_data){ .name = "vdec_hcodec_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vdec_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws), + .parent_hws = meson8b_vdec_parents, + .num_parents = ARRAY_SIZE(meson8b_vdec_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -2361,8 +2462,8 @@ static struct clk_regmap meson8b_vdec_2_sel = { .hw.init = &(struct clk_init_data){ .name = "vdec_2_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vdec_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws), + .parent_hws = meson8b_vdec_parents, + .num_parents = ARRAY_SIZE(meson8b_vdec_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -2411,8 +2512,8 @@ static struct clk_regmap meson8b_vdec_hevc_sel = { .hw.init = &(struct clk_init_data){ .name = "vdec_hevc_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vdec_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws), + .parent_hws = meson8b_vdec_parents, + .num_parents = ARRAY_SIZE(meson8b_vdec_parents), .flags = CLK_SET_RATE_PARENT, }, }; @@ -2471,27 +2572,26 @@ static struct clk_regmap meson8b_vdec_hevc = { }; /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ -static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = { +static u32 meson8b_cts_mclk_parents_val_table[] = { 1, 2, 3 }; +static const struct clk_hw *meson8b_cts_mclk_parents[] = { &meson8b_mpll0.hw, &meson8b_mpll1.hw, &meson8b_mpll2.hw }; -static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 }; - static struct clk_regmap meson8b_cts_amclk_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_AUD_CLK_CNTL, .mask = 0x3, .shift = 9, - .table = meson8b_cts_amclk_mux_table, + .table = meson8b_cts_mclk_parents_val_table, .flags = CLK_MUX_ROUND_CLOSEST, }, .hw.init = &(struct clk_init_data){ .name = "cts_amclk_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_cts_amclk_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws), + .parent_hws = meson8b_cts_mclk_parents, + .num_parents = ARRAY_SIZE(meson8b_cts_mclk_parents), }, }; @@ -2529,28 +2629,19 @@ static struct clk_regmap meson8b_cts_amclk = { }, }; -/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ -static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = { - &meson8b_mpll0.hw, - &meson8b_mpll1.hw, - &meson8b_mpll2.hw -}; - -static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 }; - static struct clk_regmap meson8b_cts_mclk_i958_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_AUD_CLK_CNTL2, .mask = 0x3, .shift = 25, - .table = meson8b_cts_mclk_i958_mux_table, + .table = meson8b_cts_mclk_parents_val_table, .flags = CLK_MUX_ROUND_CLOSEST, }, .hw.init = &(struct clk_init_data) { .name = "cts_mclk_i958_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_cts_mclk_i958_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws), + .parent_hws = meson8b_cts_mclk_parents, + .num_parents = ARRAY_SIZE(meson8b_cts_mclk_parents), }, }; @@ -2610,935 +2701,749 @@ static struct clk_regmap meson8b_cts_i958 = { }, }; -#define MESON_GATE(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw) - -/* Everything Else (EE) domain gates */ - -static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); -static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1); -static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5); -static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6); -static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7); -static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8); -static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9); -static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10); -static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11); -static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12); -static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13); -static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14); -static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15); -static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16); -static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17); -static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18); -static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19); -static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23); -static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30); - -static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2); -static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3); -static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4); -static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14); -static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15); -static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16); -static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20); -static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21); -static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22); -static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23); -static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24); -static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25); -static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26); -static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28); -static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29); -static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30); -static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31); - -static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1); -static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); -static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4); -static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); -static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); -static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11); -static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12); -static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15); -static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22); -static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25); -static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); -static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29); - -static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1); -static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2); -static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3); -static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4); -static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8); -static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9); -static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10); -static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14); -static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16); -static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20); -static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21); -static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22); -static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24); -static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25); -static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26); -static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31); +static const struct clk_parent_data meson8b_pclk_parents = { .hw = &meson8b_clk81.hw }; + +#define MESON8B_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(_name, _reg, _bit, &meson8b_pclk_parents, _flags) + +/* + * Everything Else (EE) domain gates + * + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITICAL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable + * for a particular clock. + */ +static MESON8B_PCLK(meson8b_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_spicc, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_sar_adc, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_smart_card, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_sdhc, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_stream, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_async_fifo, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_sdio, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_abuf, HHI_GCLK_MPEG0, 18, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); + +static MESON8B_PCLK(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_eth, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_blkmv, HHI_GCLK_MPEG1, 14, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_aiu, HHI_GCLK_MPEG1, 15, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_nand, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_dos_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_usb, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vdin1, HHI_GCLK_MPEG1, 28, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED); + +static MESON8B_PCLK(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_dvin, HHI_GCLK_MPEG2, 12, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_sana, HHI_GCLK_MPEG2, 22, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED); + +static MESON8B_PCLK(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); /* AIU gates */ -#define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw) - -static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw); -static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7); -static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8); -static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9); -static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10); -static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11); -static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12); -static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13); +static const struct clk_parent_data meson8b_aiu_glue_parents = { .hw = &meson8b_aiu.hw }; +static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, + &meson8b_aiu_glue_parents, CLK_IGNORE_UNUSED); + +static const struct clk_parent_data meson8b_aiu_pclk_parents = { .hw = &meson8b_aiu_glue.hw }; +#define MESON8B_AIU_PCLK(_name, _bit, _flags) \ + MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &meson8b_aiu_pclk_parents, _flags) + +static MESON8B_AIU_PCLK(meson8b_iec958, 7, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_i2s_out, 8, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_amclk, 9, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_aififo2, 10, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_mixer, 11, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_mixer_iface, 12, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_adc, 13, CLK_IGNORE_UNUSED); /* Always On (AO) domain gates */ -static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0); -static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1); -static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2); -static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3); - -static struct clk_hw_onecell_data meson8_hw_onecell_data = { - .hws = { - [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, - [CLKID_PLL_VID] = &meson8b_vid_pll.hw, - [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, - [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, - [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, - [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, - [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, - [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, - [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, - [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, - [CLKID_CLK81] = &meson8b_clk81.hw, - [CLKID_DDR] = &meson8b_ddr.hw, - [CLKID_DOS] = &meson8b_dos.hw, - [CLKID_ISA] = &meson8b_isa.hw, - [CLKID_PL301] = &meson8b_pl301.hw, - [CLKID_PERIPHS] = &meson8b_periphs.hw, - [CLKID_SPICC] = &meson8b_spicc.hw, - [CLKID_I2C] = &meson8b_i2c.hw, - [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, - [CLKID_SMART_CARD] = &meson8b_smart_card.hw, - [CLKID_RNG0] = &meson8b_rng0.hw, - [CLKID_UART0] = &meson8b_uart0.hw, - [CLKID_SDHC] = &meson8b_sdhc.hw, - [CLKID_STREAM] = &meson8b_stream.hw, - [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, - [CLKID_SDIO] = &meson8b_sdio.hw, - [CLKID_ABUF] = &meson8b_abuf.hw, - [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, - [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, - [CLKID_SPI] = &meson8b_spi.hw, - [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, - [CLKID_ETH] = &meson8b_eth.hw, - [CLKID_DEMUX] = &meson8b_demux.hw, - [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, - [CLKID_IEC958] = &meson8b_iec958.hw, - [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, - [CLKID_AMCLK] = &meson8b_amclk.hw, - [CLKID_AIFIFO2] = &meson8b_aififo2.hw, - [CLKID_MIXER] = &meson8b_mixer.hw, - [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, - [CLKID_ADC] = &meson8b_adc.hw, - [CLKID_BLKMV] = &meson8b_blkmv.hw, - [CLKID_AIU] = &meson8b_aiu.hw, - [CLKID_UART1] = &meson8b_uart1.hw, - [CLKID_G2D] = &meson8b_g2d.hw, - [CLKID_USB0] = &meson8b_usb0.hw, - [CLKID_USB1] = &meson8b_usb1.hw, - [CLKID_RESET] = &meson8b_reset.hw, - [CLKID_NAND] = &meson8b_nand.hw, - [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, - [CLKID_USB] = &meson8b_usb.hw, - [CLKID_VDIN1] = &meson8b_vdin1.hw, - [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, - [CLKID_EFUSE] = &meson8b_efuse.hw, - [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, - [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, - [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, - [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, - [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, - [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, - [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, - [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, - [CLKID_DVIN] = &meson8b_dvin.hw, - [CLKID_UART2] = &meson8b_uart2.hw, - [CLKID_SANA] = &meson8b_sana.hw, - [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, - [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, - [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, - [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, - [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, - [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, - [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, - [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, - [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, - [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, - [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, - [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, - [CLKID_ENC480P] = &meson8b_enc480p.hw, - [CLKID_RNG1] = &meson8b_rng1.hw, - [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, - [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, - [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, - [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, - [CLKID_EDP] = &meson8b_edp.hw, - [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, - [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, - [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, - [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, - [CLKID_MPLL0] = &meson8b_mpll0.hw, - [CLKID_MPLL1] = &meson8b_mpll1.hw, - [CLKID_MPLL2] = &meson8b_mpll2.hw, - [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, - [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, - [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, - [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, - [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, - [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, - [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, - [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, - [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, - [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, - [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, - [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, - [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, - [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, - [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, - [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, - [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, - [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, - [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, - [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, - [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, - [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, - [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, - [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw, - [CLKID_APB] = &meson8b_apb_clk_gate.hw, - [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, - [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, - [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, - [CLKID_AXI] = &meson8b_axi_clk_gate.hw, - [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, - [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw, - [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, - [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, - [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, - [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, - [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, - [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, - [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, - [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, - [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, - [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, - [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw, - [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, - [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw, - [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, - [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw, - [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, - [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw, - [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, - [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw, - [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, - [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw, - [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw, - [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw, - [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, - [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw, - [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, - [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw, - [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, - [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw, - [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, - [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw, - [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, - [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, - [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, - [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, - [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, - [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, - [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, - [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, - [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, - [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, - [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, - [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, - [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, - [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, - [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, - [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, - [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, - [CLKID_MALI] = &meson8b_mali_0.hw, - [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw, - [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, - [CLKID_VPU] = &meson8b_vpu_0.hw, - [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, - [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, - [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw, - [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, - [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, - [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, - [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, - [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, - [CLKID_VDEC_2] = &meson8b_vdec_2.hw, - [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, - [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, - [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, - [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, - [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, - [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, - [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, - [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, - [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, - [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, - [CLKID_CTS_I958] = &meson8b_cts_i958.hw, - [CLK_NR_CLKS] = NULL, - }, - .num = CLK_NR_CLKS, -}; - -static struct clk_hw_onecell_data meson8b_hw_onecell_data = { - .hws = { - [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, - [CLKID_PLL_VID] = &meson8b_vid_pll.hw, - [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, - [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, - [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, - [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, - [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, - [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, - [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, - [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, - [CLKID_CLK81] = &meson8b_clk81.hw, - [CLKID_DDR] = &meson8b_ddr.hw, - [CLKID_DOS] = &meson8b_dos.hw, - [CLKID_ISA] = &meson8b_isa.hw, - [CLKID_PL301] = &meson8b_pl301.hw, - [CLKID_PERIPHS] = &meson8b_periphs.hw, - [CLKID_SPICC] = &meson8b_spicc.hw, - [CLKID_I2C] = &meson8b_i2c.hw, - [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, - [CLKID_SMART_CARD] = &meson8b_smart_card.hw, - [CLKID_RNG0] = &meson8b_rng0.hw, - [CLKID_UART0] = &meson8b_uart0.hw, - [CLKID_SDHC] = &meson8b_sdhc.hw, - [CLKID_STREAM] = &meson8b_stream.hw, - [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, - [CLKID_SDIO] = &meson8b_sdio.hw, - [CLKID_ABUF] = &meson8b_abuf.hw, - [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, - [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, - [CLKID_SPI] = &meson8b_spi.hw, - [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, - [CLKID_ETH] = &meson8b_eth.hw, - [CLKID_DEMUX] = &meson8b_demux.hw, - [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, - [CLKID_IEC958] = &meson8b_iec958.hw, - [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, - [CLKID_AMCLK] = &meson8b_amclk.hw, - [CLKID_AIFIFO2] = &meson8b_aififo2.hw, - [CLKID_MIXER] = &meson8b_mixer.hw, - [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, - [CLKID_ADC] = &meson8b_adc.hw, - [CLKID_BLKMV] = &meson8b_blkmv.hw, - [CLKID_AIU] = &meson8b_aiu.hw, - [CLKID_UART1] = &meson8b_uart1.hw, - [CLKID_G2D] = &meson8b_g2d.hw, - [CLKID_USB0] = &meson8b_usb0.hw, - [CLKID_USB1] = &meson8b_usb1.hw, - [CLKID_RESET] = &meson8b_reset.hw, - [CLKID_NAND] = &meson8b_nand.hw, - [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, - [CLKID_USB] = &meson8b_usb.hw, - [CLKID_VDIN1] = &meson8b_vdin1.hw, - [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, - [CLKID_EFUSE] = &meson8b_efuse.hw, - [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, - [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, - [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, - [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, - [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, - [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, - [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, - [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, - [CLKID_DVIN] = &meson8b_dvin.hw, - [CLKID_UART2] = &meson8b_uart2.hw, - [CLKID_SANA] = &meson8b_sana.hw, - [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, - [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, - [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, - [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, - [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, - [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, - [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, - [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, - [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, - [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, - [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, - [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, - [CLKID_ENC480P] = &meson8b_enc480p.hw, - [CLKID_RNG1] = &meson8b_rng1.hw, - [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, - [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, - [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, - [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, - [CLKID_EDP] = &meson8b_edp.hw, - [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, - [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, - [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, - [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, - [CLKID_MPLL0] = &meson8b_mpll0.hw, - [CLKID_MPLL1] = &meson8b_mpll1.hw, - [CLKID_MPLL2] = &meson8b_mpll2.hw, - [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, - [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, - [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, - [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, - [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, - [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, - [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, - [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, - [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, - [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, - [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, - [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, - [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, - [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, - [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, - [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, - [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, - [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, - [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, - [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, - [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, - [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, - [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, - [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw, - [CLKID_APB] = &meson8b_apb_clk_gate.hw, - [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, - [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, - [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, - [CLKID_AXI] = &meson8b_axi_clk_gate.hw, - [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, - [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw, - [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, - [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, - [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, - [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, - [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, - [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, - [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, - [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, - [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, - [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, - [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw, - [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, - [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw, - [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, - [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw, - [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, - [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw, - [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, - [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw, - [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, - [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw, - [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw, - [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw, - [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, - [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw, - [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, - [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw, - [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, - [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw, - [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, - [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw, - [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, - [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, - [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, - [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, - [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, - [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, - [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, - [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, - [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, - [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, - [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, - [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, - [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, - [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, - [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, - [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, - [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, - [CLKID_MALI_0] = &meson8b_mali_0.hw, - [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw, - [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw, - [CLKID_MALI_1] = &meson8b_mali_1.hw, - [CLKID_MALI] = &meson8b_mali.hw, - [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw, - [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, - [CLKID_VPU_0] = &meson8b_vpu_0.hw, - [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw, - [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw, - [CLKID_VPU_1] = &meson8b_vpu_1.hw, - [CLKID_VPU] = &meson8b_vpu.hw, - [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, - [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, - [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw, - [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw, - [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw, - [CLKID_VDEC_1] = &meson8b_vdec_1.hw, - [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, - [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, - [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, - [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, - [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, - [CLKID_VDEC_2] = &meson8b_vdec_2.hw, - [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, - [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, - [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, - [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, - [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, - [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, - [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, - [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, - [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, - [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, - [CLKID_CTS_I958] = &meson8b_cts_i958.hw, - [CLK_NR_CLKS] = NULL, - }, - .num = CLK_NR_CLKS, -}; - -static struct clk_hw_onecell_data meson8m2_hw_onecell_data = { - .hws = { - [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, - [CLKID_PLL_VID] = &meson8b_vid_pll.hw, - [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, - [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, - [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, - [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, - [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, - [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, - [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, - [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, - [CLKID_CLK81] = &meson8b_clk81.hw, - [CLKID_DDR] = &meson8b_ddr.hw, - [CLKID_DOS] = &meson8b_dos.hw, - [CLKID_ISA] = &meson8b_isa.hw, - [CLKID_PL301] = &meson8b_pl301.hw, - [CLKID_PERIPHS] = &meson8b_periphs.hw, - [CLKID_SPICC] = &meson8b_spicc.hw, - [CLKID_I2C] = &meson8b_i2c.hw, - [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, - [CLKID_SMART_CARD] = &meson8b_smart_card.hw, - [CLKID_RNG0] = &meson8b_rng0.hw, - [CLKID_UART0] = &meson8b_uart0.hw, - [CLKID_SDHC] = &meson8b_sdhc.hw, - [CLKID_STREAM] = &meson8b_stream.hw, - [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, - [CLKID_SDIO] = &meson8b_sdio.hw, - [CLKID_ABUF] = &meson8b_abuf.hw, - [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, - [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, - [CLKID_SPI] = &meson8b_spi.hw, - [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, - [CLKID_ETH] = &meson8b_eth.hw, - [CLKID_DEMUX] = &meson8b_demux.hw, - [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, - [CLKID_IEC958] = &meson8b_iec958.hw, - [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, - [CLKID_AMCLK] = &meson8b_amclk.hw, - [CLKID_AIFIFO2] = &meson8b_aififo2.hw, - [CLKID_MIXER] = &meson8b_mixer.hw, - [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, - [CLKID_ADC] = &meson8b_adc.hw, - [CLKID_BLKMV] = &meson8b_blkmv.hw, - [CLKID_AIU] = &meson8b_aiu.hw, - [CLKID_UART1] = &meson8b_uart1.hw, - [CLKID_G2D] = &meson8b_g2d.hw, - [CLKID_USB0] = &meson8b_usb0.hw, - [CLKID_USB1] = &meson8b_usb1.hw, - [CLKID_RESET] = &meson8b_reset.hw, - [CLKID_NAND] = &meson8b_nand.hw, - [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, - [CLKID_USB] = &meson8b_usb.hw, - [CLKID_VDIN1] = &meson8b_vdin1.hw, - [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, - [CLKID_EFUSE] = &meson8b_efuse.hw, - [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, - [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, - [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, - [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, - [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, - [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, - [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, - [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, - [CLKID_DVIN] = &meson8b_dvin.hw, - [CLKID_UART2] = &meson8b_uart2.hw, - [CLKID_SANA] = &meson8b_sana.hw, - [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, - [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, - [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, - [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, - [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, - [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, - [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, - [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, - [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, - [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, - [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, - [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, - [CLKID_ENC480P] = &meson8b_enc480p.hw, - [CLKID_RNG1] = &meson8b_rng1.hw, - [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, - [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, - [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, - [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, - [CLKID_EDP] = &meson8b_edp.hw, - [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, - [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, - [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, - [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, - [CLKID_MPLL0] = &meson8b_mpll0.hw, - [CLKID_MPLL1] = &meson8b_mpll1.hw, - [CLKID_MPLL2] = &meson8b_mpll2.hw, - [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, - [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, - [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, - [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, - [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, - [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, - [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, - [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, - [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, - [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, - [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, - [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, - [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw, - [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, - [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, - [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, - [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, - [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, - [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, - [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, - [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, - [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, - [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, - [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw, - [CLKID_APB] = &meson8b_apb_clk_gate.hw, - [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, - [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, - [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, - [CLKID_AXI] = &meson8b_axi_clk_gate.hw, - [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, - [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw, - [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, - [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, - [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, - [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, - [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, - [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, - [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, - [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, - [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, - [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, - [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw, - [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, - [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw, - [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, - [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw, - [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, - [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw, - [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, - [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw, - [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, - [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw, - [CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw, - [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw, - [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, - [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw, - [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, - [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw, - [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, - [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw, - [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, - [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw, - [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, - [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, - [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, - [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, - [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, - [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, - [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, - [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, - [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, - [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, - [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, - [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, - [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, - [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, - [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, - [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, - [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, - [CLKID_MALI_0] = &meson8b_mali_0.hw, - [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw, - [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw, - [CLKID_MALI_1] = &meson8b_mali_1.hw, - [CLKID_MALI] = &meson8b_mali.hw, - [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw, - [CLKID_GP_PLL] = &meson8m2_gp_pll.hw, - [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw, - [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, - [CLKID_VPU_0] = &meson8b_vpu_0.hw, - [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw, - [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw, - [CLKID_VPU_1] = &meson8b_vpu_1.hw, - [CLKID_VPU] = &meson8b_vpu.hw, - [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, - [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, - [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw, - [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw, - [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw, - [CLKID_VDEC_1] = &meson8b_vdec_1.hw, - [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, - [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, - [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, - [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, - [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, - [CLKID_VDEC_2] = &meson8b_vdec_2.hw, - [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, - [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, - [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, - [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, - [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, - [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, - [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, - [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, - [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, - [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, - [CLKID_CTS_I958] = &meson8b_cts_i958.hw, - [CLK_NR_CLKS] = NULL, - }, - .num = CLK_NR_CLKS, -}; - -static struct clk_regmap *const meson8b_clk_regmaps[] = { - &meson8b_clk81, - &meson8b_ddr, - &meson8b_dos, - &meson8b_isa, - &meson8b_pl301, - &meson8b_periphs, - &meson8b_spicc, - &meson8b_i2c, - &meson8b_sar_adc, - &meson8b_smart_card, - &meson8b_rng0, - &meson8b_uart0, - &meson8b_sdhc, - &meson8b_stream, - &meson8b_async_fifo, - &meson8b_sdio, - &meson8b_abuf, - &meson8b_hiu_iface, - &meson8b_assist_misc, - &meson8b_spi, - &meson8b_i2s_spdif, - &meson8b_eth, - &meson8b_demux, - &meson8b_aiu_glue, - &meson8b_iec958, - &meson8b_i2s_out, - &meson8b_amclk, - &meson8b_aififo2, - &meson8b_mixer, - &meson8b_mixer_iface, - &meson8b_adc, - &meson8b_blkmv, - &meson8b_aiu, - &meson8b_uart1, - &meson8b_g2d, - &meson8b_usb0, - &meson8b_usb1, - &meson8b_reset, - &meson8b_nand, - &meson8b_dos_parser, - &meson8b_usb, - &meson8b_vdin1, - &meson8b_ahb_arb0, - &meson8b_efuse, - &meson8b_boot_rom, - &meson8b_ahb_data_bus, - &meson8b_ahb_ctrl_bus, - &meson8b_hdmi_intr_sync, - &meson8b_hdmi_pclk, - &meson8b_usb1_ddr_bridge, - &meson8b_usb0_ddr_bridge, - &meson8b_mmc_pclk, - &meson8b_dvin, - &meson8b_uart2, - &meson8b_sana, - &meson8b_vpu_intr, - &meson8b_sec_ahb_ahb3_bridge, - &meson8b_clk81_a9, - &meson8b_vclk2_venci0, - &meson8b_vclk2_venci1, - &meson8b_vclk2_vencp0, - &meson8b_vclk2_vencp1, - &meson8b_gclk_venci_int, - &meson8b_gclk_vencp_int, - &meson8b_dac_clk, - &meson8b_aoclk_gate, - &meson8b_iec958_gate, - &meson8b_enc480p, - &meson8b_rng1, - &meson8b_gclk_vencl_int, - &meson8b_vclk2_venclmcc, - &meson8b_vclk2_vencl, - &meson8b_vclk2_other, - &meson8b_edp, - &meson8b_ao_media_cpu, - &meson8b_ao_ahb_sram, - &meson8b_ao_ahb_bus, - &meson8b_ao_iface, - &meson8b_mpeg_clk_div, - &meson8b_mpeg_clk_sel, - &meson8b_mpll0, - &meson8b_mpll1, - &meson8b_mpll2, - &meson8b_mpll0_div, - &meson8b_mpll1_div, - &meson8b_mpll2_div, - &meson8b_fixed_pll, - &meson8b_sys_pll, - &meson8b_cpu_in_sel, - &meson8b_cpu_scale_div, - &meson8b_cpu_scale_out_sel, - &meson8b_cpu_clk, - &meson8b_mpll_prediv, - &meson8b_fclk_div2, - &meson8b_fclk_div3, - &meson8b_fclk_div4, - &meson8b_fclk_div5, - &meson8b_fclk_div7, - &meson8b_nand_clk_sel, - &meson8b_nand_clk_div, - &meson8b_nand_clk_gate, - &meson8b_fixed_pll_dco, - &meson8b_hdmi_pll_dco, - &meson8b_sys_pll_dco, - &meson8b_apb_clk_sel, - &meson8b_apb_clk_gate, - &meson8b_periph_clk_sel, - &meson8b_periph_clk_gate, - &meson8b_axi_clk_sel, - &meson8b_axi_clk_gate, - &meson8b_l2_dram_clk_sel, - &meson8b_l2_dram_clk_gate, - &meson8b_hdmi_pll_lvds_out, - &meson8b_hdmi_pll_hdmi_out, - &meson8b_vid_pll_in_sel, - &meson8b_vid_pll_in_en, - &meson8b_vid_pll_pre_div, - &meson8b_vid_pll_post_div, - &meson8b_vid_pll, - &meson8b_vid_pll_final_div, - &meson8b_vclk_in_sel, - &meson8b_vclk_in_en, - &meson8b_vclk_en, - &meson8b_vclk_div1_gate, - &meson8b_vclk_div2_div_gate, - &meson8b_vclk_div4_div_gate, - &meson8b_vclk_div6_div_gate, - &meson8b_vclk_div12_div_gate, - &meson8b_vclk2_in_sel, - &meson8b_vclk2_clk_in_en, - &meson8b_vclk2_clk_en, - &meson8b_vclk2_div1_gate, - &meson8b_vclk2_div2_div_gate, - &meson8b_vclk2_div4_div_gate, - &meson8b_vclk2_div6_div_gate, - &meson8b_vclk2_div12_div_gate, - &meson8b_cts_enct_sel, - &meson8b_cts_enct, - &meson8b_cts_encp_sel, - &meson8b_cts_encp, - &meson8b_cts_enci_sel, - &meson8b_cts_enci, - &meson8b_hdmi_tx_pixel_sel, - &meson8b_hdmi_tx_pixel, - &meson8b_cts_encl_sel, - &meson8b_cts_encl, - &meson8b_cts_vdac0_sel, - &meson8b_cts_vdac0, - &meson8b_hdmi_sys_sel, - &meson8b_hdmi_sys_div, - &meson8b_hdmi_sys, - &meson8b_mali_0_sel, - &meson8b_mali_0_div, - &meson8b_mali_0, - &meson8b_mali_1_sel, - &meson8b_mali_1_div, - &meson8b_mali_1, - &meson8b_mali, - &meson8m2_gp_pll_dco, - &meson8m2_gp_pll, - &meson8b_vpu_0_sel, - &meson8m2_vpu_0_sel, - &meson8b_vpu_0_div, - &meson8b_vpu_0, - &meson8b_vpu_1_sel, - &meson8m2_vpu_1_sel, - &meson8b_vpu_1_div, - &meson8b_vpu_1, - &meson8b_vpu, - &meson8b_vdec_1_sel, - &meson8b_vdec_1_1_div, - &meson8b_vdec_1_1, - &meson8b_vdec_1_2_div, - &meson8b_vdec_1_2, - &meson8b_vdec_1, - &meson8b_vdec_hcodec_sel, - &meson8b_vdec_hcodec_div, - &meson8b_vdec_hcodec, - &meson8b_vdec_2_sel, - &meson8b_vdec_2_div, - &meson8b_vdec_2, - &meson8b_vdec_hevc_sel, - &meson8b_vdec_hevc_div, - &meson8b_vdec_hevc_en, - &meson8b_vdec_hevc, - &meson8b_cts_amclk, - &meson8b_cts_amclk_sel, - &meson8b_cts_amclk_div, - &meson8b_cts_mclk_i958_sel, - &meson8b_cts_mclk_i958_div, - &meson8b_cts_mclk_i958, - &meson8b_cts_i958, +static MESON8B_PCLK(meson8b_ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); + +static struct clk_hw *meson8_hw_clks[] = { + [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, + [CLKID_PLL_VID] = &meson8b_vid_pll.hw, + [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, + [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, + [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, + [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, + [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, + [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, + [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, + [CLKID_MPEG_SEL] = &meson8b_clk81_sel.hw, + [CLKID_MPEG_DIV] = &meson8b_clk81_div.hw, + [CLKID_CLK81] = &meson8b_clk81.hw, + [CLKID_DDR] = &meson8b_ddr.hw, + [CLKID_DOS] = &meson8b_dos.hw, + [CLKID_ISA] = &meson8b_isa.hw, + [CLKID_PL301] = &meson8b_pl301.hw, + [CLKID_PERIPHS] = &meson8b_periphs.hw, + [CLKID_SPICC] = &meson8b_spicc.hw, + [CLKID_I2C] = &meson8b_i2c.hw, + [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, + [CLKID_SMART_CARD] = &meson8b_smart_card.hw, + [CLKID_RNG0] = &meson8b_rng0.hw, + [CLKID_UART0] = &meson8b_uart0.hw, + [CLKID_SDHC] = &meson8b_sdhc.hw, + [CLKID_STREAM] = &meson8b_stream.hw, + [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, + [CLKID_SDIO] = &meson8b_sdio.hw, + [CLKID_ABUF] = &meson8b_abuf.hw, + [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, + [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, + [CLKID_SPI] = &meson8b_spi.hw, + [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, + [CLKID_ETH] = &meson8b_eth.hw, + [CLKID_DEMUX] = &meson8b_demux.hw, + [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, + [CLKID_IEC958] = &meson8b_iec958.hw, + [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, + [CLKID_AMCLK] = &meson8b_amclk.hw, + [CLKID_AIFIFO2] = &meson8b_aififo2.hw, + [CLKID_MIXER] = &meson8b_mixer.hw, + [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, + [CLKID_ADC] = &meson8b_adc.hw, + [CLKID_BLKMV] = &meson8b_blkmv.hw, + [CLKID_AIU] = &meson8b_aiu.hw, + [CLKID_UART1] = &meson8b_uart1.hw, + [CLKID_G2D] = &meson8b_g2d.hw, + [CLKID_USB0] = &meson8b_usb0.hw, + [CLKID_USB1] = &meson8b_usb1.hw, + [CLKID_RESET] = &meson8b_reset.hw, + [CLKID_NAND] = &meson8b_nand.hw, + [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, + [CLKID_USB] = &meson8b_usb.hw, + [CLKID_VDIN1] = &meson8b_vdin1.hw, + [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, + [CLKID_EFUSE] = &meson8b_efuse.hw, + [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, + [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, + [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, + [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, + [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, + [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, + [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, + [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, + [CLKID_DVIN] = &meson8b_dvin.hw, + [CLKID_UART2] = &meson8b_uart2.hw, + [CLKID_SANA] = &meson8b_sana.hw, + [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, + [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, + [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, + [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, + [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, + [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, + [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, + [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, + [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, + [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, + [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, + [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, + [CLKID_ENC480P] = &meson8b_enc480p.hw, + [CLKID_RNG1] = &meson8b_rng1.hw, + [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, + [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, + [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, + [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, + [CLKID_EDP] = &meson8b_edp.hw, + [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, + [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, + [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, + [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, + [CLKID_MPLL0] = &meson8b_mpll0.hw, + [CLKID_MPLL1] = &meson8b_mpll1.hw, + [CLKID_MPLL2] = &meson8b_mpll2.hw, + [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, + [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, + [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, + [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, + [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, + [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, + [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, + [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, + [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, + [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, + [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, + [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, + [CLKID_NAND_CLK] = &meson8b_nand_clk.hw, + [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, + [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, + [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, + [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, + [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, + [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, + [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, + [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, + [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, + [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, + [CLKID_APB_SEL] = &meson8b_apb_sel.hw, + [CLKID_APB] = &meson8b_apb.hw, + [CLKID_PERIPH_SEL] = &meson8b_periph_sel.hw, + [CLKID_PERIPH] = &meson8b_periph.hw, + [CLKID_AXI_SEL] = &meson8b_axi_sel.hw, + [CLKID_AXI] = &meson8b_axi.hw, + [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_sel.hw, + [CLKID_L2_DRAM] = &meson8b_l2_dram.hw, + [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, + [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, + [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, + [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, + [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, + [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, + [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, + [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, + [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, + [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, + [CLKID_VCLK_DIV1] = &meson8b_vclk_div1.hw, + [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, + [CLKID_VCLK_DIV2] = &meson8b_vclk_div2.hw, + [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, + [CLKID_VCLK_DIV4] = &meson8b_vclk_div4.hw, + [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, + [CLKID_VCLK_DIV6] = &meson8b_vclk_div6.hw, + [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, + [CLKID_VCLK_DIV12] = &meson8b_vclk_div12.hw, + [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, + [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_in_en.hw, + [CLKID_VCLK2_EN] = &meson8b_vclk2_en.hw, + [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1.hw, + [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, + [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2.hw, + [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, + [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4.hw, + [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, + [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6.hw, + [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, + [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12.hw, + [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, + [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, + [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, + [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, + [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, + [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, + [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, + [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, + [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, + [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, + [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, + [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, + [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, + [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, + [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, + [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, + [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, + [CLKID_MALI] = &meson8b_mali_0.hw, + [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw, + [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, + [CLKID_VPU] = &meson8b_vpu_0.hw, + [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, + [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, + [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw, + [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, + [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, + [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, + [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, + [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, + [CLKID_VDEC_2] = &meson8b_vdec_2.hw, + [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, + [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, + [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, + [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, + [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, + [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, + [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, + [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, + [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, + [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, + [CLKID_CTS_I958] = &meson8b_cts_i958.hw, + [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, + [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, +}; + +static struct clk_hw *meson8b_hw_clks[] = { + [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, + [CLKID_PLL_VID] = &meson8b_vid_pll.hw, + [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, + [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, + [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, + [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, + [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, + [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, + [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, + [CLKID_MPEG_SEL] = &meson8b_clk81_sel.hw, + [CLKID_MPEG_DIV] = &meson8b_clk81_div.hw, + [CLKID_CLK81] = &meson8b_clk81.hw, + [CLKID_DDR] = &meson8b_ddr.hw, + [CLKID_DOS] = &meson8b_dos.hw, + [CLKID_ISA] = &meson8b_isa.hw, + [CLKID_PL301] = &meson8b_pl301.hw, + [CLKID_PERIPHS] = &meson8b_periphs.hw, + [CLKID_SPICC] = &meson8b_spicc.hw, + [CLKID_I2C] = &meson8b_i2c.hw, + [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, + [CLKID_SMART_CARD] = &meson8b_smart_card.hw, + [CLKID_RNG0] = &meson8b_rng0.hw, + [CLKID_UART0] = &meson8b_uart0.hw, + [CLKID_SDHC] = &meson8b_sdhc.hw, + [CLKID_STREAM] = &meson8b_stream.hw, + [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, + [CLKID_SDIO] = &meson8b_sdio.hw, + [CLKID_ABUF] = &meson8b_abuf.hw, + [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, + [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, + [CLKID_SPI] = &meson8b_spi.hw, + [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, + [CLKID_ETH] = &meson8b_eth.hw, + [CLKID_DEMUX] = &meson8b_demux.hw, + [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, + [CLKID_IEC958] = &meson8b_iec958.hw, + [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, + [CLKID_AMCLK] = &meson8b_amclk.hw, + [CLKID_AIFIFO2] = &meson8b_aififo2.hw, + [CLKID_MIXER] = &meson8b_mixer.hw, + [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, + [CLKID_ADC] = &meson8b_adc.hw, + [CLKID_BLKMV] = &meson8b_blkmv.hw, + [CLKID_AIU] = &meson8b_aiu.hw, + [CLKID_UART1] = &meson8b_uart1.hw, + [CLKID_G2D] = &meson8b_g2d.hw, + [CLKID_USB0] = &meson8b_usb0.hw, + [CLKID_USB1] = &meson8b_usb1.hw, + [CLKID_RESET] = &meson8b_reset.hw, + [CLKID_NAND] = &meson8b_nand.hw, + [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, + [CLKID_USB] = &meson8b_usb.hw, + [CLKID_VDIN1] = &meson8b_vdin1.hw, + [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, + [CLKID_EFUSE] = &meson8b_efuse.hw, + [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, + [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, + [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, + [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, + [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, + [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, + [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, + [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, + [CLKID_DVIN] = &meson8b_dvin.hw, + [CLKID_UART2] = &meson8b_uart2.hw, + [CLKID_SANA] = &meson8b_sana.hw, + [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, + [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, + [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, + [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, + [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, + [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, + [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, + [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, + [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, + [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, + [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, + [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, + [CLKID_ENC480P] = &meson8b_enc480p.hw, + [CLKID_RNG1] = &meson8b_rng1.hw, + [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, + [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, + [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, + [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, + [CLKID_EDP] = &meson8b_edp.hw, + [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, + [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, + [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, + [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, + [CLKID_MPLL0] = &meson8b_mpll0.hw, + [CLKID_MPLL1] = &meson8b_mpll1.hw, + [CLKID_MPLL2] = &meson8b_mpll2.hw, + [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, + [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, + [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, + [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, + [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, + [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, + [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, + [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, + [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, + [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, + [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, + [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, + [CLKID_NAND_CLK] = &meson8b_nand_clk.hw, + [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, + [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, + [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, + [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, + [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, + [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, + [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, + [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, + [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, + [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, + [CLKID_APB_SEL] = &meson8b_apb_sel.hw, + [CLKID_APB] = &meson8b_apb.hw, + [CLKID_PERIPH_SEL] = &meson8b_periph_sel.hw, + [CLKID_PERIPH] = &meson8b_periph.hw, + [CLKID_AXI_SEL] = &meson8b_axi_sel.hw, + [CLKID_AXI] = &meson8b_axi.hw, + [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_sel.hw, + [CLKID_L2_DRAM] = &meson8b_l2_dram.hw, + [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, + [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, + [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, + [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, + [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, + [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, + [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, + [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, + [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, + [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, + [CLKID_VCLK_DIV1] = &meson8b_vclk_div1.hw, + [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, + [CLKID_VCLK_DIV2] = &meson8b_vclk_div2.hw, + [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, + [CLKID_VCLK_DIV4] = &meson8b_vclk_div4.hw, + [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, + [CLKID_VCLK_DIV6] = &meson8b_vclk_div6.hw, + [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, + [CLKID_VCLK_DIV12] = &meson8b_vclk_div12.hw, + [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, + [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_in_en.hw, + [CLKID_VCLK2_EN] = &meson8b_vclk2_en.hw, + [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1.hw, + [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, + [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2.hw, + [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, + [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4.hw, + [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, + [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6.hw, + [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, + [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12.hw, + [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, + [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, + [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, + [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, + [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, + [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, + [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, + [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, + [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, + [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, + [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, + [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, + [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, + [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, + [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, + [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, + [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, + [CLKID_MALI_0] = &meson8b_mali_0.hw, + [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw, + [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw, + [CLKID_MALI_1] = &meson8b_mali_1.hw, + [CLKID_MALI] = &meson8b_mali.hw, + [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw, + [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, + [CLKID_VPU_0] = &meson8b_vpu_0.hw, + [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw, + [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw, + [CLKID_VPU_1] = &meson8b_vpu_1.hw, + [CLKID_VPU] = &meson8b_vpu.hw, + [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, + [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, + [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw, + [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw, + [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw, + [CLKID_VDEC_1] = &meson8b_vdec_1.hw, + [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, + [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, + [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, + [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, + [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, + [CLKID_VDEC_2] = &meson8b_vdec_2.hw, + [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, + [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, + [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, + [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, + [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, + [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, + [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, + [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, + [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, + [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, + [CLKID_CTS_I958] = &meson8b_cts_i958.hw, + [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, + [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, +}; + +static struct clk_hw *meson8m2_hw_clks[] = { + [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, + [CLKID_PLL_VID] = &meson8b_vid_pll.hw, + [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, + [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw, + [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw, + [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw, + [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw, + [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw, + [CLKID_CPUCLK] = &meson8b_cpu_clk.hw, + [CLKID_MPEG_SEL] = &meson8b_clk81_sel.hw, + [CLKID_MPEG_DIV] = &meson8b_clk81_div.hw, + [CLKID_CLK81] = &meson8b_clk81.hw, + [CLKID_DDR] = &meson8b_ddr.hw, + [CLKID_DOS] = &meson8b_dos.hw, + [CLKID_ISA] = &meson8b_isa.hw, + [CLKID_PL301] = &meson8b_pl301.hw, + [CLKID_PERIPHS] = &meson8b_periphs.hw, + [CLKID_SPICC] = &meson8b_spicc.hw, + [CLKID_I2C] = &meson8b_i2c.hw, + [CLKID_SAR_ADC] = &meson8b_sar_adc.hw, + [CLKID_SMART_CARD] = &meson8b_smart_card.hw, + [CLKID_RNG0] = &meson8b_rng0.hw, + [CLKID_UART0] = &meson8b_uart0.hw, + [CLKID_SDHC] = &meson8b_sdhc.hw, + [CLKID_STREAM] = &meson8b_stream.hw, + [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw, + [CLKID_SDIO] = &meson8b_sdio.hw, + [CLKID_ABUF] = &meson8b_abuf.hw, + [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw, + [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw, + [CLKID_SPI] = &meson8b_spi.hw, + [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw, + [CLKID_ETH] = &meson8b_eth.hw, + [CLKID_DEMUX] = &meson8b_demux.hw, + [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw, + [CLKID_IEC958] = &meson8b_iec958.hw, + [CLKID_I2S_OUT] = &meson8b_i2s_out.hw, + [CLKID_AMCLK] = &meson8b_amclk.hw, + [CLKID_AIFIFO2] = &meson8b_aififo2.hw, + [CLKID_MIXER] = &meson8b_mixer.hw, + [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw, + [CLKID_ADC] = &meson8b_adc.hw, + [CLKID_BLKMV] = &meson8b_blkmv.hw, + [CLKID_AIU] = &meson8b_aiu.hw, + [CLKID_UART1] = &meson8b_uart1.hw, + [CLKID_G2D] = &meson8b_g2d.hw, + [CLKID_USB0] = &meson8b_usb0.hw, + [CLKID_USB1] = &meson8b_usb1.hw, + [CLKID_RESET] = &meson8b_reset.hw, + [CLKID_NAND] = &meson8b_nand.hw, + [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw, + [CLKID_USB] = &meson8b_usb.hw, + [CLKID_VDIN1] = &meson8b_vdin1.hw, + [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw, + [CLKID_EFUSE] = &meson8b_efuse.hw, + [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw, + [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw, + [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw, + [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw, + [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw, + [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw, + [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw, + [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw, + [CLKID_DVIN] = &meson8b_dvin.hw, + [CLKID_UART2] = &meson8b_uart2.hw, + [CLKID_SANA] = &meson8b_sana.hw, + [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw, + [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw, + [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw, + [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw, + [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw, + [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw, + [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw, + [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, + [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw, + [CLKID_DAC_CLK] = &meson8b_dac_clk.hw, + [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw, + [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw, + [CLKID_ENC480P] = &meson8b_enc480p.hw, + [CLKID_RNG1] = &meson8b_rng1.hw, + [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw, + [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw, + [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw, + [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw, + [CLKID_EDP] = &meson8b_edp.hw, + [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw, + [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, + [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, + [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, + [CLKID_MPLL0] = &meson8b_mpll0.hw, + [CLKID_MPLL1] = &meson8b_mpll1.hw, + [CLKID_MPLL2] = &meson8b_mpll2.hw, + [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, + [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, + [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, + [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, + [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, + [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, + [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, + [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, + [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, + [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw, + [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw, + [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw, + [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw, + [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw, + [CLKID_NAND_CLK] = &meson8b_nand_clk.hw, + [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, + [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw, + [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, + [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, + [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, + [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, + [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, + [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, + [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, + [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, + [CLKID_APB_SEL] = &meson8b_apb_sel.hw, + [CLKID_APB] = &meson8b_apb.hw, + [CLKID_PERIPH_SEL] = &meson8b_periph_sel.hw, + [CLKID_PERIPH] = &meson8b_periph.hw, + [CLKID_AXI_SEL] = &meson8b_axi_sel.hw, + [CLKID_AXI] = &meson8b_axi.hw, + [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_sel.hw, + [CLKID_L2_DRAM] = &meson8b_l2_dram.hw, + [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw, + [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw, + [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw, + [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw, + [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw, + [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw, + [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw, + [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw, + [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw, + [CLKID_VCLK_EN] = &meson8b_vclk_en.hw, + [CLKID_VCLK_DIV1] = &meson8b_vclk_div1.hw, + [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw, + [CLKID_VCLK_DIV2] = &meson8b_vclk_div2.hw, + [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw, + [CLKID_VCLK_DIV4] = &meson8b_vclk_div4.hw, + [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw, + [CLKID_VCLK_DIV6] = &meson8b_vclk_div6.hw, + [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw, + [CLKID_VCLK_DIV12] = &meson8b_vclk_div12.hw, + [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw, + [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_in_en.hw, + [CLKID_VCLK2_EN] = &meson8b_vclk2_en.hw, + [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1.hw, + [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw, + [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2.hw, + [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw, + [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4.hw, + [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw, + [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6.hw, + [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw, + [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12.hw, + [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw, + [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw, + [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw, + [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw, + [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw, + [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw, + [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw, + [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw, + [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw, + [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw, + [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw, + [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw, + [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw, + [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw, + [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw, + [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, + [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, + [CLKID_MALI_0] = &meson8b_mali_0.hw, + [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw, + [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw, + [CLKID_MALI_1] = &meson8b_mali_1.hw, + [CLKID_MALI] = &meson8b_mali.hw, + [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw, + [CLKID_GP_PLL] = &meson8m2_gp_pll.hw, + [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw, + [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw, + [CLKID_VPU_0] = &meson8b_vpu_0.hw, + [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw, + [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw, + [CLKID_VPU_1] = &meson8b_vpu_1.hw, + [CLKID_VPU] = &meson8b_vpu.hw, + [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw, + [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw, + [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw, + [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw, + [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw, + [CLKID_VDEC_1] = &meson8b_vdec_1.hw, + [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw, + [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw, + [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw, + [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw, + [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw, + [CLKID_VDEC_2] = &meson8b_vdec_2.hw, + [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw, + [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw, + [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw, + [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw, + [CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw, + [CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw, + [CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw, + [CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw, + [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, + [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, + [CLKID_CTS_I958] = &meson8b_cts_i958.hw, + [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, + [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, }; static const struct meson8b_clk_reset_line { @@ -3635,7 +3540,6 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev, container_of(rcdev, struct meson8b_clk_reset, reset); const struct meson8b_clk_reset_line *reset; unsigned int value = 0; - unsigned long flags; if (id >= ARRAY_SIZE(meson8b_clk_reset_bits)) return -EINVAL; @@ -3645,13 +3549,9 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev, if (assert != reset->active_low) value = BIT(reset->bit_idx); - spin_lock_irqsave(&meson_clk_lock, flags); - regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, BIT(reset->bit_idx), value); - spin_unlock_irqrestore(&meson_clk_lock, flags); - return 0; } @@ -3713,16 +3613,34 @@ static struct meson8b_nb_data meson8b_cpu_nb_data = { .nb.notifier_call = meson8b_cpu_clk_notifier_cb, }; +static struct meson_clk_hw_data meson8_clks = { + .hws = meson8_hw_clks, + .num = ARRAY_SIZE(meson8_hw_clks), +}; + +static struct meson_clk_hw_data meson8b_clks = { + .hws = meson8b_hw_clks, + .num = ARRAY_SIZE(meson8b_hw_clks), +}; + +static struct meson_clk_hw_data meson8m2_clks = { + .hws = meson8m2_hw_clks, + .num = ARRAY_SIZE(meson8m2_hw_clks), +}; + static void __init meson8b_clkc_init_common(struct device_node *np, - struct clk_hw_onecell_data *clk_hw_onecell_data) + struct meson_clk_hw_data *hw_clks) { struct meson8b_clk_reset *rstc; + struct device_node *parent_np; const char *notifier_clk_name; struct clk *notifier_clk; struct regmap *map; int i, ret; - map = syscon_node_to_regmap(of_get_parent(np)); + parent_np = of_get_parent(np); + map = syscon_node_to_regmap(parent_np); + of_node_put(parent_np); if (IS_ERR(map)) { pr_err("failed to get HHI regmap - Trying obsolete regs\n"); return; @@ -3744,25 +3662,21 @@ static void __init meson8b_clkc_init_common(struct device_node *np, return; } - /* Populate regmap for the regmap backed clocks */ - for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++) - meson8b_clk_regmaps[i]->map = map; - /* * register all clks and start with the first used ID (which is * CLKID_PLL_FIXED) */ - for (i = CLKID_PLL_FIXED; i < CLK_NR_CLKS; i++) { + for (i = CLKID_PLL_FIXED; i < hw_clks->num; i++) { /* array might be sparse */ - if (!clk_hw_onecell_data->hws[i]) + if (!hw_clks->hws[i]) continue; - ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]); + ret = of_clk_hw_register(np, hw_clks->hws[i]); if (ret) return; } - meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK]; + meson8b_cpu_nb_data.cpu_clk = hw_clks->hws[CLKID_CPUCLK]; /* * FIXME we shouldn't program the muxes in notifier handlers. The @@ -3778,25 +3692,24 @@ static void __init meson8b_clkc_init_common(struct device_node *np, return; } - ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, - clk_hw_onecell_data); + ret = of_clk_add_hw_provider(np, meson_clk_hw_get, hw_clks); if (ret) pr_err("%s: failed to register clock provider\n", __func__); } static void __init meson8_clkc_init(struct device_node *np) { - return meson8b_clkc_init_common(np, &meson8_hw_onecell_data); + return meson8b_clkc_init_common(np, &meson8_clks); } static void __init meson8b_clkc_init(struct device_node *np) { - return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data); + return meson8b_clkc_init_common(np, &meson8b_clks); } static void __init meson8m2_clkc_init(struct device_node *np) { - return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data); + return meson8b_clkc_init_common(np, &meson8m2_clks); } CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc", |