diff options
Diffstat (limited to 'drivers/clk/meson/vclk.c')
| -rw-r--r-- | drivers/clk/meson/vclk.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/clk/meson/vclk.c b/drivers/clk/meson/vclk.c index e886df55d6e3..009bd1193042 100644 --- a/drivers/clk/meson/vclk.c +++ b/drivers/clk/meson/vclk.c @@ -45,11 +45,12 @@ static int meson_vclk_gate_is_enabled(struct clk_hw *hw) } const struct clk_ops meson_vclk_gate_ops = { + .init = clk_regmap_init, .enable = meson_vclk_gate_enable, .disable = meson_vclk_gate_disable, .is_enabled = meson_vclk_gate_is_enabled, }; -EXPORT_SYMBOL_GPL(meson_vclk_gate_ops); +EXPORT_SYMBOL_NS_GPL(meson_vclk_gate_ops, "CLK_MESON"); /* The VCLK Divider has supplementary reset & enable bits */ @@ -127,6 +128,7 @@ static int meson_vclk_div_is_enabled(struct clk_hw *hw) } const struct clk_ops meson_vclk_div_ops = { + .init = clk_regmap_init, .recalc_rate = meson_vclk_div_recalc_rate, .determine_rate = meson_vclk_div_determine_rate, .set_rate = meson_vclk_div_set_rate, @@ -134,8 +136,9 @@ const struct clk_ops meson_vclk_div_ops = { .disable = meson_vclk_div_disable, .is_enabled = meson_vclk_div_is_enabled, }; -EXPORT_SYMBOL_GPL(meson_vclk_div_ops); +EXPORT_SYMBOL_NS_GPL(meson_vclk_div_ops, "CLK_MESON"); MODULE_DESCRIPTION("Amlogic vclk clock driver"); MODULE_AUTHOR("Neil Armstrong <neil.armstrong@linaro.org>"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CLK_MESON"); |