diff options
Diffstat (limited to 'drivers/clk/qcom/clk-branch.c')
| -rw-r--r-- | drivers/clk/qcom/clk-branch.c | 89 |
1 files changed, 65 insertions, 24 deletions
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index 26f7af315066..444e7d8648d4 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -1,14 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/kernel.h> @@ -26,7 +19,7 @@ static bool clk_branch_in_hwcg_mode(const struct clk_branch *br) u32 val; if (!br->hwcg_reg) - return 0; + return false; regmap_read(br->clkr.regmap, br->hwcg_reg, &val); @@ -35,7 +28,7 @@ static bool clk_branch_in_hwcg_mode(const struct clk_branch *br) static bool clk_branch_check_halt(const struct clk_branch *br, bool enabling) { - bool invert = (br->halt_check == BRANCH_HALT_ENABLE); + bool invert = (br->halt_check & BRANCH_HALT_ENABLE); u32 val; regmap_read(br->clkr.regmap, br->halt_reg, &val); @@ -47,28 +40,23 @@ static bool clk_branch_check_halt(const struct clk_branch *br, bool enabling) return !!val == !enabling; } -#define BRANCH_CLK_OFF BIT(31) -#define BRANCH_NOC_FSM_STATUS_SHIFT 28 -#define BRANCH_NOC_FSM_STATUS_MASK 0x7 -#define BRANCH_NOC_FSM_STATUS_ON (0x2 << BRANCH_NOC_FSM_STATUS_SHIFT) - static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling) { u32 val; u32 mask; + bool invert = (br->halt_check & BRANCH_HALT_ENABLE); - mask = BRANCH_NOC_FSM_STATUS_MASK << BRANCH_NOC_FSM_STATUS_SHIFT; - mask |= BRANCH_CLK_OFF; + mask = CBCR_NOC_FSM_STATUS; + mask |= CBCR_CLK_OFF; regmap_read(br->clkr.regmap, br->halt_reg, &val); if (enabling) { val &= mask; - return (val & BRANCH_CLK_OFF) == 0 || - val == BRANCH_NOC_FSM_STATUS_ON; - } else { - return val & BRANCH_CLK_OFF; + return (val & CBCR_CLK_OFF) == (invert ? CBCR_CLK_OFF : 0) || + FIELD_GET(CBCR_NOC_FSM_STATUS, val) == FSM_STATUS_ON; } + return (val & CBCR_CLK_OFF) == (invert ? 0 : CBCR_CLK_OFF); } static int clk_branch_wait(const struct clk_branch *br, bool enabling, @@ -77,8 +65,11 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling, bool voted = br->halt_check & BRANCH_VOTED; const char *name = clk_hw_get_name(&br->clkr.hw); - /* Skip checking halt bit if the clock is in hardware gated mode */ - if (clk_branch_in_hwcg_mode(br)) + /* + * Skip checking halt bit if we're explicitly ignoring the bit or the + * clock is in hardware gated mode + */ + if (br->halt_check == BRANCH_HALT_SKIP || clk_branch_in_hwcg_mode(br)) return 0; if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) { @@ -144,6 +135,43 @@ static void clk_branch2_disable(struct clk_hw *hw) clk_branch_toggle(hw, false, clk_branch2_check_halt); } +static int clk_branch2_mem_enable(struct clk_hw *hw) +{ + struct clk_mem_branch *mem_br = to_clk_mem_branch(hw); + struct clk_branch branch = mem_br->branch; + u32 val; + int ret; + + regmap_assign_bits(branch.clkr.regmap, mem_br->mem_enable_reg, + mem_br->mem_enable_mask, !mem_br->mem_enable_invert); + + ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg, + val, val & mem_br->mem_enable_ack_mask, 0, 200); + if (ret) { + WARN(1, "%s mem enable failed\n", clk_hw_get_name(&branch.clkr.hw)); + return ret; + } + + return clk_branch2_enable(hw); +} + +static void clk_branch2_mem_disable(struct clk_hw *hw) +{ + struct clk_mem_branch *mem_br = to_clk_mem_branch(hw); + + regmap_assign_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg, + mem_br->mem_enable_mask, mem_br->mem_enable_invert); + + return clk_branch2_disable(hw); +} + +const struct clk_ops clk_branch2_mem_ops = { + .enable = clk_branch2_mem_enable, + .disable = clk_branch2_mem_disable, + .is_enabled = clk_is_enabled_regmap, +}; +EXPORT_SYMBOL_GPL(clk_branch2_mem_ops); + const struct clk_ops clk_branch2_ops = { .enable = clk_branch2_enable, .disable = clk_branch2_disable, @@ -151,9 +179,22 @@ const struct clk_ops clk_branch2_ops = { }; EXPORT_SYMBOL_GPL(clk_branch2_ops); +const struct clk_ops clk_branch2_aon_ops = { + .enable = clk_branch2_enable, + .is_enabled = clk_is_enabled_regmap, +}; +EXPORT_SYMBOL_GPL(clk_branch2_aon_ops); + const struct clk_ops clk_branch_simple_ops = { .enable = clk_enable_regmap, .disable = clk_disable_regmap, .is_enabled = clk_is_enabled_regmap, }; EXPORT_SYMBOL_GPL(clk_branch_simple_ops); + +const struct clk_ops clk_branch2_prepare_ops = { + .prepare = clk_branch2_enable, + .unprepare = clk_branch2_disable, + .is_prepared = clk_is_enabled_regmap, +}; +EXPORT_SYMBOL_GPL(clk_branch2_prepare_ops); |