diff options
Diffstat (limited to 'drivers/clk/qcom/clk-hfpll.c')
| -rw-r--r-- | drivers/clk/qcom/clk-hfpll.c | 39 |
1 files changed, 24 insertions, 15 deletions
diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c index 3c04805f2a55..705352aff067 100644 --- a/drivers/clk/qcom/clk-hfpll.c +++ b/drivers/clk/qcom/clk-hfpll.c @@ -44,6 +44,10 @@ static void __clk_hfpll_init_once(struct clk_hw *hw) regmap_write(regmap, hd->user_reg, regval); } + /* Write L_VAL from conf if it exist */ + if (hd->l_val) + regmap_write(regmap, hd->l_reg, hd->l_val); + if (hd->droop_reg) regmap_write(regmap, hd->droop_reg, hd->droop_val); @@ -72,13 +76,16 @@ static void __clk_hfpll_enable(struct clk_hw *hw) regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); /* Wait for PLL to lock. */ - if (hd->status_reg) { - do { - regmap_read(regmap, hd->status_reg, &val); - } while (!(val & BIT(hd->lock_bit))); - } else { + if (hd->status_reg) + /* + * Busy wait. Should never timeout, we add a timeout to + * prevent any sort of stall. + */ + regmap_read_poll_timeout(regmap, hd->status_reg, val, + !(val & BIT(hd->lock_bit)), 0, + 100 * USEC_PER_MSEC); + else udelay(60); - } /* Enable PLL output. */ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); @@ -125,20 +132,20 @@ static void clk_hfpll_disable(struct clk_hw *hw) spin_unlock_irqrestore(&h->lock, flags); } -static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int clk_hfpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_hfpll *h = to_clk_hfpll(hw); struct hfpll_data const *hd = h->d; unsigned long rrate; - rate = clamp(rate, hd->min_rate, hd->max_rate); + req->rate = clamp(req->rate, hd->min_rate, hd->max_rate); - rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate; + rrate = DIV_ROUND_UP(req->rate, req->best_parent_rate) * req->best_parent_rate; if (rrate > hd->max_rate) - rrate -= *parent_rate; + rrate -= req->best_parent_rate; - return rrate; + req->rate = rrate; + return 0; } /* @@ -196,7 +203,7 @@ static unsigned long clk_hfpll_recalc_rate(struct clk_hw *hw, return l_val * parent_rate; } -static void clk_hfpll_init(struct clk_hw *hw) +static int clk_hfpll_init(struct clk_hw *hw) { struct clk_hfpll *h = to_clk_hfpll(hw); struct hfpll_data const *hd = h->d; @@ -206,7 +213,7 @@ static void clk_hfpll_init(struct clk_hw *hw) regmap_read(regmap, hd->mode_reg, &mode); if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { __clk_hfpll_init_once(hw); - return; + return 0; } if (hd->status_reg) { @@ -218,6 +225,8 @@ static void clk_hfpll_init(struct clk_hw *hw) __clk_hfpll_init_once(hw); } } + + return 0; } static int hfpll_is_enabled(struct clk_hw *hw) @@ -236,7 +245,7 @@ const struct clk_ops clk_ops_hfpll = { .enable = clk_hfpll_enable, .disable = clk_hfpll_disable, .is_enabled = hfpll_is_enabled, - .round_rate = clk_hfpll_round_rate, + .determine_rate = clk_hfpll_determine_rate, .set_rate = clk_hfpll_set_rate, .recalc_rate = clk_hfpll_recalc_rate, .init = clk_hfpll_init, |