diff options
Diffstat (limited to 'drivers/clk/qcom/dispcc-sdm845.c')
| -rw-r--r-- | drivers/clk/qcom/dispcc-sdm845.c | 393 |
1 files changed, 294 insertions, 99 deletions
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c index 0cc4909b5dbe..2f9e9665d7e9 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -1,13 +1,13 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/regmap.h> -#include <linux/reset-controller.h> #include <dt-bindings/clock/qcom,dispcc-sdm845.h> @@ -21,7 +21,6 @@ enum { P_BI_TCXO, - P_CORE_BI_PLL_TEST_SE, P_DISP_CC_PLL0_OUT_MAIN, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, @@ -29,30 +28,55 @@ enum { P_DSI1_PHY_PLL_OUT_DSICLK, P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN_DIV, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV_CLK, +}; + +static struct clk_alpha_pll disp_cc_pll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, }; static const struct parent_map disp_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; -static const char * const disp_cc_parent_names_0[] = { - "bi_tcxo", - "dsi0_phy_pll_out_byteclk", - "dsi1_phy_pll_out_byteclk", - "core_bi_pll_test_se", +static const struct clk_parent_data disp_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" }, + { .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" }, +}; + +static const struct parent_map disp_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .fw_name = "dp_link_clk_divsel_ten", .name = "dp_link_clk_divsel_ten" }, + { .fw_name = "dp_vco_divided_clk_src_mux", .name = "dp_vco_divided_clk_src_mux" }, }; static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; -static const char * const disp_cc_parent_names_2[] = { - "bi_tcxo", - "core_bi_pll_test_se", +static const struct clk_parent_data disp_cc_parent_data_2[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, }; static const struct parent_map disp_cc_parent_map_3[] = { @@ -60,42 +84,25 @@ static const struct parent_map disp_cc_parent_map_3[] = { { P_DISP_CC_PLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_MAIN, 4 }, { P_GPLL0_OUT_MAIN_DIV, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; -static const char * const disp_cc_parent_names_3[] = { - "bi_tcxo", - "disp_cc_pll0", - "gcc_disp_gpll0_clk_src", - "gcc_disp_gpll0_div_clk_src", - "core_bi_pll_test_se", +static const struct clk_parent_data disp_cc_parent_data_3[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .hw = &disp_cc_pll0.clkr.hw }, + { .fw_name = "gcc_disp_gpll0_clk_src", .name = "gcc_disp_gpll0_clk_src" }, + { .fw_name = "gcc_disp_gpll0_div_clk_src", .name = "gcc_disp_gpll0_div_clk_src" }, }; static const struct parent_map disp_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; -static const char * const disp_cc_parent_names_4[] = { - "bi_tcxo", - "dsi0_phy_pll_out_dsiclk", - "dsi1_phy_pll_out_dsiclk", - "core_bi_pll_test_se", -}; - -static struct clk_alpha_pll disp_cc_pll0 = { - .offset = 0x0, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_pll0", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_fabia_ops, - }, - }, +static const struct clk_parent_data disp_cc_parent_data_4[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" }, + { .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" }, }; /* Return the HW recalc rate for idle use case */ @@ -106,8 +113,8 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .parent_map = disp_cc_parent_map_0, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", - .parent_names = disp_cc_parent_names_0, - .num_parents = 4, + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -121,13 +128,88 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { .parent_map = disp_cc_parent_map_0, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_clk_src", - .parent_names = disp_cc_parent_names_0, - .num_parents = 4, + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, }; +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr = 0x219c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { + .cmd_rcgr = 0x2154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr = 0x2138, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { + .cmd_rcgr = 0x2184, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel1_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr = 0x216c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_dp_ops, + }, +}; + static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), { } @@ -141,8 +223,8 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", - .parent_names = disp_cc_parent_names_0, - .num_parents = 4, + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -155,8 +237,8 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc1_clk_src", - .parent_names = disp_cc_parent_names_0, - .num_parents = 4, + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -182,8 +264,8 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", - .parent_names = disp_cc_parent_names_3, - .num_parents = 5, + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -196,8 +278,8 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .parent_map = disp_cc_parent_map_4, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", - .parent_names = disp_cc_parent_names_4, - .num_parents = 4, + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -211,8 +293,8 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { .parent_map = disp_cc_parent_map_4, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk1_clk_src", - .parent_names = disp_cc_parent_names_4, - .num_parents = 4, + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -235,8 +317,8 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk_src", - .parent_names = disp_cc_parent_names_3, - .num_parents = 5, + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -249,8 +331,8 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", - .parent_names = disp_cc_parent_names_2, - .num_parents = 2, + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -290,8 +372,8 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -308,8 +390,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_div_clk_src", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_regmap_div_ops, @@ -326,8 +408,8 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_intf_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte0_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -345,8 +427,8 @@ static struct clk_branch disp_cc_mdss_byte1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -363,8 +445,8 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_div_clk_src", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_regmap_div_ops, @@ -381,8 +463,116 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_intf_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte1_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg = 0x2054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg = 0x2048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg = 0x2040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */ +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg = 0x2044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { + .halt_reg = 0x2050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel1_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk = { + .halt_reg = 0x204c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x204c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -399,8 +589,8 @@ static struct clk_branch disp_cc_mdss_esc0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_esc0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -417,8 +607,8 @@ static struct clk_branch disp_cc_mdss_esc1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc1_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_esc1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -435,8 +625,8 @@ static struct clk_branch disp_cc_mdss_mdp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_mdp_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -453,8 +643,8 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_lut_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_mdp_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -471,8 +661,8 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_pclk0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -490,8 +680,8 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk1_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_pclk1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -508,8 +698,8 @@ static struct clk_branch disp_cc_mdss_rot_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_rot_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_rot_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -539,8 +729,8 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rscc_vsync_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_vsync_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -557,8 +747,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_vsync_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -569,6 +759,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { static struct gdsc mdss_gdsc = { .gdscr = 0x3000, + .en_few_wait_val = 0x6, + .en_rest_wait_val = 0x5, .pd = { .name = "mdss_gdsc", }, @@ -589,6 +781,19 @@ static struct clk_regmap *disp_cc_sdm845_clocks[] = { [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, + [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = + &disp_cc_mdss_dp_crypto_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = + &disp_cc_mdss_dp_pixel1_clk_src.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, @@ -658,7 +863,7 @@ static int disp_cc_sdm845_probe(struct platform_device *pdev) /* Enable hardware clock gating for DSI and MDP clocks */ regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0); - return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &disp_cc_sdm845_desc, regmap); } static struct platform_driver disp_cc_sdm845_driver = { @@ -669,17 +874,7 @@ static struct platform_driver disp_cc_sdm845_driver = { }, }; -static int __init disp_cc_sdm845_init(void) -{ - return platform_driver_register(&disp_cc_sdm845_driver); -} -subsys_initcall(disp_cc_sdm845_init); - -static void __exit disp_cc_sdm845_exit(void) -{ - platform_driver_unregister(&disp_cc_sdm845_driver); -} -module_exit(disp_cc_sdm845_exit); +module_platform_driver(disp_cc_sdm845_driver); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("QTI DISPCC SDM845 Driver"); |