diff options
Diffstat (limited to 'drivers/clk/qcom/gcc-msm8660.c')
| -rw-r--r-- | drivers/clk/qcom/gcc-msm8660.c | 361 |
1 files changed, 200 insertions, 161 deletions
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c index c347a0d44bc8..a6a4477ccdef 100644 --- a/drivers/clk/qcom/gcc-msm8660.c +++ b/drivers/clk/qcom/gcc-msm8660.c @@ -1,14 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/kernel.h> @@ -17,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> @@ -42,7 +33,9 @@ static struct clk_pll pll8 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll8", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", .name = "pxo_board", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -53,7 +46,9 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "pll8_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_hws = (const struct clk_hw*[]){ + &pll8.clkr.hw + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -70,9 +65,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = { { P_PLL8, 3 } }; -static const char * const gcc_pxo_pll8[] = { - "pxo", - "pll8_vote", +static const struct clk_parent_data gcc_pxo_pll8[] = { + { .fw_name = "pxo", .name = "pxo_board" }, + { .hw = &pll8_vote.hw }, }; static const struct parent_map gcc_pxo_pll8_cxo_map[] = { @@ -81,13 +76,13 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = { { P_CXO, 5 } }; -static const char * const gcc_pxo_pll8_cxo[] = { - "pxo", - "pll8_vote", - "cxo", +static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { + { .fw_name = "pxo", .name = "pxo_board" }, + { .hw = &pll8_vote.hw }, + { .fw_name = "cxo", .name = "cxo_board" }, }; -static struct freq_tbl clk_tbl_gsbi_uart[] = { +static const struct freq_tbl clk_tbl_gsbi_uart[] = { { 1843200, P_PLL8, 2, 6, 625 }, { 3686400, P_PLL8, 2, 12, 625 }, { 7372800, P_PLL8, 2, 24, 625 }, @@ -130,8 +125,8 @@ static struct clk_rcg gsbi1_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -146,8 +141,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_clk", - .parent_names = (const char *[]){ - "gsbi1_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_uart_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch_ops, @@ -181,8 +176,8 @@ static struct clk_rcg gsbi2_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -197,8 +192,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_clk", - .parent_names = (const char *[]){ - "gsbi2_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_uart_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch_ops, @@ -232,8 +227,8 @@ static struct clk_rcg gsbi3_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -248,8 +243,8 @@ static struct clk_branch gsbi3_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_clk", - .parent_names = (const char *[]){ - "gsbi3_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi3_uart_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch_ops, @@ -283,8 +278,8 @@ static struct clk_rcg gsbi4_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -299,8 +294,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_clk", - .parent_names = (const char *[]){ - "gsbi4_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_uart_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch_ops, @@ -334,8 +329,8 @@ static struct clk_rcg gsbi5_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -350,8 +345,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_clk", - .parent_names = (const char *[]){ - "gsbi5_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_uart_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch_ops, @@ -385,8 +380,8 @@ static struct clk_rcg gsbi6_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -401,8 +396,8 @@ static struct clk_branch gsbi6_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_clk", - .parent_names = (const char *[]){ - "gsbi6_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_uart_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch_ops, @@ -436,8 +431,8 @@ static struct clk_rcg gsbi7_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -452,8 +447,8 @@ static struct clk_branch gsbi7_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_clk", - .parent_names = (const char *[]){ - "gsbi7_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_uart_src.clkr.hw }, .num_parents = 1, .ops = &clk_branch_ops, @@ -487,8 +482,8 @@ static struct clk_rcg gsbi8_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi8_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -503,7 +498,9 @@ static struct clk_branch gsbi8_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi8_uart_clk", - .parent_names = (const char *[]){ "gsbi8_uart_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi8_uart_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -536,8 +533,8 @@ static struct clk_rcg gsbi9_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi9_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -552,7 +549,9 @@ static struct clk_branch gsbi9_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi9_uart_clk", - .parent_names = (const char *[]){ "gsbi9_uart_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi9_uart_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -585,8 +584,8 @@ static struct clk_rcg gsbi10_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi10_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -601,7 +600,9 @@ static struct clk_branch gsbi10_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi10_uart_clk", - .parent_names = (const char *[]){ "gsbi10_uart_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi10_uart_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -634,8 +635,8 @@ static struct clk_rcg gsbi11_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi11_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -650,7 +651,9 @@ static struct clk_branch gsbi11_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi11_uart_clk", - .parent_names = (const char *[]){ "gsbi11_uart_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi11_uart_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -683,8 +686,8 @@ static struct clk_rcg gsbi12_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi12_uart_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -699,7 +702,9 @@ static struct clk_branch gsbi12_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi12_uart_clk", - .parent_names = (const char *[]){ "gsbi12_uart_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi12_uart_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -707,7 +712,7 @@ static struct clk_branch gsbi12_uart_clk = { }, }; -static struct freq_tbl clk_tbl_gsbi_qup[] = { +static const struct freq_tbl clk_tbl_gsbi_qup[] = { { 1100000, P_PXO, 1, 2, 49 }, { 5400000, P_PXO, 1, 1, 5 }, { 10800000, P_PXO, 1, 2, 5 }, @@ -745,8 +750,8 @@ static struct clk_rcg gsbi1_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -761,7 +766,9 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_clk", - .parent_names = (const char *[]){ "gsbi1_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -794,8 +801,8 @@ static struct clk_rcg gsbi2_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -810,7 +817,9 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_clk", - .parent_names = (const char *[]){ "gsbi2_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -843,8 +852,8 @@ static struct clk_rcg gsbi3_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -859,7 +868,9 @@ static struct clk_branch gsbi3_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_clk", - .parent_names = (const char *[]){ "gsbi3_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi3_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -892,8 +903,8 @@ static struct clk_rcg gsbi4_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -908,7 +919,9 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_clk", - .parent_names = (const char *[]){ "gsbi4_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -941,8 +954,8 @@ static struct clk_rcg gsbi5_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -957,7 +970,9 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_clk", - .parent_names = (const char *[]){ "gsbi5_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -990,8 +1005,8 @@ static struct clk_rcg gsbi6_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1006,7 +1021,9 @@ static struct clk_branch gsbi6_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_clk", - .parent_names = (const char *[]){ "gsbi6_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1039,8 +1056,8 @@ static struct clk_rcg gsbi7_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1055,7 +1072,9 @@ static struct clk_branch gsbi7_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_clk", - .parent_names = (const char *[]){ "gsbi7_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1088,8 +1107,8 @@ static struct clk_rcg gsbi8_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi8_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1104,7 +1123,9 @@ static struct clk_branch gsbi8_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi8_qup_clk", - .parent_names = (const char *[]){ "gsbi8_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi8_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1137,8 +1158,8 @@ static struct clk_rcg gsbi9_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi9_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1153,7 +1174,9 @@ static struct clk_branch gsbi9_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi9_qup_clk", - .parent_names = (const char *[]){ "gsbi9_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi9_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1186,8 +1209,8 @@ static struct clk_rcg gsbi10_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi10_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1202,7 +1225,9 @@ static struct clk_branch gsbi10_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi10_qup_clk", - .parent_names = (const char *[]){ "gsbi10_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi10_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1235,8 +1260,8 @@ static struct clk_rcg gsbi11_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi11_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1251,7 +1276,9 @@ static struct clk_branch gsbi11_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi11_qup_clk", - .parent_names = (const char *[]){ "gsbi11_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi11_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1284,8 +1311,8 @@ static struct clk_rcg gsbi12_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi12_qup_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1300,7 +1327,9 @@ static struct clk_branch gsbi12_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi12_qup_clk", - .parent_names = (const char *[]){ "gsbi12_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi12_qup_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1346,8 +1375,8 @@ static struct clk_rcg gp0_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp0_src", - .parent_names = gcc_pxo_pll8_cxo, - .num_parents = 3, + .parent_data = gcc_pxo_pll8_cxo, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1362,7 +1391,9 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp0_clk", - .parent_names = (const char *[]){ "gp0_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp0_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1395,8 +1426,8 @@ static struct clk_rcg gp1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp1_src", - .parent_names = gcc_pxo_pll8_cxo, - .num_parents = 3, + .parent_data = gcc_pxo_pll8_cxo, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1411,7 +1442,9 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp1_clk", - .parent_names = (const char *[]){ "gp1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp1_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1444,8 +1477,8 @@ static struct clk_rcg gp2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp2_src", - .parent_names = gcc_pxo_pll8_cxo, - .num_parents = 3, + .parent_data = gcc_pxo_pll8_cxo, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1460,7 +1493,9 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp2_clk", - .parent_names = (const char *[]){ "gp2_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp2_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1496,8 +1531,8 @@ static struct clk_rcg prng_src = { .clkr.hw = { .init = &(struct clk_init_data){ .name = "prng_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, }, @@ -1512,7 +1547,9 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "prng_clk", - .parent_names = (const char *[]){ "prng_src" }, + .parent_hws = (const struct clk_hw*[]){ + &prng_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -1555,10 +1592,9 @@ static struct clk_rcg sdc1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc1_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, }, } }; @@ -1571,7 +1607,9 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc1_clk", - .parent_names = (const char *[]){ "sdc1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdc1_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1604,10 +1642,9 @@ static struct clk_rcg sdc2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc2_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, }, } }; @@ -1620,7 +1657,9 @@ static struct clk_branch sdc2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc2_clk", - .parent_names = (const char *[]){ "sdc2_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdc2_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1653,10 +1692,9 @@ static struct clk_rcg sdc3_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc3_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, }, } }; @@ -1669,7 +1707,9 @@ static struct clk_branch sdc3_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc3_clk", - .parent_names = (const char *[]){ "sdc3_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdc3_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1702,10 +1742,9 @@ static struct clk_rcg sdc4_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc4_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, }, } }; @@ -1718,7 +1757,9 @@ static struct clk_branch sdc4_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc4_clk", - .parent_names = (const char *[]){ "sdc4_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdc4_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1751,10 +1792,9 @@ static struct clk_rcg sdc5_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc5_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, }, } }; @@ -1767,7 +1807,9 @@ static struct clk_branch sdc5_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc5_clk", - .parent_names = (const char *[]){ "sdc5_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdc5_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1805,8 +1847,8 @@ static struct clk_rcg tsif_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1821,7 +1863,9 @@ static struct clk_branch tsif_ref_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk", - .parent_names = (const char *[]){ "tsif_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &tsif_ref_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1859,8 +1903,8 @@ static struct clk_rcg usb_hs1_xcvr_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1875,7 +1919,9 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb_hs1_xcvr_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1908,16 +1954,14 @@ static struct clk_rcg usb_fs1_xcvr_fs_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_fs_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, } }; -static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; - static struct clk_branch usb_fs1_xcvr_fs_clk = { .halt_reg = 0x2fcc, .halt_bit = 15, @@ -1926,7 +1970,9 @@ static struct clk_branch usb_fs1_xcvr_fs_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_fs_clk", - .parent_names = usb_fs1_xcvr_fs_src_p, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_fs_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1941,7 +1987,9 @@ static struct clk_branch usb_fs1_system_clk = { .enable_reg = 0x296c, .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ - .parent_names = usb_fs1_xcvr_fs_src_p, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_fs_src.clkr.hw, + }, .num_parents = 1, .name = "usb_fs1_system_clk", .ops = &clk_branch_ops, @@ -1975,16 +2023,14 @@ static struct clk_rcg usb_fs2_xcvr_fs_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs2_xcvr_fs_src", - .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, } }; -static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; - static struct clk_branch usb_fs2_xcvr_fs_clk = { .halt_reg = 0x2fcc, .halt_bit = 12, @@ -1993,7 +2039,9 @@ static struct clk_branch usb_fs2_xcvr_fs_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_fs2_xcvr_fs_clk", - .parent_names = usb_fs2_xcvr_fs_src_p, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs2_xcvr_fs_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2009,7 +2057,9 @@ static struct clk_branch usb_fs2_system_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb_fs2_system_clk", - .parent_names = usb_fs2_xcvr_fs_src_p, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs2_xcvr_fs_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2716,17 +2766,6 @@ MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table); static int gcc_msm8660_probe(struct platform_device *pdev) { - int ret; - struct device *dev = &pdev->dev; - - ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000); - if (ret) - return ret; - - ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000); - if (ret) - return ret; - return qcom_cc_probe(pdev, &gcc_msm8660_desc); } |