diff options
Diffstat (limited to 'drivers/clk/qcom/gcc-sdm660.c')
| -rw-r--r-- | drivers/clk/qcom/gcc-sdm660.c | 665 |
1 files changed, 377 insertions, 288 deletions
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index 6394257ca8c0..20253a06a583 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -10,7 +10,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> @@ -25,8 +24,6 @@ #include "reset.h" #include "gdsc.h" -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } - enum { P_XO, P_SLEEP_CLK, @@ -37,114 +34,14 @@ enum { P_GPLL1_EARLY_DIV, }; -static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL0_EARLY_DIV, 6 }, -}; - -static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = { - "xo", - "gpll0", - "gpll0_early_div", -}; - -static const struct parent_map gcc_parent_map_xo_gpll0[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, -}; - -static const char * const gcc_parent_names_xo_gpll0[] = { - "xo", - "gpll0", -}; - -static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_SLEEP_CLK, 5 }, - { P_GPLL0_EARLY_DIV, 6 }, -}; - -static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = { - "xo", - "gpll0", - "sleep_clk", - "gpll0_early_div", -}; - -static const struct parent_map gcc_parent_map_xo_sleep_clk[] = { - { P_XO, 0 }, - { P_SLEEP_CLK, 5 }, -}; - -static const char * const gcc_parent_names_xo_sleep_clk[] = { - "xo", - "sleep_clk", -}; - -static const struct parent_map gcc_parent_map_xo_gpll4[] = { - { P_XO, 0 }, - { P_GPLL4, 5 }, -}; - -static const char * const gcc_parent_names_xo_gpll4[] = { - "xo", - "gpll4", -}; - -static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL0_EARLY_DIV, 3 }, - { P_GPLL1, 4 }, - { P_GPLL4, 5 }, - { P_GPLL1_EARLY_DIV, 6 }, -}; - -static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { - "xo", - "gpll0", - "gpll0_early_div", - "gpll1", - "gpll4", - "gpll1_early_div", -}; - -static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL4, 5 }, - { P_GPLL0_EARLY_DIV, 6 }, -}; - -static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = { - "xo", - "gpll0", - "gpll4", - "gpll0_early_div", -}; - -static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL0_EARLY_DIV, 2 }, - { P_GPLL4, 5 }, -}; - -static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = { - "xo", - "gpll0", - "gpll0_early_div", - "gpll4", -}; - static struct clk_fixed_factor xo = { .mult = 1, .div = 1, .hw.init = &(struct clk_init_data){ .name = "xo", - .parent_names = (const char *[]){ "xo_board" }, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xo" + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -158,7 +55,9 @@ static struct clk_alpha_pll gpll0_early = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_early", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -170,7 +69,9 @@ static struct clk_fixed_factor gpll0_early_div = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll0_early_div", - .parent_names = (const char *[]){ "gpll0_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0_early.clkr.hw, + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -181,7 +82,9 @@ static struct clk_alpha_pll_postdiv gpll0 = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", - .parent_names = (const char *[]){ "gpll0_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0_early.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, }, @@ -195,7 +98,9 @@ static struct clk_alpha_pll gpll1_early = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gpll1_early", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -207,7 +112,9 @@ static struct clk_fixed_factor gpll1_early_div = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll1_early_div", - .parent_names = (const char *[]){ "gpll1_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll1_early.clkr.hw, + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -218,7 +125,9 @@ static struct clk_alpha_pll_postdiv gpll1 = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll1", - .parent_names = (const char *[]){ "gpll1_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll1_early.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, }, @@ -232,7 +141,9 @@ static struct clk_alpha_pll gpll4_early = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gpll4_early", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -245,12 +156,116 @@ static struct clk_alpha_pll_postdiv gpll4 = { .clkr.hw.init = &(struct clk_init_data) { .name = "gpll4", - .parent_names = (const char *[]) { "gpll4_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll4_early.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, }, }; +static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL0_EARLY_DIV, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_early_div.hw }, +}; + +static const struct parent_map gcc_parent_map_xo_gpll0[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, +}; + +static const struct clk_parent_data gcc_parent_data_xo_gpll0[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GPLL0_EARLY_DIV, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .fw_name = "sleep_clk" }, + { .hw = &gpll0_early_div.hw }, +}; + +static const struct parent_map gcc_parent_map_xo_sleep_clk[] = { + { P_XO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_xo_sleep_clk[] = { + { .fw_name = "xo" }, + { .fw_name = "sleep_clk" }, +}; + +static const struct parent_map gcc_parent_map_xo_gpll4[] = { + { P_XO, 0 }, + { P_GPLL4, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_xo_gpll4[] = { + { .fw_name = "xo" }, + { .hw = &gpll4.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL0_EARLY_DIV, 3 }, + { P_GPLL1, 4 }, + { P_GPLL4, 5 }, + { P_GPLL1_EARLY_DIV, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_early_div.hw }, + { .hw = &gpll1.clkr.hw }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll1_early_div.hw }, +}; + +static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 5 }, + { P_GPLL0_EARLY_DIV, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll0_early_div.hw }, +}; + +static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL0_EARLY_DIV, 2 }, + { P_GPLL4, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_early_div.hw }, + { .hw = &gpll4.clkr.hw }, +}; + static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(50000000, P_GPLL0, 12, 0, 0), @@ -265,8 +280,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -290,8 +305,8 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -304,8 +319,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -318,8 +333,8 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -332,8 +347,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -346,8 +361,8 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -360,8 +375,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -374,8 +389,8 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -407,8 +422,8 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -421,8 +436,8 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -435,8 +450,8 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_i2c_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -449,8 +464,8 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_spi_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -463,8 +478,8 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_i2c_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -477,8 +492,8 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_spi_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -491,8 +506,8 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_i2c_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -505,8 +520,8 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_spi_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -519,8 +534,8 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_i2c_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -533,8 +548,8 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_spi_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -547,8 +562,8 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart1_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -561,8 +576,8 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart2_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -582,8 +597,8 @@ static struct clk_rcg2 gp1_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -596,8 +611,8 @@ static struct clk_rcg2 gp2_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -610,8 +625,8 @@ static struct clk_rcg2 gp3_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -630,8 +645,8 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { .freq_tbl = ftbl_hmss_gpll0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_gpll0_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -651,8 +666,8 @@ static struct clk_rcg2 hmss_gpll4_clk_src = { .freq_tbl = ftbl_hmss_gpll4_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_gpll4_clk_src", - .parent_names = gcc_parent_names_xo_gpll4, - .num_parents = 2, + .parent_data = gcc_parent_data_xo_gpll4, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll4), .ops = &clk_rcg2_ops, }, }; @@ -670,8 +685,8 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = { .freq_tbl = ftbl_hmss_rbcpr_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_rbcpr_clk_src", - .parent_names = gcc_parent_names_xo_gpll0, - .num_parents = 2, + .parent_data = gcc_parent_data_xo_gpll0, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -689,8 +704,8 @@ static struct clk_rcg2 pdm2_clk_src = { .freq_tbl = ftbl_pdm2_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -711,8 +726,8 @@ static struct clk_rcg2 qspi_ser_clk_src = { .freq_tbl = ftbl_qspi_ser_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "qspi_ser_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, - .num_parents = 6, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div), .ops = &clk_rcg2_ops, }, }; @@ -737,9 +752,9 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .freq_tbl = ftbl_sdcc1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div, - .num_parents = 4, - .ops = &clk_rcg2_ops, + .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div), + .ops = &clk_rcg2_floor_ops, }, }; @@ -759,8 +774,8 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .freq_tbl = ftbl_sdcc1_ice_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -785,8 +800,8 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .freq_tbl = ftbl_sdcc2_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4, - .num_parents = 4, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4), .ops = &clk_rcg2_floor_ops, }, }; @@ -808,8 +823,8 @@ static struct clk_rcg2 ufs_axi_clk_src = { .freq_tbl = ftbl_ufs_axi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_axi_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -829,8 +844,8 @@ static struct clk_rcg2 ufs_ice_core_clk_src = { .freq_tbl = ftbl_ufs_ice_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_ice_core_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -843,8 +858,8 @@ static struct clk_rcg2 ufs_phy_aux_clk_src = { .freq_tbl = ftbl_hmss_rbcpr_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_phy_aux_clk_src", - .parent_names = gcc_parent_names_xo_sleep_clk, - .num_parents = 2, + .parent_data = gcc_parent_data_xo_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk), .ops = &clk_rcg2_ops, }, }; @@ -864,8 +879,8 @@ static struct clk_rcg2 ufs_unipro_core_clk_src = { .freq_tbl = ftbl_ufs_unipro_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_unipro_core_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -885,8 +900,8 @@ static struct clk_rcg2 usb20_master_clk_src = { .freq_tbl = ftbl_usb20_master_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_master_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -905,8 +920,8 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { .freq_tbl = ftbl_usb20_mock_utmi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_mock_utmi_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -930,8 +945,8 @@ static struct clk_rcg2 usb30_master_clk_src = { .freq_tbl = ftbl_usb30_master_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -951,8 +966,8 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .freq_tbl = ftbl_usb30_mock_utmi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -971,8 +986,8 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .freq_tbl = ftbl_usb3_phy_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", - .parent_names = gcc_parent_names_xo_sleep_clk, - .num_parents = 2, + .parent_data = gcc_parent_data_xo_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk), .ops = &clk_rcg2_ops, }, }; @@ -985,8 +1000,8 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre2_ufs_axi_clk", - .parent_names = (const char *[]){ - "ufs_axi_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ufs_axi_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1002,8 +1017,8 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre2_usb3_axi_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1071,8 +1086,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1089,8 +1104,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup1_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1107,8 +1122,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1125,8 +1140,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup2_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1143,8 +1158,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1161,8 +1176,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup3_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1179,8 +1194,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1197,8 +1212,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup4_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1215,8 +1230,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart1_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart1_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_uart1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1233,8 +1248,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart2_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart2_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_uart2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1264,8 +1279,8 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup1_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup1_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1282,8 +1297,8 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup1_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup1_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup1_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1300,8 +1315,8 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup2_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup2_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1318,8 +1333,8 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup2_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup2_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup2_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1336,8 +1351,8 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup3_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup3_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1354,8 +1369,8 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup3_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup3_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup3_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1372,8 +1387,8 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup4_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup4_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1390,8 +1405,8 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup4_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup4_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup4_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1408,8 +1423,8 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart1_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart1_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_uart1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1426,8 +1441,8 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart2_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart2_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_uart2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1457,8 +1472,8 @@ static struct clk_branch gcc_cfg_noc_usb2_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb2_axi_clk", - .parent_names = (const char *[]){ - "usb20_master_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb20_master_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1474,8 +1489,8 @@ static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb3_axi_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1503,8 +1518,8 @@ static struct clk_branch gcc_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", - .parent_names = (const char *[]){ - "gp1_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1521,8 +1536,8 @@ static struct clk_branch gcc_gp2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", - .parent_names = (const char *[]){ - "gp2_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1539,8 +1554,8 @@ static struct clk_branch gcc_gp3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", - .parent_names = (const char *[]){ - "gp3_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1584,8 +1599,8 @@ static struct clk_branch gcc_gpu_gpll0_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_clk", - .parent_names = (const char *[]){ - "gpll0", + .parent_hws = (const struct clk_hw*[]) { + &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1601,8 +1616,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk = { .enable_mask = BIT(3), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_div_clk", - .parent_names = (const char *[]){ - "gpll0_early_div", + .parent_hws = (const struct clk_hw*[]) { + &gpll0_early_div.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1632,8 +1647,8 @@ static struct clk_branch gcc_hmss_rbcpr_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_hmss_rbcpr_clk", - .parent_names = (const char *[]){ - "hmss_rbcpr_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &hmss_rbcpr_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1650,8 +1665,8 @@ static struct clk_branch gcc_mmss_gpll0_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_gpll0_clk", - .parent_names = (const char *[]){ - "gpll0", + .parent_hws = (const struct clk_hw*[]) { + &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1667,8 +1682,8 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_gpll0_div_clk", - .parent_names = (const char *[]){ - "gpll0_early_div", + .parent_hws = (const struct clk_hw*[]) { + &gpll0_early_div.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1767,8 +1782,8 @@ static struct clk_branch gcc_pdm2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", - .parent_names = (const char *[]){ - "pdm2_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1824,8 +1839,8 @@ static struct clk_branch gcc_qspi_ser_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_qspi_ser_clk", - .parent_names = (const char *[]){ - "qspi_ser_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &qspi_ser_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1881,8 +1896,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk", - .parent_names = (const char *[]){ - "sdcc1_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &sdcc1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1899,8 +1914,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ice_core_clk", - .parent_names = (const char *[]){ - "sdcc1_ice_core_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &sdcc1_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1930,8 +1945,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", - .parent_names = (const char *[]){ - "sdcc2_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1961,8 +1976,8 @@ static struct clk_branch gcc_ufs_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_axi_clk", - .parent_names = (const char *[]){ - "ufs_axi_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ufs_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1992,8 +2007,8 @@ static struct clk_branch gcc_ufs_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_ice_core_clk", - .parent_names = (const char *[]){ - "ufs_ice_core_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ufs_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2010,8 +2025,8 @@ static struct clk_branch gcc_ufs_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_aux_clk", - .parent_names = (const char *[]){ - "ufs_phy_aux_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ufs_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2067,8 +2082,8 @@ static struct clk_branch gcc_ufs_unipro_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_unipro_core_clk", - .parent_names = (const char *[]){ - "ufs_unipro_core_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ufs_unipro_core_clk_src.clkr.hw, }, .flags = CLK_SET_RATE_PARENT, .num_parents = 1, @@ -2085,8 +2100,8 @@ static struct clk_branch gcc_usb20_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb20_master_clk", - .parent_names = (const char *[]){ - "usb20_master_clk_src" + .parent_hws = (const struct clk_hw*[]) { + &usb20_master_clk_src.clkr.hw, }, .flags = CLK_SET_RATE_PARENT, .num_parents = 1, @@ -2103,8 +2118,8 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb20_mock_utmi_clk", - .parent_names = (const char *[]){ - "usb20_mock_utmi_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb20_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2134,8 +2149,8 @@ static struct clk_branch gcc_usb30_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_master_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2152,8 +2167,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_mock_utmi_clk", - .parent_names = (const char *[]){ - "usb30_mock_utmi_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb30_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2196,8 +2211,8 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_phy_aux_clk", - .parent_names = (const char *[]){ - "usb3_phy_aux_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb3_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2232,6 +2247,45 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { }, }; +static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = { + .halt_reg = 0x7d014, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x7d014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "hlos1_vote_lpass_adsp_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = { + .halt_reg = 0x7d048, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x7d048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "hlos1_vote_turing_adsp_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = { + .halt_reg = 0x7e048, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x7e048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "hlos2_vote_turing_adsp_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc ufs_gdsc = { .gdscr = 0x75004, .gds_hw_ctrl = 0x0, @@ -2262,6 +2316,33 @@ static struct gdsc pcie_0_gdsc = { .flags = VOTABLE, }; +static struct gdsc hlos1_vote_turing_adsp_gdsc = { + .gdscr = 0x7d04c, + .pd = { + .name = "hlos1_vote_turing_adsp_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos2_vote_turing_adsp_gdsc = { + .gdscr = 0x7e04c, + .pd = { + .name = "hlos2_vote_turing_adsp_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_lpass_adsp_gdsc = { + .gdscr = 0x7d034, + .pd = { + .name = "hlos1_vote_lpass_adsp_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + static struct clk_hw *gcc_sdm660_hws[] = { &xo.hw, &gpll0_early_div.hw, @@ -2394,17 +2475,25 @@ static struct clk_regmap *gcc_sdm660_clocks[] = { [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, + [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr, + [GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK] = &hlos1_vote_turing_adsp_smmu_clk.clkr, + [GCC_HLOS2_VOTE_TURING_ADSP_SMMU_CLK] = &hlos2_vote_turing_adsp_smmu_clk.clkr, }; static struct gdsc *gcc_sdm660_gdscs[] = { [UFS_GDSC] = &ufs_gdsc, [USB_30_GDSC] = &usb_30_gdsc, [PCIE_0_GDSC] = &pcie_0_gdsc, + [HLOS1_VOTE_TURING_ADSP_GDSC] = &hlos1_vote_turing_adsp_gdsc, + [HLOS2_VOTE_TURING_ADSP_GDSC] = &hlos2_vote_turing_adsp_gdsc, + [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc, }; static const struct qcom_reset_map gcc_sdm660_resets[] = { [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC1_BCR] = { 0x16000 }, [GCC_UFS_BCR] = { 0x75000 }, [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, [GCC_USB3_PHY_BCR] = { 0x50020 }, @@ -2459,7 +2548,7 @@ static int gcc_sdm660_probe(struct platform_device *pdev) if (ret) return ret; - return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap); + return qcom_cc_really_probe(&pdev->dev, &gcc_sdm660_desc, regmap); } static struct platform_driver gcc_sdm660_driver = { |