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path: root/drivers/clk/qcom/mmcc-apq8084.c
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-rw-r--r--drivers/clk/qcom/mmcc-apq8084.c1244
1 files changed, 497 insertions, 747 deletions
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index fbfcf0006739..2d334977d783 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -3,11 +3,12 @@
* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*/
+#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
+#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/regmap.h>
-#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,mmcc-apq8084.h>
#include <dt-bindings/reset/qcom,mmcc-apq8084.h>
@@ -39,6 +40,120 @@ enum {
P_MMSLEEP,
};
+static struct clk_pll mmpll0 = {
+ .l_reg = 0x0004,
+ .m_reg = 0x0008,
+ .n_reg = 0x000c,
+ .config_reg = 0x0014,
+ .mode_reg = 0x0000,
+ .status_reg = 0x001c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "mmpll0",
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap mmpll0_vote = {
+ .enable_reg = 0x0100,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "mmpll0_vote",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmpll0.clkr.hw
+ },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
+static struct clk_pll mmpll1 = {
+ .l_reg = 0x0044,
+ .m_reg = 0x0048,
+ .n_reg = 0x004c,
+ .config_reg = 0x0050,
+ .mode_reg = 0x0040,
+ .status_reg = 0x005c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "mmpll1",
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap mmpll1_vote = {
+ .enable_reg = 0x0100,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "mmpll1_vote",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmpll1.clkr.hw
+ },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
+static struct clk_pll mmpll2 = {
+ .l_reg = 0x4104,
+ .m_reg = 0x4108,
+ .n_reg = 0x410c,
+ .config_reg = 0x4110,
+ .mode_reg = 0x4100,
+ .status_reg = 0x411c,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "mmpll2",
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_pll mmpll3 = {
+ .l_reg = 0x0084,
+ .m_reg = 0x0088,
+ .n_reg = 0x008c,
+ .config_reg = 0x0090,
+ .mode_reg = 0x0080,
+ .status_reg = 0x009c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "mmpll3",
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_pll mmpll4 = {
+ .l_reg = 0x00a4,
+ .m_reg = 0x00a8,
+ .n_reg = 0x00ac,
+ .config_reg = 0x00b0,
+ .mode_reg = 0x0080,
+ .status_reg = 0x00bc,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "mmpll4",
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
{ P_XO, 0 },
{ P_MMPLL0, 1 },
@@ -46,11 +161,11 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
{ P_GPLL0, 5 }
};
-static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
- "xo",
- "mmpll0_vote",
- "mmpll1_vote",
- "mmss_gpll0_vote",
+static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0_vote.hw },
+ { .hw = &mmpll1_vote.hw },
+ { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
};
static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
@@ -62,13 +177,13 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
{ P_DSI1PLL, 3 }
};
-static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
- "xo",
- "mmpll0_vote",
- "hdmipll",
- "mmss_gpll0_vote",
- "dsi0pll",
- "dsi1pll",
+static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0_vote.hw },
+ { .fw_name = "hdmipll", .name = "hdmipll" },
+ { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
+ { .fw_name = "dsi0pll", .name = "dsi0pll" },
+ { .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
@@ -79,12 +194,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
{ P_MMPLL2, 3 }
};
-static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
- "xo",
- "mmpll0_vote",
- "mmpll1_vote",
- "mmss_gpll0_vote",
- "mmpll2",
+static const struct clk_parent_data mmcc_xo_mmpll0_1_2_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0_vote.hw },
+ { .hw = &mmpll1_vote.hw },
+ { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
+ { .hw = &mmpll2.clkr.hw },
};
static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
@@ -95,12 +210,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
{ P_MMPLL3, 3 }
};
-static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
- "xo",
- "mmpll0_vote",
- "mmpll1_vote",
- "mmss_gpll0_vote",
- "mmpll3",
+static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0_vote.hw },
+ { .hw = &mmpll1_vote.hw },
+ { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
+ { .hw = &mmpll3.clkr.hw },
};
static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
@@ -112,13 +227,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
{ P_DSI1PLL, 2 }
};
-static const char * const mmcc_xo_dsi_hdmi_edp[] = {
- "xo",
- "edp_link_clk",
- "hdmipll",
- "edp_vco_div",
- "dsi0pll",
- "dsi1pll",
+static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
+ { .fw_name = "hdmipll", .name = "hdmipll" },
+ { .fw_name = "edp_vco_div", .name = "edp_vco_div" },
+ { .fw_name = "dsi0pll", .name = "dsi0pll" },
+ { .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
@@ -130,13 +245,13 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
{ P_DSI1PLL, 2 }
};
-static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
- "xo",
- "edp_link_clk",
- "hdmipll",
- "gpll0_vote",
- "dsi0pll",
- "dsi1pll",
+static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
+ { .fw_name = "hdmipll", .name = "hdmipll" },
+ { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
+ { .fw_name = "dsi0pll", .name = "dsi0pll" },
+ { .fw_name = "dsi1pll", .name = "dsi1pll" },
};
static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
@@ -148,13 +263,13 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
{ P_DSI1PLL_BYTE, 2 }
};
-static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
- "xo",
- "edp_link_clk",
- "hdmipll",
- "gpll0_vote",
- "dsi0pllbyte",
- "dsi1pllbyte",
+static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
+ { .fw_name = "hdmipll", .name = "hdmipll" },
+ { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
+ { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
+ { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
};
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
@@ -165,12 +280,12 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
{ P_MMPLL4, 3 }
};
-static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
- "xo",
- "mmpll0",
- "mmpll1",
- "mmpll4",
- "gpll0",
+static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0.clkr.hw },
+ { .hw = &mmpll1.clkr.hw },
+ { .hw = &mmpll4.clkr.hw },
+ { .fw_name = "gpll0", .name = "gpll0" },
};
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
@@ -182,13 +297,13 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
{ P_GPLL1, 4 }
};
-static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
- "xo",
- "mmpll0",
- "mmpll1",
- "mmpll4",
- "gpll1",
- "gpll0",
+static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0.clkr.hw },
+ { .hw = &mmpll1.clkr.hw },
+ { .hw = &mmpll4.clkr.hw },
+ { .fw_name = "gpll1", .name = "gpll1" },
+ { .fw_name = "gpll0", .name = "gpll0" },
};
static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
@@ -201,114 +316,14 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
{ P_MMSLEEP, 6 }
};
-static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
- "xo",
- "mmpll0",
- "mmpll1",
- "mmpll4",
- "gpll1",
- "gpll0",
- "sleep_clk_src",
-};
-
-static struct clk_pll mmpll0 = {
- .l_reg = 0x0004,
- .m_reg = 0x0008,
- .n_reg = 0x000c,
- .config_reg = 0x0014,
- .mode_reg = 0x0000,
- .status_reg = 0x001c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mmpll0",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap mmpll0_vote = {
- .enable_reg = 0x0100,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmpll0_vote",
- .parent_names = (const char *[]){ "mmpll0" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
-static struct clk_pll mmpll1 = {
- .l_reg = 0x0044,
- .m_reg = 0x0048,
- .n_reg = 0x004c,
- .config_reg = 0x0050,
- .mode_reg = 0x0040,
- .status_reg = 0x005c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mmpll1",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap mmpll1_vote = {
- .enable_reg = 0x0100,
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "mmpll1_vote",
- .parent_names = (const char *[]){ "mmpll1" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
-static struct clk_pll mmpll2 = {
- .l_reg = 0x4104,
- .m_reg = 0x4108,
- .n_reg = 0x410c,
- .config_reg = 0x4110,
- .mode_reg = 0x4100,
- .status_reg = 0x411c,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mmpll2",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_pll mmpll3 = {
- .l_reg = 0x0084,
- .m_reg = 0x0088,
- .n_reg = 0x008c,
- .config_reg = 0x0090,
- .mode_reg = 0x0080,
- .status_reg = 0x009c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mmpll3",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_pll mmpll4 = {
- .l_reg = 0x00a4,
- .m_reg = 0x00a8,
- .n_reg = 0x00ac,
- .config_reg = 0x00b0,
- .mode_reg = 0x0080,
- .status_reg = 0x00bc,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "mmpll4",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
+static const struct clk_parent_data mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &mmpll0.clkr.hw },
+ { .hw = &mmpll1.clkr.hw },
+ { .hw = &mmpll4.clkr.hw },
+ { .fw_name = "gpll1", .name = "gpll1" },
+ { .fw_name = "gpll0", .name = "gpll0" },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static struct clk_rcg2 mmss_ahb_clk_src = {
@@ -317,13 +332,13 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
.parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_ahb_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_mmss_axi_clk[] = {
+static const struct freq_tbl ftbl_mmss_axi_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
@@ -333,6 +348,7 @@ static struct freq_tbl ftbl_mmss_axi_clk[] = {
F(333430000, P_MMPLL1, 3.5, 0, 0),
F(400000000, P_MMPLL0, 2, 0, 0),
F(466800000, P_MMPLL1, 2.5, 0, 0),
+ { }
};
static struct clk_rcg2 mmss_axi_clk_src = {
@@ -342,13 +358,13 @@ static struct clk_rcg2 mmss_axi_clk_src = {
.freq_tbl = ftbl_mmss_axi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmss_axi_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_ocmemnoc_clk[] = {
+static const struct freq_tbl ftbl_ocmemnoc_clk[] = {
F(19200000, P_XO, 1, 0, 0),
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
@@ -357,6 +373,7 @@ static struct freq_tbl ftbl_ocmemnoc_clk[] = {
F(150000000, P_GPLL0, 4, 0, 0),
F(228570000, P_MMPLL0, 3.5, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
+ { }
};
static struct clk_rcg2 ocmemnoc_clk_src = {
@@ -366,13 +383,13 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
.freq_tbl = ftbl_ocmemnoc_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ocmemnoc_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
+static const struct freq_tbl ftbl_camss_csi0_3_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
@@ -385,8 +402,8 @@ static struct clk_rcg2 csi0_clk_src = {
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -398,8 +415,8 @@ static struct clk_rcg2 csi1_clk_src = {
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -411,8 +428,8 @@ static struct clk_rcg2 csi2_clk_src = {
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -424,13 +441,13 @@ static struct clk_rcg2 csi3_clk_src = {
.freq_tbl = ftbl_camss_csi0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi3_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
+static const struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(50000000, P_GPLL0, 12, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
@@ -454,8 +471,8 @@ static struct clk_rcg2 vfe0_clk_src = {
.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -467,13 +484,13 @@ static struct clk_rcg2 vfe1_clk_src = {
.freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe1_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_mdss_mdp_clk[] = {
+static const struct freq_tbl ftbl_mdss_mdp_clk[] = {
F(37500000, P_GPLL0, 16, 0, 0),
F(60000000, P_GPLL0, 10, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
@@ -495,8 +512,8 @@ static struct clk_rcg2 mdp_clk_src = {
.freq_tbl = ftbl_mdss_mdp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
- .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -507,13 +524,13 @@ static struct clk_rcg2 gfx3d_clk_src = {
.parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_2_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_2_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
+static const struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
F(75000000, P_GPLL0, 8, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
@@ -530,8 +547,8 @@ static struct clk_rcg2 jpeg0_clk_src = {
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -543,8 +560,8 @@ static struct clk_rcg2 jpeg1_clk_src = {
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg1_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -556,8 +573,8 @@ static struct clk_rcg2 jpeg2_clk_src = {
.freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg2_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -569,8 +586,8 @@ static struct clk_rcg2 pclk0_clk_src = {
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -583,14 +600,14 @@ static struct clk_rcg2 pclk1_clk_src = {
.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk1_clk_src",
- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
-static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
+static const struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
@@ -608,13 +625,13 @@ static struct clk_rcg2 vcodec0_clk_src = {
.freq_tbl = ftbl_venus0_vcodec0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_3_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_avsync_vp_clk[] = {
+static const struct freq_tbl ftbl_avsync_vp_clk[] = {
F(150000000, P_GPLL0, 4, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
{ }
@@ -627,13 +644,13 @@ static struct clk_rcg2 vp_clk_src = {
.freq_tbl = ftbl_avsync_vp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vp_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
+static const struct freq_tbl ftbl_camss_cci_cci_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -646,13 +663,13 @@ static struct clk_rcg2 cci_clk_src = {
.freq_tbl = ftbl_camss_cci_cci_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
+static const struct freq_tbl ftbl_camss_gp0_1_clk[] = {
F(10000, P_XO, 16, 1, 120),
F(24000, P_XO, 16, 1, 50),
F(6000000, P_GPLL0, 10, 1, 10),
@@ -670,8 +687,8 @@ static struct clk_rcg2 camss_gp0_clk_src = {
.freq_tbl = ftbl_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
- .num_parents = 7,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -684,13 +701,13 @@ static struct clk_rcg2 camss_gp1_clk_src = {
.freq_tbl = ftbl_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
- .num_parents = 7,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
+static const struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0, 10, 1, 10),
F(8000000, P_GPLL0, 15, 1, 5),
@@ -712,8 +729,8 @@ static struct clk_rcg2 mclk0_clk_src = {
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
@@ -726,8 +743,8 @@ static struct clk_rcg2 mclk1_clk_src = {
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
@@ -740,8 +757,8 @@ static struct clk_rcg2 mclk2_clk_src = {
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk2_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
@@ -754,13 +771,13 @@ static struct clk_rcg2 mclk3_clk_src = {
.freq_tbl = ftbl_camss_mclk0_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk3_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll1_0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
+static const struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
{ }
@@ -773,8 +790,8 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -786,8 +803,8 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -799,13 +816,13 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
.freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi2phytimer_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
+static const struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
F(133330000, P_GPLL0, 4.5, 0, 0),
F(266670000, P_MMPLL0, 3, 0, 0),
F(320000000, P_MMPLL0, 2.5, 0, 0),
@@ -822,8 +839,8 @@ static struct clk_rcg2 cpp_clk_src = {
.freq_tbl = ftbl_camss_vfe_cpp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
- .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
- .num_parents = 5,
+ .parent_data = mmcc_xo_mmpll0_1_4_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -834,8 +851,8 @@ static struct clk_rcg2 byte0_clk_src = {
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
- .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -847,14 +864,14 @@ static struct clk_rcg2 byte1_clk_src = {
.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte1_clk_src",
- .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
-static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
+static const struct freq_tbl ftbl_mdss_edpaux_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -866,13 +883,13 @@ static struct clk_rcg2 edpaux_clk_src = {
.freq_tbl = ftbl_mdss_edpaux_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "edpaux_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_mdss_edplink_clk[] = {
+static const struct freq_tbl ftbl_mdss_edplink_clk[] = {
F(135000000, P_EDPLINK, 2, 0, 0),
F(270000000, P_EDPLINK, 11, 0, 0),
{ }
@@ -885,14 +902,14 @@ static struct clk_rcg2 edplink_clk_src = {
.freq_tbl = ftbl_mdss_edplink_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "edplink_clk_src",
- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
-static struct freq_tbl edp_pixel_freq_tbl[] = {
+static const struct freq_tbl edp_pixel_freq_tbl[] = {
{ .src = P_EDPVCO },
{ }
};
@@ -905,13 +922,13 @@ static struct clk_rcg2 edppixel_clk_src = {
.freq_tbl = edp_pixel_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "edppixel_clk_src",
- .parent_names = mmcc_xo_dsi_hdmi_edp,
- .num_parents = 6,
+ .parent_data = mmcc_xo_dsi_hdmi_edp,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
.ops = &clk_edp_pixel_ops,
},
};
-static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
+static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -923,8 +940,8 @@ static struct clk_rcg2 esc0_clk_src = {
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
- .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -936,13 +953,13 @@ static struct clk_rcg2 esc1_clk_src = {
.freq_tbl = ftbl_mdss_esc0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc1_clk_src",
- .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl extpclk_freq_tbl[] = {
+static const struct freq_tbl extpclk_freq_tbl[] = {
{ .src = P_HDMIPLL },
{ }
};
@@ -954,14 +971,14 @@ static struct clk_rcg2 extpclk_clk_src = {
.freq_tbl = extpclk_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "extpclk_clk_src",
- .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
- .num_parents = 6,
+ .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
.ops = &clk_byte_ops,
.flags = CLK_SET_RATE_PARENT,
},
};
-static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
+static const struct freq_tbl ftbl_mdss_hdmi_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -973,13 +990,13 @@ static struct clk_rcg2 hdmi_clk_src = {
.freq_tbl = ftbl_mdss_hdmi_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_mdss_vsync_clk[] = {
+static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -991,13 +1008,13 @@ static struct clk_rcg2 vsync_clk_src = {
.freq_tbl = ftbl_mdss_vsync_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
+static const struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
{ }
};
@@ -1009,13 +1026,13 @@ static struct clk_rcg2 rbcpr_clk_src = {
.freq_tbl = ftbl_mmss_rbcpr_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbcpr_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
+static const struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
F(19200000, P_XO, 1, 0, 0),
{ }
};
@@ -1027,13 +1044,13 @@ static struct clk_rcg2 rbbmtimer_clk_src = {
.freq_tbl = ftbl_oxili_rbbmtimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "rbbmtimer_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_vpu_maple_clk[] = {
+static const struct freq_tbl ftbl_vpu_maple_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(133330000, P_GPLL0, 4.5, 0, 0),
@@ -1050,13 +1067,13 @@ static struct clk_rcg2 maple_clk_src = {
.freq_tbl = ftbl_vpu_maple_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "maple_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_vpu_vdp_clk[] = {
+static const struct freq_tbl ftbl_vpu_vdp_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_MMPLL0, 4, 0, 0),
@@ -1072,13 +1089,13 @@ static struct clk_rcg2 vdp_clk_src = {
.freq_tbl = ftbl_vpu_vdp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vdp_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
-static struct freq_tbl ftbl_vpu_bus_clk[] = {
+static const struct freq_tbl ftbl_vpu_bus_clk[] = {
F(40000000, P_GPLL0, 15, 0, 0),
F(80000000, P_MMPLL0, 10, 0, 0),
{ }
@@ -1091,8 +1108,8 @@ static struct clk_rcg2 vpu_bus_clk_src = {
.freq_tbl = ftbl_vpu_bus_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vpu_bus_clk_src",
- .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
- .num_parents = 4,
+ .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
+ .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1104,7 +1121,9 @@ static struct clk_branch mmss_cxo_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_cxo_clk",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -1119,8 +1138,8 @@ static struct clk_branch mmss_sleepclk_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_sleepclk_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1136,8 +1155,8 @@ static struct clk_branch avsync_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1153,8 +1172,8 @@ static struct clk_branch avsync_edppixel_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_edppixel_clk",
- .parent_names = (const char *[]){
- "edppixel_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &edppixel_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1170,8 +1189,8 @@ static struct clk_branch avsync_extpclk_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_extpclk_clk",
- .parent_names = (const char *[]){
- "extpclk_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &extpclk_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1187,8 +1206,8 @@ static struct clk_branch avsync_pclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_pclk0_clk",
- .parent_names = (const char *[]){
- "pclk0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1204,8 +1223,8 @@ static struct clk_branch avsync_pclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_pclk1_clk",
- .parent_names = (const char *[]){
- "pclk1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1221,8 +1240,8 @@ static struct clk_branch avsync_vp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "avsync_vp_clk",
- .parent_names = (const char *[]){
- "vp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1238,8 +1257,8 @@ static struct clk_branch camss_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1255,8 +1274,8 @@ static struct clk_branch camss_cci_cci_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_cci_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1271,8 +1290,8 @@ static struct clk_branch camss_cci_cci_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_cci_cci_clk",
- .parent_names = (const char *[]){
- "cci_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &cci_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1288,8 +1307,8 @@ static struct clk_branch camss_csi0_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1304,8 +1323,8 @@ static struct clk_branch camss_csi0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1321,8 +1340,8 @@ static struct clk_branch camss_csi0phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0phy_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1338,8 +1357,8 @@ static struct clk_branch camss_csi0pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0pix_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1355,8 +1374,8 @@ static struct clk_branch camss_csi0rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi0rdi_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1372,8 +1391,8 @@ static struct clk_branch camss_csi1_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1389,8 +1408,8 @@ static struct clk_branch camss_csi1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1406,8 +1425,8 @@ static struct clk_branch camss_csi1phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1phy_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1423,8 +1442,8 @@ static struct clk_branch camss_csi1pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1pix_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1440,8 +1459,8 @@ static struct clk_branch camss_csi1rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi1rdi_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1457,8 +1476,8 @@ static struct clk_branch camss_csi2_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1473,8 +1492,8 @@ static struct clk_branch camss_csi2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2_clk",
- .parent_names = (const char *[]){
- "csi2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1490,8 +1509,8 @@ static struct clk_branch camss_csi2phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2phy_clk",
- .parent_names = (const char *[]){
- "csi2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1507,8 +1526,8 @@ static struct clk_branch camss_csi2pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2pix_clk",
- .parent_names = (const char *[]){
- "csi2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1524,8 +1543,8 @@ static struct clk_branch camss_csi2rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi2rdi_clk",
- .parent_names = (const char *[]){
- "csi2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1541,8 +1560,8 @@ static struct clk_branch camss_csi3_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1557,8 +1576,8 @@ static struct clk_branch camss_csi3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3_clk",
- .parent_names = (const char *[]){
- "csi3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1574,8 +1593,8 @@ static struct clk_branch camss_csi3phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3phy_clk",
- .parent_names = (const char *[]){
- "csi3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1591,8 +1610,8 @@ static struct clk_branch camss_csi3pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3pix_clk",
- .parent_names = (const char *[]){
- "csi3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1608,8 +1627,8 @@ static struct clk_branch camss_csi3rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi3rdi_clk",
- .parent_names = (const char *[]){
- "csi3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1625,8 +1644,8 @@ static struct clk_branch camss_csi_vfe0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe0_clk",
- .parent_names = (const char *[]){
- "vfe0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1642,8 +1661,8 @@ static struct clk_branch camss_csi_vfe1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_csi_vfe1_clk",
- .parent_names = (const char *[]){
- "vfe1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1659,8 +1678,8 @@ static struct clk_branch camss_gp0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk",
- .parent_names = (const char *[]){
- "camss_gp0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_gp0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1676,8 +1695,8 @@ static struct clk_branch camss_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk",
- .parent_names = (const char *[]){
- "camss_gp1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_gp1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1693,8 +1712,8 @@ static struct clk_branch camss_ispif_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_ispif_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1710,8 +1729,8 @@ static struct clk_branch camss_jpeg_jpeg0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg0_clk",
- .parent_names = (const char *[]){
- "jpeg0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &jpeg0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1727,8 +1746,8 @@ static struct clk_branch camss_jpeg_jpeg1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg1_clk",
- .parent_names = (const char *[]){
- "jpeg1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &jpeg1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1744,8 +1763,8 @@ static struct clk_branch camss_jpeg_jpeg2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg2_clk",
- .parent_names = (const char *[]){
- "jpeg2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &jpeg2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1761,8 +1780,8 @@ static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1777,8 +1796,8 @@ static struct clk_branch camss_jpeg_jpeg_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_jpeg_jpeg_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1793,8 +1812,8 @@ static struct clk_branch camss_mclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk0_clk",
- .parent_names = (const char *[]){
- "mclk0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1810,8 +1829,8 @@ static struct clk_branch camss_mclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk1_clk",
- .parent_names = (const char *[]){
- "mclk1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1827,8 +1846,8 @@ static struct clk_branch camss_mclk2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk2_clk",
- .parent_names = (const char *[]){
- "mclk2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk2_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1844,8 +1863,8 @@ static struct clk_branch camss_mclk3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_mclk3_clk",
- .parent_names = (const char *[]){
- "mclk3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk3_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1861,8 +1880,8 @@ static struct clk_branch camss_micro_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_micro_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1877,8 +1896,8 @@ static struct clk_branch camss_phy0_csi0phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy0_csi0phytimer_clk",
- .parent_names = (const char *[]){
- "csi0phytimer_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1894,8 +1913,8 @@ static struct clk_branch camss_phy1_csi1phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy1_csi1phytimer_clk",
- .parent_names = (const char *[]){
- "csi1phytimer_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1911,8 +1930,8 @@ static struct clk_branch camss_phy2_csi2phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_phy2_csi2phytimer_clk",
- .parent_names = (const char *[]){
- "csi2phytimer_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi2phytimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1928,8 +1947,8 @@ static struct clk_branch camss_top_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_top_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1945,8 +1964,8 @@ static struct clk_branch camss_vfe_cpp_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_cpp_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1962,8 +1981,8 @@ static struct clk_branch camss_vfe_cpp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_cpp_clk",
- .parent_names = (const char *[]){
- "cpp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &cpp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1979,8 +1998,8 @@ static struct clk_branch camss_vfe_vfe0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe0_clk",
- .parent_names = (const char *[]){
- "vfe0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1996,8 +2015,8 @@ static struct clk_branch camss_vfe_vfe1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe1_clk",
- .parent_names = (const char *[]){
- "vfe1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2013,8 +2032,8 @@ static struct clk_branch camss_vfe_vfe_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2030,8 +2049,8 @@ static struct clk_branch camss_vfe_vfe_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "camss_vfe_vfe_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2047,8 +2066,8 @@ static struct clk_branch mdss_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2064,8 +2083,8 @@ static struct clk_branch mdss_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2081,8 +2100,8 @@ static struct clk_branch mdss_byte0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte0_clk",
- .parent_names = (const char *[]){
- "byte0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &byte0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2098,8 +2117,8 @@ static struct clk_branch mdss_byte1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_byte1_clk",
- .parent_names = (const char *[]){
- "byte1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &byte1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2115,8 +2134,8 @@ static struct clk_branch mdss_edpaux_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edpaux_clk",
- .parent_names = (const char *[]){
- "edpaux_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &edpaux_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2132,8 +2151,8 @@ static struct clk_branch mdss_edplink_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edplink_clk",
- .parent_names = (const char *[]){
- "edplink_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &edplink_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2149,8 +2168,8 @@ static struct clk_branch mdss_edppixel_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_edppixel_clk",
- .parent_names = (const char *[]){
- "edppixel_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &edppixel_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2166,8 +2185,8 @@ static struct clk_branch mdss_esc0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc0_clk",
- .parent_names = (const char *[]){
- "esc0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &esc0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2183,8 +2202,8 @@ static struct clk_branch mdss_esc1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_esc1_clk",
- .parent_names = (const char *[]){
- "esc1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &esc1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2200,8 +2219,8 @@ static struct clk_branch mdss_extpclk_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_extpclk_clk",
- .parent_names = (const char *[]){
- "extpclk_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &extpclk_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2217,8 +2236,8 @@ static struct clk_branch mdss_hdmi_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2234,8 +2253,8 @@ static struct clk_branch mdss_hdmi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_hdmi_clk",
- .parent_names = (const char *[]){
- "hdmi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &hdmi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2251,8 +2270,8 @@ static struct clk_branch mdss_mdp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_clk",
- .parent_names = (const char *[]){
- "mdp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2268,8 +2287,8 @@ static struct clk_branch mdss_mdp_lut_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_mdp_lut_clk",
- .parent_names = (const char *[]){
- "mdp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2285,8 +2304,8 @@ static struct clk_branch mdss_pclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk0_clk",
- .parent_names = (const char *[]){
- "pclk0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pclk0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2302,8 +2321,8 @@ static struct clk_branch mdss_pclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_pclk1_clk",
- .parent_names = (const char *[]){
- "pclk1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pclk1_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2319,8 +2338,8 @@ static struct clk_branch mdss_vsync_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mdss_vsync_clk",
- .parent_names = (const char *[]){
- "vsync_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vsync_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2336,8 +2355,8 @@ static struct clk_branch mmss_rbcpr_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_rbcpr_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2353,127 +2372,8 @@ static struct clk_branch mmss_rbcpr_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_rbcpr_clk",
- .parent_names = (const char *[]){
- "rbcpr_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_ahb_clk = {
- .halt_reg = 0x0230,
- .clkr = {
- .enable_reg = 0x0230,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_ahb_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_axi_clk = {
- .halt_reg = 0x0210,
- .clkr = {
- .enable_reg = 0x0210,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_axi_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_axi_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_csi0_clk = {
- .halt_reg = 0x023c,
- .clkr = {
- .enable_reg = 0x023c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_csi0_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_csi0_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_gfx3d_clk = {
- .halt_reg = 0x022c,
- .clkr = {
- .enable_reg = 0x022c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_gfx3d_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_gfx3d_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_jpeg0_clk = {
- .halt_reg = 0x0204,
- .clkr = {
- .enable_reg = 0x0204,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_jpeg0_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_jpeg0_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_jpeg1_clk = {
- .halt_reg = 0x0208,
- .clkr = {
- .enable_reg = 0x0208,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_jpeg1_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_jpeg1_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_jpeg2_clk = {
- .halt_reg = 0x0224,
- .clkr = {
- .enable_reg = 0x0224,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_jpeg2_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_jpeg2_div_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &rbcpr_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2482,143 +2382,6 @@ static struct clk_branch mmss_spdm_jpeg2_clk = {
},
};
-static struct clk_branch mmss_spdm_mdp_clk = {
- .halt_reg = 0x020c,
- .clkr = {
- .enable_reg = 0x020c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_mdp_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_mdp_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_pclk0_clk = {
- .halt_reg = 0x0234,
- .clkr = {
- .enable_reg = 0x0234,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_pclk0_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_pclk0_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_pclk1_clk = {
- .halt_reg = 0x0228,
- .clkr = {
- .enable_reg = 0x0228,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_pclk1_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_pclk1_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_vcodec0_clk = {
- .halt_reg = 0x0214,
- .clkr = {
- .enable_reg = 0x0214,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_vcodec0_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_vcodec0_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_vfe0_clk = {
- .halt_reg = 0x0218,
- .clkr = {
- .enable_reg = 0x0218,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_vfe0_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_vfe0_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_vfe1_clk = {
- .halt_reg = 0x021c,
- .clkr = {
- .enable_reg = 0x021c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_vfe1_clk",
- .parent_names = (const char *[]){
- "mmss_spdm_vfe1_div_clk",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_rm_axi_clk = {
- .halt_reg = 0x0304,
- .clkr = {
- .enable_reg = 0x0304,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_rm_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
- .halt_reg = 0x0308,
- .clkr = {
- .enable_reg = 0x0308,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "mmss_spdm_rm_ocmemnoc_clk",
- .parent_names = (const char *[]){
- "ocmemnoc_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-
static struct clk_branch mmss_misc_ahb_clk = {
.halt_reg = 0x502c,
.clkr = {
@@ -2626,8 +2389,8 @@ static struct clk_branch mmss_misc_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_misc_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2643,8 +2406,8 @@ static struct clk_branch mmss_mmssnoc_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2660,8 +2423,8 @@ static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_bto_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2677,8 +2440,8 @@ static struct clk_branch mmss_mmssnoc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_mmssnoc_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
@@ -2694,8 +2457,8 @@ static struct clk_branch mmss_s0_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "mmss_s0_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2711,8 +2474,8 @@ static struct clk_branch ocmemcx_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ocmemcx_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2728,8 +2491,8 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "ocmemcx_ocmemnoc_clk",
- .parent_names = (const char *[]){
- "ocmemnoc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ocmemnoc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2745,8 +2508,8 @@ static struct clk_branch oxili_ocmemgx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_ocmemgx_clk",
- .parent_names = (const char *[]){
- "gfx3d_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gfx3d_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2762,8 +2525,8 @@ static struct clk_branch oxili_gfx3d_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_gfx3d_clk",
- .parent_names = (const char *[]){
- "gfx3d_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gfx3d_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2779,8 +2542,8 @@ static struct clk_branch oxili_rbbmtimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxili_rbbmtimer_clk",
- .parent_names = (const char *[]){
- "rbbmtimer_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &rbbmtimer_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2796,8 +2559,8 @@ static struct clk_branch oxilicx_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "oxilicx_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2813,8 +2576,8 @@ static struct clk_branch venus0_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2830,8 +2593,8 @@ static struct clk_branch venus0_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2847,8 +2610,8 @@ static struct clk_branch venus0_core0_vcodec_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_core0_vcodec_clk",
- .parent_names = (const char *[]){
- "vcodec0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vcodec0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2864,8 +2627,8 @@ static struct clk_branch venus0_core1_vcodec_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_core1_vcodec_clk",
- .parent_names = (const char *[]){
- "vcodec0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vcodec0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2881,8 +2644,8 @@ static struct clk_branch venus0_ocmemnoc_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_ocmemnoc_clk",
- .parent_names = (const char *[]){
- "ocmemnoc_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ocmemnoc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2898,8 +2661,8 @@ static struct clk_branch venus0_vcodec0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "venus0_vcodec0_clk",
- .parent_names = (const char *[]){
- "vcodec0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vcodec0_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2915,8 +2678,8 @@ static struct clk_branch vpu_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_ahb_clk",
- .parent_names = (const char *[]){
- "mmss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_ahb_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2932,8 +2695,8 @@ static struct clk_branch vpu_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_axi_clk",
- .parent_names = (const char *[]){
- "mmss_axi_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mmss_axi_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2949,8 +2712,8 @@ static struct clk_branch vpu_bus_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_bus_clk",
- .parent_names = (const char *[]){
- "vpu_bus_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vpu_bus_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2966,7 +2729,9 @@ static struct clk_branch vpu_cxo_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_cxo_clk",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "xo", .name = "xo_board" },
+ },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2981,8 +2746,8 @@ static struct clk_branch vpu_maple_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_maple_clk",
- .parent_names = (const char *[]){
- "maple_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &maple_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2998,8 +2763,8 @@ static struct clk_branch vpu_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_sleep_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = (const struct clk_parent_data[]){
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3015,8 +2780,8 @@ static struct clk_branch vpu_vdp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "vpu_vdp_clk",
- .parent_names = (const char *[]){
- "vdp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vdp_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3251,21 +3016,6 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
[MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
[MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
- [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
- [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
- [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
- [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
- [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
- [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
- [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
- [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
- [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
- [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
- [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
- [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
- [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
- [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
- [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
[MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
[MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
generated by cgit (git 2.34.1) at 2025-12-25 19:06:14 +0000