diff options
Diffstat (limited to 'drivers/clk/renesas/r8a7743-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a7743-cpg-mssr.c | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas/r8a7743-cpg-mssr.c index 6dc0b3082aa6..0bba12a48d22 100644 --- a/drivers/clk/renesas/r8a7743-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c @@ -1,16 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 /* * r8a7743 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2016 Cogent Embedded Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation; of the License. */ #include <linux/device.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/of.h> #include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a7743-cpg-mssr.h> @@ -37,7 +35,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7743_core_clks[] __initconst = { +static struct cpg_core_clk r8a7743_core_clks[] __initdata = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("usb_extal", CLK_USB_EXTAL), @@ -52,7 +50,6 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_BASE("z", R8A7743_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0), - DEF_BASE("lb", R8A7743_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1), DEF_BASE("sdh", R8A7743_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), DEF_BASE("sd0", R8A7743_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), @@ -63,6 +60,7 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = { DEF_FIXED("zs", R8A7743_CLK_ZS, CLK_PLL1, 6, 1), DEF_FIXED("hp", R8A7743_CLK_HP, CLK_PLL1, 12, 1), DEF_FIXED("b", R8A7743_CLK_B, CLK_PLL1, 12, 1), + DEF_FIXED("lb", R8A7743_CLK_LB, CLK_PLL1, 24, 1), DEF_FIXED("p", R8A7743_CLK_P, CLK_PLL1, 24, 1), DEF_FIXED("cl", R8A7743_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("m2", R8A7743_CLK_M2, CLK_PLL1, 8, 1), @@ -94,7 +92,7 @@ static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = { DEF_MOD("tmu0", 125, R8A7743_CLK_CP), DEF_MOD("vsp1du1", 127, R8A7743_CLK_ZS), DEF_MOD("vsp1du0", 128, R8A7743_CLK_ZS), - DEF_MOD("vsp1-sy", 131, R8A7743_CLK_ZS), + DEF_MOD("vsps", 131, R8A7743_CLK_ZS), DEF_MOD("scifa2", 202, R8A7743_CLK_MP), DEF_MOD("scifa1", 203, R8A7743_CLK_MP), DEF_MOD("scifa0", 204, R8A7743_CLK_MP), @@ -117,6 +115,7 @@ static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = { DEF_MOD("cmt1", 329, R8A7743_CLK_R), DEF_MOD("usbhs-dmac0", 330, R8A7743_CLK_HP), DEF_MOD("usbhs-dmac1", 331, R8A7743_CLK_HP), + DEF_MOD("rwdt", 402, R8A7743_CLK_R), DEF_MOD("irqc", 407, R8A7743_CLK_CP), DEF_MOD("intc-sys", 408, R8A7743_CLK_ZS), DEF_MOD("audio-dmac1", 501, R8A7743_CLK_HP), @@ -195,6 +194,7 @@ static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = { }; static const unsigned int r8a7743_crit_mod_clks[] __initconst = { + MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-SYS (GIC) */ }; @@ -236,6 +236,8 @@ static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { static int __init r8a7743_cpg_mssr_init(struct device *dev) { const struct rcar_gen2_cpg_pll_config *cpg_pll_config; + struct device_node *np = dev->of_node; + unsigned int i; u32 cpg_mode; int error; @@ -245,6 +247,14 @@ static int __init r8a7743_cpg_mssr_init(struct device *dev) cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (of_device_is_compatible(np, "renesas,r8a7744-cpg-mssr")) { + /* RZ/G1N uses a 1/5 divider for ZG */ + for (i = 0; i < ARRAY_SIZE(r8a7743_core_clks); i++) + if (r8a7743_core_clks[i].id == R8A7743_CLK_ZG) { + r8a7743_core_clks[i].div = 5; + break; + } + } return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode); } |