diff options
Diffstat (limited to 'drivers/clk/renesas/renesas-cpg-mssr.h')
| -rw-r--r-- | drivers/clk/renesas/renesas-cpg-mssr.h | 47 |
1 files changed, 31 insertions, 16 deletions
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 1c3c057d17f5..ad11ab5f0069 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -8,6 +8,8 @@ #ifndef __CLK_RENESAS_CPG_MSSR_H__ #define __CLK_RENESAS_CPG_MSSR_H__ +#include <linux/notifier.h> + /* * Definitions of CPG Core Clocks * @@ -27,6 +29,31 @@ struct cpg_core_clk { unsigned int div; unsigned int mult; unsigned int offset; + union { + const char * const *parent_names; + const struct clk_div_table *dtable; + }; + u32 conf; + u16 flag; + u8 mux_flags; + u8 num_parents; +}; + +/** + * struct cpg_mssr_pub - data shared with device-specific clk registration code + * + * @base0: CPG/MSSR register block base0 address + * @base1: CPG/MSSR register block base1 address + * @notifiers: Notifier chain to save/restore clock state for system resume + * @rmw_lock: protects RMW register accesses + * @clks: pointer to clocks + */ +struct cpg_mssr_pub { + void __iomem *base0; + void __iomem *base1; + struct raw_notifier_head notifiers; + spinlock_t rmw_lock; + struct clk **clks; }; enum clk_types { @@ -89,6 +116,7 @@ enum clk_reg_layout { CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0, CLK_REG_LAYOUT_RZ_A, CLK_REG_LAYOUT_RCAR_GEN4, + CLK_REG_LAYOUT_RZ_T2H, }; /** @@ -153,8 +181,7 @@ struct cpg_mssr_info { struct clk *(*cpg_clk_register)(struct device *dev, const struct cpg_core_clk *core, const struct cpg_mssr_info *info, - struct clk **clks, void __iomem *base, - struct raw_notifier_head *notifiers); + struct cpg_mssr_pub *pub); }; extern const struct cpg_mssr_info r7s9210_cpg_mssr_info; @@ -180,6 +207,8 @@ extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info; extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info; extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info; +extern const struct cpg_mssr_info r8a779h0_cpg_mssr_info; +extern const struct cpg_mssr_info r9a09g077_cpg_mssr_info; void __init cpg_mssr_early_init(struct device_node *np, const struct cpg_mssr_info *info); @@ -187,21 +216,7 @@ void __init cpg_mssr_early_init(struct device_node *np, /* * Helpers for fixing up clock tables depending on SoC revision */ - -struct mssr_mod_reparent { - unsigned int clk, parent; -}; - - -extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks, - unsigned int num_core_clks, - unsigned int first_clk, - unsigned int last_clk); extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks, unsigned int num_mod_clks, const unsigned int *clks, unsigned int n); -extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks, - unsigned int num_mod_clks, - const struct mssr_mod_reparent *clks, - unsigned int n); #endif |