diff options
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu-sun8i-v3s.c')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 177 |
1 files changed, 68 insertions, 109 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index f49724a22540..05595ac51b76 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -8,7 +8,9 @@ #include <linux/clk-provider.h> #include <linux/io.h> -#include <linux/of_address.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include "ccu_common.h" #include "ccu_reset.h" @@ -345,12 +347,13 @@ static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram", static const char * const de_parents[] = { "pll-video", "pll-periph0" }; static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, - 0x104, 0, 4, 24, 2, BIT(31), - CLK_SET_RATE_PARENT); + 0x104, 0, 4, 24, 3, BIT(31), + CLK_SET_RATE_NO_REPARENT); -static const char * const tcon_parents[] = { "pll-video" }; +static const char * const tcon_parents[] = { "pll-video", "pll-periph0" }; static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents, - 0x118, 0, 4, 24, 3, BIT(31), 0); + 0x118, 0, 4, 24, 3, BIT(31), + CLK_SET_RATE_NO_REPARENT); static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(31), 0); @@ -360,11 +363,11 @@ static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents, 0x130, 0, 5, 8, 3, BIT(15), 0); -static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" }; -static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents, +static const char * const csi_sclk_parents[] = { "pll-video", "pll-isp" }; +static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, 0x134, 16, 4, 24, 3, BIT(31), 0); -static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents, +static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents, 0x134, 0, 5, 8, 3, BIT(15), 0); static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", @@ -419,6 +422,7 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] = { &bus_de_clk.common, &bus_codec_clk.common, &bus_pio_clk.common, + &bus_i2s0_clk.common, &bus_i2c0_clk.common, &bus_i2c1_clk.common, &bus_uart0_clk.common, @@ -437,6 +441,7 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] = { &mmc2_output_clk.common, &ce_clk.common, &spi0_clk.common, + &i2s0_clk.common, &usb_phy0_clk.common, &usb_ohci0_clk.common, &dram_clk.common, @@ -448,7 +453,7 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] = { &tcon_clk.common, &csi_misc_clk.common, &csi0_mclk_clk.common, - &csi1_sclk_clk.common, + &csi_sclk_clk.common, &csi1_mclk_clk.common, &ve_clk.common, &ac_dig_clk.common, @@ -461,80 +466,6 @@ static const struct clk_hw *clk_parent_pll_audio[] = { &pll_audio_base_clk.common.hw }; -static struct ccu_common *sun8i_v3_ccu_clks[] = { - &pll_cpu_clk.common, - &pll_audio_base_clk.common, - &pll_video_clk.common, - &pll_ve_clk.common, - &pll_ddr0_clk.common, - &pll_periph0_clk.common, - &pll_isp_clk.common, - &pll_periph1_clk.common, - &pll_ddr1_clk.common, - &cpu_clk.common, - &axi_clk.common, - &ahb1_clk.common, - &apb1_clk.common, - &apb2_clk.common, - &ahb2_clk.common, - &bus_ce_clk.common, - &bus_dma_clk.common, - &bus_mmc0_clk.common, - &bus_mmc1_clk.common, - &bus_mmc2_clk.common, - &bus_dram_clk.common, - &bus_emac_clk.common, - &bus_hstimer_clk.common, - &bus_spi0_clk.common, - &bus_otg_clk.common, - &bus_ehci0_clk.common, - &bus_ohci0_clk.common, - &bus_ve_clk.common, - &bus_tcon0_clk.common, - &bus_csi_clk.common, - &bus_de_clk.common, - &bus_codec_clk.common, - &bus_pio_clk.common, - &bus_i2s0_clk.common, - &bus_i2c0_clk.common, - &bus_i2c1_clk.common, - &bus_uart0_clk.common, - &bus_uart1_clk.common, - &bus_uart2_clk.common, - &bus_ephy_clk.common, - &bus_dbg_clk.common, - &mmc0_clk.common, - &mmc0_sample_clk.common, - &mmc0_output_clk.common, - &mmc1_clk.common, - &mmc1_sample_clk.common, - &mmc1_output_clk.common, - &mmc2_clk.common, - &mmc2_sample_clk.common, - &mmc2_output_clk.common, - &ce_clk.common, - &spi0_clk.common, - &i2s0_clk.common, - &usb_phy0_clk.common, - &usb_ohci0_clk.common, - &dram_clk.common, - &dram_ve_clk.common, - &dram_csi_clk.common, - &dram_ohci_clk.common, - &dram_ehci_clk.common, - &de_clk.common, - &tcon_clk.common, - &csi_misc_clk.common, - &csi0_mclk_clk.common, - &csi1_sclk_clk.common, - &csi1_mclk_clk.common, - &ve_clk.common, - &ac_dig_clk.common, - &avs_clk.common, - &mbus_clk.common, - &mipi_csi_clk.common, -}; - /* We hardcode the divider to 1 for SDM support */ static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", clk_parent_pll_audio, @@ -621,7 +552,7 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { [CLK_TCON0] = &tcon_clk.common.hw, [CLK_CSI_MISC] = &csi_misc_clk.common.hw, [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, - [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw, + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, [CLK_VE] = &ve_clk.common.hw, [CLK_AC_DIG] = &ac_dig_clk.common.hw, @@ -703,7 +634,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = { [CLK_TCON0] = &tcon_clk.common.hw, [CLK_CSI_MISC] = &csi_misc_clk.common.hw, [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, - [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw, + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, [CLK_VE] = &ve_clk.common.hw, [CLK_AC_DIG] = &ac_dig_clk.common.hw, @@ -714,7 +645,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = { .num = CLK_I2S0 + 1, }; -static struct ccu_reset_map sun8i_v3s_ccu_resets[] = { +static const struct ccu_reset_map sun8i_v3s_ccu_resets[] = { [RST_USB_PHY0] = { 0x0cc, BIT(0) }, [RST_MBUS] = { 0x0fc, BIT(31) }, @@ -749,7 +680,7 @@ static struct ccu_reset_map sun8i_v3s_ccu_resets[] = { [RST_BUS_UART2] = { 0x2d8, BIT(18) }, }; -static struct ccu_reset_map sun8i_v3_ccu_resets[] = { +static const struct ccu_reset_map sun8i_v3_ccu_resets[] = { [RST_USB_PHY0] = { 0x0cc, BIT(0) }, [RST_MBUS] = { 0x0fc, BIT(31) }, @@ -796,8 +727,8 @@ static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = { }; static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = { - .ccu_clks = sun8i_v3_ccu_clks, - .num_ccu_clks = ARRAY_SIZE(sun8i_v3_ccu_clks), + .ccu_clks = sun8i_v3s_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks), .hw_clks = &sun8i_v3_hw_clks, @@ -805,38 +736,66 @@ static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = { .num_resets = ARRAY_SIZE(sun8i_v3_ccu_resets), }; -static void __init sun8i_v3_v3s_ccu_init(struct device_node *node, - const struct sunxi_ccu_desc *ccu_desc) +static int sun8i_v3s_ccu_probe(struct platform_device *pdev) { + const struct sunxi_ccu_desc *desc; void __iomem *reg; u32 val; - reg = of_io_request_and_map(node, 0, of_node_full_name(node)); - if (IS_ERR(reg)) { - pr_err("%pOF: Could not map the clock registers\n", node); - return; - } + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + reg = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg)) + return PTR_ERR(reg); /* Force the PLL-Audio-1x divider to 1 */ val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG); val &= ~GENMASK(19, 16); writel(val, reg + SUN8I_V3S_PLL_AUDIO_REG); - sunxi_ccu_probe(node, reg, ccu_desc); -} + /* + * Assign the DE and TCON clock to the video PLL. Both clocks need to + * have the same parent for the units to work together. + */ -static void __init sun8i_v3s_ccu_setup(struct device_node *node) -{ - sun8i_v3_v3s_ccu_init(node, &sun8i_v3s_ccu_desc); -} + val = readl(reg + de_clk.common.reg); + val &= ~GENMASK(de_clk.mux.shift + de_clk.mux.width - 1, + de_clk.mux.shift); + writel(val, reg + de_clk.common.reg); -static void __init sun8i_v3_ccu_setup(struct device_node *node) -{ - sun8i_v3_v3s_ccu_init(node, &sun8i_v3_ccu_desc); + val = readl(reg + tcon_clk.common.reg); + val &= ~GENMASK(tcon_clk.mux.shift + tcon_clk.mux.width - 1, + tcon_clk.mux.shift); + writel(val, reg + tcon_clk.common.reg); + + return devm_sunxi_ccu_probe(&pdev->dev, reg, desc); } -CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu", - sun8i_v3s_ccu_setup); +static const struct of_device_id sun8i_v3s_ccu_ids[] = { + { + .compatible = "allwinner,sun8i-v3-ccu", + .data = &sun8i_v3_ccu_desc, + }, + { + .compatible = "allwinner,sun8i-v3s-ccu", + .data = &sun8i_v3s_ccu_desc, + }, + { } +}; +MODULE_DEVICE_TABLE(of, sun8i_v3s_ccu_ids); + +static struct platform_driver sun8i_v3s_ccu_driver = { + .probe = sun8i_v3s_ccu_probe, + .driver = { + .name = "sun8i-v3s-ccu", + .suppress_bind_attrs = true, + .of_match_table = sun8i_v3s_ccu_ids, + }, +}; +module_platform_driver(sun8i_v3s_ccu_driver); -CLK_OF_DECLARE(sun8i_v3_ccu, "allwinner,sun8i-v3-ccu", - sun8i_v3_ccu_setup); +MODULE_IMPORT_NS("SUNXI_CCU"); +MODULE_DESCRIPTION("Support for the Allwinner V3s CCU"); +MODULE_LICENSE("GPL"); |