diff options
Diffstat (limited to 'drivers/gpio/gpio-stmpe.c')
| -rw-r--r-- | drivers/gpio/gpio-stmpe.c | 549 |
1 files changed, 326 insertions, 223 deletions
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c index b33bad1bb4df..6faf30347a36 100644 --- a/drivers/gpio/gpio-stmpe.c +++ b/drivers/gpio/gpio-stmpe.c @@ -1,20 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) ST-Ericsson SA 2010 * - * License Terms: GNU General Public License, version 2 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson */ -#include <linux/module.h> +#include <linux/bitops.h> +#include <linux/cleanup.h> +#include <linux/gpio/driver.h> #include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/gpio.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> #include <linux/interrupt.h> -#include <linux/of.h> #include <linux/mfd/stmpe.h> +#include <linux/property.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/string_choices.h> /* * These registers are modified under the irq bus lock and cached to avoid @@ -22,35 +23,28 @@ */ enum { REG_RE, REG_FE, REG_IE }; +enum { LSB, CSB, MSB }; + #define CACHE_NR_REGS 3 -#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8) +/* No variant has more than 24 GPIOs */ +#define CACHE_NR_BANKS (24 / 8) struct stmpe_gpio { struct gpio_chip chip; struct stmpe *stmpe; - struct device *dev; struct mutex irq_lock; - struct irq_domain *domain; - - int irq_base; - unsigned norequest_mask; - + u32 norequest_mask; /* Caches of interrupt control registers for bus_lock */ u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; }; -static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip) -{ - return container_of(chip, struct stmpe_gpio, chip); -} - static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) { - struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; - u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8); - u8 mask = 1 << (offset % 8); + u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; + u8 mask = BIT(offset % 8); int ret; ret = stmpe_reg_read(stmpe, reg); @@ -60,33 +54,55 @@ static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) return !!(ret & mask); } -static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +static int stmpe_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) { - struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; - u8 reg = stmpe->regs[which] - (offset / 8); - u8 mask = 1 << (offset % 8); + u8 reg = stmpe->regs[which + (offset / 8)]; + u8 mask = BIT(offset % 8); /* * Some variants have single register for gpio set/clear functionality. * For them we need to write 0 to clear and 1 to set. */ if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) - stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); - else - stmpe_reg_write(stmpe, reg, mask); + return stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); + + return stmpe_reg_write(stmpe, reg, mask); +} + +static int stmpe_gpio_get_direction(struct gpio_chip *chip, + unsigned offset) +{ + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); + struct stmpe *stmpe = stmpe_gpio->stmpe; + u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); + u8 mask = BIT(offset % 8); + int ret; + + ret = stmpe_reg_read(stmpe, reg); + if (ret < 0) + return ret; + + if (ret & mask) + return GPIO_LINE_DIRECTION_OUT; + + return GPIO_LINE_DIRECTION_IN; } static int stmpe_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int val) { - struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; - u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); - u8 mask = 1 << (offset % 8); + u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; + u8 mask = BIT(offset % 8); + int ret; - stmpe_gpio_set(chip, offset, val); + ret = stmpe_gpio_set(chip, offset, val); + if (ret) + return ret; return stmpe_set_bits(stmpe, reg, mask, mask); } @@ -94,64 +110,59 @@ static int stmpe_gpio_direction_output(struct gpio_chip *chip, static int stmpe_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { - struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; - u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); - u8 mask = 1 << (offset % 8); + u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; + u8 mask = BIT(offset % 8); return stmpe_set_bits(stmpe, reg, mask, 0); } -static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); - - return irq_create_mapping(stmpe_gpio->domain, offset); -} - static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) { - struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); struct stmpe *stmpe = stmpe_gpio->stmpe; - if (stmpe_gpio->norequest_mask & (1 << offset)) + if (stmpe_gpio->norequest_mask & BIT(offset)) return -EINVAL; - return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO); + return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO); } -static struct gpio_chip template_chip = { +static const struct gpio_chip template_chip = { .label = "stmpe", .owner = THIS_MODULE, + .get_direction = stmpe_gpio_get_direction, .direction_input = stmpe_gpio_direction_input, .get = stmpe_gpio_get, .direction_output = stmpe_gpio_direction_output, .set = stmpe_gpio_set, - .to_irq = stmpe_gpio_to_irq, .request = stmpe_gpio_request, - .can_sleep = 1, + .can_sleep = true, }; static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) { - struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); int offset = d->hwirq; int regoffset = offset / 8; - int mask = 1 << (offset % 8); + int mask = BIT(offset % 8); - if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) + if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH) return -EINVAL; - /* STMPE801 doesn't have RE and FE registers */ - if (stmpe_gpio->stmpe->partnum == STMPE801) + /* STMPE801 and STMPE 1600 don't have RE and FE registers */ + if (stmpe_gpio->stmpe->partnum == STMPE801 || + stmpe_gpio->stmpe->partnum == STMPE1600) return 0; - if (type == IRQ_TYPE_EDGE_RISING) + if (type & IRQ_TYPE_EDGE_RISING) stmpe_gpio->regs[REG_RE][regoffset] |= mask; else stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; - if (type == IRQ_TYPE_EDGE_FALLING) + if (type & IRQ_TYPE_EDGE_FALLING) stmpe_gpio->regs[REG_FE][regoffset] |= mask; else stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; @@ -161,27 +172,54 @@ static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) static void stmpe_gpio_irq_lock(struct irq_data *d) { - struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); mutex_lock(&stmpe_gpio->irq_lock); } static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) { - struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); struct stmpe *stmpe = stmpe_gpio->stmpe; int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); - static const u8 regmap[] = { - [REG_RE] = STMPE_IDX_GPRER_LSB, - [REG_FE] = STMPE_IDX_GPFER_LSB, - [REG_IE] = STMPE_IDX_IEGPIOR_LSB, + static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = { + [REG_RE][LSB] = STMPE_IDX_GPRER_LSB, + [REG_RE][CSB] = STMPE_IDX_GPRER_CSB, + [REG_RE][MSB] = STMPE_IDX_GPRER_MSB, + [REG_FE][LSB] = STMPE_IDX_GPFER_LSB, + [REG_FE][CSB] = STMPE_IDX_GPFER_CSB, + [REG_FE][MSB] = STMPE_IDX_GPFER_MSB, + [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB, + [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB, + [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB, }; - int i, j; + int ret, i, j; + + /* + * STMPE1600: to be able to get IRQ from pins, + * a read must be done on GPMR register, or a write in + * GPSR or GPCR registers + */ + if (stmpe->partnum == STMPE1600) { + ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]); + if (ret < 0) { + dev_err(stmpe->dev, "Failed to read GPMR_LSB: %d\n", ret); + goto err; + } + ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]); + if (ret < 0) { + dev_err(stmpe->dev, "Failed to read GPMR_CSB: %d\n", ret); + goto err; + } + } for (i = 0; i < CACHE_NR_REGS; i++) { - /* STMPE801 doesn't have RE and FE registers */ - if ((stmpe->partnum == STMPE801) && - (i != REG_IE)) + /* STMPE801 and STMPE1600 don't have RE and FE registers */ + if ((stmpe->partnum == STMPE801 || + stmpe->partnum == STMPE1600) && + (i != REG_IE)) continue; for (j = 0; j < num_banks; j++) { @@ -192,58 +230,191 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) continue; stmpe_gpio->oldregs[i][j] = new; - stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new); + stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new); } } +err: mutex_unlock(&stmpe_gpio->irq_lock); } static void stmpe_gpio_irq_mask(struct irq_data *d) { - struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); int offset = d->hwirq; int regoffset = offset / 8; - int mask = 1 << (offset % 8); + int mask = BIT(offset % 8); stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; + gpiochip_disable_irq(gc, offset); } static void stmpe_gpio_irq_unmask(struct irq_data *d) { - struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); int offset = d->hwirq; int regoffset = offset / 8; - int mask = 1 << (offset % 8); + int mask = BIT(offset % 8); + gpiochip_enable_irq(gc, offset); stmpe_gpio->regs[REG_IE][regoffset] |= mask; } -static struct irq_chip stmpe_gpio_irq_chip = { +static void stmpe_dbg_show_one(struct seq_file *s, struct gpio_chip *gc, + unsigned int offset) +{ + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); + struct stmpe *stmpe = stmpe_gpio->stmpe; + bool val = !!stmpe_gpio_get(gc, offset); + u8 bank = offset / 8; + u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank]; + u8 mask = BIT(offset % 8); + int ret; + u8 dir; + + char *label __free(kfree) = gpiochip_dup_line_label(gc, offset); + if (IS_ERR(label)) + return; + + ret = stmpe_reg_read(stmpe, dir_reg); + if (ret < 0) + return; + dir = !!(ret & mask); + + if (dir) { + seq_printf(s, " gpio-%-3d (%-20.20s) out %s", + offset, label ?: "(none)", str_hi_lo(val)); + } else { + u8 edge_det_reg; + u8 rise_reg; + u8 fall_reg; + u8 irqen_reg; + + static const char * const edge_det_values[] = { + "edge-inactive", + "edge-asserted", + "not-supported" + }; + static const char * const rise_values[] = { + "no-rising-edge-detection", + "rising-edge-detection", + "not-supported" + }; + static const char * const fall_values[] = { + "no-falling-edge-detection", + "falling-edge-detection", + "not-supported" + }; + #define NOT_SUPPORTED_IDX 2 + u8 edge_det = NOT_SUPPORTED_IDX; + u8 rise = NOT_SUPPORTED_IDX; + u8 fall = NOT_SUPPORTED_IDX; + bool irqen; + + switch (stmpe->partnum) { + case STMPE610: + case STMPE811: + case STMPE1601: + case STMPE2401: + case STMPE2403: + edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank]; + ret = stmpe_reg_read(stmpe, edge_det_reg); + if (ret < 0) + return; + edge_det = !!(ret & mask); + fallthrough; + case STMPE1801: + rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank]; + fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank]; + + ret = stmpe_reg_read(stmpe, rise_reg); + if (ret < 0) + return; + rise = !!(ret & mask); + ret = stmpe_reg_read(stmpe, fall_reg); + if (ret < 0) + return; + fall = !!(ret & mask); + fallthrough; + case STMPE801: + case STMPE1600: + irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank]; + break; + + default: + return; + } + + ret = stmpe_reg_read(stmpe, irqen_reg); + if (ret < 0) + return; + irqen = !!(ret & mask); + + seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s", + offset, label ?: "(none)", + str_hi_lo(val), + edge_det_values[edge_det], + irqen ? "IRQ-enabled" : "IRQ-disabled", + rise_values[rise], + fall_values[fall]); + } +} + +static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc) +{ + unsigned i; + + for (i = 0; i < gc->ngpio; i++) { + stmpe_dbg_show_one(s, gc, i); + seq_putc(s, '\n'); + } +} + +static const struct irq_chip stmpe_gpio_irq_chip = { .name = "stmpe-gpio", .irq_bus_lock = stmpe_gpio_irq_lock, .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, .irq_mask = stmpe_gpio_irq_mask, .irq_unmask = stmpe_gpio_irq_unmask, .irq_set_type = stmpe_gpio_irq_set_type, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, }; +#define MAX_GPIOS 24 + static irqreturn_t stmpe_gpio_irq(int irq, void *dev) { struct stmpe_gpio *stmpe_gpio = dev; struct stmpe *stmpe = stmpe_gpio->stmpe; - u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; + u8 statmsbreg; int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); - u8 status[num_banks]; + u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)]; int ret; int i; + /* + * the stmpe_block_read() call below, imposes to set statmsbreg + * with the register located at the lowest address. As STMPE1600 + * variant is the only one which respect registers address's order + * (LSB regs located at lowest address than MSB ones) whereas all + * the others have a registers layout with MSB located before the + * LSB regs. + */ + if (stmpe->partnum == STMPE1600) + statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB]; + else + statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; + ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); if (ret < 0) return IRQ_NONE; for (i = 0; i < num_banks; i++) { - int bank = num_banks - i - 1; + int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i : + num_banks - i - 1; unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; unsigned int stat = status[i]; @@ -254,193 +425,125 @@ static irqreturn_t stmpe_gpio_irq(int irq, void *dev) while (stat) { int bit = __ffs(stat); int line = bank * 8 + bit; - int virq = irq_find_mapping(stmpe_gpio->domain, line); + int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain, + line); - handle_nested_irq(virq); - stat &= ~(1 << bit); + handle_nested_irq(child_irq); + stat &= ~BIT(bit); } - stmpe_reg_write(stmpe, statmsbreg + i, status[i]); - - /* Edge detect register is not present on 801 */ - if (stmpe->partnum != STMPE801) - stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] - + i, status[i]); + /* + * interrupt status register write has no effect on + * 801/1801/1600, bits are cleared when read. + * Edge detect register is not present on 801/1600/1801 + */ + if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 && + stmpe->partnum != STMPE1801) { + stmpe_reg_write(stmpe, statmsbreg + i, status[i]); + stmpe_reg_write(stmpe, + stmpe->regs[STMPE_IDX_GPEDR_MSB] + i, + status[i]); + } } return IRQ_HANDLED; } -static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int virq, - irq_hw_number_t hwirq) +static void stmpe_init_irq_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) { - struct stmpe_gpio *stmpe_gpio = d->host_data; - - if (!stmpe_gpio) - return -EINVAL; - - irq_set_chip_data(hwirq, stmpe_gpio); - irq_set_chip_and_handler(hwirq, &stmpe_gpio_irq_chip, - handle_simple_irq); - irq_set_nested_thread(hwirq, 1); -#ifdef CONFIG_ARM - set_irq_flags(hwirq, IRQF_VALID); -#else - irq_set_noprobe(hwirq); -#endif + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); + int i; - return 0; -} + if (!stmpe_gpio->norequest_mask) + return; -static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int virq) -{ -#ifdef CONFIG_ARM - set_irq_flags(virq, 0); -#endif - irq_set_chip_and_handler(virq, NULL, NULL); - irq_set_chip_data(virq, NULL); + /* Forbid unused lines to be mapped as IRQs */ + for (i = 0; i < sizeof(u32); i++) { + if (stmpe_gpio->norequest_mask & BIT(i)) + clear_bit(i, valid_mask); + } } -static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = { - .unmap = stmpe_gpio_irq_unmap, - .map = stmpe_gpio_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio, - struct device_node *np) +static void stmpe_gpio_disable(void *stmpe) { - int base = 0; - - if (!np) - base = stmpe_gpio->irq_base; - - stmpe_gpio->domain = irq_domain_add_simple(np, - stmpe_gpio->chip.ngpio, base, - &stmpe_gpio_irq_simple_ops, stmpe_gpio); - if (!stmpe_gpio->domain) { - dev_err(stmpe_gpio->dev, "failed to create irqdomain\n"); - return -ENOSYS; - } - - return 0; + stmpe_disable(stmpe, STMPE_BLOCK_GPIO); } static int stmpe_gpio_probe(struct platform_device *pdev) { - struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); - struct device_node *np = pdev->dev.of_node; - struct stmpe_gpio_platform_data *pdata; + struct device *dev = &pdev->dev; + struct stmpe *stmpe = dev_get_drvdata(dev->parent); struct stmpe_gpio *stmpe_gpio; - int ret; - int irq = 0; + int ret, irq; - pdata = stmpe->pdata->gpio; - - irq = platform_get_irq(pdev, 0); + if (stmpe->num_gpios > MAX_GPIOS) { + dev_err(dev, "Need to increase maximum GPIO number\n"); + return -EINVAL; + } - stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL); + stmpe_gpio = devm_kzalloc(dev, sizeof(*stmpe_gpio), GFP_KERNEL); if (!stmpe_gpio) return -ENOMEM; mutex_init(&stmpe_gpio->irq_lock); - stmpe_gpio->dev = &pdev->dev; stmpe_gpio->stmpe = stmpe; stmpe_gpio->chip = template_chip; stmpe_gpio->chip.ngpio = stmpe->num_gpios; - stmpe_gpio->chip.dev = &pdev->dev; -#ifdef CONFIG_OF - stmpe_gpio->chip.of_node = np; -#endif - stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1; - - if (pdata) - stmpe_gpio->norequest_mask = pdata->norequest_mask; - else if (np) - of_property_read_u32(np, "st,norequest-mask", - &stmpe_gpio->norequest_mask); - - if (irq >= 0) - stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0); - else - dev_info(&pdev->dev, - "device configured in no-irq mode; " - "irqs are not available\n"); + stmpe_gpio->chip.parent = dev; + stmpe_gpio->chip.base = -1; + + if (IS_ENABLED(CONFIG_DEBUG_FS)) + stmpe_gpio->chip.dbg_show = stmpe_dbg_show; + + device_property_read_u32(dev, "st,norequest-mask", &stmpe_gpio->norequest_mask); ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); if (ret) - goto out_free; + return ret; - if (irq >= 0) { - ret = stmpe_gpio_irq_init(stmpe_gpio, np); - if (ret) - goto out_disable; + ret = devm_add_action_or_reset(dev, stmpe_gpio_disable, stmpe); + if (ret) + return ret; - ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, - IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio); - if (ret) { - dev_err(&pdev->dev, "unable to get irq: %d\n", ret); - goto out_disable; - } - } + irq = platform_get_irq(pdev, 0); + if (irq > 0) { + struct gpio_irq_chip *girq; - ret = gpiochip_add(&stmpe_gpio->chip); - if (ret) { - dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); - goto out_freeirq; + ret = devm_request_threaded_irq(dev, irq, NULL, stmpe_gpio_irq, + IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio); + if (ret) + return dev_err_probe(dev, ret, "unable to register IRQ handler\n"); + + girq = &stmpe_gpio->chip.irq; + gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip); + /* This will let us handle the parent IRQ in the driver */ + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->parents = NULL; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + girq->threaded = true; + girq->init_valid_mask = stmpe_init_irq_valid_mask; } - if (pdata && pdata->setup) - pdata->setup(stmpe, stmpe_gpio->chip.base); - - platform_set_drvdata(pdev, stmpe_gpio); - - return 0; - -out_freeirq: - if (irq >= 0) - free_irq(irq, stmpe_gpio); -out_disable: - stmpe_disable(stmpe, STMPE_BLOCK_GPIO); -out_free: - kfree(stmpe_gpio); - return ret; + return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio); } -static int stmpe_gpio_remove(struct platform_device *pdev) -{ - struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev); - struct stmpe *stmpe = stmpe_gpio->stmpe; - struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio; - int irq = platform_get_irq(pdev, 0); - int ret; - - if (pdata && pdata->remove) - pdata->remove(stmpe, stmpe_gpio->chip.base); - - ret = gpiochip_remove(&stmpe_gpio->chip); - if (ret < 0) { - dev_err(stmpe_gpio->dev, - "unable to remove gpiochip: %d\n", ret); - return ret; - } - - stmpe_disable(stmpe, STMPE_BLOCK_GPIO); - - if (irq >= 0) - free_irq(irq, stmpe_gpio); - - kfree(stmpe_gpio); - - return 0; -} +static const struct of_device_id stmpe_gpio_of_matches[] = { + { .compatible = "st,stmpe-gpio", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, stmpe_gpio_of_matches); static struct platform_driver stmpe_gpio_driver = { - .driver.name = "stmpe-gpio", - .driver.owner = THIS_MODULE, + .driver = { + .name = "stmpe-gpio", + .of_match_table = stmpe_gpio_of_matches, + }, .probe = stmpe_gpio_probe, - .remove = stmpe_gpio_remove, }; static int __init stmpe_gpio_init(void) @@ -455,6 +558,6 @@ static void __exit stmpe_gpio_exit(void) } module_exit(stmpe_gpio_exit); -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("STMPExxxx GPIO driver"); +MODULE_DESCRIPTION("STMPE expander GPIO"); MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>"); +MODULE_LICENSE("GPL"); |