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path: root/drivers/gpu/drm/amd/amdgpu/vi.h
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vi.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.h112
1 files changed, 0 insertions, 112 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.h b/drivers/gpu/drm/amd/amdgpu/vi.h
index 719587b8b0cb..575d7aed5d32 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.h
+++ b/drivers/gpu/drm/amd/amdgpu/vi.h
@@ -28,116 +28,4 @@ void vi_srbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
int vi_set_ip_blocks(struct amdgpu_device *adev);
-struct amdgpu_ce_ib_state
-{
- uint32_t ce_ib_completion_status;
- uint32_t ce_constegnine_count;
- uint32_t ce_ibOffset_ib1;
- uint32_t ce_ibOffset_ib2;
-}; /* Total of 4 DWORD */
-
-struct amdgpu_de_ib_state
-{
- uint32_t ib_completion_status;
- uint32_t de_constEngine_count;
- uint32_t ib_offset_ib1;
- uint32_t ib_offset_ib2;
- uint32_t preamble_begin_ib1;
- uint32_t preamble_begin_ib2;
- uint32_t preamble_end_ib1;
- uint32_t preamble_end_ib2;
- uint32_t draw_indirect_baseLo;
- uint32_t draw_indirect_baseHi;
- uint32_t disp_indirect_baseLo;
- uint32_t disp_indirect_baseHi;
- uint32_t gds_backup_addrlo;
- uint32_t gds_backup_addrhi;
- uint32_t index_base_addrlo;
- uint32_t index_base_addrhi;
- uint32_t sample_cntl;
-}; /* Total of 17 DWORD */
-
-struct amdgpu_ce_ib_state_chained_ib
-{
- /* section of non chained ib part */
- uint32_t ce_ib_completion_status;
- uint32_t ce_constegnine_count;
- uint32_t ce_ibOffset_ib1;
- uint32_t ce_ibOffset_ib2;
-
- /* section of chained ib */
- uint32_t ce_chainib_addrlo_ib1;
- uint32_t ce_chainib_addrlo_ib2;
- uint32_t ce_chainib_addrhi_ib1;
- uint32_t ce_chainib_addrhi_ib2;
- uint32_t ce_chainib_size_ib1;
- uint32_t ce_chainib_size_ib2;
-}; /* total 10 DWORD */
-
-struct amdgpu_de_ib_state_chained_ib
-{
- /* section of non chained ib part */
- uint32_t ib_completion_status;
- uint32_t de_constEngine_count;
- uint32_t ib_offset_ib1;
- uint32_t ib_offset_ib2;
-
- /* section of chained ib */
- uint32_t chain_ib_addrlo_ib1;
- uint32_t chain_ib_addrlo_ib2;
- uint32_t chain_ib_addrhi_ib1;
- uint32_t chain_ib_addrhi_ib2;
- uint32_t chain_ib_size_ib1;
- uint32_t chain_ib_size_ib2;
-
- /* section of non chained ib part */
- uint32_t preamble_begin_ib1;
- uint32_t preamble_begin_ib2;
- uint32_t preamble_end_ib1;
- uint32_t preamble_end_ib2;
-
- /* section of chained ib */
- uint32_t chain_ib_pream_addrlo_ib1;
- uint32_t chain_ib_pream_addrlo_ib2;
- uint32_t chain_ib_pream_addrhi_ib1;
- uint32_t chain_ib_pream_addrhi_ib2;
-
- /* section of non chained ib part */
- uint32_t draw_indirect_baseLo;
- uint32_t draw_indirect_baseHi;
- uint32_t disp_indirect_baseLo;
- uint32_t disp_indirect_baseHi;
- uint32_t gds_backup_addrlo;
- uint32_t gds_backup_addrhi;
- uint32_t index_base_addrlo;
- uint32_t index_base_addrhi;
- uint32_t sample_cntl;
-}; /* Total of 27 DWORD */
-
-struct amdgpu_gfx_meta_data
-{
- /* 4 DWORD, address must be 4KB aligned */
- struct amdgpu_ce_ib_state ce_payload;
- uint32_t reserved1[60];
- /* 17 DWORD, address must be 64B aligned */
- struct amdgpu_de_ib_state de_payload;
- /* PFP IB base address which get pre-empted */
- uint32_t DeIbBaseAddrLo;
- uint32_t DeIbBaseAddrHi;
- uint32_t reserved2[941];
-}; /* Total of 4K Bytes */
-
-struct amdgpu_gfx_meta_data_chained_ib
-{
- /* 10 DWORD, address must be 4KB aligned */
- struct amdgpu_ce_ib_state_chained_ib ce_payload;
- uint32_t reserved1[54];
- /* 27 DWORD, address must be 64B aligned */
- struct amdgpu_de_ib_state_chained_ib de_payload;
- /* PFP IB base address which get pre-empted */
- uint32_t DeIbBaseAddrLo;
- uint32_t DeIbBaseAddrHi;
- uint32_t reserved2[931];
-}; /* Total of 4K Bytes */
-
#endif