diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 690 |
1 files changed, 444 insertions, 246 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ee8453bf958f..1d917be36fc4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -44,6 +44,8 @@ #include "dml2/dml2_wrapper.h" +#include "dmub/inc/dmub_cmd.h" + struct abm_save_restore; /* forward declaration */ @@ -51,13 +53,20 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.273" +#define DC_VER "3.2.334" -#define MAX_SURFACES 3 +/** + * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC + */ +#define MAX_SURFACES 4 +/** + * MAX_PLANES - representative of the upper bound of planes that are supported by the HW + */ #define MAX_PLANES 6 #define MAX_STREAMS 6 #define MIN_VIEWPORT_SIZE 12 #define MAX_NUM_EDP 2 +#define MAX_HOST_ROUTERS_NUM 2 /* Display Core Interfaces */ struct dc_versions { @@ -219,6 +228,12 @@ struct dc_dmub_caps { bool mclk_sw; bool subvp_psr; bool gecc_enable; + uint8_t fams_ver; + bool aux_backlight_support; +}; + +struct dc_scl_caps { + bool sharpener_support; }; struct dc_caps { @@ -234,6 +249,7 @@ struct dc_caps { uint32_t i2c_speed_in_khz_hdcp; uint32_t dmdata_alloc_size; unsigned int max_cursor_size; + unsigned int max_buffered_cursor_size; unsigned int max_video_width; /* * max video plane width that can be safely assumed to be always @@ -267,6 +283,7 @@ struct dc_caps { bool edp_dsc_support; bool vbios_lttpr_aware; bool vbios_lttpr_enable; + bool fused_io_supported; uint32_t max_otg_num; uint32_t max_cab_allocation_bytes; uint32_t cache_line_size; @@ -279,8 +296,15 @@ struct dc_caps { uint16_t subvp_vertical_int_margin_us; bool seamless_odm; uint32_t max_v_total; + bool vtotal_limited_by_fp2; uint32_t max_disp_clock_khz_at_vmin; uint8_t subvp_drr_vblank_start_margin_us; + bool cursor_not_scaled; + bool dcmode_power_limits_present; + bool sequential_ono; + /* Conservative limit for DCC cases which require ODM4:1 to support*/ + uint32_t dcc_plane_width_limit; + struct dc_scl_caps scl_caps; }; struct dc_bug_wa { @@ -294,11 +318,18 @@ struct dc_bug_wa { uint8_t dcfclk : 1; uint8_t dcfclk_ds: 1; } clock_update_disable_mask; + bool skip_psr_ips_crtc_disable; }; struct dc_dcc_surface_param { struct dc_size surface_size; enum surface_pixel_format format; - enum swizzle_mode_values swizzle_mode; + unsigned int plane0_pitch; + struct dc_size plane1_size; + unsigned int plane1_pitch; + union { + enum swizzle_mode_values swizzle_mode; + enum swizzle_mode_addr3_values swizzle_mode_addr3; + }; enum dc_scan_direction scan; }; @@ -306,12 +337,15 @@ struct dc_dcc_setting { unsigned int max_compressed_blk_size; unsigned int max_uncompressed_blk_size; bool independent_64b_blks; - //These bitfields to be used starting with DCN + //These bitfields to be used starting with DCN 3.0 struct { - uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) - uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN - uint32_t dcc_256_128_128 : 1; //available starting with DCN - uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) + uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) + uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 + uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 + uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) + uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) + uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x + uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) } dcc_controls; }; @@ -379,7 +413,6 @@ struct dc; struct dc_plane_state; struct dc_state; - struct dc_cap_funcs { bool (*get_dcc_compression_cap)(const struct dc *dc, const struct dc_dcc_surface_param *input, @@ -416,12 +449,15 @@ struct dc_config { bool enable_windowed_mpo_odm; bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 uint32_t allow_edp_hotplug_detection; + bool skip_riommu_prefetch_wa; bool clamp_min_dcfclk; uint64_t vblank_alignment_dto_params; uint8_t vblank_alignment_max_frame_time_diff; bool is_asymmetric_memory; bool is_single_rank_dimm; bool is_vmin_only_asic; + bool use_spl; + bool prefer_easf; bool use_pipe_ctx_sync_logic; bool ignore_dpref_ss; bool enable_mipi_converter_optimization; @@ -434,7 +470,17 @@ struct dc_config { bool enable_auto_dpm_test_logs; unsigned int disable_ips; unsigned int disable_ips_in_vpb; + bool disable_ips_in_dpms_off; bool usb4_bw_alloc_support; + bool allow_0_dtb_clk; + bool use_assr_psp_message; + bool support_edp0_on_dp1; + unsigned int enable_fpo_flicker_detection; + bool disable_hbr_audio_dp2; + bool consolidated_dpia_dp_lt; + bool set_pipe_unlock_order; + bool enable_dpia_pre_training; + bool unify_link_enc_assignment; }; enum visual_confirm { @@ -449,6 +495,11 @@ enum visual_confirm { VISUAL_CONFIRM_REPLAY = 12, VISUAL_CONFIRM_SUBVP = 14, VISUAL_CONFIRM_MCLK_SWITCH = 16, + VISUAL_CONFIRM_FAMS2 = 19, + VISUAL_CONFIRM_HW_CURSOR = 20, + VISUAL_CONFIRM_VABC = 21, + VISUAL_CONFIRM_DCC = 22, + VISUAL_CONFIRM_EXPLICIT = 0x80000000, }; enum dc_psr_power_opts { @@ -476,6 +527,13 @@ enum dcc_option { DCC_HALF_REQ_DISALBE = 2, }; +enum in_game_fams_config { + INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams + INGAME_FAMS_DISABLE, // disable in-game fams + INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display + INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies +}; + /** * enum pipe_split_policy - Pipe split strategy supported by DCN * @@ -562,6 +620,7 @@ struct dc_clocks { bool prev_p_state_change_support; bool fclk_prev_p_state_change_support; int num_ways; + int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; /* * @fw_based_mclk_switching @@ -580,6 +639,10 @@ struct dc_clocks { int max_supported_dispclk_khz; int bw_dppclk_khz; /*a copy of dppclk_khz*/ int bw_dispclk_khz; + int idle_dramclk_khz; + int idle_fclk_khz; + int subvp_prefetch_dramclk_khz; + int subvp_prefetch_fclk_khz; }; struct dc_bw_validation_profile { @@ -693,6 +756,9 @@ enum pg_hw_pipe_resources { PG_MPCC, PG_OPP, PG_OPTC, + PG_DPSTREAM, + PG_HDMISTREAM, + PG_PHYSYMCLK, PG_HW_PIPE_RESOURCES_NUM_ELEMENT }; @@ -719,7 +785,11 @@ union dpia_debug_options { uint32_t extend_aux_rd_interval:1; /* bit 2 */ uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ - uint32_t reserved:27; + uint32_t disable_usb4_pm_support:1; /* bit 5 */ + uint32_t enable_consolidated_dpia_dp_lt:1; /* bit 6 */ + uint32_t enable_dpia_pre_training:1; /* bit 7 */ + uint32_t unify_link_enc_assignment:1; /* bit 8 */ + uint32_t reserved:24; } bits; uint32_t raw; }; @@ -817,7 +887,6 @@ struct dc_debug_options { bool sanity_checks; bool max_disp_clk; bool surface_trace; - bool timing_trace; bool clock_trace; bool validation_trace; bool bandwidth_calcs_trace; @@ -837,6 +906,9 @@ struct dc_debug_options { bool voltage_align_fclk; bool disable_min_fclk; + bool hdcp_lc_force_fw_enable; + bool hdcp_lc_enable_sw_fallback; + bool disable_dfs_bypass; bool disable_dpp_power_gate; bool disable_hubp_power_gate; @@ -887,6 +959,7 @@ struct dc_debug_options { bool disable_z9_mpc; unsigned int force_fclk_khz; bool enable_tri_buf; + bool ips_disallow_entry; bool dmub_offload_enabled; bool dmcub_emulation; bool disable_idle_power_optimizations; @@ -926,7 +999,7 @@ struct dc_debug_options { /* Enable dmub aux for legacy ddc */ bool enable_dmub_aux_for_legacy_ddc; bool disable_fams; - bool disable_fams_gaming; + enum in_game_fams_config disable_fams_gaming; /* FEC/PSR1 sequence enable delay in 100us */ uint8_t fec_enable_delay_in100us; bool enable_driver_sequence_debug; @@ -935,6 +1008,7 @@ struct dc_debug_options { bool disable_z10; bool enable_z9_disable_interface; bool psr_skip_crtc_disable; + uint32_t ips_skip_crtc_disable_mask; union dpia_debug_options dpia_debug; bool disable_fixed_vs_aux_timeout_wa; uint32_t fixed_vs_aux_delay_config_wa; @@ -960,6 +1034,7 @@ struct dc_debug_options { bool enable_single_display_2to1_odm_policy; bool enable_double_buffered_dsc_pg_support; bool enable_dp_dig_pixel_rate_div_policy; + bool using_dml21; enum lttpr_mode lttpr_mode_override; unsigned int dsc_delay_factor_wa_x1000; unsigned int min_prefetch_in_strobe_ns; @@ -987,14 +1062,38 @@ struct dc_debug_options { bool psp_disabled_wa; unsigned int ips2_eval_delay_us; unsigned int ips2_entry_delay_us; + bool optimize_ips_handshake; bool disable_dmub_reallow_idle; bool disable_timeout; bool disable_extblankadj; + bool enable_idle_reg_checks; unsigned int static_screen_wait_frames; + uint32_t pwm_freq; bool force_chroma_subsampling_1tap; + unsigned int dcc_meta_propagation_delay_us; + bool disable_422_left_edge_pixel; + bool dml21_force_pstate_method; + uint32_t dml21_force_pstate_method_values[MAX_PIPES]; + uint32_t dml21_disable_pstate_method_mask; + union fw_assisted_mclk_switch_version fams_version; + union dmub_fams2_global_feature_config fams2_config; + unsigned int force_cositing; + unsigned int disable_spl; + unsigned int force_easf; + unsigned int force_sharpness; + unsigned int force_sharpness_level; + unsigned int force_lls; + bool notify_dpia_hr_bw; + bool enable_ips_visual_confirm; + unsigned int sharpen_policy; + unsigned int scale_to_sharpness_policy; + bool skip_full_updated_if_possible; + unsigned int enable_oled_edp_power_up_opt; + bool enable_hblank_borrow; + bool force_subvp_df_throttle; + uint32_t acpi_transition_bitmasks[MAX_PIPES]; }; -struct gpu_info_soc_bounding_box_v1_0; /* Generic structure that can be used to query properties of DC. More fields * can be added as required. @@ -1003,76 +1102,6 @@ struct dc_current_properties { unsigned int cursor_size_limit; }; -struct dc { - struct dc_debug_options debug; - struct dc_versions versions; - struct dc_caps caps; - struct dc_cap_funcs cap_funcs; - struct dc_config config; - struct dc_bounding_box_overrides bb_overrides; - struct dc_bug_wa work_arounds; - struct dc_context *ctx; - struct dc_phy_addr_space_config vm_pa_config; - - uint8_t link_count; - struct dc_link *links[MAX_PIPES * 2]; - struct link_service *link_srv; - - struct dc_state *current_state; - struct resource_pool *res_pool; - - struct clk_mgr *clk_mgr; - - /* Display Engine Clock levels */ - struct dm_pp_clock_levels sclk_lvls; - - /* Inputs into BW and WM calculations. */ - struct bw_calcs_dceip *bw_dceip; - struct bw_calcs_vbios *bw_vbios; - struct dcn_soc_bounding_box *dcn_soc; - struct dcn_ip_params *dcn_ip; - struct display_mode_lib dml; - - /* HW functions */ - struct hw_sequencer_funcs hwss; - struct dce_hwseq *hwseq; - - /* Require to optimize clocks and bandwidth for added/removed planes */ - bool optimized_required; - bool wm_optimized_required; - bool idle_optimizations_allowed; - bool enable_c20_dtm_b0; - - /* Require to maintain clocks and bandwidth for UEFI enabled HW */ - - /* FBC compressor */ - struct compressor *fbc_compressor; - - struct dc_debug_data debug_data; - struct dpcd_vendor_signature vendor_signature; - - const char *build_id; - struct vm_helper *vm_helper; - - uint32_t *dcn_reg_offsets; - uint32_t *nbio_reg_offsets; - uint32_t *clk_reg_offsets; - - /* Scratch memory */ - struct { - struct { - /* - * For matching clock_limits table in driver with table - * from PMFW. - */ - struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; - } update_bw_bounding_box; - } scratch; - - struct dml2_configuration_options dml2_options; - enum dc_acpi_cm_power_state power_state; -}; - enum frame_buffer_mode { FRAME_BUFFER_MODE_LOCAL_ONLY = 0, FRAME_BUFFER_MODE_ZFB_ONLY, @@ -1088,6 +1117,8 @@ struct dchub_init_data { bool dchub_info_valid; }; +struct dml2_soc_bb; + struct dc_init_data { struct hw_asic_id asic_id; void *driver; /* ctx */ @@ -1120,6 +1151,7 @@ struct dc_init_data { uint32_t *dcn_reg_offsets; uint32_t *nbio_reg_offsets; uint32_t *clk_reg_offsets; + struct dml2_soc_bb *bb_from_dmub; }; struct dc_callback_init { @@ -1252,7 +1284,6 @@ union surface_update_flags { uint32_t rotation_change:1; uint32_t swizzle_change:1; uint32_t scaling_change:1; - uint32_t clip_size_change: 1; uint32_t position_change:1; uint32_t in_transfer_func_change:1; uint32_t input_csc_change:1; @@ -1271,12 +1302,16 @@ union surface_update_flags { uint32_t stereo_format_change:1; uint32_t lut_3d:1; uint32_t tmz_changed:1; + uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ uint32_t full_update:1; + uint32_t sdr_white_level_nits:1; } bits; uint32_t raw; }; +#define DC_REMOVE_PLANE_POINTERS 1 + struct dc_plane_state { struct dc_plane_address address; struct dc_plane_flip_time time; @@ -1287,13 +1322,13 @@ struct dc_plane_state { struct rect clip_rect; struct plane_size plane_size; - union dc_tiling_info tiling_info; + struct dc_tiling_info tiling_info; struct dc_plane_dcc_param dcc; - struct dc_gamma *gamma_correction; - struct dc_transfer_func *in_transfer_func; - struct dc_bias_and_scale *bias_and_scale; + struct dc_gamma gamma_correction; + struct dc_transfer_func in_transfer_func; + struct dc_bias_and_scale bias_and_scale; struct dc_csc_transform input_csc_color_matrix; struct fixed31_32 coeff_reduction_factor; struct fixed31_32 hdr_mult; @@ -1304,9 +1339,9 @@ struct dc_plane_state { enum dc_color_space color_space; - struct dc_3dlut *lut3d_func; - struct dc_transfer_func *in_shaper_func; - struct dc_transfer_func *blend_tf; + struct dc_3dlut lut3d_func; + struct dc_transfer_func in_shaper_func; + struct dc_transfer_func blend_tf; struct dc_transfer_func *gamcor_tf; enum surface_pixel_format format; @@ -1342,11 +1377,23 @@ struct dc_plane_state { struct tg_color visual_confirm_color; bool is_statically_allocated; + enum chroma_cositing cositing; + enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; + bool mcm_lut1d_enable; + struct dc_cm2_func_luts mcm_luts; + bool lut_bank_a; + enum mpcc_movable_cm_location mcm_location; + struct dc_csc_transform cursor_csc_color_matrix; + bool adaptive_sharpness_en; + int adaptive_sharpness_policy; + int sharpness_level; + enum linear_light_scaling linear_light_scaling; + unsigned int sdr_white_level_nits; }; struct dc_plane_info { struct plane_size plane_size; - union dc_tiling_info tiling_info; + struct dc_tiling_info tiling_info; struct dc_plane_dcc_param dcc; enum surface_pixel_format format; enum dc_rotation_angle rotation; @@ -1360,150 +1407,29 @@ struct dc_plane_info { int global_alpha_value; bool input_csc_enabled; int layer_index; + enum chroma_cositing cositing; }; -struct dc_scaling_info { - struct rect src_rect; - struct rect dst_rect; - struct rect clip_rect; - struct scaling_taps scaling_quality; -}; - -struct dc_fast_update { - const struct dc_flip_addrs *flip_addr; - const struct dc_gamma *gamma; - const struct colorspace_transform *gamut_remap_matrix; - const struct dc_csc_transform *input_csc_color_matrix; - const struct fixed31_32 *coeff_reduction_factor; - struct dc_transfer_func *out_transfer_func; - struct dc_csc_transform *output_csc_transform; -}; - -struct dc_surface_update { - struct dc_plane_state *surface; - - /* isr safe update parameters. null means no updates */ - const struct dc_flip_addrs *flip_addr; - const struct dc_plane_info *plane_info; - const struct dc_scaling_info *scaling_info; - struct fixed31_32 hdr_mult; - /* following updates require alloc/sleep/spin that is not isr safe, - * null means no updates - */ - const struct dc_gamma *gamma; - const struct dc_transfer_func *in_transfer_func; - - const struct dc_csc_transform *input_csc_color_matrix; - const struct fixed31_32 *coeff_reduction_factor; - const struct dc_transfer_func *func_shaper; - const struct dc_3dlut *lut3d_func; - const struct dc_transfer_func *blend_tf; - const struct colorspace_transform *gamut_remap_matrix; -}; - -/* - * Create a new surface with default parameters; - */ -void dc_gamma_retain(struct dc_gamma *dc_gamma); -void dc_gamma_release(struct dc_gamma **dc_gamma); -struct dc_gamma *dc_create_gamma(void); - -void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); -void dc_transfer_func_release(struct dc_transfer_func *dc_tf); -struct dc_transfer_func *dc_create_transfer_func(void); - -struct dc_3dlut *dc_create_3dlut_func(void); -void dc_3dlut_func_release(struct dc_3dlut *lut); -void dc_3dlut_func_retain(struct dc_3dlut *lut); - -void dc_post_update_surfaces_to_stream( - struct dc *dc); - #include "dc_stream.h" -/** - * struct dc_validation_set - Struct to store surface/stream associations for validation - */ -struct dc_validation_set { - /** - * @stream: Stream state properties - */ - struct dc_stream_state *stream; - - /** - * @plane_states: Surface state +struct dc_scratch_space { + /* used to temporarily backup plane states of a stream during + * dc update. The reason is that plane states are overwritten + * with surface updates in dc update. Once they are overwritten + * current state is no longer valid. We want to temporarily + * store current value in plane states so we can still recover + * a valid current state during dc update. */ - struct dc_plane_state *plane_states[MAX_SURFACES]; + struct dc_plane_state plane_states[MAX_SURFACES]; - /** - * @plane_count: Total of active planes - */ - uint8_t plane_count; + struct dc_stream_state stream_state; }; -bool dc_validate_boot_timing(const struct dc *dc, - const struct dc_sink *sink, - struct dc_crtc_timing *crtc_timing); - -enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); - -void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); - -enum dc_status dc_validate_with_context(struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct dc_state *context, - bool fast_validate); - -bool dc_set_generic_gpio_for_stereo(bool enable, - struct gpio_service *gpio_service); - -/* - * fast_validate: we return after determining if we can support the new state, - * but before we populate the programming info - */ -enum dc_status dc_validate_global_state( - struct dc *dc, - struct dc_state *new_ctx, - bool fast_validate); - -bool dc_acquire_release_mpc_3dlut( - struct dc *dc, bool acquire, - struct dc_stream_state *stream, - struct dc_3dlut **lut, - struct dc_transfer_func **shaper); - -bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); -void get_audio_check(struct audio_info *aud_modes, - struct audio_check *aud_chk); - -enum dc_status dc_commit_streams(struct dc *dc, - struct dc_stream_state *streams[], - uint8_t stream_count); - - -struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, - struct dc_stream_state *stream, - int mpcc_inst); - - -uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); - -void dc_set_disable_128b_132b_stream_overhead(bool disable); - -/* The function returns minimum bandwidth required to drive a given timing - * return - minimum required timing bandwidth in kbps. - */ -uint32_t dc_bandwidth_in_kbps_from_timing( - const struct dc_crtc_timing *timing, - const enum dc_link_encoding_format link_encoding); - -/* Link Interfaces */ /* * A link contains one or more sinks and their connected status. * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. */ -struct dc_link { + struct dc_link { struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; unsigned int sink_count; struct dc_sink *local_sink; @@ -1512,6 +1438,7 @@ struct dc_link { enum signal_type connector_signal; enum dc_irq_source irq_source_hpd; enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ + enum dc_irq_source irq_source_read_request;/* Read Request */ bool is_hpd_filter_disabled; bool dp_ss_off; @@ -1619,7 +1546,6 @@ struct dc_link { union dpcd_sink_ext_caps dpcd_sink_ext_caps; struct psr_settings psr_settings; - struct replay_settings replay_settings; /* Drive settings read from integrated info table */ @@ -1643,7 +1569,9 @@ struct dc_link { bool dongle_mode_timing_override; bool blank_stream_on_ocs_change; bool read_dpcd204h_on_irq_hpd; + bool force_dp_ffe_preset; } wa_flags; + union dc_dp_ffe_preset forced_dp_ffe_preset; struct link_mst_stream_allocation_table mst_stream_alloc_table; struct dc_link_status link_status; @@ -1655,11 +1583,247 @@ struct dc_link { struct dc_panel_config panel_config; struct phy_state phy_state; + uint32_t phy_transition_bitmask; // BW ALLOCATON USB4 ONLY struct dc_dpia_bw_alloc dpia_bw_alloc_config; bool skip_implict_edp_power_control; + enum backlight_control_type backlight_control_type; }; +struct dc { + struct dc_debug_options debug; + struct dc_versions versions; + struct dc_caps caps; + struct dc_cap_funcs cap_funcs; + struct dc_config config; + struct dc_bounding_box_overrides bb_overrides; + struct dc_bug_wa work_arounds; + struct dc_context *ctx; + struct dc_phy_addr_space_config vm_pa_config; + + uint8_t link_count; + struct dc_link *links[MAX_LINKS]; + struct link_service *link_srv; + + struct dc_state *current_state; + struct resource_pool *res_pool; + + struct clk_mgr *clk_mgr; + + /* Display Engine Clock levels */ + struct dm_pp_clock_levels sclk_lvls; + + /* Inputs into BW and WM calculations. */ + struct bw_calcs_dceip *bw_dceip; + struct bw_calcs_vbios *bw_vbios; + struct dcn_soc_bounding_box *dcn_soc; + struct dcn_ip_params *dcn_ip; + struct display_mode_lib dml; + + /* HW functions */ + struct hw_sequencer_funcs hwss; + struct dce_hwseq *hwseq; + + /* Require to optimize clocks and bandwidth for added/removed planes */ + bool optimized_required; + bool wm_optimized_required; + bool idle_optimizations_allowed; + bool enable_c20_dtm_b0; + + /* Require to maintain clocks and bandwidth for UEFI enabled HW */ + + /* FBC compressor */ + struct compressor *fbc_compressor; + + struct dc_debug_data debug_data; + struct dpcd_vendor_signature vendor_signature; + + const char *build_id; + struct vm_helper *vm_helper; + + uint32_t *dcn_reg_offsets; + uint32_t *nbio_reg_offsets; + uint32_t *clk_reg_offsets; + + /* Scratch memory */ + struct { + struct { + /* + * For matching clock_limits table in driver with table + * from PMFW. + */ + struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; + } update_bw_bounding_box; + struct dc_scratch_space current_state; + struct dc_scratch_space new_state; + struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack + struct dc_link temp_link; + bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ + } scratch; + + struct dml2_configuration_options dml2_options; + struct dml2_configuration_options dml2_tmp; + enum dc_acpi_cm_power_state power_state; + +}; + +struct dc_scaling_info { + struct rect src_rect; + struct rect dst_rect; + struct rect clip_rect; + struct scaling_taps scaling_quality; +}; + +struct dc_fast_update { + const struct dc_flip_addrs *flip_addr; + const struct dc_gamma *gamma; + const struct colorspace_transform *gamut_remap_matrix; + const struct dc_csc_transform *input_csc_color_matrix; + const struct fixed31_32 *coeff_reduction_factor; + struct dc_transfer_func *out_transfer_func; + struct dc_csc_transform *output_csc_transform; + const struct dc_csc_transform *cursor_csc_color_matrix; +}; + +struct dc_surface_update { + struct dc_plane_state *surface; + + /* isr safe update parameters. null means no updates */ + const struct dc_flip_addrs *flip_addr; + const struct dc_plane_info *plane_info; + const struct dc_scaling_info *scaling_info; + struct fixed31_32 hdr_mult; + /* following updates require alloc/sleep/spin that is not isr safe, + * null means no updates + */ + const struct dc_gamma *gamma; + const struct dc_transfer_func *in_transfer_func; + + const struct dc_csc_transform *input_csc_color_matrix; + const struct fixed31_32 *coeff_reduction_factor; + const struct dc_transfer_func *func_shaper; + const struct dc_3dlut *lut3d_func; + const struct dc_transfer_func *blend_tf; + const struct colorspace_transform *gamut_remap_matrix; + /* + * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) + * + * change cm2_params.component_settings: Full update + * change cm2_params.cm2_luts: Fast update + */ + const struct dc_cm2_parameters *cm2_params; + const struct dc_csc_transform *cursor_csc_color_matrix; + unsigned int sdr_white_level_nits; + struct dc_bias_and_scale bias_and_scale; +}; + +/* + * Create a new surface with default parameters; + */ +void dc_gamma_retain(struct dc_gamma *dc_gamma); +void dc_gamma_release(struct dc_gamma **dc_gamma); +struct dc_gamma *dc_create_gamma(void); + +void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); +void dc_transfer_func_release(struct dc_transfer_func *dc_tf); +struct dc_transfer_func *dc_create_transfer_func(void); + +struct dc_3dlut *dc_create_3dlut_func(void); +void dc_3dlut_func_release(struct dc_3dlut *lut); +void dc_3dlut_func_retain(struct dc_3dlut *lut); + +void dc_post_update_surfaces_to_stream( + struct dc *dc); + +#include "dc_stream.h" + +/** + * struct dc_validation_set - Struct to store surface/stream associations for validation + */ +struct dc_validation_set { + /** + * @stream: Stream state properties + */ + struct dc_stream_state *stream; + + /** + * @plane_states: Surface state + */ + struct dc_plane_state *plane_states[MAX_SURFACES]; + + /** + * @plane_count: Total of active planes + */ + uint8_t plane_count; +}; + +bool dc_validate_boot_timing(const struct dc *dc, + const struct dc_sink *sink, + struct dc_crtc_timing *crtc_timing); + +enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); + +enum dc_status dc_validate_with_context(struct dc *dc, + const struct dc_validation_set set[], + int set_count, + struct dc_state *context, + bool fast_validate); + +bool dc_set_generic_gpio_for_stereo(bool enable, + struct gpio_service *gpio_service); + +/* + * fast_validate: we return after determining if we can support the new state, + * but before we populate the programming info + */ +enum dc_status dc_validate_global_state( + struct dc *dc, + struct dc_state *new_ctx, + bool fast_validate); + +bool dc_acquire_release_mpc_3dlut( + struct dc *dc, bool acquire, + struct dc_stream_state *stream, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper); + +bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); +void get_audio_check(struct audio_info *aud_modes, + struct audio_check *aud_chk); + +bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); +void populate_fast_updates(struct dc_fast_update *fast_update, + struct dc_surface_update *srf_updates, + int surface_count, + struct dc_stream_update *stream_update); +/* + * Set up streams and links associated to drive sinks + * The streams parameter is an absolute set of all active streams. + * + * After this call: + * Phy, Encoder, Timing Generator are programmed and enabled. + * New streams are enabled with blank stream; no memory read. + */ +enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); + + +struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, + struct dc_stream_state *stream, + int mpcc_inst); + + +uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); + +void dc_set_disable_128b_132b_stream_overhead(bool disable); + +/* The function returns minimum bandwidth required to drive a given timing + * return - minimum required timing bandwidth in kbps. + */ +uint32_t dc_bandwidth_in_kbps_from_timing( + const struct dc_crtc_timing *timing, + const enum dc_link_encoding_format link_encoding); + +/* Link Interfaces */ /* Return an enumerated dc_link. * dc_link order is constant and determined at * boot time. They cannot be created or destroyed. @@ -1801,6 +1965,9 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *payload, enum aux_return_code_type *operation_result); +struct ddc_service * +dc_get_oem_i2c_device(struct dc *dc); + bool dc_is_oem_i2c_device_present( struct dc *dc, size_t slave_address @@ -1881,6 +2048,24 @@ uint32_t dc_link_bandwidth_kbps( const struct dc_link *link, const struct dc_link_settings *link_setting); +struct dp_audio_bandwidth_params { + const struct dc_crtc_timing *crtc_timing; + enum dp_link_encoding link_encoding; + uint32_t channel_count; + uint32_t sample_rate_hz; +}; + +/* The function calculates the minimum size of hblank (in bytes) needed to + * support the specified channel count and sample rate combination, given the + * link encoding and timing to be used. This calculation is not supported + * for 8b/10b SST. + * + * return - min hblank size in bytes, 0 if 8b/10b SST. + */ +uint32_t dc_link_required_hblank_size_bytes( + const struct dc_link *link, + struct dp_audio_bandwidth_params *audio_params); + /* The function takes a snapshot of current link resource allocation state * @dc: pointer to dc of the dm calling this * @map: a dc link resource snapshot defined internally to dc. @@ -2075,8 +2260,7 @@ void dc_link_edp_panel_backlight_power_on(struct dc_link *link, * and 16 bit fractional, where 1.0 is max backlight value. */ bool dc_link_set_backlight_level(const struct dc_link *dc_link, - uint32_t backlight_pwm_u16_16, - uint32_t frame_ramp); + struct set_backlight_level_params *backlight_level_params); /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ bool dc_link_set_backlight_level_nits(struct dc_link *link, @@ -2179,19 +2363,6 @@ unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); /* - * Handle function for when the status of the Request above is complete. - * We will find out the result of allocating on CM and update structs. - * - * @link: pointer to the dc_link struct instance - * @bw: Allocated or Estimated BW depending on the result - * @result: Response type - * - * return: none - */ -void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, - uint8_t bw, uint8_t result); - -/* * Handle the USB4 BW Allocation related functionality here: * Plug => Try to allocate max bw from timing parameters supported by the sink * Unplug => de-allocate bw @@ -2199,9 +2370,8 @@ void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, * @link: pointer to the dc_link struct instance * @peak_bw: Peak bw used by the link/sink * - * return: allocated bw else return 0 */ -int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( +void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( struct dc_link *link, int peak_bw); /* @@ -2241,6 +2411,13 @@ struct dc_sink_dsc_caps { struct dsc_dec_dpcd_caps dsc_dec_caps; }; +struct dc_sink_hblank_expansion_caps { + // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), + // 'false' if they are sink's HBlank expansion caps + bool is_virtual_dpcd_hblank_expansion; + struct hblank_expansion_dpcd_caps dpcd_caps; +}; + struct dc_sink_fec_caps { bool is_rx_fec_supported; bool is_topology_fec_supported; @@ -2267,6 +2444,7 @@ struct dc_sink { struct scdc_caps scdc_caps; struct dc_sink_dsc_caps dsc_caps; struct dc_sink_fec_caps fec_caps; + struct dc_sink_hblank_expansion_caps hblank_expansion_caps; bool is_vsc_sdp_colorimetry_supported; @@ -2335,11 +2513,17 @@ bool dc_is_dmcu_initialized(struct dc *dc); enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); -bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, - struct dc_cursor_attributes *cursor_attr); +bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, + unsigned int pitch, + unsigned int height, + enum surface_pixel_format format, + struct dc_cursor_attributes *cursor_attr); + +#define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) +#define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) -void dc_allow_idle_optimizations(struct dc *dc, bool allow); -void dc_exit_ips_for_hw_access(struct dc *dc); +void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); +void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); bool dc_dmub_is_ips_idle_state(struct dc *dc); /* set min and max memory clock to lowest and highest DPM level, respectively */ @@ -2361,6 +2545,8 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable); bool dc_set_replay_allow_active(struct dc *dc, bool active); +bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); + void dc_z10_restore(const struct dc *dc); void dc_z10_save_init(struct dc *dc); @@ -2392,6 +2578,8 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, uint8_t mst_alloc_slots, uint8_t *mst_slots_in_use); +void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); + void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, uint32_t hpd_int_enable); @@ -2405,13 +2593,23 @@ struct dc_power_profile { struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); +unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); + /* DSC Interfaces */ #include "dc_dsc.h" +void dc_get_visual_confirm_for_stream( + struct dc *dc, + struct dc_stream_state *stream_state, + struct tg_color *color); + /* Disable acc mode Interfaces */ void dc_disable_accelerated_mode(struct dc *dc); bool dc_is_timing_changed(struct dc_stream_state *cur_stream, struct dc_stream_state *new_stream); +bool dc_is_cursor_limit_pending(struct dc *dc); +bool dc_can_clear_cursor_limit(struct dc *dc); + #endif /* DC_INTERFACE_H_ */ |