diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 964 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h | 463 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 1396 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 797 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 1468 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 659 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 1628 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 742 |
10 files changed, 3 insertions, 8121 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile index 8dc7938c36d8..9923d0d620d4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile @@ -25,9 +25,8 @@ DCN10 = dcn10_ipp.o \ dcn10_hw_sequencer_debug.o \ dcn10_opp.o \ - dcn10_hubp.o dcn10_mpc.o \ + dcn10_mpc.o \ dcn10_cm_common.o \ - dcn10_hubbub.o dcn10_stream_encoder.o dcn10_link_encoder.o AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c deleted file mode 100644 index 6dd355a03033..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +++ /dev/null @@ -1,964 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "dcn10_hubp.h" -#include "dcn10_hubbub.h" -#include "reg_helper.h" - -#define CTX \ - hubbub1->base.ctx -#define DC_LOGGER \ - hubbub1->base.ctx->logger -#define REG(reg)\ - hubbub1->regs->reg - -#undef FN -#define FN(reg_name, field_name) \ - hubbub1->shifts->field_name, hubbub1->masks->field_name - -void hubbub1_wm_read_state(struct hubbub *hubbub, - struct dcn_hubbub_wm *wm) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - struct dcn_hubbub_wm_set *s; - - memset(wm, 0, sizeof(struct dcn_hubbub_wm)); - - s = &wm->sets[0]; - s->wm_set = 0; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); - } - s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); - - s = &wm->sets[1]; - s->wm_set = 1; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); - } - s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); - - s = &wm->sets[2]; - s->wm_set = 2; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C); - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); - } - s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); - - s = &wm->sets[3]; - s->wm_set = 3; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D); - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); - } - s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); -} - -void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - /* - * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 1 means do not allow stutter - * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0 means allow stutter - */ - - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, - DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow); -} - -bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubbub) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - uint32_t enable = 0; - - REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, &enable); - - return enable ? true : false; -} - - -bool hubbub1_verify_allow_pstate_change_high( - struct hubbub *hubbub) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - - /* pstate latency is ~20us so if we wait over 40us and pstate allow - * still not asserted, we are probably stuck and going to hang - * - * TODO: Figure out why it takes ~100us on linux - * pstate takes around ~100us (up to 200us) on linux. Unknown currently - * as to why it takes that long on linux - */ - const unsigned int pstate_wait_timeout_us = 200; - const unsigned int pstate_wait_expected_timeout_us = 180; - static unsigned int max_sampled_pstate_wait_us; /* data collection */ - static bool forced_pstate_allow; /* help with revert wa */ - - unsigned int debug_data = 0; - unsigned int i; - - if (forced_pstate_allow) { - /* we hacked to force pstate allow to prevent hang last time - * we verify_allow_pstate_change_high. so disable force - * here so we can check status - */ - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0); - forced_pstate_allow = false; - } - - /* The following table only applies to DCN1 and DCN2, - * for newer DCNs, need to consult with HW IP folks to read RTL - * HUBBUB:DCHUBBUB_TEST_ARB_DEBUG10 DCHUBBUBDEBUGIND:0xB - * description - * 0: Pipe0 Plane0 Allow Pstate Change - * 1: Pipe0 Plane1 Allow Pstate Change - * 2: Pipe0 Cursor0 Allow Pstate Change - * 3: Pipe0 Cursor1 Allow Pstate Change - * 4: Pipe1 Plane0 Allow Pstate Change - * 5: Pipe1 Plane1 Allow Pstate Change - * 6: Pipe1 Cursor0 Allow Pstate Change - * 7: Pipe1 Cursor1 Allow Pstate Change - * 8: Pipe2 Plane0 Allow Pstate Change - * 9: Pipe2 Plane1 Allow Pstate Change - * 10: Pipe2 Cursor0 Allow Pstate Change - * 11: Pipe2 Cursor1 Allow Pstate Change - * 12: Pipe3 Plane0 Allow Pstate Change - * 13: Pipe3 Plane1 Allow Pstate Change - * 14: Pipe3 Cursor0 Allow Pstate Change - * 15: Pipe3 Cursor1 Allow Pstate Change - * 16: Pipe4 Plane0 Allow Pstate Change - * 17: Pipe4 Plane1 Allow Pstate Change - * 18: Pipe4 Cursor0 Allow Pstate Change - * 19: Pipe4 Cursor1 Allow Pstate Change - * 20: Pipe5 Plane0 Allow Pstate Change - * 21: Pipe5 Plane1 Allow Pstate Change - * 22: Pipe5 Cursor0 Allow Pstate Change - * 23: Pipe5 Cursor1 Allow Pstate Change - * 24: Pipe6 Plane0 Allow Pstate Change - * 25: Pipe6 Plane1 Allow Pstate Change - * 26: Pipe6 Cursor0 Allow Pstate Change - * 27: Pipe6 Cursor1 Allow Pstate Change - * 28: WB0 Allow Pstate Change - * 29: WB1 Allow Pstate Change - * 30: Arbiter's allow_pstate_change - * 31: SOC pstate change request - */ - - REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub1->debug_test_index_pstate); - - for (i = 0; i < pstate_wait_timeout_us; i++) { - debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA); - - if (debug_data & (1 << 30)) { - - if (i > pstate_wait_expected_timeout_us) - DC_LOG_WARNING("pstate took longer than expected ~%dus\n", - i); - - return true; - } - if (max_sampled_pstate_wait_us < i) - max_sampled_pstate_wait_us = i; - - udelay(1); - } - - /* force pstate allow to prevent system hang - * and break to debugger to investigate - */ - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1); - forced_pstate_allow = true; - - DC_LOG_WARNING("pstate TEST_DEBUG_DATA: 0x%X\n", - debug_data); - - return false; -} - -static uint32_t convert_and_clamp( - uint32_t wm_ns, - uint32_t refclk_mhz, - uint32_t clamp_value) -{ - uint32_t ret_val = 0; - ret_val = wm_ns * refclk_mhz; - ret_val /= 1000; - - if (ret_val > clamp_value) - ret_val = clamp_value; - - return ret_val; -} - - -void hubbub1_wm_change_req_wa(struct hubbub *hubbub) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - - REG_UPDATE_SEQ_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); -} - -bool hubbub1_program_urgent_watermarks( - struct hubbub *hubbub, - union dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - uint32_t prog_wm_value; - bool wm_pending = false; - - /* Repeat for water mark set A, B, C and D. */ - /* clock state A */ - if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) { - hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); - - DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.urgent_ns, prog_wm_value); - } else if (watermarks->a.urgent_ns < hubbub1->watermarks.a.urgent_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub1->watermarks.a.pte_meta_urgent_ns) { - hubbub1->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.pte_meta_urgent_ns, prog_wm_value); - } else if (watermarks->a.pte_meta_urgent_ns < hubbub1->watermarks.a.pte_meta_urgent_ns) - wm_pending = true; - - /* clock state B */ - if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) { - hubbub1->watermarks.b.urgent_ns = watermarks->b.urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); - - DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.urgent_ns, prog_wm_value); - } else if (watermarks->b.urgent_ns < hubbub1->watermarks.b.urgent_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->b.pte_meta_urgent_ns > hubbub1->watermarks.b.pte_meta_urgent_ns) { - hubbub1->watermarks.b.pte_meta_urgent_ns = watermarks->b.pte_meta_urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->b.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.pte_meta_urgent_ns, prog_wm_value); - } else if (watermarks->b.pte_meta_urgent_ns < hubbub1->watermarks.b.pte_meta_urgent_ns) - wm_pending = true; - - /* clock state C */ - if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) { - hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); - - DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.urgent_ns, prog_wm_value); - } else if (watermarks->c.urgent_ns < hubbub1->watermarks.c.urgent_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->c.pte_meta_urgent_ns > hubbub1->watermarks.c.pte_meta_urgent_ns) { - hubbub1->watermarks.c.pte_meta_urgent_ns = watermarks->c.pte_meta_urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->c.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.pte_meta_urgent_ns, prog_wm_value); - } else if (watermarks->c.pte_meta_urgent_ns < hubbub1->watermarks.c.pte_meta_urgent_ns) - wm_pending = true; - - /* clock state D */ - if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) { - hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); - - DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.urgent_ns, prog_wm_value); - } else if (watermarks->d.urgent_ns < hubbub1->watermarks.d.urgent_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->d.pte_meta_urgent_ns > hubbub1->watermarks.d.pte_meta_urgent_ns) { - hubbub1->watermarks.d.pte_meta_urgent_ns = watermarks->d.pte_meta_urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->d.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.pte_meta_urgent_ns, prog_wm_value); - } else if (watermarks->d.pte_meta_urgent_ns < hubbub1->watermarks.d.pte_meta_urgent_ns) - wm_pending = true; - - return wm_pending; -} - -bool hubbub1_program_stutter_watermarks( - struct hubbub *hubbub, - union dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - uint32_t prog_wm_value; - bool wm_pending = false; - - /* clock state A */ - if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns - > hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) { - hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - } else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns - < hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns - > hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) { - hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns = - watermarks->a.cstate_pstate.cstate_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); - } else if (watermarks->a.cstate_pstate.cstate_exit_ns - < hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) - wm_pending = true; - - /* clock state B */ - if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns - > hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) { - hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - } else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns - < hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns - > hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) { - hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns = - watermarks->b.cstate_pstate.cstate_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); - } else if (watermarks->b.cstate_pstate.cstate_exit_ns - < hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) - wm_pending = true; - - /* clock state C */ - if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns - > hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) { - hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - } else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns - < hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns - > hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) { - hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns = - watermarks->c.cstate_pstate.cstate_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); - } else if (watermarks->c.cstate_pstate.cstate_exit_ns - < hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) - wm_pending = true; - - /* clock state D */ - if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns - > hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) { - hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - } else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns - < hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns - > hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) { - hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns = - watermarks->d.cstate_pstate.cstate_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); - } else if (watermarks->d.cstate_pstate.cstate_exit_ns - < hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) - wm_pending = true; - - return wm_pending; -} - -bool hubbub1_program_pstate_watermarks( - struct hubbub *hubbub, - union dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - uint32_t prog_wm_value; - bool wm_pending = false; - - /* clock state A */ - if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns - > hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) { - hubbub1->watermarks.a.cstate_pstate.pstate_change_ns = - watermarks->a.cstate_pstate.pstate_change_ns; - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); - } else if (watermarks->a.cstate_pstate.pstate_change_ns - < hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) - wm_pending = true; - - /* clock state B */ - if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns - > hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) { - hubbub1->watermarks.b.cstate_pstate.pstate_change_ns = - watermarks->b.cstate_pstate.pstate_change_ns; - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); - } else if (watermarks->b.cstate_pstate.pstate_change_ns - < hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) - wm_pending = true; - - /* clock state C */ - if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns - > hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) { - hubbub1->watermarks.c.cstate_pstate.pstate_change_ns = - watermarks->c.cstate_pstate.pstate_change_ns; - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); - } else if (watermarks->c.cstate_pstate.pstate_change_ns - < hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) - wm_pending = true; - - /* clock state D */ - if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns - > hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) { - hubbub1->watermarks.d.cstate_pstate.pstate_change_ns = - watermarks->d.cstate_pstate.pstate_change_ns; - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); - } else if (watermarks->d.cstate_pstate.pstate_change_ns - < hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) - wm_pending = true; - - return wm_pending; -} - -bool hubbub1_program_watermarks( - struct hubbub *hubbub, - union dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - bool wm_pending = false; - /* - * Need to clamp to max of the register values (i.e. no wrap) - * for dcn1, all wm registers are 21-bit wide - */ - if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - if (hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - if (hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL, - DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); - REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, - DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68); - - hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); - -#if 0 - REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); -#endif - return wm_pending; -} - -void hubbub1_update_dchub( - struct hubbub *hubbub, - struct dchub_init_data *dh_data) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - - if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) { - ASSERT(false); - /*should not come here*/ - return; - } - /* TODO: port code from dal2 */ - switch (dh_data->fb_mode) { - case FRAME_BUFFER_MODE_ZFB_ONLY: - /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ - REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP, - SDPIF_FB_TOP, 0); - - REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE, - SDPIF_FB_BASE, 0x0FFFF); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_LOCAL_ONLY: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, 0); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, 0X03FFFF); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, 0); - break; - default: - break; - } - - dh_data->dchub_initialzied = true; - dh_data->dchub_info_valid = false; -} - -void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - - uint32_t watermark_change_req; - - REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req); - - if (watermark_change_req) - watermark_change_req = 0; - else - watermark_change_req = 1; - - REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); -} - -void hubbub1_soft_reset(struct hubbub *hubbub, bool reset) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - - uint32_t reset_en = reset ? 1 : 0; - - REG_UPDATE(DCHUBBUB_SOFT_RESET, - DCHUBBUB_GLOBAL_SOFT_RESET, reset_en); -} - -static bool hubbub1_dcc_support_swizzle( - enum swizzle_mode_values swizzle, - unsigned int bytes_per_element, - enum segment_order *segment_order_horz, - enum segment_order *segment_order_vert) -{ - bool standard_swizzle = false; - bool display_swizzle = false; - - switch (swizzle) { - case DC_SW_4KB_S: - case DC_SW_64KB_S: - case DC_SW_VAR_S: - case DC_SW_4KB_S_X: - case DC_SW_64KB_S_X: - case DC_SW_VAR_S_X: - standard_swizzle = true; - break; - case DC_SW_4KB_D: - case DC_SW_64KB_D: - case DC_SW_VAR_D: - case DC_SW_4KB_D_X: - case DC_SW_64KB_D_X: - case DC_SW_VAR_D_X: - display_swizzle = true; - break; - default: - break; - } - - if (bytes_per_element == 1 && standard_swizzle) { - *segment_order_horz = segment_order__contiguous; - *segment_order_vert = segment_order__na; - return true; - } - if (bytes_per_element == 2 && standard_swizzle) { - *segment_order_horz = segment_order__non_contiguous; - *segment_order_vert = segment_order__contiguous; - return true; - } - if (bytes_per_element == 4 && standard_swizzle) { - *segment_order_horz = segment_order__non_contiguous; - *segment_order_vert = segment_order__contiguous; - return true; - } - if (bytes_per_element == 8 && standard_swizzle) { - *segment_order_horz = segment_order__na; - *segment_order_vert = segment_order__contiguous; - return true; - } - if (bytes_per_element == 8 && display_swizzle) { - *segment_order_horz = segment_order__contiguous; - *segment_order_vert = segment_order__non_contiguous; - return true; - } - - return false; -} - -static bool hubbub1_dcc_support_pixel_format( - enum surface_pixel_format format, - unsigned int *bytes_per_element) -{ - /* DML: get_bytes_per_element */ - switch (format) { - case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: - case SURFACE_PIXEL_FORMAT_GRPH_RGB565: - *bytes_per_element = 2; - return true; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: - case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: - *bytes_per_element = 4; - return true; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: - *bytes_per_element = 8; - return true; - default: - return false; - } -} - -static void hubbub1_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height, - unsigned int bytes_per_element) -{ - /* copied from DML. might want to refactor DML to leverage from DML */ - /* DML : get_blk256_size */ - if (bytes_per_element == 1) { - *blk256_width = 16; - *blk256_height = 16; - } else if (bytes_per_element == 2) { - *blk256_width = 16; - *blk256_height = 8; - } else if (bytes_per_element == 4) { - *blk256_width = 8; - *blk256_height = 8; - } else if (bytes_per_element == 8) { - *blk256_width = 8; - *blk256_height = 4; - } -} - -static void hubbub1_det_request_size( - unsigned int height, - unsigned int width, - unsigned int bpe, - bool *req128_horz_wc, - bool *req128_vert_wc) -{ - unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */ - - unsigned int blk256_height = 0; - unsigned int blk256_width = 0; - unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc; - - hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe); - - swath_bytes_horz_wc = width * blk256_height * bpe; - swath_bytes_vert_wc = height * blk256_width * bpe; - - *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ? - false : /* full 256B request */ - true; /* half 128b request */ - - *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ? - false : /* full 256B request */ - true; /* half 128b request */ -} - -static bool hubbub1_get_dcc_compression_cap(struct hubbub *hubbub, - const struct dc_dcc_surface_param *input, - struct dc_surface_dcc_cap *output) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - struct dc *dc = hubbub1->base.ctx->dc; - - /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */ - enum dcc_control dcc_control; - unsigned int bpe; - enum segment_order segment_order_horz, segment_order_vert; - bool req128_horz_wc, req128_vert_wc; - - memset(output, 0, sizeof(*output)); - - if (dc->debug.disable_dcc == DCC_DISABLE) - return false; - - if (!hubbub1->base.funcs->dcc_support_pixel_format(input->format, &bpe)) - return false; - - if (!hubbub1->base.funcs->dcc_support_swizzle(input->swizzle_mode, bpe, - &segment_order_horz, &segment_order_vert)) - return false; - - hubbub1_det_request_size(input->surface_size.height, input->surface_size.width, - bpe, &req128_horz_wc, &req128_vert_wc); - - if (!req128_horz_wc && !req128_vert_wc) { - dcc_control = dcc_control__256_256_xxx; - } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) { - if (!req128_horz_wc) - dcc_control = dcc_control__256_256_xxx; - else if (segment_order_horz == segment_order__contiguous) - dcc_control = dcc_control__128_128_xxx; - else - dcc_control = dcc_control__256_64_64; - } else if (input->scan == SCAN_DIRECTION_VERTICAL) { - if (!req128_vert_wc) - dcc_control = dcc_control__256_256_xxx; - else if (segment_order_vert == segment_order__contiguous) - dcc_control = dcc_control__128_128_xxx; - else - dcc_control = dcc_control__256_64_64; - } else { - if ((req128_horz_wc && - segment_order_horz == segment_order__non_contiguous) || - (req128_vert_wc && - segment_order_vert == segment_order__non_contiguous)) - /* access_dir not known, must use most constraining */ - dcc_control = dcc_control__256_64_64; - else - /* reg128 is true for either horz and vert - * but segment_order is contiguous - */ - dcc_control = dcc_control__128_128_xxx; - } - - if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE && - dcc_control != dcc_control__256_256_xxx) - return false; - - switch (dcc_control) { - case dcc_control__256_256_xxx: - output->grph.rgb.max_uncompressed_blk_size = 256; - output->grph.rgb.max_compressed_blk_size = 256; - output->grph.rgb.independent_64b_blks = false; - break; - case dcc_control__128_128_xxx: - output->grph.rgb.max_uncompressed_blk_size = 128; - output->grph.rgb.max_compressed_blk_size = 128; - output->grph.rgb.independent_64b_blks = false; - break; - case dcc_control__256_64_64: - output->grph.rgb.max_uncompressed_blk_size = 256; - output->grph.rgb.max_compressed_blk_size = 64; - output->grph.rgb.independent_64b_blks = true; - break; - default: - ASSERT(false); - break; - } - - output->capable = true; - output->const_color_support = false; - - return true; -} - -static const struct hubbub_funcs hubbub1_funcs = { - .update_dchub = hubbub1_update_dchub, - .dcc_support_swizzle = hubbub1_dcc_support_swizzle, - .dcc_support_pixel_format = hubbub1_dcc_support_pixel_format, - .get_dcc_compression_cap = hubbub1_get_dcc_compression_cap, - .wm_read_state = hubbub1_wm_read_state, - .program_watermarks = hubbub1_program_watermarks, - .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, - .allow_self_refresh_control = hubbub1_allow_self_refresh_control, - .verify_allow_pstate_change_high = hubbub1_verify_allow_pstate_change_high, -}; - -void hubbub1_construct(struct hubbub *hubbub, - struct dc_context *ctx, - const struct dcn_hubbub_registers *hubbub_regs, - const struct dcn_hubbub_shift *hubbub_shift, - const struct dcn_hubbub_mask *hubbub_mask) -{ - struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); - - hubbub1->base.ctx = ctx; - - hubbub1->base.funcs = &hubbub1_funcs; - - hubbub1->regs = hubbub_regs; - hubbub1->shifts = hubbub_shift; - hubbub1->masks = hubbub_mask; - - hubbub1->debug_test_index_pstate = 0x7; - if (ctx->dce_version == DCN_VERSION_1_01) - hubbub1->debug_test_index_pstate = 0xB; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h deleted file mode 100644 index d1f9e63944c8..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +++ /dev/null @@ -1,463 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_HUBBUB_DCN10_H__ -#define __DC_HUBBUB_DCN10_H__ - -#include "core_types.h" -#include "dchubbub.h" - -#define TO_DCN10_HUBBUB(hubbub)\ - container_of(hubbub, struct dcn10_hubbub, base) - -#define HUBBUB_REG_LIST_DCN_COMMON()\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ - SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ - SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ - SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ - SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ - SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ - SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ - SR(DCHUBBUB_ARB_SAT_LEVEL),\ - SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ - SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ - SR(DCHUBBUB_TEST_DEBUG_INDEX), \ - SR(DCHUBBUB_TEST_DEBUG_DATA),\ - SR(DCHUBBUB_SOFT_RESET) - -#define HUBBUB_VM_REG_LIST() \ - SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\ - SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\ - SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\ - SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D) - -#define HUBBUB_SR_WATERMARK_REG_LIST()\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D) - -#define HUBBUB_REG_LIST_DCN10(id)\ - HUBBUB_REG_LIST_DCN_COMMON(), \ - HUBBUB_VM_REG_LIST(), \ - HUBBUB_SR_WATERMARK_REG_LIST(), \ - SR(DCHUBBUB_SDPIF_FB_TOP),\ - SR(DCHUBBUB_SDPIF_FB_BASE),\ - SR(DCHUBBUB_SDPIF_FB_OFFSET),\ - SR(DCHUBBUB_SDPIF_AGP_BASE),\ - SR(DCHUBBUB_SDPIF_AGP_BOT),\ - SR(DCHUBBUB_SDPIF_AGP_TOP) - -struct dcn_hubbub_registers { - uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A; - uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A; - uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A; - uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B; - uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B; - uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B; - uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C; - uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C; - uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C; - uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D; - uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D; - uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D; - uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL; - uint32_t DCHUBBUB_ARB_SAT_LEVEL; - uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND; - uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; - uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL; - uint32_t DCHUBBUB_TEST_DEBUG_INDEX; - uint32_t DCHUBBUB_TEST_DEBUG_DATA; - uint32_t DCHUBBUB_SDPIF_FB_TOP; - uint32_t DCHUBBUB_SDPIF_FB_BASE; - uint32_t DCHUBBUB_SDPIF_FB_OFFSET; - uint32_t DCHUBBUB_SDPIF_AGP_BASE; - uint32_t DCHUBBUB_SDPIF_AGP_BOT; - uint32_t DCHUBBUB_SDPIF_AGP_TOP; - uint32_t DCHUBBUB_CRC_CTRL; - uint32_t DCHUBBUB_SOFT_RESET; - uint32_t DCN_VM_FB_LOCATION_BASE; - uint32_t DCN_VM_FB_LOCATION_TOP; - uint32_t DCN_VM_FB_OFFSET; - uint32_t DCN_VM_AGP_BOT; - uint32_t DCN_VM_AGP_TOP; - uint32_t DCN_VM_AGP_BASE; - uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB; - uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB; - uint32_t DCN_VM_FAULT_ADDR_MSB; - uint32_t DCN_VM_FAULT_ADDR_LSB; - uint32_t DCN_VM_FAULT_CNTL; - uint32_t DCN_VM_FAULT_STATUS; - uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A; - uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B; - uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C; - uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D; - uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A; - uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B; - uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C; - uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D; - uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A; - uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B; - uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C; - uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D; - uint32_t DCHUBBUB_ARB_HOSTVM_CNTL; - uint32_t DCHVM_CTRL0; - uint32_t DCHVM_MEM_CTRL; - uint32_t DCHVM_CLK_CTRL; - uint32_t DCHVM_RIOMMU_CTRL0; - uint32_t DCHVM_RIOMMU_STAT0; - uint32_t DCHUBBUB_DET0_CTRL; - uint32_t DCHUBBUB_DET1_CTRL; - uint32_t DCHUBBUB_DET2_CTRL; - uint32_t DCHUBBUB_DET3_CTRL; - uint32_t DCHUBBUB_COMPBUF_CTRL; - uint32_t COMPBUF_RESERVED_SPACE; - uint32_t DCHUBBUB_DEBUG_CTRL_0; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C; - uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D; - uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D; - uint32_t DCHUBBUB_ARB_USR_RETRAINING_CNTL; - uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A; - uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B; - uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C; - uint32_t DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D; - uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A; - uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B; - uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C; - uint32_t DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D; - uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A; - uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B; - uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C; - uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D; - uint32_t DCHUBBUB_ARB_MALL_CNTL; - uint32_t SDPIF_REQUEST_RATE_LIMIT; - uint32_t DCHUBBUB_SDPIF_CFG0; - uint32_t DCHUBBUB_SDPIF_CFG1; - uint32_t DCHUBBUB_CLOCK_CNTL; - uint32_t DCHUBBUB_MEM_PWR_MODE_CTRL; - uint32_t DCHUBBUB_ARB_QOS_FORCE; -}; - -#define HUBBUB_REG_FIELD_LIST_DCN32(type) \ - type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE;\ - type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE;\ - type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST;\ - type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE;\ - type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A;\ - type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B;\ - type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C;\ - type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D;\ - type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A;\ - type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B;\ - type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C;\ - type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D;\ - type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A;\ - type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;\ - type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;\ - type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;\ - type MALL_PREFETCH_COMPLETE;\ - type MALL_IN_USE - - #define HUBBUB_REG_FIELD_LIST_DCN35(type) \ - type DCHUBBUB_FGCG_REP_DIS;\ - type DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE - -/* set field name */ -#define HUBBUB_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix - -#define HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh)\ - HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ - HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh) - -#define HUBBUB_MASK_SH_LIST_STUTTER(mask_sh) \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, mask_sh) - -#define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\ - HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ - HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ - HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \ - HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ - HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ - HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ - HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ - HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh) - -#define DCN_HUBBUB_REG_FIELD_LIST(type) \ - type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ - type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\ - type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\ - type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\ - type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\ - type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\ - type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\ - type DCHUBBUB_ARB_SAT_LEVEL;\ - type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\ - type DCHUBBUB_GLOBAL_TIMER_REFDIV;\ - type DCHUBBUB_GLOBAL_SOFT_RESET; \ - type SDPIF_FB_TOP;\ - type SDPIF_FB_BASE;\ - type SDPIF_FB_OFFSET;\ - type SDPIF_AGP_BASE;\ - type SDPIF_AGP_BOT;\ - type SDPIF_AGP_TOP;\ - type FB_BASE;\ - type FB_TOP;\ - type FB_OFFSET;\ - type AGP_BOT;\ - type AGP_TOP;\ - type AGP_BASE;\ - type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;\ - type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;\ - type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;\ - type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;\ - type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\ - type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\ - type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ - type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ - type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\ - type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\ - type DCN_VM_FAULT_ADDR_MSB;\ - type DCN_VM_FAULT_ADDR_LSB;\ - type DCN_VM_ERROR_STATUS_CLEAR;\ - type DCN_VM_ERROR_STATUS_MODE;\ - type DCN_VM_ERROR_INTERRUPT_ENABLE;\ - type DCN_VM_RANGE_FAULT_DISABLE;\ - type DCN_VM_PRQ_FAULT_DISABLE;\ - type DCN_VM_ERROR_STATUS;\ - type DCN_VM_ERROR_VMID;\ - type DCN_VM_ERROR_TABLE_LEVEL;\ - type DCN_VM_ERROR_PIPE;\ - type DCN_VM_ERROR_INTERRUPT_STATUS - -#define HUBBUB_STUTTER_REG_FIELD_LIST(type) \ - type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\ - type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;\ - type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;\ - type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;\ - type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;\ - type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;\ - type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\ - type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D - -#define HUBBUB_HVM_REG_FIELD_LIST(type) \ - type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\ - type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\ - type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\ - type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\ - type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ - type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ - type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\ - type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\ - type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\ - type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\ - type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\ - type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\ - type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\ - type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\ - type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\ - type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\ - type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\ - type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\ - type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\ - type HOSTVM_INIT_REQ; \ - type HVM_GPUVMRET_PWR_REQ_DIS; \ - type HVM_GPUVMRET_FORCE_REQ; \ - type HVM_GPUVMRET_POWER_STATUS; \ - type HVM_DISPCLK_R_GATE_DIS; \ - type HVM_DISPCLK_G_GATE_DIS; \ - type HVM_DCFCLK_R_GATE_DIS; \ - type HVM_DCFCLK_G_GATE_DIS; \ - type TR_REQ_REQCLKREQ_MODE; \ - type TW_RSP_COMPCLKREQ_MODE; \ - type HOSTVM_PREFETCH_REQ; \ - type HOSTVM_POWERSTATUS; \ - type RIOMMU_ACTIVE; \ - type HOSTVM_PREFETCH_DONE - -#define HUBBUB_RET_REG_FIELD_LIST(type) \ - type DET_DEPTH;\ - type DET0_SIZE;\ - type DET1_SIZE;\ - type DET2_SIZE;\ - type DET3_SIZE;\ - type DET0_SIZE_CURRENT;\ - type DET1_SIZE_CURRENT;\ - type DET2_SIZE_CURRENT;\ - type DET3_SIZE_CURRENT;\ - type COMPBUF_SIZE;\ - type COMPBUF_SIZE_CURRENT;\ - type CONFIG_ERROR;\ - type COMPBUF_RESERVED_SPACE_64B;\ - type COMPBUF_RESERVED_SPACE_ZS;\ - type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;\ - type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;\ - type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;\ - type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;\ - type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;\ - type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\ - type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\ - type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;\ - type SDPIF_REQUEST_RATE_LIMIT;\ - type DISPCLK_R_DCHUBBUB_GATE_DIS;\ - type DCFCLK_R_DCHUBBUB_GATE_DIS;\ - type SDPIF_MAX_NUM_OUTSTANDING;\ - type DCHUBBUB_ARB_MAX_REQ_OUTSTAND;\ - type SDPIF_PORT_CONTROL;\ - type DET_MEM_PWR_LS_MODE - - -struct dcn_hubbub_shift { - DCN_HUBBUB_REG_FIELD_LIST(uint8_t); - HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); - HUBBUB_HVM_REG_FIELD_LIST(uint8_t); - HUBBUB_RET_REG_FIELD_LIST(uint8_t); - HUBBUB_REG_FIELD_LIST_DCN32(uint8_t); - HUBBUB_REG_FIELD_LIST_DCN35(uint8_t); -}; - -struct dcn_hubbub_mask { - DCN_HUBBUB_REG_FIELD_LIST(uint32_t); - HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t); - HUBBUB_HVM_REG_FIELD_LIST(uint32_t); - HUBBUB_RET_REG_FIELD_LIST(uint32_t); - HUBBUB_REG_FIELD_LIST_DCN32(uint32_t); - HUBBUB_REG_FIELD_LIST_DCN35(uint32_t); -}; - -struct dc; - -struct dcn10_hubbub { - struct hubbub base; - const struct dcn_hubbub_registers *regs; - const struct dcn_hubbub_shift *shifts; - const struct dcn_hubbub_mask *masks; - unsigned int debug_test_index_pstate; - union dcn_watermark_set watermarks; -}; - -void hubbub1_update_dchub( - struct hubbub *hubbub, - struct dchub_init_data *dh_data); - -bool hubbub1_verify_allow_pstate_change_high( - struct hubbub *hubbub); - -void hubbub1_wm_change_req_wa(struct hubbub *hubbub); - -bool hubbub1_program_watermarks( - struct hubbub *hubbub, - union dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower); - -void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow); - -bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub); - -void hubbub1_toggle_watermark_change_req( - struct hubbub *hubbub); - -void hubbub1_wm_read_state(struct hubbub *hubbub, - struct dcn_hubbub_wm *wm); - -void hubbub1_soft_reset(struct hubbub *hubbub, bool reset); -void hubbub1_construct(struct hubbub *hubbub, - struct dc_context *ctx, - const struct dcn_hubbub_registers *hubbub_regs, - const struct dcn_hubbub_shift *hubbub_shift, - const struct dcn_hubbub_mask *hubbub_mask); - -bool hubbub1_program_urgent_watermarks( - struct hubbub *hubbub, - union dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower); -bool hubbub1_program_stutter_watermarks( - struct hubbub *hubbub, - union dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower); -bool hubbub1_program_pstate_watermarks( - struct hubbub *hubbub, - union dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c deleted file mode 100644 index bf399819ca80..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ /dev/null @@ -1,1396 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ -#include "dm_services.h" -#include "dce_calcs.h" -#include "reg_helper.h" -#include "basics/conversion.h" -#include "dcn10_hubp.h" - -#define REG(reg)\ - hubp1->hubp_regs->reg - -#define CTX \ - hubp1->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name - -void hubp1_set_blank(struct hubp *hubp, bool blank) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - uint32_t blank_en = blank ? 1 : 0; - - REG_UPDATE_2(DCHUBP_CNTL, - HUBP_BLANK_EN, blank_en, - HUBP_TTU_DISABLE, blank_en); - - if (blank) { - uint32_t reg_val = REG_READ(DCHUBP_CNTL); - - if (reg_val) { - /* init sequence workaround: in case HUBP is - * power gated, this wait would timeout. - * - * we just wrote reg_val to non-0, if it stay 0 - * it means HUBP is gated - */ - REG_WAIT(DCHUBP_CNTL, - HUBP_NO_OUTSTANDING_REQ, 1, - 1, 200); - } - - hubp->mpcc_id = 0xf; - hubp->opp_id = OPP_ID_INVALID; - } -} - -static void hubp1_disconnect(struct hubp *hubp) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_UPDATE(DCHUBP_CNTL, - HUBP_TTU_DISABLE, 1); - - REG_UPDATE(CURSOR_CONTROL, - CURSOR_ENABLE, 0); -} - -static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - uint32_t disable = disable_hubp ? 1 : 0; - - REG_UPDATE(DCHUBP_CNTL, - HUBP_DISABLE, disable); -} - -static unsigned int hubp1_get_underflow_status(struct hubp *hubp) -{ - uint32_t hubp_underflow = 0; - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_GET(DCHUBP_CNTL, - HUBP_UNDERFLOW_STATUS, - &hubp_underflow); - - return hubp_underflow; -} - - -void hubp1_clear_underflow(struct hubp *hubp) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); -} - -static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - uint32_t blank_en = blank ? 1 : 0; - - REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); -} - -void hubp1_vready_workaround(struct hubp *hubp, - struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) -{ - uint32_t value = 0; - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - /* set HBUBREQ_DEBUG_DB[12] = 1 */ - value = REG_READ(HUBPREQ_DEBUG_DB); - - /* hack mode disable */ - value |= 0x100; - value &= ~0x1000; - - if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width - + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { - /* if (eco_fix_needed(otg_global_sync_timing) - * set HBUBREQ_DEBUG_DB[12] = 1 */ - value |= 0x1000; - } - - REG_WRITE(HUBPREQ_DEBUG_DB, value); -} - -void hubp1_program_tiling( - struct hubp *hubp, - const union dc_tiling_info *info, - const enum surface_pixel_format pixel_format) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_UPDATE_6(DCSURF_ADDR_CONFIG, - NUM_PIPES, log_2(info->gfx9.num_pipes), - NUM_BANKS, log_2(info->gfx9.num_banks), - PIPE_INTERLEAVE, info->gfx9.pipe_interleave, - NUM_SE, log_2(info->gfx9.num_shader_engines), - NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), - MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); - - REG_UPDATE_4(DCSURF_TILING_CONFIG, - SW_MODE, info->gfx9.swizzle, - META_LINEAR, info->gfx9.meta_linear, - RB_ALIGNED, info->gfx9.rb_aligned, - PIPE_ALIGNED, info->gfx9.pipe_aligned); -} - -void hubp1_program_size( - struct hubp *hubp, - enum surface_pixel_format format, - const struct plane_size *plane_size, - struct dc_plane_dcc_param *dcc) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; - - /* Program data and meta surface pitch (calculation from addrlib) - * 444 or 420 luma - */ - if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { - ASSERT(plane_size->chroma_pitch != 0); - /* Chroma pitch zero can cause system hang! */ - - pitch = plane_size->surface_pitch - 1; - meta_pitch = dcc->meta_pitch - 1; - pitch_c = plane_size->chroma_pitch - 1; - meta_pitch_c = dcc->meta_pitch_c - 1; - } else { - pitch = plane_size->surface_pitch - 1; - meta_pitch = dcc->meta_pitch - 1; - pitch_c = 0; - meta_pitch_c = 0; - } - - if (!dcc->enable) { - meta_pitch = 0; - meta_pitch_c = 0; - } - - REG_UPDATE_2(DCSURF_SURFACE_PITCH, - PITCH, pitch, META_PITCH, meta_pitch); - - if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) - REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, - PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); -} - -void hubp1_program_rotation( - struct hubp *hubp, - enum dc_rotation_angle rotation, - bool horizontal_mirror) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - uint32_t mirror; - - - if (horizontal_mirror) - mirror = 1; - else - mirror = 0; - - /* Program rotation angle and horz mirror - no mirror */ - if (rotation == ROTATION_ANGLE_0) - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - ROTATION_ANGLE, 0, - H_MIRROR_EN, mirror); - else if (rotation == ROTATION_ANGLE_90) - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - ROTATION_ANGLE, 1, - H_MIRROR_EN, mirror); - else if (rotation == ROTATION_ANGLE_180) - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - ROTATION_ANGLE, 2, - H_MIRROR_EN, mirror); - else if (rotation == ROTATION_ANGLE_270) - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - ROTATION_ANGLE, 3, - H_MIRROR_EN, mirror); -} - -void hubp1_program_pixel_format( - struct hubp *hubp, - enum surface_pixel_format format) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - uint32_t red_bar = 3; - uint32_t blue_bar = 2; - - /* swap for ABGR format */ - if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { - red_bar = 2; - blue_bar = 3; - } - - REG_UPDATE_2(HUBPRET_CONTROL, - CROSSBAR_SRC_CB_B, blue_bar, - CROSSBAR_SRC_CR_R, red_bar); - - /* Mapping is same as ipp programming (cnvc) */ - - switch (format) { - case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 1); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB565: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 3); - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 8); - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 10); - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 24); - break; - - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 65); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 64); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 67); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 66); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 12); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 112); - break; - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 113); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 114); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 118); - break; - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 119); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGBE: - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 116, - ALPHA_PLANE_EN, 0); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 116, - ALPHA_PLANE_EN, 1); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - /* don't see the need of program the xbar in DCN 1.0 */ -} - -bool hubp1_program_surface_flip_and_addr( - struct hubp *hubp, - const struct dc_plane_address *address, - bool flip_immediate) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - - //program flip type - REG_UPDATE(DCSURF_FLIP_CONTROL, - SURFACE_FLIP_TYPE, flip_immediate); - - - if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { - REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); - REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); - - } else { - // turn off stereo if not in stereo - REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); - REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); - } - - - - /* HW automatically latch rest of address register on write to - * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used - * - * program high first and then the low addr, order matters! - */ - switch (address->type) { - case PLN_ADDR_TYPE_GRAPHICS: - /* DCN1.0 does not support const color - * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 - * base on address->grph.dcc_const_color - * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma - * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma - */ - - if (address->grph.addr.quad_part == 0) - break; - - REG_UPDATE_2(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_TMZ, address->tmz_surface, - PRIMARY_META_SURFACE_TMZ, address->tmz_surface); - - if (address->grph.meta_addr.quad_part != 0) { - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_META_SURFACE_ADDRESS_HIGH, - address->grph.meta_addr.high_part); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, - PRIMARY_META_SURFACE_ADDRESS, - address->grph.meta_addr.low_part); - } - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_SURFACE_ADDRESS_HIGH, - address->grph.addr.high_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, - PRIMARY_SURFACE_ADDRESS, - address->grph.addr.low_part); - break; - case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: - if (address->video_progressive.luma_addr.quad_part == 0 - || address->video_progressive.chroma_addr.quad_part == 0) - break; - - REG_UPDATE_4(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_TMZ, address->tmz_surface, - PRIMARY_SURFACE_TMZ_C, address->tmz_surface, - PRIMARY_META_SURFACE_TMZ, address->tmz_surface, - PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); - - if (address->video_progressive.luma_meta_addr.quad_part != 0) { - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, - PRIMARY_META_SURFACE_ADDRESS_HIGH_C, - address->video_progressive.chroma_meta_addr.high_part); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, - PRIMARY_META_SURFACE_ADDRESS_C, - address->video_progressive.chroma_meta_addr.low_part); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_META_SURFACE_ADDRESS_HIGH, - address->video_progressive.luma_meta_addr.high_part); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, - PRIMARY_META_SURFACE_ADDRESS, - address->video_progressive.luma_meta_addr.low_part); - } - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, - PRIMARY_SURFACE_ADDRESS_HIGH_C, - address->video_progressive.chroma_addr.high_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, - PRIMARY_SURFACE_ADDRESS_C, - address->video_progressive.chroma_addr.low_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_SURFACE_ADDRESS_HIGH, - address->video_progressive.luma_addr.high_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, - PRIMARY_SURFACE_ADDRESS, - address->video_progressive.luma_addr.low_part); - break; - case PLN_ADDR_TYPE_GRPH_STEREO: - if (address->grph_stereo.left_addr.quad_part == 0) - break; - if (address->grph_stereo.right_addr.quad_part == 0) - break; - - REG_UPDATE_8(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_TMZ, address->tmz_surface, - PRIMARY_SURFACE_TMZ_C, address->tmz_surface, - PRIMARY_META_SURFACE_TMZ, address->tmz_surface, - PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, - SECONDARY_SURFACE_TMZ, address->tmz_surface, - SECONDARY_SURFACE_TMZ_C, address->tmz_surface, - SECONDARY_META_SURFACE_TMZ, address->tmz_surface, - SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); - - if (address->grph_stereo.right_meta_addr.quad_part != 0) { - - REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, - SECONDARY_META_SURFACE_ADDRESS_HIGH, - address->grph_stereo.right_meta_addr.high_part); - - REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, - SECONDARY_META_SURFACE_ADDRESS, - address->grph_stereo.right_meta_addr.low_part); - } - if (address->grph_stereo.left_meta_addr.quad_part != 0) { - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_META_SURFACE_ADDRESS_HIGH, - address->grph_stereo.left_meta_addr.high_part); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, - PRIMARY_META_SURFACE_ADDRESS, - address->grph_stereo.left_meta_addr.low_part); - } - - REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, - SECONDARY_SURFACE_ADDRESS_HIGH, - address->grph_stereo.right_addr.high_part); - - REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, - SECONDARY_SURFACE_ADDRESS, - address->grph_stereo.right_addr.low_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_SURFACE_ADDRESS_HIGH, - address->grph_stereo.left_addr.high_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, - PRIMARY_SURFACE_ADDRESS, - address->grph_stereo.left_addr.low_part); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - hubp->request_address = *address; - - return true; -} - -void hubp1_dcc_control(struct hubp *hubp, bool enable, - enum hubp_ind_block_size independent_64b_blks) -{ - uint32_t dcc_en = enable ? 1 : 0; - uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_UPDATE_4(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_DCC_EN, dcc_en, - PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, - SECONDARY_SURFACE_DCC_EN, dcc_en, - SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); -} - -void hubp1_program_surface_config( - struct hubp *hubp, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - struct plane_size *plane_size, - enum dc_rotation_angle rotation, - struct dc_plane_dcc_param *dcc, - bool horizontal_mirror, - unsigned int compat_level) -{ - hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); - hubp1_program_tiling(hubp, tiling_info, format); - hubp1_program_size(hubp, format, plane_size, dcc); - hubp1_program_rotation(hubp, rotation, horizontal_mirror); - hubp1_program_pixel_format(hubp, format); -} - -void hubp1_program_requestor( - struct hubp *hubp, - struct _vcs_dpi_display_rq_regs_st *rq_regs) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_UPDATE(HUBPRET_CONTROL, - DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); - REG_SET_4(DCN_EXPANSION_MODE, 0, - DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, - PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, - MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, - CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); - REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, - CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, - MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, - META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, - MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, - DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, - MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, - SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, - PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); - REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, - CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, - MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, - META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, - MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, - DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, - MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, - SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, - PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); -} - - -void hubp1_program_deadline( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - /* DLG - Per hubp */ - REG_SET_2(BLANK_OFFSET_0, 0, - REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, - DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); - - REG_SET(BLANK_OFFSET_1, 0, - MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); - - REG_SET(DST_DIMENSIONS, 0, - REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); - - REG_SET_2(DST_AFTER_SCALER, 0, - REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, - DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); - - REG_SET(REF_FREQ_TO_PIX_FREQ, 0, - REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); - - /* DLG - Per luma/chroma */ - REG_SET(VBLANK_PARAMETERS_1, 0, - REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); - - if (REG(NOM_PARAMETERS_0)) - REG_SET(NOM_PARAMETERS_0, 0, - DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); - - if (REG(NOM_PARAMETERS_1)) - REG_SET(NOM_PARAMETERS_1, 0, - REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); - - REG_SET(NOM_PARAMETERS_4, 0, - DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); - - REG_SET(NOM_PARAMETERS_5, 0, - REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); - - REG_SET_2(PER_LINE_DELIVERY, 0, - REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, - REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); - - REG_SET(VBLANK_PARAMETERS_2, 0, - REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); - - if (REG(NOM_PARAMETERS_2)) - REG_SET(NOM_PARAMETERS_2, 0, - DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); - - if (REG(NOM_PARAMETERS_3)) - REG_SET(NOM_PARAMETERS_3, 0, - REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); - - REG_SET(NOM_PARAMETERS_6, 0, - DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); - - REG_SET(NOM_PARAMETERS_7, 0, - REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); - - /* TTU - per hubp */ - REG_SET_2(DCN_TTU_QOS_WM, 0, - QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, - QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); - - /* TTU - per luma/chroma */ - /* Assumed surf0 is luma and 1 is chroma */ - - REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, - REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, - QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, - QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); - - REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, - REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, - QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, - QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); - - REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, - REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, - QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, - QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); -} - -static void hubp1_setup( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr, - struct _vcs_dpi_display_rq_regs_st *rq_regs, - struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) -{ - /* otg is locked when this func is called. Register are double buffered. - * disable the requestors is not needed - */ - hubp1_program_requestor(hubp, rq_regs); - hubp1_program_deadline(hubp, dlg_attr, ttu_attr); - hubp1_vready_workaround(hubp, pipe_dest); -} - -static void hubp1_setup_interdependent( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_SET_2(PREFETCH_SETTINS, 0, - DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, - VRATIO_PREFETCH, dlg_attr->vratio_prefetch); - - REG_SET(PREFETCH_SETTINS_C, 0, - VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); - - REG_SET_2(VBLANK_PARAMETERS_0, 0, - DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, - DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); - - REG_SET(VBLANK_PARAMETERS_3, 0, - REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); - - REG_SET(VBLANK_PARAMETERS_4, 0, - REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); - - REG_SET_2(PER_LINE_DELIVERY_PRE, 0, - REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, - REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); - - REG_SET(DCN_SURF0_TTU_CNTL1, 0, - REFCYC_PER_REQ_DELIVERY_PRE, - ttu_attr->refcyc_per_req_delivery_pre_l); - REG_SET(DCN_SURF1_TTU_CNTL1, 0, - REFCYC_PER_REQ_DELIVERY_PRE, - ttu_attr->refcyc_per_req_delivery_pre_c); - REG_SET(DCN_CUR0_TTU_CNTL1, 0, - REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); - - REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, - MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, - QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); -} - -bool hubp1_is_flip_pending(struct hubp *hubp) -{ - uint32_t flip_pending = 0; - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - struct dc_plane_address earliest_inuse_address; - - if (hubp && hubp->power_gated) - return false; - - REG_GET(DCSURF_FLIP_CONTROL, - SURFACE_FLIP_PENDING, &flip_pending); - - REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, - SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); - - REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, - SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); - - if (flip_pending) - return true; - - if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) - return true; - - return false; -} - -static uint32_t aperture_default_system = 1; -static uint32_t context0_default_system; /* = 0;*/ - -static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, - struct vm_system_aperture_param *apt) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - PHYSICAL_ADDRESS_LOC mc_vm_apt_default; - PHYSICAL_ADDRESS_LOC mc_vm_apt_low; - PHYSICAL_ADDRESS_LOC mc_vm_apt_high; - - mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; - mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12; - mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12; - - REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, - MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */ - MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); - REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, - MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); - - REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, - MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part); - REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, - MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part); - - REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part); - REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part); -} - -static void hubp1_set_vm_context0_settings(struct hubp *hubp, - const struct vm_context0_param *vm0) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - /* pte base */ - REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0, - VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part); - REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0, - VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part); - - /* pte start */ - REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0, - VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part); - REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0, - VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part); - - /* pte end */ - REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0, - VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part); - REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0, - VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part); - - /* fault handling */ - REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, - VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part, - VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system); - REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, - VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); - - /* control: enable VM PTE*/ - REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, - ENABLE_L1_TLB, 1, - SYSTEM_ACCESS_MODE, 3); -} - -void min_set_viewport( - struct hubp *hubp, - const struct rect *viewport, - const struct rect *viewport_c) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, - PRI_VIEWPORT_WIDTH, viewport->width, - PRI_VIEWPORT_HEIGHT, viewport->height); - - REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, - PRI_VIEWPORT_X_START, viewport->x, - PRI_VIEWPORT_Y_START, viewport->y); - - /*for stereo*/ - REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, - SEC_VIEWPORT_WIDTH, viewport->width, - SEC_VIEWPORT_HEIGHT, viewport->height); - - REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, - SEC_VIEWPORT_X_START, viewport->x, - SEC_VIEWPORT_Y_START, viewport->y); - - /* DC supports NV12 only at the moment */ - REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, - PRI_VIEWPORT_WIDTH_C, viewport_c->width, - PRI_VIEWPORT_HEIGHT_C, viewport_c->height); - - REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, - PRI_VIEWPORT_X_START_C, viewport_c->x, - PRI_VIEWPORT_Y_START_C, viewport_c->y); - - REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, - SEC_VIEWPORT_WIDTH_C, viewport_c->width, - SEC_VIEWPORT_HEIGHT_C, viewport_c->height); - - REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, - SEC_VIEWPORT_X_START_C, viewport_c->x, - SEC_VIEWPORT_Y_START_C, viewport_c->y); -} - -void hubp1_read_state_common(struct hubp *hubp) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - struct dcn_hubp_state *s = &hubp1->state; - struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; - struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; - struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; - uint32_t aperture_low_msb, aperture_low_lsb; - uint32_t aperture_high_msb, aperture_high_lsb; - - /* Requester */ - REG_GET(HUBPRET_CONTROL, - DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); - REG_GET_4(DCN_EXPANSION_MODE, - DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, - PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, - MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, - CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); - - REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, - MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, &aperture_low_msb); - - REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, - MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, &aperture_low_lsb); - - REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, &aperture_high_msb); - - REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, &aperture_high_lsb); - - // On DCN1, aperture is broken down into MSB and LSB; only keep bits [47:18] to match later DCN format - rq_regs->aperture_low_addr = (aperture_low_msb << 26) | (aperture_low_lsb >> 6); - rq_regs->aperture_high_addr = (aperture_high_msb << 26) | (aperture_high_lsb >> 6); - - /* DLG - Per hubp */ - REG_GET_2(BLANK_OFFSET_0, - REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, - DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); - - REG_GET(BLANK_OFFSET_1, - MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); - - REG_GET(DST_DIMENSIONS, - REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); - - REG_GET_2(DST_AFTER_SCALER, - REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, - DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); - - if (REG(PREFETCH_SETTINS)) - REG_GET_2(PREFETCH_SETTINS, - DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, - VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); - else - REG_GET_2(PREFETCH_SETTINGS, - DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, - VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); - - REG_GET_2(VBLANK_PARAMETERS_0, - DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, - DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); - - REG_GET(REF_FREQ_TO_PIX_FREQ, - REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); - - /* DLG - Per luma/chroma */ - REG_GET(VBLANK_PARAMETERS_1, - REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); - - REG_GET(VBLANK_PARAMETERS_3, - REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); - - if (REG(NOM_PARAMETERS_0)) - REG_GET(NOM_PARAMETERS_0, - DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); - - if (REG(NOM_PARAMETERS_1)) - REG_GET(NOM_PARAMETERS_1, - REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); - - REG_GET(NOM_PARAMETERS_4, - DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); - - REG_GET(NOM_PARAMETERS_5, - REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); - - REG_GET_2(PER_LINE_DELIVERY_PRE, - REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, - REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); - - REG_GET_2(PER_LINE_DELIVERY, - REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, - REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); - - if (REG(PREFETCH_SETTINS_C)) - REG_GET(PREFETCH_SETTINS_C, - VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); - else - REG_GET(PREFETCH_SETTINGS_C, - VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); - - REG_GET(VBLANK_PARAMETERS_2, - REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); - - REG_GET(VBLANK_PARAMETERS_4, - REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); - - if (REG(NOM_PARAMETERS_2)) - REG_GET(NOM_PARAMETERS_2, - DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); - - if (REG(NOM_PARAMETERS_3)) - REG_GET(NOM_PARAMETERS_3, - REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); - - REG_GET(NOM_PARAMETERS_6, - DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); - - REG_GET(NOM_PARAMETERS_7, - REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); - - /* TTU - per hubp */ - REG_GET_2(DCN_TTU_QOS_WM, - QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, - QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); - - REG_GET_2(DCN_GLOBAL_TTU_CNTL, - MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, - QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); - - /* TTU - per luma/chroma */ - /* Assumed surf0 is luma and 1 is chroma */ - - REG_GET_3(DCN_SURF0_TTU_CNTL0, - REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, - QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, - QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); - - REG_GET(DCN_SURF0_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, - &ttu_attr->refcyc_per_req_delivery_pre_l); - - REG_GET_3(DCN_SURF1_TTU_CNTL0, - REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, - QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, - QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); - - REG_GET(DCN_SURF1_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, - &ttu_attr->refcyc_per_req_delivery_pre_c); - - /* Rest of hubp */ - REG_GET(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, &s->pixel_format); - - REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, - SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); - - REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, - SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); - - REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, - PRI_VIEWPORT_WIDTH, &s->viewport_width, - PRI_VIEWPORT_HEIGHT, &s->viewport_height); - - REG_GET_2(DCSURF_SURFACE_CONFIG, - ROTATION_ANGLE, &s->rotation_angle, - H_MIRROR_EN, &s->h_mirror_en); - - REG_GET(DCSURF_TILING_CONFIG, - SW_MODE, &s->sw_mode); - - REG_GET(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_DCC_EN, &s->dcc_en); - - REG_GET_3(DCHUBP_CNTL, - HUBP_BLANK_EN, &s->blank_en, - HUBP_TTU_DISABLE, &s->ttu_disable, - HUBP_UNDERFLOW_STATUS, &s->underflow_status); - - REG_GET(HUBP_CLK_CNTL, - HUBP_CLOCK_ENABLE, &s->clock_en); - - REG_GET(DCN_GLOBAL_TTU_CNTL, - MIN_TTU_VBLANK, &s->min_ttu_vblank); - - REG_GET_2(DCN_TTU_QOS_WM, - QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, - QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); - - REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, - PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); - - REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, - PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); - - REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, - PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo); - - REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, - PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi); -} - -void hubp1_read_state(struct hubp *hubp) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - struct dcn_hubp_state *s = &hubp1->state; - struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; - - hubp1_read_state_common(hubp); - - REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, - CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, - MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, - META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, - MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, - DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, - MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, - SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, - PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); - - REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, - CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, - MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, - META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, - MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, - DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, - MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, - SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, - PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); - -} -enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) -{ - enum cursor_pitch hw_pitch; - - switch (pitch) { - case 64: - hw_pitch = CURSOR_PITCH_64_PIXELS; - break; - case 128: - hw_pitch = CURSOR_PITCH_128_PIXELS; - break; - case 256: - hw_pitch = CURSOR_PITCH_256_PIXELS; - break; - default: - DC_ERR("Invalid cursor pitch of %d. " - "Only 64/128/256 is supported on DCN.\n", pitch); - hw_pitch = CURSOR_PITCH_64_PIXELS; - break; - } - return hw_pitch; -} - -static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk( - unsigned int cur_width, - enum dc_cursor_color_format format) -{ - enum cursor_lines_per_chunk line_per_chunk; - - if (format == CURSOR_MODE_MONO) - /* impl B. expansion in CUR Buffer reader */ - line_per_chunk = CURSOR_LINE_PER_CHUNK_16; - else if (cur_width <= 32) - line_per_chunk = CURSOR_LINE_PER_CHUNK_16; - else if (cur_width <= 64) - line_per_chunk = CURSOR_LINE_PER_CHUNK_8; - else if (cur_width <= 128) - line_per_chunk = CURSOR_LINE_PER_CHUNK_4; - else - line_per_chunk = CURSOR_LINE_PER_CHUNK_2; - - return line_per_chunk; -} - -void hubp1_cursor_set_attributes( - struct hubp *hubp, - const struct dc_cursor_attributes *attr) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); - enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk( - attr->width, attr->color_format); - - hubp->curs_attr = *attr; - - REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, - CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); - REG_UPDATE(CURSOR_SURFACE_ADDRESS, - CURSOR_SURFACE_ADDRESS, attr->address.low_part); - - REG_UPDATE_2(CURSOR_SIZE, - CURSOR_WIDTH, attr->width, - CURSOR_HEIGHT, attr->height); - - REG_UPDATE_3(CURSOR_CONTROL, - CURSOR_MODE, attr->color_format, - CURSOR_PITCH, hw_pitch, - CURSOR_LINES_PER_CHUNK, lpc); - - REG_SET_2(CURSOR_SETTINS, 0, - /* no shift of the cursor HDL schedule */ - CURSOR0_DST_Y_OFFSET, 0, - /* used to shift the cursor chunk request deadline */ - CURSOR0_CHUNK_HDL_ADJUST, 3); -} - -void hubp1_cursor_set_position( - struct hubp *hubp, - const struct dc_cursor_position *pos, - const struct dc_cursor_mi_param *param) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - int x_pos = pos->x - param->viewport.x; - int y_pos = pos->y - param->viewport.y; - int x_hotspot = pos->x_hotspot; - int y_hotspot = pos->y_hotspot; - int src_x_offset = x_pos - pos->x_hotspot; - int src_y_offset = y_pos - pos->y_hotspot; - int cursor_height = (int)hubp->curs_attr.height; - int cursor_width = (int)hubp->curs_attr.width; - uint32_t dst_x_offset; - uint32_t cur_en = pos->enable ? 1 : 0; - - hubp->curs_pos = *pos; - - /* - * Guard aganst cursor_set_position() from being called with invalid - * attributes - * - * TODO: Look at combining cursor_set_position() and - * cursor_set_attributes() into cursor_update() - */ - if (hubp->curs_attr.address.quad_part == 0) - return; - - // Transform cursor width / height and hotspots for offset calculations - if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { - swap(cursor_height, cursor_width); - swap(x_hotspot, y_hotspot); - - if (param->rotation == ROTATION_ANGLE_90) { - // hotspot = (-y, x) - src_x_offset = x_pos - (cursor_width - x_hotspot); - src_y_offset = y_pos - y_hotspot; - } else if (param->rotation == ROTATION_ANGLE_270) { - // hotspot = (y, -x) - src_x_offset = x_pos - x_hotspot; - src_y_offset = y_pos - (cursor_height - y_hotspot); - } - } else if (param->rotation == ROTATION_ANGLE_180) { - // hotspot = (-x, -y) - if (!param->mirror) - src_x_offset = x_pos - (cursor_width - x_hotspot); - - src_y_offset = y_pos - (cursor_height - y_hotspot); - } - - dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; - dst_x_offset *= param->ref_clk_khz; - dst_x_offset /= param->pixel_clk_khz; - - ASSERT(param->h_scale_ratio.value); - - if (param->h_scale_ratio.value) - dst_x_offset = dc_fixpt_floor(dc_fixpt_div( - dc_fixpt_from_int(dst_x_offset), - param->h_scale_ratio)); - - if (src_x_offset >= (int)param->viewport.width) - cur_en = 0; /* not visible beyond right edge*/ - - if (src_x_offset + cursor_width <= 0) - cur_en = 0; /* not visible beyond left edge*/ - - if (src_y_offset >= (int)param->viewport.height) - cur_en = 0; /* not visible beyond bottom edge*/ - - if (src_y_offset + cursor_height <= 0) - cur_en = 0; /* not visible beyond top edge*/ - - if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) - hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); - - REG_UPDATE(CURSOR_CONTROL, - CURSOR_ENABLE, cur_en); - - REG_SET_2(CURSOR_POSITION, 0, - CURSOR_X_POSITION, pos->x, - CURSOR_Y_POSITION, pos->y); - - REG_SET_2(CURSOR_HOT_SPOT, 0, - CURSOR_HOT_SPOT_X, pos->x_hotspot, - CURSOR_HOT_SPOT_Y, pos->y_hotspot); - - REG_SET(CURSOR_DST_OFFSET, 0, - CURSOR_DST_X_OFFSET, dst_x_offset); - /* TODO Handle surface pixel formats other than 4:4:4 */ -} - -/** - * hubp1_clk_cntl - Disable or enable clocks for DCHUBP - * - * @hubp: hubp struct reference. - * @enable: Set true for enabling gate clock. - * - * When enabling/disabling DCHUBP clock, we affect dcfclk/dppclk. - */ -void hubp1_clk_cntl(struct hubp *hubp, bool enable) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - uint32_t clk_enable = enable ? 1 : 0; - - REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); -} - -void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); -} - -bool hubp1_in_blank(struct hubp *hubp) -{ - uint32_t in_blank; - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank); - return in_blank ? true : false; -} - -void hubp1_soft_reset(struct hubp *hubp, bool reset) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0); -} - -/** - * hubp1_set_flip_int - Enable surface flip interrupt - * - * @hubp: hubp struct reference. - */ -void hubp1_set_flip_int(struct hubp *hubp) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT, - SURFACE_FLIP_INT_MASK, 1); - - return; -} - -/** - * hubp1_wait_pipe_read_start - wait for hubp ret path starting read. - * - * @hubp: hubp struct reference. - */ -static void hubp1_wait_pipe_read_start(struct hubp *hubp) -{ - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - - REG_WAIT(HUBPRET_READ_LINE_STATUS, - PIPE_READ_VBLANK, 0, - 1, 1000); -} - -void hubp1_init(struct hubp *hubp) -{ - //do nothing -} -static const struct hubp_funcs dcn10_hubp_funcs = { - .hubp_program_surface_flip_and_addr = - hubp1_program_surface_flip_and_addr, - .hubp_program_surface_config = - hubp1_program_surface_config, - .hubp_is_flip_pending = hubp1_is_flip_pending, - .hubp_setup = hubp1_setup, - .hubp_setup_interdependent = hubp1_setup_interdependent, - .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings, - .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings, - .set_blank = hubp1_set_blank, - .dcc_control = hubp1_dcc_control, - .mem_program_viewport = min_set_viewport, - .set_hubp_blank_en = hubp1_set_hubp_blank_en, - .set_cursor_attributes = hubp1_cursor_set_attributes, - .set_cursor_position = hubp1_cursor_set_position, - .hubp_disconnect = hubp1_disconnect, - .hubp_clk_cntl = hubp1_clk_cntl, - .hubp_vtg_sel = hubp1_vtg_sel, - .hubp_read_state = hubp1_read_state, - .hubp_clear_underflow = hubp1_clear_underflow, - .hubp_disable_control = hubp1_disable_control, - .hubp_get_underflow_status = hubp1_get_underflow_status, - .hubp_init = hubp1_init, - - .dmdata_set_attributes = NULL, - .dmdata_load = NULL, - .hubp_soft_reset = hubp1_soft_reset, - .hubp_in_blank = hubp1_in_blank, - .hubp_set_flip_int = hubp1_set_flip_int, - .hubp_wait_pipe_read_start = hubp1_wait_pipe_read_start, -}; - -/*****************************************/ -/* Constructor, Destructor */ -/*****************************************/ - -void dcn10_hubp_construct( - struct dcn10_hubp *hubp1, - struct dc_context *ctx, - uint32_t inst, - const struct dcn_mi_registers *hubp_regs, - const struct dcn_mi_shift *hubp_shift, - const struct dcn_mi_mask *hubp_mask) -{ - hubp1->base.funcs = &dcn10_hubp_funcs; - hubp1->base.ctx = ctx; - hubp1->hubp_regs = hubp_regs; - hubp1->hubp_shift = hubp_shift; - hubp1->hubp_mask = hubp_mask; - hubp1->base.inst = inst; - hubp1->base.opp_id = OPP_ID_INVALID; - hubp1->base.mpcc_id = 0xf; -} - - diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h deleted file mode 100644 index 69119b2fdce2..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +++ /dev/null @@ -1,797 +0,0 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_MEM_INPUT_DCN10_H__ -#define __DC_MEM_INPUT_DCN10_H__ - -#include "hubp.h" - -#define TO_DCN10_HUBP(hubp)\ - container_of(hubp, struct dcn10_hubp, base) - -/* Register address initialization macro for all ASICs (including those with reduced functionality) */ -#define HUBP_REG_LIST_DCN(id)\ - SRI(DCHUBP_CNTL, HUBP, id),\ - SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ - SRI(HUBPREQ_DEBUG, HUBP, id),\ - SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ - SRI(DCSURF_TILING_CONFIG, HUBP, id),\ - SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\ - SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ - SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \ - SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \ - SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \ - SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \ - SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \ - SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \ - SRI(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \ - SRI(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \ - SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ - SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\ - SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ - SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\ - SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ - SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\ - SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\ - SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\ - SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ - SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\ - SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ - SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),\ - SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ - SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\ - SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\ - SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\ - SRI(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id),\ - SRI(HUBPRET_CONTROL, HUBPRET, id),\ - SRI(HUBPRET_READ_LINE_STATUS, HUBPRET, id),\ - SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\ - SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\ - SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\ - SRI(BLANK_OFFSET_0, HUBPREQ, id),\ - SRI(BLANK_OFFSET_1, HUBPREQ, id),\ - SRI(DST_DIMENSIONS, HUBPREQ, id),\ - SRI(DST_AFTER_SCALER, HUBPREQ, id),\ - SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\ - SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\ - SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\ - SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\ - SRI(NOM_PARAMETERS_4, HUBPREQ, id),\ - SRI(NOM_PARAMETERS_5, HUBPREQ, id),\ - SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\ - SRI(PER_LINE_DELIVERY, HUBPREQ, id),\ - SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\ - SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\ - SRI(NOM_PARAMETERS_6, HUBPREQ, id),\ - SRI(NOM_PARAMETERS_7, HUBPREQ, id),\ - SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\ - SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\ - SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\ - SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\ - SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\ - SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ - SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\ - SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\ - SRI(HUBP_CLK_CNTL, HUBP, id) - -/* Register address initialization macro for ASICs with VM */ -#define HUBP_REG_LIST_DCN_VM(id)\ - SRI(NOM_PARAMETERS_0, HUBPREQ, id),\ - SRI(NOM_PARAMETERS_1, HUBPREQ, id),\ - SRI(NOM_PARAMETERS_2, HUBPREQ, id),\ - SRI(NOM_PARAMETERS_3, HUBPREQ, id),\ - SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id) - -#define HUBP_REG_LIST_DCN10(id)\ - HUBP_REG_LIST_DCN(id),\ - HUBP_REG_LIST_DCN_VM(id),\ - SRI(PREFETCH_SETTINS, HUBPREQ, id),\ - SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\ - SRI(CURSOR_SETTINS, HUBPREQ, id), \ - SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \ - SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \ - SRI(CURSOR_SIZE, CURSOR, id), \ - SRI(CURSOR_CONTROL, CURSOR, id), \ - SRI(CURSOR_POSITION, CURSOR, id), \ - SRI(CURSOR_HOT_SPOT, CURSOR, id), \ - SRI(CURSOR_DST_OFFSET, CURSOR, id) - -#define HUBP_COMMON_REG_VARIABLE_LIST \ - uint32_t DCHUBP_CNTL; \ - uint32_t HUBPREQ_DEBUG_DB; \ - uint32_t HUBPREQ_DEBUG; \ - uint32_t DCSURF_ADDR_CONFIG; \ - uint32_t DCSURF_TILING_CONFIG; \ - uint32_t DCSURF_SURFACE_PITCH; \ - uint32_t DCSURF_SURFACE_PITCH_C; \ - uint32_t DCSURF_SURFACE_CONFIG; \ - uint32_t DCSURF_FLIP_CONTROL; \ - uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \ - uint32_t DCSURF_PRI_VIEWPORT_START; \ - uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \ - uint32_t DCSURF_SEC_VIEWPORT_START; \ - uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \ - uint32_t DCSURF_PRI_VIEWPORT_START_C; \ - uint32_t DCSURF_SEC_VIEWPORT_DIMENSION_C; \ - uint32_t DCSURF_SEC_VIEWPORT_START_C; \ - uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \ - uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \ - uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \ - uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \ - uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \ - uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \ - uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \ - uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \ - uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \ - uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \ - uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C; \ - uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_C; \ - uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \ - uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \ - uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C; \ - uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_C; \ - uint32_t DCSURF_SURFACE_INUSE; \ - uint32_t DCSURF_SURFACE_INUSE_HIGH; \ - uint32_t DCSURF_SURFACE_INUSE_C; \ - uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \ - uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \ - uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \ - uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \ - uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \ - uint32_t DCSURF_SURFACE_CONTROL; \ - uint32_t DCSURF_SURFACE_FLIP_INTERRUPT; \ - uint32_t HUBPRET_CONTROL; \ - uint32_t HUBPRET_READ_LINE_STATUS; \ - uint32_t DCN_EXPANSION_MODE; \ - uint32_t DCHUBP_REQ_SIZE_CONFIG; \ - uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \ - uint32_t BLANK_OFFSET_0; \ - uint32_t BLANK_OFFSET_1; \ - uint32_t DST_DIMENSIONS; \ - uint32_t DST_AFTER_SCALER; \ - uint32_t PREFETCH_SETTINS; \ - uint32_t PREFETCH_SETTINGS; \ - uint32_t VBLANK_PARAMETERS_0; \ - uint32_t REF_FREQ_TO_PIX_FREQ; \ - uint32_t VBLANK_PARAMETERS_1; \ - uint32_t VBLANK_PARAMETERS_3; \ - uint32_t NOM_PARAMETERS_0; \ - uint32_t NOM_PARAMETERS_1; \ - uint32_t NOM_PARAMETERS_4; \ - uint32_t NOM_PARAMETERS_5; \ - uint32_t PER_LINE_DELIVERY_PRE; \ - uint32_t PER_LINE_DELIVERY; \ - uint32_t PREFETCH_SETTINS_C; \ - uint32_t PREFETCH_SETTINGS_C; \ - uint32_t VBLANK_PARAMETERS_2; \ - uint32_t VBLANK_PARAMETERS_4; \ - uint32_t NOM_PARAMETERS_2; \ - uint32_t NOM_PARAMETERS_3; \ - uint32_t NOM_PARAMETERS_6; \ - uint32_t NOM_PARAMETERS_7; \ - uint32_t DCN_TTU_QOS_WM; \ - uint32_t DCN_GLOBAL_TTU_CNTL; \ - uint32_t DCN_SURF0_TTU_CNTL0; \ - uint32_t DCN_SURF0_TTU_CNTL1; \ - uint32_t DCN_SURF1_TTU_CNTL0; \ - uint32_t DCN_SURF1_TTU_CNTL1; \ - uint32_t DCN_CUR0_TTU_CNTL0; \ - uint32_t DCN_CUR0_TTU_CNTL1; \ - uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \ - uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \ - uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \ - uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \ - uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \ - uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \ - uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \ - uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \ - uint32_t DCN_VM_MX_L1_TLB_CNTL; \ - uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \ - uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \ - uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \ - uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \ - uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \ - uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \ - uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \ - uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \ - uint32_t CURSOR_SETTINS; \ - uint32_t CURSOR_SETTINGS; \ - uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \ - uint32_t CURSOR_SURFACE_ADDRESS; \ - uint32_t CURSOR_SIZE; \ - uint32_t CURSOR_CONTROL; \ - uint32_t CURSOR_POSITION; \ - uint32_t CURSOR_HOT_SPOT; \ - uint32_t CURSOR_DST_OFFSET; \ - uint32_t HUBP_CLK_CNTL - -#define HUBP_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix - -/* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */ -/*1.x, 2.x, and 3.x*/ -#define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\ - HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ - HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ - HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ - HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_STATUS, PIPE_READ_VBLANK, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\ - HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\ - HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\ - HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\ - HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\ - HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\ - HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\ - HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\ - HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\ - HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\ - HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\ - HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\ - HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\ - HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\ - HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\ - HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\ - HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\ - HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\ - HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\ - HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\ - HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\ - HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ - HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh) -/*2.x and 1.x only*/ -#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\ - HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ - HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) - -/*2.x and 1.x only*/ -#define HUBP_MASK_SH_LIST_DCN(mask_sh)\ - HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh) - -/* Mask/shift struct generation macro for ASICs with VM */ -#define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\ - HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ - HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\ - HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ - HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh) - -#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\ - HUBP_MASK_SH_LIST_DCN(mask_sh),\ - HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ - HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\ - HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\ - HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ - HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ - HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ - HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) - -#define DCN_HUBP_REG_FIELD_BASE_LIST(type) \ - type HUBP_BLANK_EN;\ - type HUBP_DISABLE;\ - type HUBP_TTU_DISABLE;\ - type HUBP_NO_OUTSTANDING_REQ;\ - type HUBP_VTG_SEL;\ - type HUBP_UNDERFLOW_STATUS;\ - type HUBP_UNDERFLOW_CLEAR;\ - type HUBP_IN_BLANK;\ - type NUM_PIPES;\ - type NUM_BANKS;\ - type PIPE_INTERLEAVE;\ - type NUM_SE;\ - type NUM_RB_PER_SE;\ - type MAX_COMPRESSED_FRAGS;\ - type SW_MODE;\ - type META_LINEAR;\ - type RB_ALIGNED;\ - type PIPE_ALIGNED;\ - type PITCH;\ - type META_PITCH;\ - type PITCH_C;\ - type META_PITCH_C;\ - type ROTATION_ANGLE;\ - type H_MIRROR_EN;\ - type SURFACE_PIXEL_FORMAT;\ - type SURFACE_FLIP_TYPE;\ - type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\ - type SURFACE_FLIP_IN_STEREOSYNC;\ - type SURFACE_UPDATE_LOCK;\ - type SURFACE_FLIP_PENDING;\ - type PRI_VIEWPORT_WIDTH; \ - type PRI_VIEWPORT_HEIGHT; \ - type PRI_VIEWPORT_X_START; \ - type PRI_VIEWPORT_Y_START; \ - type SEC_VIEWPORT_WIDTH; \ - type SEC_VIEWPORT_HEIGHT; \ - type SEC_VIEWPORT_X_START; \ - type SEC_VIEWPORT_Y_START; \ - type PRI_VIEWPORT_WIDTH_C; \ - type PRI_VIEWPORT_HEIGHT_C; \ - type PRI_VIEWPORT_X_START_C; \ - type PRI_VIEWPORT_Y_START_C; \ - type SEC_VIEWPORT_WIDTH_C; \ - type SEC_VIEWPORT_HEIGHT_C; \ - type SEC_VIEWPORT_X_START_C; \ - type SEC_VIEWPORT_Y_START_C; \ - type PRIMARY_SURFACE_ADDRESS_HIGH;\ - type PRIMARY_SURFACE_ADDRESS;\ - type SECONDARY_SURFACE_ADDRESS_HIGH;\ - type SECONDARY_SURFACE_ADDRESS;\ - type PRIMARY_META_SURFACE_ADDRESS_HIGH;\ - type PRIMARY_META_SURFACE_ADDRESS;\ - type SECONDARY_META_SURFACE_ADDRESS_HIGH;\ - type SECONDARY_META_SURFACE_ADDRESS;\ - type PRIMARY_SURFACE_ADDRESS_HIGH_C;\ - type PRIMARY_SURFACE_ADDRESS_C;\ - type SECONDARY_SURFACE_ADDRESS_HIGH_C;\ - type SECONDARY_SURFACE_ADDRESS_C;\ - type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\ - type PRIMARY_META_SURFACE_ADDRESS_C;\ - type SECONDARY_META_SURFACE_ADDRESS_HIGH_C;\ - type SECONDARY_META_SURFACE_ADDRESS_C;\ - type SURFACE_INUSE_ADDRESS;\ - type SURFACE_INUSE_ADDRESS_HIGH;\ - type SURFACE_INUSE_ADDRESS_C;\ - type SURFACE_INUSE_ADDRESS_HIGH_C;\ - type SURFACE_EARLIEST_INUSE_ADDRESS;\ - type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\ - type SURFACE_EARLIEST_INUSE_ADDRESS_C;\ - type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\ - type PRIMARY_SURFACE_TMZ;\ - type PRIMARY_SURFACE_TMZ_C;\ - type SECONDARY_SURFACE_TMZ;\ - type SECONDARY_SURFACE_TMZ_C;\ - type PRIMARY_META_SURFACE_TMZ;\ - type PRIMARY_META_SURFACE_TMZ_C;\ - type SECONDARY_META_SURFACE_TMZ;\ - type SECONDARY_META_SURFACE_TMZ_C;\ - type PRIMARY_SURFACE_DCC_EN;\ - type PRIMARY_SURFACE_DCC_IND_64B_BLK;\ - type SECONDARY_SURFACE_DCC_EN;\ - type SECONDARY_SURFACE_DCC_IND_64B_BLK;\ - type SURFACE_FLIP_INT_MASK;\ - type DET_BUF_PLANE1_BASE_ADDRESS;\ - type CROSSBAR_SRC_CB_B;\ - type CROSSBAR_SRC_CR_R;\ - type PIPE_READ_VBLANK;\ - type DRQ_EXPANSION_MODE;\ - type PRQ_EXPANSION_MODE;\ - type MRQ_EXPANSION_MODE;\ - type CRQ_EXPANSION_MODE;\ - type CHUNK_SIZE;\ - type MIN_CHUNK_SIZE;\ - type META_CHUNK_SIZE;\ - type MIN_META_CHUNK_SIZE;\ - type DPTE_GROUP_SIZE;\ - type MPTE_GROUP_SIZE;\ - type SWATH_HEIGHT;\ - type PTE_ROW_HEIGHT_LINEAR;\ - type CHUNK_SIZE_C;\ - type MIN_CHUNK_SIZE_C;\ - type META_CHUNK_SIZE_C;\ - type MIN_META_CHUNK_SIZE_C;\ - type DPTE_GROUP_SIZE_C;\ - type MPTE_GROUP_SIZE_C;\ - type SWATH_HEIGHT_C;\ - type PTE_ROW_HEIGHT_LINEAR_C;\ - type REFCYC_H_BLANK_END;\ - type DLG_V_BLANK_END;\ - type MIN_DST_Y_NEXT_START;\ - type REFCYC_PER_HTOTAL;\ - type REFCYC_X_AFTER_SCALER;\ - type DST_Y_AFTER_SCALER;\ - type DST_Y_PREFETCH;\ - type VRATIO_PREFETCH;\ - type DST_Y_PER_VM_VBLANK;\ - type DST_Y_PER_ROW_VBLANK;\ - type REF_FREQ_TO_PIX_FREQ;\ - type REFCYC_PER_PTE_GROUP_VBLANK_L;\ - type REFCYC_PER_META_CHUNK_VBLANK_L;\ - type DST_Y_PER_PTE_ROW_NOM_L;\ - type REFCYC_PER_PTE_GROUP_NOM_L;\ - type DST_Y_PER_META_ROW_NOM_L;\ - type REFCYC_PER_META_CHUNK_NOM_L;\ - type REFCYC_PER_LINE_DELIVERY_PRE_L;\ - type REFCYC_PER_LINE_DELIVERY_PRE_C;\ - type REFCYC_PER_LINE_DELIVERY_L;\ - type REFCYC_PER_LINE_DELIVERY_C;\ - type VRATIO_PREFETCH_C;\ - type REFCYC_PER_PTE_GROUP_VBLANK_C;\ - type REFCYC_PER_META_CHUNK_VBLANK_C;\ - type DST_Y_PER_PTE_ROW_NOM_C;\ - type REFCYC_PER_PTE_GROUP_NOM_C;\ - type DST_Y_PER_META_ROW_NOM_C;\ - type REFCYC_PER_META_CHUNK_NOM_C;\ - type QoS_LEVEL_LOW_WM;\ - type QoS_LEVEL_HIGH_WM;\ - type MIN_TTU_VBLANK;\ - type QoS_LEVEL_FLIP;\ - type REFCYC_PER_REQ_DELIVERY;\ - type QoS_LEVEL_FIXED;\ - type QoS_RAMP_DISABLE;\ - type REFCYC_PER_REQ_DELIVERY_PRE;\ - type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\ - type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\ - type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\ - type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\ - type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\ - type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\ - type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\ - type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM;\ - type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\ - type ENABLE_L1_TLB;\ - type SYSTEM_ACCESS_MODE;\ - type HUBP_CLOCK_ENABLE;\ - type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ - type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ - type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ - type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\ - type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\ - type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\ - type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\ - type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\ - type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\ - type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ - type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ - type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ - /* todo: get these from GVM instead of reading registers ourselves */\ - type PAGE_DIRECTORY_ENTRY_HI32;\ - type PAGE_DIRECTORY_ENTRY_LO32;\ - type LOGICAL_PAGE_NUMBER_HI4;\ - type LOGICAL_PAGE_NUMBER_LO32;\ - type PHYSICAL_PAGE_ADDR_HI4;\ - type PHYSICAL_PAGE_ADDR_LO32;\ - type PHYSICAL_PAGE_NUMBER_MSB;\ - type PHYSICAL_PAGE_NUMBER_LSB;\ - type LOGICAL_ADDR;\ - type CURSOR0_DST_Y_OFFSET; \ - type CURSOR0_CHUNK_HDL_ADJUST; \ - type CURSOR_SURFACE_ADDRESS_HIGH; \ - type CURSOR_SURFACE_ADDRESS; \ - type CURSOR_WIDTH; \ - type CURSOR_HEIGHT; \ - type CURSOR_MODE; \ - type CURSOR_2X_MAGNIFY; \ - type CURSOR_PITCH; \ - type CURSOR_LINES_PER_CHUNK; \ - type CURSOR_ENABLE; \ - type CURSOR_X_POSITION; \ - type CURSOR_Y_POSITION; \ - type CURSOR_HOT_SPOT_X; \ - type CURSOR_HOT_SPOT_Y; \ - type CURSOR_DST_X_OFFSET; \ - type OUTPUT_FP - -#define DCN_HUBP_REG_FIELD_LIST(type) \ - DCN_HUBP_REG_FIELD_BASE_LIST(type);\ - type ALPHA_PLANE_EN - -struct dcn_mi_registers { - HUBP_COMMON_REG_VARIABLE_LIST; -}; - -struct dcn_mi_shift { - DCN_HUBP_REG_FIELD_LIST(uint8_t); -}; - -struct dcn_mi_mask { - DCN_HUBP_REG_FIELD_LIST(uint32_t); -}; - -struct dcn_hubp_state { - struct _vcs_dpi_display_dlg_regs_st dlg_attr; - struct _vcs_dpi_display_ttu_regs_st ttu_attr; - struct _vcs_dpi_display_rq_regs_st rq_regs; - uint32_t pixel_format; - uint32_t inuse_addr_hi; - uint32_t inuse_addr_lo; - uint32_t viewport_width; - uint32_t viewport_height; - uint32_t rotation_angle; - uint32_t h_mirror_en; - uint32_t sw_mode; - uint32_t dcc_en; - uint32_t blank_en; - uint32_t clock_en; - uint32_t underflow_status; - uint32_t ttu_disable; - uint32_t min_ttu_vblank; - uint32_t qos_level_low_wm; - uint32_t qos_level_high_wm; - uint32_t primary_surface_addr_lo; - uint32_t primary_surface_addr_hi; - uint32_t primary_meta_addr_lo; - uint32_t primary_meta_addr_hi; - uint32_t uclk_pstate_force; - uint32_t hubp_cntl; - uint32_t flip_control; -}; - -struct dcn10_hubp { - struct hubp base; - struct dcn_hubp_state state; - const struct dcn_mi_registers *hubp_regs; - const struct dcn_mi_shift *hubp_shift; - const struct dcn_mi_mask *hubp_mask; -}; - -void hubp1_program_surface_config( - struct hubp *hubp, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - struct plane_size *plane_size, - enum dc_rotation_angle rotation, - struct dc_plane_dcc_param *dcc, - bool horizontal_mirror, - unsigned int compat_level); - -void hubp1_program_deadline( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr); - -void hubp1_program_requestor( - struct hubp *hubp, - struct _vcs_dpi_display_rq_regs_st *rq_regs); - -void hubp1_program_pixel_format( - struct hubp *hubp, - enum surface_pixel_format format); - -void hubp1_program_size( - struct hubp *hubp, - enum surface_pixel_format format, - const struct plane_size *plane_size, - struct dc_plane_dcc_param *dcc); - -void hubp1_program_rotation( - struct hubp *hubp, - enum dc_rotation_angle rotation, - bool horizontal_mirror); - -void hubp1_program_tiling( - struct hubp *hubp, - const union dc_tiling_info *info, - const enum surface_pixel_format pixel_format); - -void hubp1_dcc_control(struct hubp *hubp, - bool enable, - enum hubp_ind_block_size independent_64b_blks); - -bool hubp1_program_surface_flip_and_addr( - struct hubp *hubp, - const struct dc_plane_address *address, - bool flip_immediate); - -bool hubp1_is_flip_pending(struct hubp *hubp); - -void hubp1_cursor_set_attributes( - struct hubp *hubp, - const struct dc_cursor_attributes *attr); - -void hubp1_cursor_set_position( - struct hubp *hubp, - const struct dc_cursor_position *pos, - const struct dc_cursor_mi_param *param); - -void hubp1_set_blank(struct hubp *hubp, bool blank); - -void min_set_viewport(struct hubp *hubp, - const struct rect *viewport, - const struct rect *viewport_c); - -void hubp1_clk_cntl(struct hubp *hubp, bool enable); -void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst); - -void dcn10_hubp_construct( - struct dcn10_hubp *hubp1, - struct dc_context *ctx, - uint32_t inst, - const struct dcn_mi_registers *hubp_regs, - const struct dcn_mi_shift *hubp_shift, - const struct dcn_mi_mask *hubp_mask); - -void hubp1_read_state(struct hubp *hubp); -void hubp1_clear_underflow(struct hubp *hubp); - -enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch); - -void hubp1_vready_workaround(struct hubp *hubp, - struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); - -void hubp1_init(struct hubp *hubp); -void hubp1_read_state_common(struct hubp *hubp); -bool hubp1_in_blank(struct hubp *hubp); -void hubp1_soft_reset(struct hubp *hubp, bool reset); - -void hubp1_set_flip_int(struct hubp *hubp); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c index c51b717e5622..05df502a54f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c @@ -40,8 +40,8 @@ #include "ipp.h" #include "mpc.h" #include "reg_helper.h" -#include "dcn10_hubp.h" -#include "dcn10_hubbub.h" +#include "dcn10/dcn10_hubp.h" +#include "dcn10/dcn10_hubbub.h" #include "dcn10_cm_common.h" #include "clk_mgr.h" diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c deleted file mode 100644 index 4d0eed7598b2..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c +++ /dev/null @@ -1,1468 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "reg_helper.h" - -#include "core_types.h" -#include "link_encoder.h" -#include "dcn10_link_encoder.h" -#include "stream_encoder.h" -#include "dc_bios_types.h" - -#include "gpio_service_interface.h" - -#define CTX \ - enc10->base.ctx -#define DC_LOGGER \ - enc10->base.ctx->logger - -#define REG(reg)\ - (enc10->link_regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - enc10->link_shift->field_name, enc10->link_mask->field_name - - -/* - * @brief - * Trigger Source Select - * ASIC-dependent, actual values for register programming - */ -#define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0 -#define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1 -#define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2 -#define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4 -#define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08 -#define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10 -#define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20 -#define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40 - -enum { - DP_MST_UPDATE_MAX_RETRY = 50 -}; - -static const struct link_encoder_funcs dcn10_lnk_enc_funcs = { - .validate_output_with_stream = - dcn10_link_encoder_validate_output_with_stream, - .hw_init = dcn10_link_encoder_hw_init, - .setup = dcn10_link_encoder_setup, - .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, - .enable_dp_output = dcn10_link_encoder_enable_dp_output, - .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output, - .disable_output = dcn10_link_encoder_disable_output, - .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, - .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, - .update_mst_stream_allocation_table = - dcn10_link_encoder_update_mst_stream_allocation_table, - .psr_program_dp_dphy_fast_training = - dcn10_psr_program_dp_dphy_fast_training, - .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, - .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, - .enable_hpd = dcn10_link_encoder_enable_hpd, - .disable_hpd = dcn10_link_encoder_disable_hpd, - .is_dig_enabled = dcn10_is_dig_enabled, - .get_dig_frontend = dcn10_get_dig_frontend, - .get_dig_mode = dcn10_get_dig_mode, - .destroy = dcn10_link_encoder_destroy, - .get_max_link_cap = dcn10_link_encoder_get_max_link_cap, -}; - -static enum bp_result link_transmitter_control( - struct dcn10_link_encoder *enc10, - struct bp_transmitter_control *cntl) -{ - enum bp_result result; - struct dc_bios *bp = enc10->base.ctx->dc_bios; - - result = bp->funcs->transmitter_control(bp, cntl); - - return result; -} - -static void enable_phy_bypass_mode( - struct dcn10_link_encoder *enc10, - bool enable) -{ - /* This register resides in DP back end block; - * transmitter is used for the offset - */ - REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); - -} - -static void disable_prbs_symbols( - struct dcn10_link_encoder *enc10, - bool disable) -{ - /* This register resides in DP back end block; - * transmitter is used for the offset - */ - REG_UPDATE_4(DP_DPHY_CNTL, - DPHY_ATEST_SEL_LANE0, disable, - DPHY_ATEST_SEL_LANE1, disable, - DPHY_ATEST_SEL_LANE2, disable, - DPHY_ATEST_SEL_LANE3, disable); -} - -static void disable_prbs_mode( - struct dcn10_link_encoder *enc10) -{ - REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); -} - -static void program_pattern_symbols( - struct dcn10_link_encoder *enc10, - uint16_t pattern_symbols[8]) -{ - /* This register resides in DP back end block; - * transmitter is used for the offset - */ - REG_SET_3(DP_DPHY_SYM0, 0, - DPHY_SYM1, pattern_symbols[0], - DPHY_SYM2, pattern_symbols[1], - DPHY_SYM3, pattern_symbols[2]); - - /* This register resides in DP back end block; - * transmitter is used for the offset - */ - REG_SET_3(DP_DPHY_SYM1, 0, - DPHY_SYM4, pattern_symbols[3], - DPHY_SYM5, pattern_symbols[4], - DPHY_SYM6, pattern_symbols[5]); - - /* This register resides in DP back end block; - * transmitter is used for the offset - */ - REG_SET_2(DP_DPHY_SYM2, 0, - DPHY_SYM7, pattern_symbols[6], - DPHY_SYM8, pattern_symbols[7]); -} - -static void set_dp_phy_pattern_d102( - struct dcn10_link_encoder *enc10) -{ - /* Disable PHY Bypass mode to setup the test pattern */ - enable_phy_bypass_mode(enc10, false); - - /* For 10-bit PRBS or debug symbols - * please use the following sequence: - * - * Enable debug symbols on the lanes - */ - disable_prbs_symbols(enc10, true); - - /* Disable PRBS mode */ - disable_prbs_mode(enc10); - - /* Program debug symbols to be output */ - { - uint16_t pattern_symbols[8] = { - 0x2AA, 0x2AA, 0x2AA, 0x2AA, - 0x2AA, 0x2AA, 0x2AA, 0x2AA - }; - - program_pattern_symbols(enc10, pattern_symbols); - } - - /* Enable phy bypass mode to enable the test pattern */ - - enable_phy_bypass_mode(enc10, true); -} - -static void set_link_training_complete( - struct dcn10_link_encoder *enc10, - bool complete) -{ - /* This register resides in DP back end block; - * transmitter is used for the offset - */ - REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); - -} - -void dcn10_link_encoder_set_dp_phy_pattern_training_pattern( - struct link_encoder *enc, - uint32_t index) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - /* Write Training Pattern */ - - REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index); - - /* Set HW Register Training Complete to false */ - - set_link_training_complete(enc10, false); - - /* Disable PHY Bypass mode to output Training Pattern */ - - enable_phy_bypass_mode(enc10, false); - - /* Disable PRBS mode */ - disable_prbs_mode(enc10); -} - -static void setup_panel_mode( - struct dcn10_link_encoder *enc10, - enum dp_panel_mode panel_mode) -{ - uint32_t value; - - if (!REG(DP_DPHY_INTERNAL_CTRL)) - return; - - value = REG_READ(DP_DPHY_INTERNAL_CTRL); - - switch (panel_mode) { - case DP_PANEL_MODE_EDP: - value = 0x1; - break; - case DP_PANEL_MODE_SPECIAL: - value = 0x11; - break; - default: - value = 0x0; - break; - } - - REG_WRITE(DP_DPHY_INTERNAL_CTRL, value); -} - -static void set_dp_phy_pattern_symbol_error( - struct dcn10_link_encoder *enc10) -{ - /* Disable PHY Bypass mode to setup the test pattern */ - enable_phy_bypass_mode(enc10, false); - - /* program correct panel mode*/ - setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT); - - /* A PRBS23 pattern is used for most DP electrical measurements. */ - - /* Enable PRBS symbols on the lanes */ - disable_prbs_symbols(enc10, false); - - /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */ - REG_UPDATE_2(DP_DPHY_PRBS_CNTL, - DPHY_PRBS_SEL, 1, - DPHY_PRBS_EN, 1); - - /* Enable phy bypass mode to enable the test pattern */ - enable_phy_bypass_mode(enc10, true); -} - -static void set_dp_phy_pattern_prbs7( - struct dcn10_link_encoder *enc10) -{ - /* Disable PHY Bypass mode to setup the test pattern */ - enable_phy_bypass_mode(enc10, false); - - /* A PRBS7 pattern is used for most DP electrical measurements. */ - - /* Enable PRBS symbols on the lanes */ - disable_prbs_symbols(enc10, false); - - /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */ - REG_UPDATE_2(DP_DPHY_PRBS_CNTL, - DPHY_PRBS_SEL, 0, - DPHY_PRBS_EN, 1); - - /* Enable phy bypass mode to enable the test pattern */ - enable_phy_bypass_mode(enc10, true); -} - -static void set_dp_phy_pattern_80bit_custom( - struct dcn10_link_encoder *enc10, - const uint8_t *pattern) -{ - /* Disable PHY Bypass mode to setup the test pattern */ - enable_phy_bypass_mode(enc10, false); - - /* Enable debug symbols on the lanes */ - - disable_prbs_symbols(enc10, true); - - /* Enable PHY bypass mode to enable the test pattern */ - /* TODO is it really needed ? */ - - enable_phy_bypass_mode(enc10, true); - - /* Program 80 bit custom pattern */ - { - uint16_t pattern_symbols[8]; - - pattern_symbols[0] = - ((pattern[1] & 0x03) << 8) | pattern[0]; - pattern_symbols[1] = - ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f); - pattern_symbols[2] = - ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f); - pattern_symbols[3] = - (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03); - pattern_symbols[4] = - ((pattern[6] & 0x03) << 8) | pattern[5]; - pattern_symbols[5] = - ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f); - pattern_symbols[6] = - ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f); - pattern_symbols[7] = - (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03); - - program_pattern_symbols(enc10, pattern_symbols); - } - - /* Enable phy bypass mode to enable the test pattern */ - - enable_phy_bypass_mode(enc10, true); -} - -static void set_dp_phy_pattern_hbr2_compliance_cp2520_2( - struct dcn10_link_encoder *enc10, - unsigned int cp2520_pattern) -{ - - /* previously there is a register DP_HBR2_EYE_PATTERN - * that is enabled to get the pattern. - * But it does not work with the latest spec change, - * so we are programming the following registers manually. - * - * The following settings have been confirmed - * by Nick Chorney and Sandra Liu - */ - - /* Disable PHY Bypass mode to setup the test pattern */ - - enable_phy_bypass_mode(enc10, false); - - /* Setup DIG encoder in DP SST mode */ - enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT); - - /* ensure normal panel mode. */ - setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT); - - /* no vbid after BS (SR) - * DP_LINK_FRAMING_CNTL changed history Sandra Liu - * 11000260 / 11000104 / 110000FC - */ - REG_UPDATE_3(DP_LINK_FRAMING_CNTL, - DP_IDLE_BS_INTERVAL, 0xFC, - DP_VBID_DISABLE, 1, - DP_VID_ENHANCED_FRAME_MODE, 1); - - /* swap every BS with SR */ - REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); - - /* select cp2520 patterns */ - if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) - REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, - DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); - else - /* pre-DCE11 can only generate CP2520 pattern 2 */ - ASSERT(cp2520_pattern == 2); - - /* set link training complete */ - set_link_training_complete(enc10, true); - - /* disable video stream */ - REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); - - /* Disable PHY Bypass mode to setup the test pattern */ - enable_phy_bypass_mode(enc10, false); -} - -static void set_dp_phy_pattern_passthrough_mode( - struct dcn10_link_encoder *enc10, - enum dp_panel_mode panel_mode) -{ - /* program correct panel mode */ - setup_panel_mode(enc10, panel_mode); - - /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT - * in case we were doing HBR2 compliance pattern before - */ - REG_UPDATE_3(DP_LINK_FRAMING_CNTL, - DP_IDLE_BS_INTERVAL, 0x2000, - DP_VBID_DISABLE, 0, - DP_VID_ENHANCED_FRAME_MODE, 1); - - REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); - - /* set link training complete */ - set_link_training_complete(enc10, true); - - /* Disable PHY Bypass mode to setup the test pattern */ - enable_phy_bypass_mode(enc10, false); - - /* Disable PRBS mode */ - disable_prbs_mode(enc10); -} - -/* return value is bit-vector */ -static uint8_t get_frontend_source( - enum engine_id engine) -{ - switch (engine) { - case ENGINE_ID_DIGA: - return DCN10_DIG_FE_SOURCE_SELECT_DIGA; - case ENGINE_ID_DIGB: - return DCN10_DIG_FE_SOURCE_SELECT_DIGB; - case ENGINE_ID_DIGC: - return DCN10_DIG_FE_SOURCE_SELECT_DIGC; - case ENGINE_ID_DIGD: - return DCN10_DIG_FE_SOURCE_SELECT_DIGD; - case ENGINE_ID_DIGE: - return DCN10_DIG_FE_SOURCE_SELECT_DIGE; - case ENGINE_ID_DIGF: - return DCN10_DIG_FE_SOURCE_SELECT_DIGF; - case ENGINE_ID_DIGG: - return DCN10_DIG_FE_SOURCE_SELECT_DIGG; - default: - ASSERT_CRITICAL(false); - return DCN10_DIG_FE_SOURCE_SELECT_INVALID; - } -} - -unsigned int dcn10_get_dig_frontend(struct link_encoder *enc) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - int32_t value; - enum engine_id result; - - REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); - - switch (value) { - case DCN10_DIG_FE_SOURCE_SELECT_DIGA: - result = ENGINE_ID_DIGA; - break; - case DCN10_DIG_FE_SOURCE_SELECT_DIGB: - result = ENGINE_ID_DIGB; - break; - case DCN10_DIG_FE_SOURCE_SELECT_DIGC: - result = ENGINE_ID_DIGC; - break; - case DCN10_DIG_FE_SOURCE_SELECT_DIGD: - result = ENGINE_ID_DIGD; - break; - case DCN10_DIG_FE_SOURCE_SELECT_DIGE: - result = ENGINE_ID_DIGE; - break; - case DCN10_DIG_FE_SOURCE_SELECT_DIGF: - result = ENGINE_ID_DIGF; - break; - case DCN10_DIG_FE_SOURCE_SELECT_DIGG: - result = ENGINE_ID_DIGG; - break; - default: - // invalid source select DIG - result = ENGINE_ID_UNKNOWN; - } - - return result; - -} - -void enc1_configure_encoder( - struct dcn10_link_encoder *enc10, - const struct dc_link_settings *link_settings) -{ - /* set number of lanes */ - REG_SET(DP_CONFIG, 0, - DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); - - /* setup scrambler */ - REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); -} - -void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc, - bool exit_link_training_required) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - if (exit_link_training_required) - REG_UPDATE(DP_DPHY_FAST_TRAINING, - DPHY_RX_FAST_TRAINING_CAPABLE, 1); - else { - REG_UPDATE(DP_DPHY_FAST_TRAINING, - DPHY_RX_FAST_TRAINING_CAPABLE, 0); - /*In DCE 11, we are able to pre-program a Force SR register - * to be able to trigger SR symbol after 5 idle patterns - * transmitted. Upon PSR Exit, DMCU can trigger - * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to - * DPHY_LOAD_BS_COUNT_START and the internal counter - * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be - * replaced by SR symbol once. - */ - - REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5); - } -} - -void dcn10_psr_program_secondary_packet(struct link_encoder *enc, - unsigned int sdp_transmit_line_num_deadline) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - REG_UPDATE_2(DP_SEC_CNTL1, - DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline, - DP_SEC_GSP0_PRIORITY, 1); -} - -bool dcn10_is_dig_enabled(struct link_encoder *enc) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - uint32_t value; - - REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); - return value; -} - -static void link_encoder_disable(struct dcn10_link_encoder *enc10) -{ - /* reset training pattern */ - REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0, - DPHY_TRAINING_PATTERN_SEL, 0); - - /* reset training complete */ - REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0); - - /* reset panel mode */ - setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT); -} - -static void hpd_initialize( - struct dcn10_link_encoder *enc10) -{ - /* Associate HPD with DIG_BE */ - enum hpd_source_id hpd_source = enc10->base.hpd_source; - - REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source); -} - -bool dcn10_link_encoder_validate_dvi_output( - const struct dcn10_link_encoder *enc10, - enum signal_type connector_signal, - enum signal_type signal, - const struct dc_crtc_timing *crtc_timing) -{ - uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK; - - if (signal == SIGNAL_TYPE_DVI_DUAL_LINK) - max_pixel_clock *= 2; - - /* This handles the case of HDMI downgrade to DVI we don't want to - * we don't want to cap the pixel clock if the DDI is not DVI. - */ - if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK && - connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) - max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock; - - /* DVI only support RGB pixel encoding */ - if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) - return false; - - /*connect DVI via adpater's HDMI connector*/ - if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK || - connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) && - signal != SIGNAL_TYPE_HDMI_TYPE_A && - crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10)) - return false; - if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) - return false; - - if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10)) - return false; - - /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */ - switch (crtc_timing->display_color_depth) { - case COLOR_DEPTH_666: - case COLOR_DEPTH_888: - break; - case COLOR_DEPTH_101010: - case COLOR_DEPTH_161616: - if (signal != SIGNAL_TYPE_DVI_DUAL_LINK) - return false; - break; - default: - return false; - } - - return true; -} - -static bool dcn10_link_encoder_validate_hdmi_output( - const struct dcn10_link_encoder *enc10, - const struct dc_crtc_timing *crtc_timing, - const struct dc_edid_caps *edid_caps, - int adjusted_pix_clk_100hz) -{ - enum dc_color_depth max_deep_color = - enc10->base.features.max_hdmi_deep_color; - - // check pixel clock against edid specified max TMDS clk - if (edid_caps->max_tmds_clk_mhz != 0 && - adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000) - return false; - - if (max_deep_color < crtc_timing->display_color_depth) - return false; - - if (crtc_timing->display_color_depth < COLOR_DEPTH_888) - return false; - if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) - return false; - - if ((adjusted_pix_clk_100hz == 0) || - (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10))) - return false; - - /* DCE11 HW does not support 420 */ - if (!enc10->base.features.hdmi_ycbcr420_supported && - crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) - return false; - - if ((!enc10->base.features.flags.bits.HDMI_6GB_EN || - enc10->base.ctx->dc->debug.hdmi20_disable) && - adjusted_pix_clk_100hz >= 3000000) - return false; - if (enc10->base.ctx->dc->debug.hdmi20_disable && - crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) - return false; - return true; -} - -bool dcn10_link_encoder_validate_dp_output( - const struct dcn10_link_encoder *enc10, - const struct dc_crtc_timing *crtc_timing) -{ - if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) { - if (!enc10->base.features.dp_ycbcr420_supported) - return false; - } - - return true; -} - -void dcn10_link_encoder_construct( - struct dcn10_link_encoder *enc10, - const struct encoder_init_data *init_data, - const struct encoder_feature_support *enc_features, - const struct dcn10_link_enc_registers *link_regs, - const struct dcn10_link_enc_aux_registers *aux_regs, - const struct dcn10_link_enc_hpd_registers *hpd_regs, - const struct dcn10_link_enc_shift *link_shift, - const struct dcn10_link_enc_mask *link_mask) -{ - struct bp_encoder_cap_info bp_cap_info = {0}; - const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; - enum bp_result result = BP_RESULT_OK; - - enc10->base.funcs = &dcn10_lnk_enc_funcs; - enc10->base.ctx = init_data->ctx; - enc10->base.id = init_data->encoder; - - enc10->base.hpd_source = init_data->hpd_source; - enc10->base.connector = init_data->connector; - - enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; - - enc10->base.features = *enc_features; - - enc10->base.transmitter = init_data->transmitter; - - /* set the flag to indicate whether driver poll the I2C data pin - * while doing the DP sink detect - */ - -/* if (dal_adapter_service_is_feature_supported(as, - FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) - enc10->base.features.flags.bits. - DP_SINK_DETECT_POLL_DATA_PIN = true;*/ - - enc10->base.output_signals = - SIGNAL_TYPE_DVI_SINGLE_LINK | - SIGNAL_TYPE_DVI_DUAL_LINK | - SIGNAL_TYPE_LVDS | - SIGNAL_TYPE_DISPLAY_PORT | - SIGNAL_TYPE_DISPLAY_PORT_MST | - SIGNAL_TYPE_EDP | - SIGNAL_TYPE_HDMI_TYPE_A; - - /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. - * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. - * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer - * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. - * Prefer DIG assignment is decided by board design. - * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design - * and VBIOS will filter out 7 UNIPHY for DCE 8.0. - * By this, adding DIGG should not hurt DCE 8.0. - * This will let DCE 8.1 share DCE 8.0 as much as possible - */ - - enc10->link_regs = link_regs; - enc10->aux_regs = aux_regs; - enc10->hpd_regs = hpd_regs; - enc10->link_shift = link_shift; - enc10->link_mask = link_mask; - - switch (enc10->base.transmitter) { - case TRANSMITTER_UNIPHY_A: - enc10->base.preferred_engine = ENGINE_ID_DIGA; - break; - case TRANSMITTER_UNIPHY_B: - enc10->base.preferred_engine = ENGINE_ID_DIGB; - break; - case TRANSMITTER_UNIPHY_C: - enc10->base.preferred_engine = ENGINE_ID_DIGC; - break; - case TRANSMITTER_UNIPHY_D: - enc10->base.preferred_engine = ENGINE_ID_DIGD; - break; - case TRANSMITTER_UNIPHY_E: - enc10->base.preferred_engine = ENGINE_ID_DIGE; - break; - case TRANSMITTER_UNIPHY_F: - enc10->base.preferred_engine = ENGINE_ID_DIGF; - break; - case TRANSMITTER_UNIPHY_G: - enc10->base.preferred_engine = ENGINE_ID_DIGG; - break; - default: - ASSERT_CRITICAL(false); - enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; - } - - /* default to one to mirror Windows behavior */ - enc10->base.features.flags.bits.HDMI_6GB_EN = 1; - - result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios, - enc10->base.id, &bp_cap_info); - - /* Override features with DCE-specific values */ - if (result == BP_RESULT_OK) { - enc10->base.features.flags.bits.IS_HBR2_CAPABLE = - bp_cap_info.DP_HBR2_EN; - enc10->base.features.flags.bits.IS_HBR3_CAPABLE = - bp_cap_info.DP_HBR3_EN; - enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; - enc10->base.features.flags.bits.DP_IS_USB_C = - bp_cap_info.DP_IS_USB_C; - } else { - DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", - __func__, - result); - } - if (enc10->base.ctx->dc->debug.hdmi20_disable) { - enc10->base.features.flags.bits.HDMI_6GB_EN = 0; - } -} - -bool dcn10_link_encoder_validate_output_with_stream( - struct link_encoder *enc, - const struct dc_stream_state *stream) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - bool is_valid; - - //if SCDC (340-600MHz) is disabled, set to HDMI 1.4 timing limit - if (stream->sink->edid_caps.panel_patch.skip_scdc_overwrite && - enc10->base.features.max_hdmi_pixel_clock > 300000) - enc10->base.features.max_hdmi_pixel_clock = 300000; - - switch (stream->signal) { - case SIGNAL_TYPE_DVI_SINGLE_LINK: - case SIGNAL_TYPE_DVI_DUAL_LINK: - is_valid = dcn10_link_encoder_validate_dvi_output( - enc10, - stream->link->connector_signal, - stream->signal, - &stream->timing); - break; - case SIGNAL_TYPE_HDMI_TYPE_A: - is_valid = dcn10_link_encoder_validate_hdmi_output( - enc10, - &stream->timing, - &stream->sink->edid_caps, - stream->phy_pix_clk * 10); - break; - case SIGNAL_TYPE_DISPLAY_PORT: - case SIGNAL_TYPE_DISPLAY_PORT_MST: - is_valid = dcn10_link_encoder_validate_dp_output( - enc10, &stream->timing); - break; - case SIGNAL_TYPE_EDP: - is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false; - break; - case SIGNAL_TYPE_VIRTUAL: - is_valid = true; - break; - default: - is_valid = false; - break; - } - - return is_valid; -} - -void dcn10_link_encoder_hw_init( - struct link_encoder *enc) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - struct bp_transmitter_control cntl = { 0 }; - enum bp_result result; - - cntl.action = TRANSMITTER_CONTROL_INIT; - cntl.engine_id = ENGINE_ID_UNKNOWN; - cntl.transmitter = enc10->base.transmitter; - cntl.connector_obj_id = enc10->base.connector; - cntl.lanes_number = LANE_COUNT_FOUR; - cntl.coherent = false; - cntl.hpd_sel = enc10->base.hpd_source; - - if (enc10->base.connector.id == CONNECTOR_ID_EDP) - cntl.signal = SIGNAL_TYPE_EDP; - - result = link_transmitter_control(enc10, &cntl); - - if (result != BP_RESULT_OK) { - DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", - __func__); - BREAK_TO_DEBUGGER(); - return; - } - - if (enc10->base.connector.id == CONNECTOR_ID_LVDS) { - cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS; - - result = link_transmitter_control(enc10, &cntl); - - ASSERT(result == BP_RESULT_OK); - - } - dcn10_aux_initialize(enc10); - - /* reinitialize HPD. - * hpd_initialize() will pass DIG_FE id to HW context. - * All other routine within HW context will use fe_engine_offset - * as DIG_FE id even caller pass DIG_FE id. - * So this routine must be called first. - */ - hpd_initialize(enc10); -} - -void dcn10_link_encoder_destroy(struct link_encoder **enc) -{ - kfree(TO_DCN10_LINK_ENC(*enc)); - *enc = NULL; -} - -void dcn10_link_encoder_setup( - struct link_encoder *enc, - enum signal_type signal) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - switch (signal) { - case SIGNAL_TYPE_EDP: - case SIGNAL_TYPE_DISPLAY_PORT: - /* DP SST */ - REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0); - break; - case SIGNAL_TYPE_LVDS: - /* LVDS */ - REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1); - break; - case SIGNAL_TYPE_DVI_SINGLE_LINK: - case SIGNAL_TYPE_DVI_DUAL_LINK: - /* TMDS-DVI */ - REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2); - break; - case SIGNAL_TYPE_HDMI_TYPE_A: - /* TMDS-HDMI */ - REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3); - break; - case SIGNAL_TYPE_DISPLAY_PORT_MST: - /* DP MST */ - REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); - break; - default: - ASSERT_CRITICAL(false); - /* invalid mode ! */ - break; - } - -} - -/* TODO: still need depth or just pass in adjusted pixel clock? */ -void dcn10_link_encoder_enable_tmds_output( - struct link_encoder *enc, - enum clock_source_id clock_source, - enum dc_color_depth color_depth, - enum signal_type signal, - uint32_t pixel_clock) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - struct bp_transmitter_control cntl = { 0 }; - enum bp_result result; - - /* Enable the PHY */ - - cntl.action = TRANSMITTER_CONTROL_ENABLE; - cntl.engine_id = enc->preferred_engine; - cntl.transmitter = enc10->base.transmitter; - cntl.pll_id = clock_source; - cntl.signal = signal; - if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK) - cntl.lanes_number = 8; - else - cntl.lanes_number = 4; - - cntl.hpd_sel = enc10->base.hpd_source; - - cntl.pixel_clock = pixel_clock; - cntl.color_depth = color_depth; - - result = link_transmitter_control(enc10, &cntl); - - if (result != BP_RESULT_OK) { - DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", - __func__); - BREAK_TO_DEBUGGER(); - } -} - -void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa( - struct link_encoder *enc, - enum clock_source_id clock_source, - enum dc_color_depth color_depth, - enum signal_type signal, - uint32_t pixel_clock) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - dcn10_link_encoder_enable_tmds_output( - enc, clock_source, color_depth, signal, pixel_clock); - - REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); -} - -/* enables DP PHY output */ -void dcn10_link_encoder_enable_dp_output( - struct link_encoder *enc, - const struct dc_link_settings *link_settings, - enum clock_source_id clock_source) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - struct bp_transmitter_control cntl = { 0 }; - enum bp_result result; - - /* Enable the PHY */ - - /* number_of_lanes is used for pixel clock adjust, - * but it's not passed to asic_control. - * We need to set number of lanes manually. - */ - enc1_configure_encoder(enc10, link_settings); - - cntl.action = TRANSMITTER_CONTROL_ENABLE; - cntl.engine_id = enc->preferred_engine; - cntl.transmitter = enc10->base.transmitter; - cntl.pll_id = clock_source; - cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; - cntl.lanes_number = link_settings->lane_count; - cntl.hpd_sel = enc10->base.hpd_source; - cntl.pixel_clock = link_settings->link_rate - * LINK_RATE_REF_FREQ_IN_KHZ; - /* TODO: check if undefined works */ - cntl.color_depth = COLOR_DEPTH_UNDEFINED; - - result = link_transmitter_control(enc10, &cntl); - - if (result != BP_RESULT_OK) { - DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", - __func__); - BREAK_TO_DEBUGGER(); - } -} - -/* enables DP PHY output in MST mode */ -void dcn10_link_encoder_enable_dp_mst_output( - struct link_encoder *enc, - const struct dc_link_settings *link_settings, - enum clock_source_id clock_source) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - struct bp_transmitter_control cntl = { 0 }; - enum bp_result result; - - /* Enable the PHY */ - - /* number_of_lanes is used for pixel clock adjust, - * but it's not passed to asic_control. - * We need to set number of lanes manually. - */ - enc1_configure_encoder(enc10, link_settings); - - cntl.action = TRANSMITTER_CONTROL_ENABLE; - cntl.engine_id = ENGINE_ID_UNKNOWN; - cntl.transmitter = enc10->base.transmitter; - cntl.pll_id = clock_source; - cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; - cntl.lanes_number = link_settings->lane_count; - cntl.hpd_sel = enc10->base.hpd_source; - cntl.pixel_clock = link_settings->link_rate - * LINK_RATE_REF_FREQ_IN_KHZ; - /* TODO: check if undefined works */ - cntl.color_depth = COLOR_DEPTH_UNDEFINED; - - result = link_transmitter_control(enc10, &cntl); - - if (result != BP_RESULT_OK) { - DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", - __func__); - BREAK_TO_DEBUGGER(); - } -} -/* - * @brief - * Disable transmitter and its encoder - */ -void dcn10_link_encoder_disable_output( - struct link_encoder *enc, - enum signal_type signal) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - struct bp_transmitter_control cntl = { 0 }; - enum bp_result result; - - if (enc->funcs->is_dig_enabled && !enc->funcs->is_dig_enabled(enc)) { - /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ - /*in DP_Alt_No_Connect case, we turn off the dig already, - after excuation the PHY w/a sequence, not allow touch PHY any more*/ - return; - } - /* Power-down RX and disable GPU PHY should be paired. - * Disabling PHY without powering down RX may cause - * symbol lock loss, on which we will get DP Sink interrupt. - */ - - /* There is a case for the DP active dongles - * where we want to disable the PHY but keep RX powered, - * for those we need to ignore DP Sink interrupt - * by checking lane count that has been set - * on the last do_enable_output(). - */ - - /* disable transmitter */ - cntl.action = TRANSMITTER_CONTROL_DISABLE; - cntl.transmitter = enc10->base.transmitter; - cntl.hpd_sel = enc10->base.hpd_source; - cntl.signal = signal; - cntl.connector_obj_id = enc10->base.connector; - - result = link_transmitter_control(enc10, &cntl); - - if (result != BP_RESULT_OK) { - DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", - __func__); - BREAK_TO_DEBUGGER(); - return; - } - - /* disable encoder */ - if (dc_is_dp_signal(signal)) - link_encoder_disable(enc10); -} - -void dcn10_link_encoder_dp_set_lane_settings( - struct link_encoder *enc, - const struct dc_link_settings *link_settings, - const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - union dpcd_training_lane_set training_lane_set = { { 0 } }; - int32_t lane = 0; - struct bp_transmitter_control cntl = { 0 }; - - if (!link_settings) { - BREAK_TO_DEBUGGER(); - return; - } - - cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; - cntl.transmitter = enc10->base.transmitter; - cntl.connector_obj_id = enc10->base.connector; - cntl.lanes_number = link_settings->lane_count; - cntl.hpd_sel = enc10->base.hpd_source; - cntl.pixel_clock = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; - - for (lane = 0; lane < link_settings->lane_count; lane++) { - /* translate lane settings */ - - training_lane_set.bits.VOLTAGE_SWING_SET = - lane_settings[lane].VOLTAGE_SWING; - training_lane_set.bits.PRE_EMPHASIS_SET = - lane_settings[lane].PRE_EMPHASIS; - - /* post cursor 2 setting only applies to HBR2 link rate */ - if (link_settings->link_rate == LINK_RATE_HIGH2) { - /* this is passed to VBIOS - * to program post cursor 2 level - */ - training_lane_set.bits.POST_CURSOR2_SET = - lane_settings[lane].POST_CURSOR2; - } - - cntl.lane_select = lane; - cntl.lane_settings = training_lane_set.raw; - - /* call VBIOS table to set voltage swing and pre-emphasis */ - link_transmitter_control(enc10, &cntl); - } -} - -/* set DP PHY test and training patterns */ -void dcn10_link_encoder_dp_set_phy_pattern( - struct link_encoder *enc, - const struct encoder_set_dp_phy_pattern_param *param) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - switch (param->dp_phy_pattern) { - case DP_TEST_PATTERN_TRAINING_PATTERN1: - dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); - break; - case DP_TEST_PATTERN_TRAINING_PATTERN2: - dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); - break; - case DP_TEST_PATTERN_TRAINING_PATTERN3: - dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); - break; - case DP_TEST_PATTERN_TRAINING_PATTERN4: - dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); - break; - case DP_TEST_PATTERN_D102: - set_dp_phy_pattern_d102(enc10); - break; - case DP_TEST_PATTERN_SYMBOL_ERROR: - set_dp_phy_pattern_symbol_error(enc10); - break; - case DP_TEST_PATTERN_PRBS7: - set_dp_phy_pattern_prbs7(enc10); - break; - case DP_TEST_PATTERN_80BIT_CUSTOM: - set_dp_phy_pattern_80bit_custom( - enc10, param->custom_pattern); - break; - case DP_TEST_PATTERN_CP2520_1: - set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 1); - break; - case DP_TEST_PATTERN_CP2520_2: - set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 2); - break; - case DP_TEST_PATTERN_CP2520_3: - set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 3); - break; - case DP_TEST_PATTERN_VIDEO_MODE: { - set_dp_phy_pattern_passthrough_mode( - enc10, param->dp_panel_mode); - break; - } - - default: - /* invalid phy pattern */ - ASSERT_CRITICAL(false); - break; - } -} - -static void fill_stream_allocation_row_info( - const struct link_mst_stream_allocation *stream_allocation, - uint32_t *src, - uint32_t *slots) -{ - const struct stream_encoder *stream_enc = stream_allocation->stream_enc; - - if (stream_enc) { - *src = stream_enc->id; - *slots = stream_allocation->slot_count; - } else { - *src = 0; - *slots = 0; - } -} - -/* programs DP MST VC payload allocation */ -void dcn10_link_encoder_update_mst_stream_allocation_table( - struct link_encoder *enc, - const struct link_mst_stream_allocation_table *table) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - uint32_t value1 = 0; - uint32_t value2 = 0; - uint32_t slots = 0; - uint32_t src = 0; - uint32_t retries = 0; - - /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/ - - /* --- Set MSE Stream Attribute - - * Setup VC Payload Table on Tx Side, - * Issue allocation change trigger - * to commit payload on both tx and rx side - */ - - /* we should clean-up table each time */ - - if (table->stream_count >= 1) { - fill_stream_allocation_row_info( - &table->stream_allocations[0], - &src, - &slots); - } else { - src = 0; - slots = 0; - } - - REG_UPDATE_2(DP_MSE_SAT0, - DP_MSE_SAT_SRC0, src, - DP_MSE_SAT_SLOT_COUNT0, slots); - - if (table->stream_count >= 2) { - fill_stream_allocation_row_info( - &table->stream_allocations[1], - &src, - &slots); - } else { - src = 0; - slots = 0; - } - - REG_UPDATE_2(DP_MSE_SAT0, - DP_MSE_SAT_SRC1, src, - DP_MSE_SAT_SLOT_COUNT1, slots); - - if (table->stream_count >= 3) { - fill_stream_allocation_row_info( - &table->stream_allocations[2], - &src, - &slots); - } else { - src = 0; - slots = 0; - } - - REG_UPDATE_2(DP_MSE_SAT1, - DP_MSE_SAT_SRC2, src, - DP_MSE_SAT_SLOT_COUNT2, slots); - - if (table->stream_count >= 4) { - fill_stream_allocation_row_info( - &table->stream_allocations[3], - &src, - &slots); - } else { - src = 0; - slots = 0; - } - - REG_UPDATE_2(DP_MSE_SAT1, - DP_MSE_SAT_SRC3, src, - DP_MSE_SAT_SLOT_COUNT3, slots); - - /* --- wait for transaction finish */ - - /* send allocation change trigger (ACT) ? - * this step first sends the ACT, - * then double buffers the SAT into the hardware - * making the new allocation active on the DP MST mode link - */ - - /* DP_MSE_SAT_UPDATE: - * 0 - No Action - * 1 - Update SAT with trigger - * 2 - Update SAT without trigger - */ - REG_UPDATE(DP_MSE_SAT_UPDATE, - DP_MSE_SAT_UPDATE, 1); - - /* wait for update to complete - * (i.e. DP_MSE_SAT_UPDATE field is reset to 0) - * then wait for the transmission - * of at least 16 MTP headers on immediate local link. - * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0 - * a value of 1 indicates that DP MST mode - * is in the 16 MTP keepout region after a VC has been added. - * MST stream bandwidth (VC rate) can be configured - * after this bit is cleared - */ - do { - udelay(10); - - REG_READ(DP_MSE_SAT_UPDATE); - - REG_GET(DP_MSE_SAT_UPDATE, - DP_MSE_SAT_UPDATE, &value1); - - REG_GET(DP_MSE_SAT_UPDATE, - DP_MSE_16_MTP_KEEPOUT, &value2); - - /* bit field DP_MSE_SAT_UPDATE is set to 1 already */ - if (!value1 && !value2) - break; - ++retries; - } while (retries < DP_MST_UPDATE_MAX_RETRY); -} - -void dcn10_link_encoder_connect_dig_be_to_fe( - struct link_encoder *enc, - enum engine_id engine, - bool connect) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - uint32_t field; - - if (engine != ENGINE_ID_UNKNOWN) { - - REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); - - if (connect) - field |= get_frontend_source(engine); - else - field &= ~get_frontend_source(engine); - - REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field); - } -} - - -#define HPD_REG(reg)\ - (enc10->hpd_regs->reg) - -#define HPD_REG_READ(reg_name) \ - dm_read_reg(CTX, HPD_REG(reg_name)) - -#define HPD_REG_UPDATE_N(reg_name, n, ...) \ - generic_reg_update_ex(CTX, \ - HPD_REG(reg_name), \ - n, __VA_ARGS__) - -#define HPD_REG_UPDATE(reg_name, field, val) \ - HPD_REG_UPDATE_N(reg_name, 1, \ - FN(reg_name, field), val) - -void dcn10_link_encoder_enable_hpd(struct link_encoder *enc) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - HPD_REG_UPDATE(DC_HPD_CONTROL, - DC_HPD_EN, 1); -} - -void dcn10_link_encoder_disable_hpd(struct link_encoder *enc) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - HPD_REG_UPDATE(DC_HPD_CONTROL, - DC_HPD_EN, 0); -} - -#define AUX_REG(reg)\ - (enc10->aux_regs->reg) - -#define AUX_REG_READ(reg_name) \ - dm_read_reg(CTX, AUX_REG(reg_name)) - -#define AUX_REG_UPDATE_N(reg_name, n, ...) \ - generic_reg_update_ex(CTX, \ - AUX_REG(reg_name), \ - n, __VA_ARGS__) - -#define AUX_REG_UPDATE(reg_name, field, val) \ - AUX_REG_UPDATE_N(reg_name, 1, \ - FN(reg_name, field), val) - -#define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \ - AUX_REG_UPDATE_N(reg, 2,\ - FN(reg, f1), v1,\ - FN(reg, f2), v2) - -void dcn10_aux_initialize(struct dcn10_link_encoder *enc10) -{ - enum hpd_source_id hpd_source = enc10->base.hpd_source; - - AUX_REG_UPDATE_2(AUX_CONTROL, - AUX_HPD_SEL, hpd_source, - AUX_LS_READ_EN, 0); - - /* 1/4 window (the maximum allowed) */ - AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0, - AUX_RX_RECEIVE_WINDOW, 0); -} - -enum signal_type dcn10_get_dig_mode( - struct link_encoder *enc) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - uint32_t value; - REG_GET(DIG_BE_CNTL, DIG_MODE, &value); - switch (value) { - case 1: - return SIGNAL_TYPE_DISPLAY_PORT; - case 2: - return SIGNAL_TYPE_DVI_SINGLE_LINK; - case 3: - return SIGNAL_TYPE_HDMI_TYPE_A; - case 5: - return SIGNAL_TYPE_DISPLAY_PORT_MST; - default: - return SIGNAL_TYPE_NONE; - } -} - -void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc, - struct dc_link_settings *link_settings) -{ - /* Set Default link settings */ - struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH, - LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0}; - - /* Higher link settings based on feature supported */ - if (enc->features.flags.bits.IS_HBR2_CAPABLE) - max_link_cap.link_rate = LINK_RATE_HIGH2; - - if (enc->features.flags.bits.IS_HBR3_CAPABLE) - max_link_cap.link_rate = LINK_RATE_HIGH3; - - if (enc->features.flags.bits.IS_UHBR10_CAPABLE) - max_link_cap.link_rate = LINK_RATE_UHBR10; - - if (enc->features.flags.bits.IS_UHBR13_5_CAPABLE) - max_link_cap.link_rate = LINK_RATE_UHBR13_5; - - if (enc->features.flags.bits.IS_UHBR20_CAPABLE) - max_link_cap.link_rate = LINK_RATE_UHBR20; - - *link_settings = max_link_cap; -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h deleted file mode 100644 index b7a89c39f445..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +++ /dev/null @@ -1,659 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_LINK_ENCODER__DCN10_H__ -#define __DC_LINK_ENCODER__DCN10_H__ - -#include "link_encoder.h" - -#define TO_DCN10_LINK_ENC(link_encoder)\ - container_of(link_encoder, struct dcn10_link_encoder, base) - -#define AUX_REG_LIST(id)\ - SRI(AUX_CONTROL, DP_AUX, id), \ - SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \ - SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id) - -#define HPD_REG_LIST(id)\ - SRI(DC_HPD_CONTROL, HPD, id) - -#define LE_DCN_COMMON_REG_LIST(id) \ - SRI(DIG_BE_CNTL, DIG, id), \ - SRI(DIG_BE_EN_CNTL, DIG, id), \ - SRI(DIG_CLOCK_PATTERN, DIG, id), \ - SRI(TMDS_CTL_BITS, DIG, id), \ - SRI(DP_CONFIG, DP, id), \ - SRI(DP_DPHY_CNTL, DP, id), \ - SRI(DP_DPHY_PRBS_CNTL, DP, id), \ - SRI(DP_DPHY_SCRAM_CNTL, DP, id),\ - SRI(DP_DPHY_SYM0, DP, id), \ - SRI(DP_DPHY_SYM1, DP, id), \ - SRI(DP_DPHY_SYM2, DP, id), \ - SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \ - SRI(DP_LINK_CNTL, DP, id), \ - SRI(DP_LINK_FRAMING_CNTL, DP, id), \ - SRI(DP_MSE_SAT0, DP, id), \ - SRI(DP_MSE_SAT1, DP, id), \ - SRI(DP_MSE_SAT2, DP, id), \ - SRI(DP_MSE_SAT_UPDATE, DP, id), \ - SRI(DP_SEC_CNTL, DP, id), \ - SRI(DP_VID_STREAM_CNTL, DP, id), \ - SRI(DP_DPHY_FAST_TRAINING, DP, id), \ - SRI(DP_SEC_CNTL1, DP, id), \ - SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ - SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) - - -#define LE_DCN10_REG_LIST(id)\ - SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - LE_DCN_COMMON_REG_LIST(id) - -struct dcn10_link_enc_aux_registers { - uint32_t AUX_CONTROL; - uint32_t AUX_DPHY_RX_CONTROL0; - uint32_t AUX_DPHY_TX_CONTROL; - uint32_t AUX_DPHY_RX_CONTROL1; -}; - -struct dcn10_link_enc_hpd_registers { - uint32_t DC_HPD_CONTROL; -}; - -struct dcn10_link_enc_registers { - uint32_t DIG_BE_CNTL; - uint32_t DIG_BE_EN_CNTL; - uint32_t DIG_CLOCK_PATTERN; - uint32_t DP_CONFIG; - uint32_t DP_DPHY_CNTL; - uint32_t DP_DPHY_INTERNAL_CTRL; - uint32_t DP_DPHY_PRBS_CNTL; - uint32_t DP_DPHY_SCRAM_CNTL; - uint32_t DP_DPHY_SYM0; - uint32_t DP_DPHY_SYM1; - uint32_t DP_DPHY_SYM2; - uint32_t DP_DPHY_TRAINING_PATTERN_SEL; - uint32_t DP_LINK_CNTL; - uint32_t DP_LINK_FRAMING_CNTL; - uint32_t DP_MSE_SAT0; - uint32_t DP_MSE_SAT1; - uint32_t DP_MSE_SAT2; - uint32_t DP_MSE_SAT_UPDATE; - uint32_t DP_SEC_CNTL; - uint32_t DP_VID_STREAM_CNTL; - uint32_t DP_DPHY_FAST_TRAINING; - uint32_t DP_DPHY_BS_SR_SWAP_CNTL; - uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; - uint32_t DP_SEC_CNTL1; - uint32_t TMDS_CTL_BITS; - /* DCCG */ - uint32_t CLOCK_ENABLE; - /* DIG */ - uint32_t DIG_LANE_ENABLE; - /* UNIPHY */ - uint32_t CHANNEL_XBAR_CNTL; - /* DPCS */ - uint32_t RDPCSTX_PHY_CNTL3; - uint32_t RDPCSTX_PHY_CNTL4; - uint32_t RDPCSTX_PHY_CNTL5; - uint32_t RDPCSTX_PHY_CNTL6; - uint32_t RDPCSPIPE_PHY_CNTL6; - uint32_t RDPCSTX_PHY_CNTL7; - uint32_t RDPCSTX_PHY_CNTL8; - uint32_t RDPCSTX_PHY_CNTL9; - uint32_t RDPCSTX_PHY_CNTL10; - uint32_t RDPCSTX_PHY_CNTL11; - uint32_t RDPCSTX_PHY_CNTL12; - uint32_t RDPCSTX_PHY_CNTL13; - uint32_t RDPCSTX_PHY_CNTL14; - uint32_t RDPCSTX_PHY_CNTL15; - uint32_t RDPCSTX_CNTL; - uint32_t RDPCSTX_CLOCK_CNTL; - uint32_t RDPCSTX_PHY_CNTL0; - uint32_t RDPCSTX_PHY_CNTL2; - uint32_t RDPCSTX_PLL_UPDATE_DATA; - uint32_t RDPCS_TX_CR_ADDR; - uint32_t RDPCS_TX_CR_DATA; - uint32_t DPCSTX_TX_CLOCK_CNTL; - uint32_t DPCSTX_TX_CNTL; - uint32_t RDPCSTX_INTERRUPT_CONTROL; - uint32_t RDPCSTX_PHY_FUSE0; - uint32_t RDPCSTX_PHY_FUSE1; - uint32_t RDPCSTX_PHY_FUSE2; - uint32_t RDPCSTX_PHY_FUSE3; - uint32_t RDPCSTX_PHY_RX_LD_VAL; - uint32_t DPCSTX_DEBUG_CONFIG; - uint32_t RDPCSTX_DEBUG_CONFIG; - uint32_t RDPCSTX0_RDPCSTX_SCRATCH; - uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG; - uint32_t DCIO_SOFT_RESET; - /* indirect registers */ - uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2; - uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3; - uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2; - uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3; - uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2; - uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3; - uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2; - uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3; - uint32_t TMDS_DCBALANCER_CONTROL; - uint32_t PHYA_LINK_CNTL2; - uint32_t PHYB_LINK_CNTL2; - uint32_t PHYC_LINK_CNTL2; - uint32_t DIO_LINKA_CNTL; - uint32_t DIO_LINKB_CNTL; - uint32_t DIO_LINKC_CNTL; - uint32_t DIO_LINKD_CNTL; - uint32_t DIO_LINKE_CNTL; - uint32_t DIO_LINKF_CNTL; - uint32_t DIO_CLK_CNTL; - uint32_t DIG_BE_CLK_CNTL; -}; - -#define LE_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix - -#define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\ - LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\ - LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\ - LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\ - LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\ - LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\ - LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\ - LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\ - LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\ - LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\ - LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\ - LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\ - LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\ - LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\ - LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\ - LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\ - LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\ - LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\ - LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\ - LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ - LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\ - LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\ - LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\ - LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\ - LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\ - LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh) - -#define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \ - type DIG_ENABLE;\ - type DIG_HPD_SELECT;\ - type DIG_MODE;\ - type DIG_FE_SOURCE_SELECT;\ - type DIG_CLOCK_PATTERN;\ - type DPHY_BYPASS;\ - type DPHY_ATEST_SEL_LANE0;\ - type DPHY_ATEST_SEL_LANE1;\ - type DPHY_ATEST_SEL_LANE2;\ - type DPHY_ATEST_SEL_LANE3;\ - type DPHY_PRBS_EN;\ - type DPHY_PRBS_SEL;\ - type DPHY_SYM1;\ - type DPHY_SYM2;\ - type DPHY_SYM3;\ - type DPHY_SYM4;\ - type DPHY_SYM5;\ - type DPHY_SYM6;\ - type DPHY_SYM7;\ - type DPHY_SYM8;\ - type DPHY_SCRAMBLER_BS_COUNT;\ - type DPHY_SCRAMBLER_ADVANCE;\ - type DPHY_RX_FAST_TRAINING_CAPABLE;\ - type DPHY_LOAD_BS_COUNT;\ - type DPHY_TRAINING_PATTERN_SEL;\ - type DP_DPHY_HBR2_PATTERN_CONTROL;\ - type DP_LINK_TRAINING_COMPLETE;\ - type DP_IDLE_BS_INTERVAL;\ - type DP_VBID_DISABLE;\ - type DP_VID_ENHANCED_FRAME_MODE;\ - type DP_VID_STREAM_ENABLE;\ - type DP_UDI_LANES;\ - type DP_SEC_GSP0_LINE_NUM;\ - type DP_SEC_GSP0_PRIORITY;\ - type DP_MSE_SAT_SRC0;\ - type DP_MSE_SAT_SRC1;\ - type DP_MSE_SAT_SRC2;\ - type DP_MSE_SAT_SRC3;\ - type DP_MSE_SAT_SLOT_COUNT0;\ - type DP_MSE_SAT_SLOT_COUNT1;\ - type DP_MSE_SAT_SLOT_COUNT2;\ - type DP_MSE_SAT_SLOT_COUNT3;\ - type DP_MSE_SAT_UPDATE;\ - type DP_MSE_16_MTP_KEEPOUT;\ - type DC_HPD_EN;\ - type TMDS_CTL0;\ - type AUX_HPD_SEL;\ - type AUX_LS_READ_EN;\ - type AUX_RX_RECEIVE_WINDOW - - -#define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \ - type RDPCS_PHY_DP_TX0_DATA_EN;\ - type RDPCS_PHY_DP_TX1_DATA_EN;\ - type RDPCS_PHY_DP_TX2_DATA_EN;\ - type RDPCS_PHY_DP_TX3_DATA_EN;\ - type RDPCS_PHY_DP_TX0_PSTATE;\ - type RDPCS_PHY_DP_TX1_PSTATE;\ - type RDPCS_PHY_DP_TX2_PSTATE;\ - type RDPCS_PHY_DP_TX3_PSTATE;\ - type RDPCS_PHY_DP_TX0_MPLL_EN;\ - type RDPCS_PHY_DP_TX1_MPLL_EN;\ - type RDPCS_PHY_DP_TX2_MPLL_EN;\ - type RDPCS_PHY_DP_TX3_MPLL_EN;\ - type RDPCS_TX_FIFO_LANE0_EN;\ - type RDPCS_TX_FIFO_LANE1_EN;\ - type RDPCS_TX_FIFO_LANE2_EN;\ - type RDPCS_TX_FIFO_LANE3_EN;\ - type RDPCS_EXT_REFCLK_EN;\ - type RDPCS_TX_FIFO_EN;\ - type UNIPHY_LINK_ENABLE;\ - type UNIPHY_CHANNEL0_XBAR_SOURCE;\ - type UNIPHY_CHANNEL1_XBAR_SOURCE;\ - type UNIPHY_CHANNEL2_XBAR_SOURCE;\ - type UNIPHY_CHANNEL3_XBAR_SOURCE;\ - type UNIPHY_CHANNEL0_INVERT;\ - type UNIPHY_CHANNEL1_INVERT;\ - type UNIPHY_CHANNEL2_INVERT;\ - type UNIPHY_CHANNEL3_INVERT;\ - type UNIPHY_LINK_ENABLE_HPD_MASK;\ - type UNIPHY_LANE_STAGGER_DELAY;\ - type RDPCS_SRAMCLK_BYPASS;\ - type RDPCS_SRAMCLK_EN;\ - type RDPCS_SRAMCLK_CLOCK_ON;\ - type DPCS_TX_FIFO_EN;\ - type RDPCS_PHY_DP_TX0_DISABLE;\ - type RDPCS_PHY_DP_TX1_DISABLE;\ - type RDPCS_PHY_DP_TX2_DISABLE;\ - type RDPCS_PHY_DP_TX3_DISABLE;\ - type RDPCS_PHY_DP_TX0_CLK_RDY;\ - type RDPCS_PHY_DP_TX1_CLK_RDY;\ - type RDPCS_PHY_DP_TX2_CLK_RDY;\ - type RDPCS_PHY_DP_TX3_CLK_RDY;\ - type RDPCS_PHY_DP_TX0_REQ;\ - type RDPCS_PHY_DP_TX1_REQ;\ - type RDPCS_PHY_DP_TX2_REQ;\ - type RDPCS_PHY_DP_TX3_REQ;\ - type RDPCS_PHY_DP_TX0_ACK;\ - type RDPCS_PHY_DP_TX1_ACK;\ - type RDPCS_PHY_DP_TX2_ACK;\ - type RDPCS_PHY_DP_TX3_ACK;\ - type RDPCS_PHY_DP_TX0_RESET;\ - type RDPCS_PHY_DP_TX1_RESET;\ - type RDPCS_PHY_DP_TX2_RESET;\ - type RDPCS_PHY_DP_TX3_RESET;\ - type RDPCS_PHY_RESET;\ - type RDPCS_PHY_CR_MUX_SEL;\ - type RDPCS_PHY_REF_RANGE;\ - type RDPCS_PHY_DP4_POR;\ - type RDPCS_SRAM_BYPASS;\ - type RDPCS_SRAM_EXT_LD_DONE;\ - type RDPCS_PHY_DP_TX0_TERM_CTRL;\ - type RDPCS_PHY_DP_TX1_TERM_CTRL;\ - type RDPCS_PHY_DP_TX2_TERM_CTRL;\ - type RDPCS_PHY_DP_TX3_TERM_CTRL;\ - type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\ - type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\ - type RDPCS_PHY_DP_MPLLB_SSC_EN;\ - type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\ - type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\ - type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\ - type RDPCS_PHY_DP_MPLLB_FRACN_EN;\ - type RDPCS_PHY_DP_MPLLB_PMIX_EN;\ - type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\ - type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\ - type RDPCS_PHY_DP_MPLLB_FRACN_REM;\ - type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\ - type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\ - type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\ - type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\ - type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\ - type RDPCS_PHY_TX_VBOOST_LVL;\ - type RDPCS_PHY_HDMIMODE_ENABLE;\ - type RDPCS_PHY_DP_REF_CLK_EN;\ - type RDPCS_PLL_UPDATE_DATA;\ - type RDPCS_SRAM_INIT_DONE;\ - type RDPCS_TX_CR_ADDR;\ - type RDPCS_TX_CR_DATA;\ - type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\ - type RDPCS_PHY_DP_MPLLB_STATE;\ - type RDPCS_PHY_DP_TX0_WIDTH;\ - type RDPCS_PHY_DP_TX0_RATE;\ - type RDPCS_PHY_DP_TX1_WIDTH;\ - type RDPCS_PHY_DP_TX1_RATE;\ - type RDPCS_PHY_DP_TX2_WIDTH;\ - type RDPCS_PHY_DP_TX2_RATE;\ - type RDPCS_PHY_DP_TX3_WIDTH;\ - type RDPCS_PHY_DP_TX3_RATE;\ - type DPCS_SYMCLK_CLOCK_ON;\ - type DPCS_SYMCLK_GATE_DIS;\ - type DPCS_SYMCLK_EN;\ - type RDPCS_SYMCLK_DIV2_CLOCK_ON;\ - type RDPCS_SYMCLK_DIV2_GATE_DIS;\ - type RDPCS_SYMCLK_DIV2_EN;\ - type DPCS_TX_DATA_SWAP;\ - type DPCS_TX_DATA_ORDER_INVERT;\ - type DPCS_TX_FIFO_RD_START_DELAY;\ - type RDPCS_TX_FIFO_RD_START_DELAY;\ - type RDPCS_REG_FIFO_ERROR_MASK;\ - type RDPCS_TX_FIFO_ERROR_MASK;\ - type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\ - type RDPCS_DPALT_4LANE_TOGGLE_MASK;\ - type RDPCS_PHY_DPALT_DP4;\ - type RDPCS_PHY_DPALT_DISABLE;\ - type RDPCS_PHY_DPALT_DISABLE_ACK;\ - type RDPCS_PHY_DP_MPLLB_V2I;\ - type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\ - type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\ - type RDPCS_PHY_RX_VREF_CTRL;\ - type RDPCS_PHY_DP_MPLLB_CP_INT;\ - type RDPCS_PHY_DP_MPLLB_CP_PROP;\ - type RDPCS_PHY_RX_REF_LD_VAL;\ - type RDPCS_PHY_RX_VCO_LD_VAL;\ - type DPCSTX_DEBUG_CONFIG; \ - type RDPCSTX_DEBUG_CONFIG; \ - type RDPCS_PHY_DP_TX0_EQ_MAIN;\ - type RDPCS_PHY_DP_TX0_EQ_PRE;\ - type RDPCS_PHY_DP_TX0_EQ_POST;\ - type RDPCS_PHY_DP_TX1_EQ_MAIN;\ - type RDPCS_PHY_DP_TX1_EQ_PRE;\ - type RDPCS_PHY_DP_TX1_EQ_POST;\ - type RDPCS_PHY_DP_TX2_EQ_MAIN;\ - type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\ - type RDPCS_PHY_DP_TX2_EQ_PRE;\ - type RDPCS_PHY_DP_TX2_EQ_POST;\ - type RDPCS_PHY_DP_TX3_EQ_MAIN;\ - type RDPCS_PHY_DCO_RANGE;\ - type RDPCS_PHY_DCO_FINETUNE;\ - type RDPCS_PHY_DP_TX3_EQ_PRE;\ - type RDPCS_PHY_DP_TX3_EQ_POST;\ - type RDPCS_PHY_SUP_PRE_HP;\ - type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\ - type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\ - type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\ - type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\ - type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\ - type UNIPHYA_SOFT_RESET;\ - type UNIPHYB_SOFT_RESET;\ - type UNIPHYC_SOFT_RESET;\ - type UNIPHYD_SOFT_RESET;\ - type UNIPHYE_SOFT_RESET;\ - type UNIPHYF_SOFT_RESET - -#define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \ - type DIG_LANE0EN;\ - type DIG_LANE1EN;\ - type DIG_LANE2EN;\ - type DIG_LANE3EN;\ - type DIG_CLK_EN;\ - type SYMCLKA_CLOCK_ENABLE;\ - type DPHY_FEC_EN;\ - type DPHY_FEC_READY_SHADOW;\ - type DPHY_FEC_ACTIVE_STATUS;\ - DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\ - type VCO_LD_VAL_OVRD;\ - type VCO_LD_VAL_OVRD_EN;\ - type REF_LD_VAL_OVRD;\ - type REF_LD_VAL_OVRD_EN;\ - type AUX_RX_START_WINDOW; \ - type AUX_RX_HALF_SYM_DETECT_LEN; \ - type AUX_RX_TRANSITION_FILTER_EN; \ - type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \ - type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \ - type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \ - type AUX_RX_PHASE_DETECT_LEN; \ - type AUX_RX_DETECTION_THRESHOLD; \ - type AUX_TX_PRECHARGE_LEN; \ - type AUX_TX_PRECHARGE_SYMBOLS; \ - type AUX_MODE_DET_CHECK_DELAY;\ - type DPCS_DBG_CBUS_DIS;\ - type AUX_RX_PRECHARGE_SKIP;\ - type AUX_RX_TIMEOUT_LEN;\ - type AUX_RX_TIMEOUT_LEN_MUL - -#define DCN30_LINK_ENCODER_REG_FIELD_LIST(type) \ - type TMDS_SYNC_DCBAL_EN;\ - type PHY_HPO_DIG_SRC_SEL;\ - type PHY_HPO_ENC_SRC_SEL;\ - type DPCS_TX_HDMI_FRL_MODE;\ - type DPCS_TX_DATA_SWAP_10_BIT;\ - type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\ - type RDPCS_TX_CLK_EN - -#define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \ - type ENC_TYPE_SEL;\ - type HPO_DP_ENC_SEL;\ - type HPO_HDMI_ENC_SEL - -#define DCN35_LINK_ENCODER_REG_FIELD_LIST(type) \ - type DIG_BE_ENABLE;\ - type DIG_RB_SWITCH_EN;\ - type DIG_BE_MODE;\ - type DIG_BE_CLK_EN;\ - type DIG_BE_SOFT_RESET;\ - type HDCP_SOFT_RESET;\ - type DIG_BE_SYMCLK_G_CLOCK_ON;\ - type DIG_BE_SYMCLK_G_HDCP_CLOCK_ON;\ - type DIG_BE_SYMCLK_G_TMDS_CLOCK_ON;\ - type DISPCLK_R_GATE_DIS;\ - type DISPCLK_G_GATE_DIS;\ - type REFCLK_R_GATE_DIS;\ - type REFCLK_G_GATE_DIS;\ - type SOCCLK_G_GATE_DIS;\ - type SYMCLK_FE_R_GATE_DIS;\ - type SYMCLK_FE_G_GATE_DIS;\ - type SYMCLK_R_GATE_DIS;\ - type SYMCLK_G_GATE_DIS;\ - type DIO_FGCG_REP_DIS;\ - type DISPCLK_G_HDCP_GATE_DIS;\ - type SYMCLKA_G_HDCP_GATE_DIS;\ - type SYMCLKB_G_HDCP_GATE_DIS;\ - type SYMCLKC_G_HDCP_GATE_DIS;\ - type SYMCLKD_G_HDCP_GATE_DIS;\ - type SYMCLKE_G_HDCP_GATE_DIS;\ - type SYMCLKF_G_HDCP_GATE_DIS;\ - type SYMCLKG_G_HDCP_GATE_DIS - -struct dcn10_link_enc_shift { - DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t); - DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t); - DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t); - DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t); - DCN35_LINK_ENCODER_REG_FIELD_LIST(uint8_t); -}; - -struct dcn10_link_enc_mask { - DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t); - DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t); - DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t); - DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t); - DCN35_LINK_ENCODER_REG_FIELD_LIST(uint32_t); -}; - -struct dcn10_link_encoder { - struct link_encoder base; - const struct dcn10_link_enc_registers *link_regs; - const struct dcn10_link_enc_aux_registers *aux_regs; - const struct dcn10_link_enc_hpd_registers *hpd_regs; - const struct dcn10_link_enc_shift *link_shift; - const struct dcn10_link_enc_mask *link_mask; -}; - - -void dcn10_link_encoder_construct( - struct dcn10_link_encoder *enc10, - const struct encoder_init_data *init_data, - const struct encoder_feature_support *enc_features, - const struct dcn10_link_enc_registers *link_regs, - const struct dcn10_link_enc_aux_registers *aux_regs, - const struct dcn10_link_enc_hpd_registers *hpd_regs, - const struct dcn10_link_enc_shift *link_shift, - const struct dcn10_link_enc_mask *link_mask); - -bool dcn10_link_encoder_validate_dvi_output( - const struct dcn10_link_encoder *enc10, - enum signal_type connector_signal, - enum signal_type signal, - const struct dc_crtc_timing *crtc_timing); - -bool dcn10_link_encoder_validate_rgb_output( - const struct dcn10_link_encoder *enc10, - const struct dc_crtc_timing *crtc_timing); - -bool dcn10_link_encoder_validate_dp_output( - const struct dcn10_link_encoder *enc10, - const struct dc_crtc_timing *crtc_timing); - -bool dcn10_link_encoder_validate_wireless_output( - const struct dcn10_link_encoder *enc10, - const struct dc_crtc_timing *crtc_timing); - -bool dcn10_link_encoder_validate_output_with_stream( - struct link_encoder *enc, - const struct dc_stream_state *stream); - -/****************** HW programming ************************/ - -/* initialize HW */ /* why do we initialze aux in here? */ -void dcn10_link_encoder_hw_init(struct link_encoder *enc); - -void dcn10_link_encoder_destroy(struct link_encoder **enc); - -/* program DIG_MODE in DIG_BE */ -/* TODO can this be combined with enable_output? */ -void dcn10_link_encoder_setup( - struct link_encoder *enc, - enum signal_type signal); - -void enc1_configure_encoder( - struct dcn10_link_encoder *enc10, - const struct dc_link_settings *link_settings); - -/* enables TMDS PHY output */ -/* TODO: still need depth or just pass in adjusted pixel clock? */ -void dcn10_link_encoder_enable_tmds_output( - struct link_encoder *enc, - enum clock_source_id clock_source, - enum dc_color_depth color_depth, - enum signal_type signal, - uint32_t pixel_clock); - -void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa( - struct link_encoder *enc, - enum clock_source_id clock_source, - enum dc_color_depth color_depth, - enum signal_type signal, - uint32_t pixel_clock); - -/* enables DP PHY output */ -void dcn10_link_encoder_enable_dp_output( - struct link_encoder *enc, - const struct dc_link_settings *link_settings, - enum clock_source_id clock_source); - -/* enables DP PHY output in MST mode */ -void dcn10_link_encoder_enable_dp_mst_output( - struct link_encoder *enc, - const struct dc_link_settings *link_settings, - enum clock_source_id clock_source); - -/* disable PHY output */ -void dcn10_link_encoder_disable_output( - struct link_encoder *enc, - enum signal_type signal); - -/* set DP lane settings */ -void dcn10_link_encoder_dp_set_lane_settings( - struct link_encoder *enc, - const struct dc_link_settings *link_settings, - const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); - -void dcn10_link_encoder_dp_set_phy_pattern( - struct link_encoder *enc, - const struct encoder_set_dp_phy_pattern_param *param); - -/* programs DP MST VC payload allocation */ -void dcn10_link_encoder_update_mst_stream_allocation_table( - struct link_encoder *enc, - const struct link_mst_stream_allocation_table *table); - -void dcn10_link_encoder_connect_dig_be_to_fe( - struct link_encoder *enc, - enum engine_id engine, - bool connect); - -void dcn10_link_encoder_set_dp_phy_pattern_training_pattern( - struct link_encoder *enc, - uint32_t index); - -void dcn10_link_encoder_enable_hpd(struct link_encoder *enc); - -void dcn10_link_encoder_disable_hpd(struct link_encoder *enc); - -void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc, - bool exit_link_training_required); - -void dcn10_psr_program_secondary_packet(struct link_encoder *enc, - unsigned int sdp_transmit_line_num_deadline); - -bool dcn10_is_dig_enabled(struct link_encoder *enc); - -unsigned int dcn10_get_dig_frontend(struct link_encoder *enc); - -void dcn10_aux_initialize(struct dcn10_link_encoder *enc10); - -enum signal_type dcn10_get_dig_mode( - struct link_encoder *enc); - -void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc, - struct dc_link_settings *link_settings); -#endif /* __DC_LINK_ENCODER__DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c deleted file mode 100644 index f496e952ceec..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +++ /dev/null @@ -1,1628 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "dc_bios_types.h" -#include "dcn10_stream_encoder.h" -#include "reg_helper.h" -#include "hw_shared.h" -#include "link.h" -#include "dpcd_defs.h" -#include "dcn30/dcn30_afmt.h" - -#define DC_LOGGER \ - enc1->base.ctx->logger - -#define REG(reg)\ - (enc1->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - enc1->se_shift->field_name, enc1->se_mask->field_name - -#define VBI_LINE_0 0 -#define DP_BLANK_MAX_RETRY 20 -#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 - - -enum { - DP_MST_UPDATE_MAX_RETRY = 50 -}; - -#define CTX \ - enc1->base.ctx - -void enc1_update_generic_info_packet( - struct dcn10_stream_encoder *enc1, - uint32_t packet_index, - const struct dc_info_packet *info_packet) -{ - /* TODOFPGA Figure out a proper number for max_retries polling for lock - * use 50 for now. - */ - uint32_t max_retries = 50; - - /*we need turn on clock before programming AFMT block*/ - REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); - - if (packet_index >= 8) - ASSERT(0); - - /* poll dig_update_lock is not locked -> asic internal signal - * assume otg master lock will unlock it - */ -/* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, - 0, 10, max_retries);*/ - - /* check if HW reading GSP memory */ - REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, - 0, 10, max_retries); - - /* HW does is not reading GSP memory not reading too long -> - * something wrong. clear GPS memory access and notify? - * hw SW is writing to GSP memory - */ - REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); - - /* choose which generic packet to use */ - REG_UPDATE(AFMT_VBI_PACKET_CONTROL, - AFMT_GENERIC_INDEX, packet_index); - - /* write generic packet header - * (4th byte is for GENERIC0 only) - */ - REG_SET_4(AFMT_GENERIC_HDR, 0, - AFMT_GENERIC_HB0, info_packet->hb0, - AFMT_GENERIC_HB1, info_packet->hb1, - AFMT_GENERIC_HB2, info_packet->hb2, - AFMT_GENERIC_HB3, info_packet->hb3); - - /* write generic packet contents - * (we never use last 4 bytes) - * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers - */ - { - const uint32_t *content = - (const uint32_t *) &info_packet->sb[0]; - - REG_WRITE(AFMT_GENERIC_0, *content++); - REG_WRITE(AFMT_GENERIC_1, *content++); - REG_WRITE(AFMT_GENERIC_2, *content++); - REG_WRITE(AFMT_GENERIC_3, *content++); - REG_WRITE(AFMT_GENERIC_4, *content++); - REG_WRITE(AFMT_GENERIC_5, *content++); - REG_WRITE(AFMT_GENERIC_6, *content++); - REG_WRITE(AFMT_GENERIC_7, *content); - } - - switch (packet_index) { - case 0: - REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC0_IMMEDIATE_UPDATE, 1); - break; - case 1: - REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC1_IMMEDIATE_UPDATE, 1); - break; - case 2: - REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC2_IMMEDIATE_UPDATE, 1); - break; - case 3: - REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC3_IMMEDIATE_UPDATE, 1); - break; - case 4: - REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC4_IMMEDIATE_UPDATE, 1); - break; - case 5: - REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC5_IMMEDIATE_UPDATE, 1); - break; - case 6: - REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC6_IMMEDIATE_UPDATE, 1); - break; - case 7: - REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC7_IMMEDIATE_UPDATE, 1); - break; - default: - break; - } -} - -static void enc1_update_hdmi_info_packet( - struct dcn10_stream_encoder *enc1, - uint32_t packet_index, - const struct dc_info_packet *info_packet) -{ - uint32_t cont, send, line; - - if (info_packet->valid) { - enc1_update_generic_info_packet( - enc1, - packet_index, - info_packet); - - /* enable transmission of packet(s) - - * packet transmission begins on the next frame - */ - cont = 1; - /* send packet(s) every frame */ - send = 1; - /* select line number to send packets on */ - line = 2; - } else { - cont = 0; - send = 0; - line = 0; - } - - /* choose which generic packet control to use */ - switch (packet_index) { - case 0: - REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, - HDMI_GENERIC0_CONT, cont, - HDMI_GENERIC0_SEND, send, - HDMI_GENERIC0_LINE, line); - break; - case 1: - REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, - HDMI_GENERIC1_CONT, cont, - HDMI_GENERIC1_SEND, send, - HDMI_GENERIC1_LINE, line); - break; - case 2: - REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, - HDMI_GENERIC0_CONT, cont, - HDMI_GENERIC0_SEND, send, - HDMI_GENERIC0_LINE, line); - break; - case 3: - REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, - HDMI_GENERIC1_CONT, cont, - HDMI_GENERIC1_SEND, send, - HDMI_GENERIC1_LINE, line); - break; - case 4: - REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, - HDMI_GENERIC0_CONT, cont, - HDMI_GENERIC0_SEND, send, - HDMI_GENERIC0_LINE, line); - break; - case 5: - REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, - HDMI_GENERIC1_CONT, cont, - HDMI_GENERIC1_SEND, send, - HDMI_GENERIC1_LINE, line); - break; - case 6: - REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, - HDMI_GENERIC0_CONT, cont, - HDMI_GENERIC0_SEND, send, - HDMI_GENERIC0_LINE, line); - break; - case 7: - REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, - HDMI_GENERIC1_CONT, cont, - HDMI_GENERIC1_SEND, send, - HDMI_GENERIC1_LINE, line); - break; - default: - /* invalid HW packet index */ - DC_LOG_WARNING( - "Invalid HW packet index: %s()\n", - __func__); - return; - } -} - -/* setup stream encoder in dp mode */ -void enc1_stream_encoder_dp_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing, - enum dc_color_space output_color_space, - bool use_vsc_sdp_for_colorimetry, - uint32_t enable_sdp_splitting) -{ - uint32_t h_active_start; - uint32_t v_active_start; - uint32_t misc0 = 0; - uint32_t misc1 = 0; - uint32_t h_blank; - uint32_t h_back_porch; - uint8_t synchronous_clock = 0; /* asynchronous mode */ - uint8_t colorimetry_bpc; - uint8_t dp_pixel_encoding = 0; - uint8_t dp_component_depth = 0; - - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - struct dc_crtc_timing hw_crtc_timing = *crtc_timing; - - if (hw_crtc_timing.flags.INTERLACE) { - /*the input timing is in VESA spec format with Interlace flag =1*/ - hw_crtc_timing.v_total /= 2; - hw_crtc_timing.v_border_top /= 2; - hw_crtc_timing.v_addressable /= 2; - hw_crtc_timing.v_border_bottom /= 2; - hw_crtc_timing.v_front_porch /= 2; - hw_crtc_timing.v_sync_width /= 2; - } - - - /* set pixel encoding */ - switch (hw_crtc_timing.pixel_encoding) { - case PIXEL_ENCODING_YCBCR422: - dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422; - break; - case PIXEL_ENCODING_YCBCR444: - dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444; - - if (hw_crtc_timing.flags.Y_ONLY) - if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) - /* HW testing only, no use case yet. - * Color depth of Y-only could be - * 8, 10, 12, 16 bits - */ - dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY; - - /* Note: DP_MSA_MISC1 bit 7 is the indicator - * of Y-only mode. - * This bit is set in HW if register - * DP_PIXEL_ENCODING is programmed to 0x4 - */ - break; - case PIXEL_ENCODING_YCBCR420: - dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420; - break; - default: - dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444; - break; - } - - misc1 = REG_READ(DP_MSA_MISC); - /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used. - * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the - * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7, - * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care"). - */ - if (use_vsc_sdp_for_colorimetry) - misc1 = misc1 | 0x40; - else - misc1 = misc1 & ~0x40; - - /* set color depth */ - switch (hw_crtc_timing.display_color_depth) { - case COLOR_DEPTH_666: - dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; - break; - case COLOR_DEPTH_888: - dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC; - break; - case COLOR_DEPTH_101010: - dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC; - break; - case COLOR_DEPTH_121212: - dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC; - break; - case COLOR_DEPTH_161616: - dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC; - break; - default: - dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; - break; - } - - /* Set DP pixel encoding and component depth */ - REG_UPDATE_2(DP_PIXEL_FORMAT, - DP_PIXEL_ENCODING, dp_pixel_encoding, - DP_COMPONENT_DEPTH, dp_component_depth); - - /* set dynamic range and YCbCr range */ - - switch (hw_crtc_timing.display_color_depth) { - case COLOR_DEPTH_666: - colorimetry_bpc = 0; - break; - case COLOR_DEPTH_888: - colorimetry_bpc = 1; - break; - case COLOR_DEPTH_101010: - colorimetry_bpc = 2; - break; - case COLOR_DEPTH_121212: - colorimetry_bpc = 3; - break; - default: - colorimetry_bpc = 0; - break; - } - - misc0 = misc0 | synchronous_clock; - misc0 = colorimetry_bpc << 5; - - switch (output_color_space) { - case COLOR_SPACE_SRGB: - misc1 = misc1 & ~0x80; /* bit7 = 0*/ - break; - case COLOR_SPACE_SRGB_LIMITED: - misc0 = misc0 | 0x8; /* bit3=1 */ - misc1 = misc1 & ~0x80; /* bit7 = 0*/ - break; - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YCBCR601_LIMITED: - misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ - misc1 = misc1 & ~0x80; /* bit7 = 0*/ - if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) - misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ - else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) - misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ - break; - case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YCBCR709_LIMITED: - misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ - misc1 = misc1 & ~0x80; /* bit7 = 0*/ - if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) - misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ - else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) - misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ - break; - case COLOR_SPACE_2020_RGB_LIMITEDRANGE: - case COLOR_SPACE_2020_RGB_FULLRANGE: - case COLOR_SPACE_2020_YCBCR: - case COLOR_SPACE_XR_RGB: - case COLOR_SPACE_MSREF_SCRGB: - case COLOR_SPACE_ADOBERGB: - case COLOR_SPACE_DCIP3: - case COLOR_SPACE_XV_YCC_709: - case COLOR_SPACE_XV_YCC_601: - case COLOR_SPACE_DISPLAYNATIVE: - case COLOR_SPACE_DOLBYVISION: - case COLOR_SPACE_APPCTRL: - case COLOR_SPACE_CUSTOMPOINTS: - case COLOR_SPACE_UNKNOWN: - case COLOR_SPACE_YCBCR709_BLACK: - /* do nothing */ - break; - } - - REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); - REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ - - /* dcn new register - * dc_crtc_timing is vesa dmt struct. data from edid - */ - REG_SET_2(DP_MSA_TIMING_PARAM1, 0, - DP_MSA_HTOTAL, hw_crtc_timing.h_total, - DP_MSA_VTOTAL, hw_crtc_timing.v_total); - - /* calculate from vesa timing parameters - * h_active_start related to leading edge of sync - */ - - h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - - hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; - - h_back_porch = h_blank - hw_crtc_timing.h_front_porch - - hw_crtc_timing.h_sync_width; - - /* start at beginning of left border */ - h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; - - - v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - - hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - - hw_crtc_timing.v_front_porch; - - - /* start at beginning of left border */ - REG_SET_2(DP_MSA_TIMING_PARAM2, 0, - DP_MSA_HSTART, h_active_start, - DP_MSA_VSTART, v_active_start); - - REG_SET_4(DP_MSA_TIMING_PARAM3, 0, - DP_MSA_HSYNCWIDTH, - hw_crtc_timing.h_sync_width, - DP_MSA_HSYNCPOLARITY, - !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, - DP_MSA_VSYNCWIDTH, - hw_crtc_timing.v_sync_width, - DP_MSA_VSYNCPOLARITY, - !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY); - - /* HWDITH include border or overscan */ - REG_SET_2(DP_MSA_TIMING_PARAM4, 0, - DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + - hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, - DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + - hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom); -} - -void enc1_stream_encoder_set_stream_attribute_helper( - struct dcn10_stream_encoder *enc1, - struct dc_crtc_timing *crtc_timing) -{ - switch (crtc_timing->pixel_encoding) { - case PIXEL_ENCODING_YCBCR422: - REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); - break; - default: - REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); - break; - } - REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); -} - -/* setup stream encoder in hdmi mode */ -void enc1_stream_encoder_hdmi_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing, - int actual_pix_clk_khz, - bool enable_audio) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - struct bp_encoder_control cntl = {0}; - - cntl.action = ENCODER_CONTROL_SETUP; - cntl.engine_id = enc1->base.id; - cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; - cntl.enable_dp_audio = enable_audio; - cntl.pixel_clock = actual_pix_clk_khz; - cntl.lanes_number = LANE_COUNT_FOUR; - - if (enc1->base.bp->funcs->encoder_control( - enc1->base.bp, &cntl) != BP_RESULT_OK) - return; - - enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); - - /* setup HDMI engine */ - REG_UPDATE_6(HDMI_CONTROL, - HDMI_PACKET_GEN_VERSION, 1, - HDMI_KEEPOUT_MODE, 1, - HDMI_DEEP_COLOR_ENABLE, 0, - HDMI_DATA_SCRAMBLE_EN, 0, - HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, - HDMI_CLOCK_CHANNEL_RATE, 0); - - - switch (crtc_timing->display_color_depth) { - case COLOR_DEPTH_888: - REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); - DC_LOG_DEBUG("HDMI source set to 24BPP deep color depth\n"); - break; - case COLOR_DEPTH_101010: - if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 1, - HDMI_DEEP_COLOR_ENABLE, 0); - DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \ - "disabled for YCBCR422 pixel encoding\n"); - } else { - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 1, - HDMI_DEEP_COLOR_ENABLE, 1); - DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \ - "enabled for YCBCR422 non-pixel encoding\n"); - } - break; - case COLOR_DEPTH_121212: - if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 2, - HDMI_DEEP_COLOR_ENABLE, 0); - DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \ - "disabled for YCBCR422 pixel encoding\n"); - } else { - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 2, - HDMI_DEEP_COLOR_ENABLE, 1); - DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \ - "enabled for non-pixel YCBCR422 encoding\n"); - } - break; - case COLOR_DEPTH_161616: - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 3, - HDMI_DEEP_COLOR_ENABLE, 1); - DC_LOG_DEBUG("HDMI source deep color depth enabled in" \ - "reserved mode\n"); - break; - default: - break; - } - - if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { - /* enable HDMI data scrambler - * HDMI_CLOCK_CHANNEL_RATE_MORE_340M - * Clock channel frequency is 1/4 of character rate. - */ - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DATA_SCRAMBLE_EN, 1, - HDMI_CLOCK_CHANNEL_RATE, 1); - } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { - - /* TODO: New feature for DCE11, still need to implement */ - - /* enable HDMI data scrambler - * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE - * Clock channel frequency is the same - * as character rate - */ - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DATA_SCRAMBLE_EN, 1, - HDMI_CLOCK_CHANNEL_RATE, 0); - } - - - REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, - HDMI_GC_CONT, 1, - HDMI_GC_SEND, 1, - HDMI_NULL_SEND, 1); - - REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); - - /* following belongs to audio */ - REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); - - REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); - - REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, - VBI_LINE_0 + 2); - - REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); -} - -/* setup stream encoder in dvi mode */ -void enc1_stream_encoder_dvi_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing, - bool is_dual_link) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - struct bp_encoder_control cntl = {0}; - - cntl.action = ENCODER_CONTROL_SETUP; - cntl.engine_id = enc1->base.id; - cntl.signal = is_dual_link ? - SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; - cntl.enable_dp_audio = false; - cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; - cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; - - if (enc1->base.bp->funcs->encoder_control( - enc1->base.bp, &cntl) != BP_RESULT_OK) - return; - - ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); - ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); - enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); -} - -void enc1_stream_encoder_set_throttled_vcp_size( - struct stream_encoder *enc, - struct fixed31_32 avg_time_slots_per_mtp) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t x = dc_fixpt_floor( - avg_time_slots_per_mtp); - uint32_t y = dc_fixpt_ceil( - dc_fixpt_shl( - dc_fixpt_sub_int( - avg_time_slots_per_mtp, - x), - 26)); - - // If y rounds up to integer, carry it over to x. - if (y >> 26) { - x += 1; - y = 0; - } - - REG_SET_2(DP_MSE_RATE_CNTL, 0, - DP_MSE_RATE_X, x, - DP_MSE_RATE_Y, y); - - /* wait for update to be completed on the link */ - /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ - /* is reset to 0 (not pending) */ - REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, - 0, - 10, DP_MST_UPDATE_MAX_RETRY); -} - -static void enc1_stream_encoder_update_hdmi_info_packets( - struct stream_encoder *enc, - const struct encoder_info_frame *info_frame) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - /* for bring up, disable dp double TODO */ - REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); - - /*Always add mandatory packets first followed by optional ones*/ - enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi); - enc1_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif); - enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); - enc1_update_hdmi_info_packet(enc1, 3, &info_frame->vendor); - enc1_update_hdmi_info_packet(enc1, 4, &info_frame->spd); - enc1_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd); -} - -static void enc1_stream_encoder_stop_hdmi_info_packets( - struct stream_encoder *enc) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - /* stop generic packets 0 & 1 on HDMI */ - REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, - HDMI_GENERIC1_CONT, 0, - HDMI_GENERIC1_LINE, 0, - HDMI_GENERIC1_SEND, 0, - HDMI_GENERIC0_CONT, 0, - HDMI_GENERIC0_LINE, 0, - HDMI_GENERIC0_SEND, 0); - - /* stop generic packets 2 & 3 on HDMI */ - REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, - HDMI_GENERIC0_CONT, 0, - HDMI_GENERIC0_LINE, 0, - HDMI_GENERIC0_SEND, 0, - HDMI_GENERIC1_CONT, 0, - HDMI_GENERIC1_LINE, 0, - HDMI_GENERIC1_SEND, 0); - - /* stop generic packets 2 & 3 on HDMI */ - REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, - HDMI_GENERIC0_CONT, 0, - HDMI_GENERIC0_LINE, 0, - HDMI_GENERIC0_SEND, 0, - HDMI_GENERIC1_CONT, 0, - HDMI_GENERIC1_LINE, 0, - HDMI_GENERIC1_SEND, 0); - - REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, - HDMI_GENERIC0_CONT, 0, - HDMI_GENERIC0_LINE, 0, - HDMI_GENERIC0_SEND, 0, - HDMI_GENERIC1_CONT, 0, - HDMI_GENERIC1_LINE, 0, - HDMI_GENERIC1_SEND, 0); -} - -void enc1_stream_encoder_update_dp_info_packets( - struct stream_encoder *enc, - const struct encoder_info_frame *info_frame) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t value = 0; - - if (info_frame->vsc.valid) - enc1_update_generic_info_packet( - enc1, - 0, /* packetIndex */ - &info_frame->vsc); - - /* VSC SDP at packetIndex 1 is used by PSR in DMCUB FW. - * Note that the enablement of GSP1 is not done below, - * it's done in FW. - */ - if (info_frame->vsc.valid) - enc1_update_generic_info_packet( - enc1, - 1, /* packetIndex */ - &info_frame->vsc); - - if (info_frame->spd.valid) - enc1_update_generic_info_packet( - enc1, - 2, /* packetIndex */ - &info_frame->spd); - - if (info_frame->hdrsmd.valid) - enc1_update_generic_info_packet( - enc1, - 3, /* packetIndex */ - &info_frame->hdrsmd); - - /* packetIndex 4 is used for send immediate sdp message, and please - * use other packetIndex (such as 5,6) for other info packet - */ - - if (info_frame->adaptive_sync.valid) - enc1_update_generic_info_packet( - enc1, - 5, /* packetIndex */ - &info_frame->adaptive_sync); - - /* enable/disable transmission of packet(s). - * If enabled, packet transmission begins on the next frame - */ - REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); - REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); - REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); - REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid); - - /* This bit is the master enable bit. - * When enabling secondary stream engine, - * this master bit must also be set. - * This register shared with audio info frame. - * Therefore we need to enable master bit - * if at least on of the fields is not 0 - */ - value = REG_READ(DP_SEC_CNTL); - if (value) - REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); -} - -void enc1_stream_encoder_send_immediate_sdp_message( - struct stream_encoder *enc, - const uint8_t *custom_sdp_message, - unsigned int sdp_message_size) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t value = 0; - - /* TODOFPGA Figure out a proper number for max_retries polling for lock - * use 50 for now. - */ - uint32_t max_retries = 50; - - /* check if GSP4 is transmitted */ - REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, - 0, 10, max_retries); - - /* disable GSP4 transmitting */ - REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0); - - /* transmit GSP4 at the earliest time in a frame */ - REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1); - - /*we need turn on clock before programming AFMT block*/ - REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); - - /* check if HW reading GSP memory */ - REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, - 0, 10, max_retries); - - /* HW does is not reading GSP memory not reading too long -> - * something wrong. clear GPS memory access and notify? - * hw SW is writing to GSP memory - */ - REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); - - /* use generic packet 4 for immediate sdp message */ - REG_UPDATE(AFMT_VBI_PACKET_CONTROL, - AFMT_GENERIC_INDEX, 4); - - /* write generic packet header - * (4th byte is for GENERIC0 only) - */ - REG_SET_4(AFMT_GENERIC_HDR, 0, - AFMT_GENERIC_HB0, custom_sdp_message[0], - AFMT_GENERIC_HB1, custom_sdp_message[1], - AFMT_GENERIC_HB2, custom_sdp_message[2], - AFMT_GENERIC_HB3, custom_sdp_message[3]); - - /* write generic packet contents - * (we never use last 4 bytes) - * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers - */ - { - const uint32_t *content = - (const uint32_t *) &custom_sdp_message[4]; - - REG_WRITE(AFMT_GENERIC_0, *content++); - REG_WRITE(AFMT_GENERIC_1, *content++); - REG_WRITE(AFMT_GENERIC_2, *content++); - REG_WRITE(AFMT_GENERIC_3, *content++); - REG_WRITE(AFMT_GENERIC_4, *content++); - REG_WRITE(AFMT_GENERIC_5, *content++); - REG_WRITE(AFMT_GENERIC_6, *content++); - REG_WRITE(AFMT_GENERIC_7, *content); - } - - /* check whether GENERIC4 registers double buffer update in immediate mode - * is pending - */ - REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, - 0, 10, max_retries); - - /* atomically update double-buffered GENERIC4 registers in immediate mode - * (update immediately) - */ - REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC4_IMMEDIATE_UPDATE, 1); - - /* enable GSP4 transmitting */ - REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1); - - /* This bit is the master enable bit. - * When enabling secondary stream engine, - * this master bit must also be set. - * This register shared with audio info frame. - * Therefore we need to enable master bit - * if at least on of the fields is not 0 - */ - value = REG_READ(DP_SEC_CNTL); - if (value) - REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); -} - -void enc1_stream_encoder_stop_dp_info_packets( - struct stream_encoder *enc) -{ - /* stop generic packets on DP */ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t value = 0; - - REG_SET_10(DP_SEC_CNTL, 0, - DP_SEC_GSP0_ENABLE, 0, - DP_SEC_GSP1_ENABLE, 0, - DP_SEC_GSP2_ENABLE, 0, - DP_SEC_GSP3_ENABLE, 0, - DP_SEC_GSP4_ENABLE, 0, - DP_SEC_GSP5_ENABLE, 0, - DP_SEC_GSP6_ENABLE, 0, - DP_SEC_GSP7_ENABLE, 0, - DP_SEC_MPG_ENABLE, 0, - DP_SEC_STREAM_ENABLE, 0); - - /* this register shared with audio info frame. - * therefore we need to keep master enabled - * if at least one of the fields is not 0 */ - value = REG_READ(DP_SEC_CNTL); - if (value) - REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); - -} - -void enc1_stream_encoder_dp_blank( - struct dc_link *link, - struct stream_encoder *enc) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t reg1 = 0; - uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; - - /* Note: For CZ, we are changing driver default to disable - * stream deferred to next VBLANK. If results are positive, we - * will make the same change to all DCE versions. There are a - * handful of panels that cannot handle disable stream at - * HBLANK and will result in a white line flash across the - * screen on stream disable. - */ - REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); - if ((reg1 & 0x1) == 0) - /*stream not enabled*/ - return; - /* Specify the video stream disable point - * (2 = start of the next vertical blank) - */ - REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); - /* Larger delay to wait until VBLANK - use max retry of - * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode + - * a little more because we may not trust delay accuracy. - */ - max_retries = DP_BLANK_MAX_RETRY * 501; - - /* disable DP stream */ - REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); - - link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM); - - /* the encoder stops sending the video stream - * at the start of the vertical blanking. - * Poll for DP_VID_STREAM_STATUS == 0 - */ - - REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, - 0, - 10, max_retries); - - /* Tell the DP encoder to ignore timing from CRTC, must be done after - * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is - * complete, stream status will be stuck in video stream enabled state, - * i.e. DP_VID_STREAM_STATUS stuck at 1. - */ - - REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); - - link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET); -} - -/* output video stream to link encoder */ -void enc1_stream_encoder_dp_unblank( - struct dc_link *link, - struct stream_encoder *enc, - const struct encoder_unblank_param *param) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { - uint32_t n_vid = 0x8000; - uint32_t m_vid; - uint32_t n_multiply = 0; - uint64_t m_vid_l = n_vid; - - /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ - if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { - /*this param->pixel_clk_khz is half of 444 rate for 420 already*/ - n_multiply = 1; - } - /* M / N = Fstream / Flink - * m_vid / n_vid = pixel rate / link rate - */ - - m_vid_l *= param->timing.pix_clk_100hz / 10; - m_vid_l = div_u64(m_vid_l, - param->link_settings.link_rate - * LINK_RATE_REF_FREQ_IN_KHZ); - - m_vid = (uint32_t) m_vid_l; - - /* enable auto measurement */ - - REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); - - /* auto measurement need 1 full 0x8000 symbol cycle to kick in, - * therefore program initial value for Mvid and Nvid - */ - - REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); - - REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); - - REG_UPDATE_2(DP_VID_TIMING, - DP_VID_M_N_GEN_EN, 1, - DP_VID_N_MUL, n_multiply); - } - - /* set DIG_START to 0x1 to resync FIFO */ - - REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); - - /* switch DP encoder to CRTC data */ - - REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); - - /* wait 100us for DIG/DP logic to prime - * (i.e. a few video lines) - */ - udelay(100); - - /* the hardware would start sending video at the start of the next DP - * frame (i.e. rising edge of the vblank). - * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this - * register has no effect on enable transition! HW always guarantees - * VID_STREAM enable at start of next frame, and this is not - * programmable - */ - - REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); - - link->dc->link_srv->dp_trace_source_sequence(link, - DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); -} - -void enc1_stream_encoder_set_avmute( - struct stream_encoder *enc, - bool enable) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - unsigned int value = enable ? 1 : 0; - - REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); -} - -void enc1_reset_hdmi_stream_attribute( - struct stream_encoder *enc) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - REG_UPDATE_5(HDMI_CONTROL, - HDMI_PACKET_GEN_VERSION, 1, - HDMI_KEEPOUT_MODE, 1, - HDMI_DEEP_COLOR_ENABLE, 0, - HDMI_DATA_SCRAMBLE_EN, 0, - HDMI_CLOCK_CHANNEL_RATE, 0); -} - - -#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 -#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 - -#include "include/audio_types.h" - - -/* 25.2MHz/1.001*/ -/* 25.2MHz/1.001*/ -/* 25.2MHz*/ -/* 27MHz */ -/* 27MHz*1.001*/ -/* 27MHz*1.001*/ -/* 54MHz*/ -/* 54MHz*1.001*/ -/* 74.25MHz/1.001*/ -/* 74.25MHz*/ -/* 148.5MHz/1.001*/ -/* 148.5MHz*/ - -static const struct audio_clock_info audio_clock_info_table[16] = { - {2517, 4576, 28125, 7007, 31250, 6864, 28125}, - {2518, 4576, 28125, 7007, 31250, 6864, 28125}, - {2520, 4096, 25200, 6272, 28000, 6144, 25200}, - {2700, 4096, 27000, 6272, 30000, 6144, 27000}, - {2702, 4096, 27027, 6272, 30030, 6144, 27027}, - {2703, 4096, 27027, 6272, 30030, 6144, 27027}, - {5400, 4096, 54000, 6272, 60000, 6144, 54000}, - {5405, 4096, 54054, 6272, 60060, 6144, 54054}, - {7417, 11648, 210937, 17836, 234375, 11648, 140625}, - {7425, 4096, 74250, 6272, 82500, 6144, 74250}, - {14835, 11648, 421875, 8918, 234375, 5824, 140625}, - {14850, 4096, 148500, 6272, 165000, 6144, 148500}, - {29670, 5824, 421875, 4459, 234375, 5824, 281250}, - {29700, 3072, 222750, 4704, 247500, 5120, 247500}, - {59340, 5824, 843750, 8918, 937500, 5824, 562500}, - {59400, 3072, 445500, 9408, 990000, 6144, 594000} -}; - -static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { - {2517, 9152, 84375, 7007, 48875, 9152, 56250}, - {2518, 9152, 84375, 7007, 48875, 9152, 56250}, - {2520, 4096, 37800, 6272, 42000, 6144, 37800}, - {2700, 4096, 40500, 6272, 45000, 6144, 40500}, - {2702, 8192, 81081, 6272, 45045, 8192, 54054}, - {2703, 8192, 81081, 6272, 45045, 8192, 54054}, - {5400, 4096, 81000, 6272, 90000, 6144, 81000}, - {5405, 4096, 81081, 6272, 90090, 6144, 81081}, - {7417, 11648, 316406, 17836, 351562, 11648, 210937}, - {7425, 4096, 111375, 6272, 123750, 6144, 111375}, - {14835, 11648, 632812, 17836, 703125, 11648, 421875}, - {14850, 4096, 222750, 6272, 247500, 6144, 222750}, - {29670, 5824, 632812, 8918, 703125, 5824, 421875}, - {29700, 4096, 445500, 4704, 371250, 5120, 371250} -}; - -static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { - {2517, 4576, 56250, 7007, 62500, 6864, 56250}, - {2518, 4576, 56250, 7007, 62500, 6864, 56250}, - {2520, 4096, 50400, 6272, 56000, 6144, 50400}, - {2700, 4096, 54000, 6272, 60000, 6144, 54000}, - {2702, 4096, 54054, 6267, 60060, 8192, 54054}, - {2703, 4096, 54054, 6272, 60060, 8192, 54054}, - {5400, 4096, 108000, 6272, 120000, 6144, 108000}, - {5405, 4096, 108108, 6272, 120120, 6144, 108108}, - {7417, 11648, 421875, 17836, 468750, 11648, 281250}, - {7425, 4096, 148500, 6272, 165000, 6144, 148500}, - {14835, 11648, 843750, 8918, 468750, 11648, 281250}, - {14850, 4096, 297000, 6272, 330000, 6144, 297000}, - {29670, 5824, 843750, 4459, 468750, 5824, 562500}, - {29700, 3072, 445500, 4704, 495000, 5120, 495000} - - -}; - -static union audio_cea_channels speakers_to_channels( - struct audio_speaker_flags speaker_flags) -{ - union audio_cea_channels cea_channels = {0}; - - /* these are one to one */ - cea_channels.channels.FL = speaker_flags.FL_FR; - cea_channels.channels.FR = speaker_flags.FL_FR; - cea_channels.channels.LFE = speaker_flags.LFE; - cea_channels.channels.FC = speaker_flags.FC; - - /* if Rear Left and Right exist move RC speaker to channel 7 - * otherwise to channel 5 - */ - if (speaker_flags.RL_RR) { - cea_channels.channels.RL_RC = speaker_flags.RL_RR; - cea_channels.channels.RR = speaker_flags.RL_RR; - cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; - } else { - cea_channels.channels.RL_RC = speaker_flags.RC; - } - - /* FRONT Left Right Center and REAR Left Right Center are exclusive */ - if (speaker_flags.FLC_FRC) { - cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; - cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; - } else { - cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; - cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; - } - - return cea_channels; -} - -void get_audio_clock_info( - enum dc_color_depth color_depth, - uint32_t crtc_pixel_clock_100Hz, - uint32_t actual_pixel_clock_100Hz, - struct audio_clock_info *audio_clock_info) -{ - const struct audio_clock_info *clock_info; - uint32_t index; - uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; - uint32_t audio_array_size; - - switch (color_depth) { - case COLOR_DEPTH_161616: - clock_info = audio_clock_info_table_48bpc; - audio_array_size = ARRAY_SIZE( - audio_clock_info_table_48bpc); - break; - case COLOR_DEPTH_121212: - clock_info = audio_clock_info_table_36bpc; - audio_array_size = ARRAY_SIZE( - audio_clock_info_table_36bpc); - break; - default: - clock_info = audio_clock_info_table; - audio_array_size = ARRAY_SIZE( - audio_clock_info_table); - break; - } - - if (clock_info != NULL) { - /* search for exact pixel clock in table */ - for (index = 0; index < audio_array_size; index++) { - if (clock_info[index].pixel_clock_in_10khz > - crtc_pixel_clock_in_10khz) - break; /* not match */ - else if (clock_info[index].pixel_clock_in_10khz == - crtc_pixel_clock_in_10khz) { - /* match found */ - *audio_clock_info = clock_info[index]; - return; - } - } - } - - /* not found */ - if (actual_pixel_clock_100Hz == 0) - actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz; - - /* See HDMI spec the table entry under - * pixel clock of "Other". */ - audio_clock_info->pixel_clock_in_10khz = - actual_pixel_clock_100Hz / 100; - audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10; - audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10; - audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10; - - audio_clock_info->n_32khz = 4096; - audio_clock_info->n_44khz = 6272; - audio_clock_info->n_48khz = 6144; -} - -static void enc1_se_audio_setup( - struct stream_encoder *enc, - unsigned int az_inst, - struct audio_info *audio_info) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - uint32_t channels = 0; - - ASSERT(audio_info); - if (audio_info == NULL) - /* This should not happen.it does so we don't get BSOD*/ - return; - - channels = speakers_to_channels(audio_info->flags.speaker_flags).all; - - /* setup the audio stream source select (audio -> dig mapping) */ - REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); - - /* Channel allocation */ - REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); -} - -static void enc1_se_setup_hdmi_audio( - struct stream_encoder *enc, - const struct audio_crtc_info *crtc_info) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - struct audio_clock_info audio_clock_info = {0}; - - /* HDMI_AUDIO_PACKET_CONTROL */ - REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, - HDMI_AUDIO_DELAY_EN, 1); - - /* AFMT_AUDIO_PACKET_CONTROL */ - REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); - - /* AFMT_AUDIO_PACKET_CONTROL2 */ - REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, - AFMT_AUDIO_LAYOUT_OVRD, 0, - AFMT_60958_OSF_OVRD, 0); - - /* HDMI_ACR_PACKET_CONTROL */ - REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, - HDMI_ACR_AUTO_SEND, 1, - HDMI_ACR_SOURCE, 0, - HDMI_ACR_AUDIO_PRIORITY, 0); - - /* Program audio clock sample/regeneration parameters */ - get_audio_clock_info(crtc_info->color_depth, - crtc_info->requested_pixel_clock_100Hz, - crtc_info->calculated_pixel_clock_100Hz, - &audio_clock_info); - DC_LOG_HW_AUDIO( - "\n%s:Input::requested_pixel_clock_100Hz = %d" \ - "calculated_pixel_clock_100Hz = %d \n", __func__, \ - crtc_info->requested_pixel_clock_100Hz, \ - crtc_info->calculated_pixel_clock_100Hz); - - /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ - REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); - - /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ - REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); - - /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ - REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); - - /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ - REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); - - /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ - REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); - - /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ - REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); - - /* Video driver cannot know in advance which sample rate will - * be used by HD Audio driver - * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is - * programmed below in interruppt callback - */ - - /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & - * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK - */ - REG_UPDATE_2(AFMT_60958_0, - AFMT_60958_CS_CHANNEL_NUMBER_L, 1, - AFMT_60958_CS_CLOCK_ACCURACY, 0); - - /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ - REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); - - /* AFMT_60958_2 now keep this settings until - * Programming guide comes out - */ - REG_UPDATE_6(AFMT_60958_2, - AFMT_60958_CS_CHANNEL_NUMBER_2, 3, - AFMT_60958_CS_CHANNEL_NUMBER_3, 4, - AFMT_60958_CS_CHANNEL_NUMBER_4, 5, - AFMT_60958_CS_CHANNEL_NUMBER_5, 6, - AFMT_60958_CS_CHANNEL_NUMBER_6, 7, - AFMT_60958_CS_CHANNEL_NUMBER_7, 8); -} - -static void enc1_se_setup_dp_audio( - struct stream_encoder *enc) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - /* --- DP Audio packet configurations --- */ - - /* ATP Configuration */ - REG_SET(DP_SEC_AUD_N, 0, - DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); - - /* Async/auto-calc timestamp mode */ - REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, - DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); - - /* --- The following are the registers - * copied from the SetupHDMI --- - */ - - /* AFMT_AUDIO_PACKET_CONTROL */ - REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); - - /* AFMT_AUDIO_PACKET_CONTROL2 */ - /* Program the ATP and AIP next */ - REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, - AFMT_AUDIO_LAYOUT_OVRD, 0, - AFMT_60958_OSF_OVRD, 0); - - /* AFMT_INFOFRAME_CONTROL0 */ - REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); - - /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ - REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); -} - -void enc1_se_enable_audio_clock( - struct stream_encoder *enc, - bool enable) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - if (REG(AFMT_CNTL) == 0) - return; /* DCE8/10 does not have this register */ - - REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); - - /* wait for AFMT clock to turn on, - * expectation: this should complete in 1-2 reads - * - * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); - * - * TODO: wait for clock_on does not work well. May need HW - * program sequence. But audio seems work normally even without wait - * for clock_on status change - */ -} - -void enc1_se_enable_dp_audio( - struct stream_encoder *enc) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - /* Enable Audio packets */ - REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); - - /* Program the ATP and AIP next */ - REG_UPDATE_2(DP_SEC_CNTL, - DP_SEC_ATP_ENABLE, 1, - DP_SEC_AIP_ENABLE, 1); - - /* Program STREAM_ENABLE after all the other enables. */ - REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); -} - -static void enc1_se_disable_dp_audio( - struct stream_encoder *enc) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t value = 0; - - /* Disable Audio packets */ - REG_UPDATE_5(DP_SEC_CNTL, - DP_SEC_ASP_ENABLE, 0, - DP_SEC_ATP_ENABLE, 0, - DP_SEC_AIP_ENABLE, 0, - DP_SEC_ACM_ENABLE, 0, - DP_SEC_STREAM_ENABLE, 0); - - /* This register shared with encoder info frame. Therefore we need to - * keep master enabled if at least on of the fields is not 0 - */ - value = REG_READ(DP_SEC_CNTL); - if (value != 0) - REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); - -} - -void enc1_se_audio_mute_control( - struct stream_encoder *enc, - bool mute) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); -} - -void enc1_se_dp_audio_setup( - struct stream_encoder *enc, - unsigned int az_inst, - struct audio_info *info) -{ - enc1_se_audio_setup(enc, az_inst, info); -} - -void enc1_se_dp_audio_enable( - struct stream_encoder *enc) -{ - enc1_se_enable_audio_clock(enc, true); - enc1_se_setup_dp_audio(enc); - enc1_se_enable_dp_audio(enc); -} - -void enc1_se_dp_audio_disable( - struct stream_encoder *enc) -{ - enc1_se_disable_dp_audio(enc); - enc1_se_enable_audio_clock(enc, false); -} - -void enc1_se_hdmi_audio_setup( - struct stream_encoder *enc, - unsigned int az_inst, - struct audio_info *info, - struct audio_crtc_info *audio_crtc_info) -{ - enc1_se_enable_audio_clock(enc, true); - enc1_se_setup_hdmi_audio(enc, audio_crtc_info); - enc1_se_audio_setup(enc, az_inst, info); -} - -void enc1_se_hdmi_audio_disable( - struct stream_encoder *enc) -{ - if (enc->afmt && enc->afmt->funcs->afmt_powerdown) - enc->afmt->funcs->afmt_powerdown(enc->afmt); - - enc1_se_enable_audio_clock(enc, false); -} - - -void enc1_setup_stereo_sync( - struct stream_encoder *enc, - int tg_inst, bool enable) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); - REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); -} - -void enc1_dig_connect_to_otg( - struct stream_encoder *enc, - int tg_inst) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); -} - -unsigned int enc1_dig_source_otg( - struct stream_encoder *enc) -{ - uint32_t tg_inst = 0; - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); - - return tg_inst; -} - -bool enc1_stream_encoder_dp_get_pixel_format( - struct stream_encoder *enc, - enum dc_pixel_encoding *encoding, - enum dc_color_depth *depth) -{ - uint32_t hw_encoding = 0; - uint32_t hw_depth = 0; - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - if (enc == NULL || - encoding == NULL || - depth == NULL) - return false; - - REG_GET_2(DP_PIXEL_FORMAT, - DP_PIXEL_ENCODING, &hw_encoding, - DP_COMPONENT_DEPTH, &hw_depth); - - switch (hw_depth) { - case DP_COMPONENT_PIXEL_DEPTH_6BPC: - *depth = COLOR_DEPTH_666; - break; - case DP_COMPONENT_PIXEL_DEPTH_8BPC: - *depth = COLOR_DEPTH_888; - break; - case DP_COMPONENT_PIXEL_DEPTH_10BPC: - *depth = COLOR_DEPTH_101010; - break; - case DP_COMPONENT_PIXEL_DEPTH_12BPC: - *depth = COLOR_DEPTH_121212; - break; - case DP_COMPONENT_PIXEL_DEPTH_16BPC: - *depth = COLOR_DEPTH_161616; - break; - default: - *depth = COLOR_DEPTH_UNDEFINED; - break; - } - - switch (hw_encoding) { - case DP_PIXEL_ENCODING_TYPE_RGB444: - *encoding = PIXEL_ENCODING_RGB; - break; - case DP_PIXEL_ENCODING_TYPE_YCBCR422: - *encoding = PIXEL_ENCODING_YCBCR422; - break; - case DP_PIXEL_ENCODING_TYPE_YCBCR444: - case DP_PIXEL_ENCODING_TYPE_Y_ONLY: - *encoding = PIXEL_ENCODING_YCBCR444; - break; - case DP_PIXEL_ENCODING_TYPE_YCBCR420: - *encoding = PIXEL_ENCODING_YCBCR420; - break; - default: - *encoding = PIXEL_ENCODING_UNDEFINED; - break; - } - return true; -} - -static const struct stream_encoder_funcs dcn10_str_enc_funcs = { - .dp_set_stream_attribute = - enc1_stream_encoder_dp_set_stream_attribute, - .hdmi_set_stream_attribute = - enc1_stream_encoder_hdmi_set_stream_attribute, - .dvi_set_stream_attribute = - enc1_stream_encoder_dvi_set_stream_attribute, - .set_throttled_vcp_size = - enc1_stream_encoder_set_throttled_vcp_size, - .update_hdmi_info_packets = - enc1_stream_encoder_update_hdmi_info_packets, - .stop_hdmi_info_packets = - enc1_stream_encoder_stop_hdmi_info_packets, - .update_dp_info_packets = - enc1_stream_encoder_update_dp_info_packets, - .send_immediate_sdp_message = - enc1_stream_encoder_send_immediate_sdp_message, - .stop_dp_info_packets = - enc1_stream_encoder_stop_dp_info_packets, - .dp_blank = - enc1_stream_encoder_dp_blank, - .dp_unblank = - enc1_stream_encoder_dp_unblank, - .audio_mute_control = enc1_se_audio_mute_control, - - .dp_audio_setup = enc1_se_dp_audio_setup, - .dp_audio_enable = enc1_se_dp_audio_enable, - .dp_audio_disable = enc1_se_dp_audio_disable, - - .hdmi_audio_setup = enc1_se_hdmi_audio_setup, - .hdmi_audio_disable = enc1_se_hdmi_audio_disable, - .setup_stereo_sync = enc1_setup_stereo_sync, - .set_avmute = enc1_stream_encoder_set_avmute, - .dig_connect_to_otg = enc1_dig_connect_to_otg, - .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, - .dig_source_otg = enc1_dig_source_otg, - - .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, -}; - -void dcn10_stream_encoder_construct( - struct dcn10_stream_encoder *enc1, - struct dc_context *ctx, - struct dc_bios *bp, - enum engine_id eng_id, - const struct dcn10_stream_enc_registers *regs, - const struct dcn10_stream_encoder_shift *se_shift, - const struct dcn10_stream_encoder_mask *se_mask) -{ - enc1->base.funcs = &dcn10_str_enc_funcs; - enc1->base.ctx = ctx; - enc1->base.id = eng_id; - enc1->base.bp = bp; - enc1->regs = regs; - enc1->se_shift = se_shift; - enc1->se_mask = se_mask; - enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h deleted file mode 100644 index 1b96972b9d0f..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +++ /dev/null @@ -1,742 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_STREAM_ENCODER_DCN10_H__ -#define __DC_STREAM_ENCODER_DCN10_H__ - -#include "stream_encoder.h" - -#define DCN10STRENC_FROM_STRENC(stream_encoder)\ - container_of(stream_encoder, struct dcn10_stream_encoder, base) - -#define SE_COMMON_DCN_REG_LIST(id) \ - SRI(AFMT_CNTL, DIG, id), \ - SRI(AFMT_GENERIC_0, DIG, id), \ - SRI(AFMT_GENERIC_1, DIG, id), \ - SRI(AFMT_GENERIC_2, DIG, id), \ - SRI(AFMT_GENERIC_3, DIG, id), \ - SRI(AFMT_GENERIC_4, DIG, id), \ - SRI(AFMT_GENERIC_5, DIG, id), \ - SRI(AFMT_GENERIC_6, DIG, id), \ - SRI(AFMT_GENERIC_7, DIG, id), \ - SRI(AFMT_GENERIC_HDR, DIG, id), \ - SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \ - SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \ - SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \ - SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \ - SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \ - SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \ - SRI(AFMT_60958_0, DIG, id), \ - SRI(AFMT_60958_1, DIG, id), \ - SRI(AFMT_60958_2, DIG, id), \ - SRI(DIG_FE_CNTL, DIG, id), \ - SRI(DIG_FIFO_STATUS, DIG, id), \ - SRI(HDMI_CONTROL, DIG, id), \ - SRI(HDMI_DB_CONTROL, DIG, id), \ - SRI(HDMI_GC, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ - SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \ - SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \ - SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \ - SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\ - SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\ - SRI(HDMI_ACR_32_0, DIG, id),\ - SRI(HDMI_ACR_32_1, DIG, id),\ - SRI(HDMI_ACR_44_0, DIG, id),\ - SRI(HDMI_ACR_44_1, DIG, id),\ - SRI(HDMI_ACR_48_0, DIG, id),\ - SRI(HDMI_ACR_48_1, DIG, id),\ - SRI(DP_DB_CNTL, DP, id), \ - SRI(DP_MSA_MISC, DP, id), \ - SRI(DP_MSA_VBID_MISC, DP, id), \ - SRI(DP_MSA_COLORIMETRY, DP, id), \ - SRI(DP_MSA_TIMING_PARAM1, DP, id), \ - SRI(DP_MSA_TIMING_PARAM2, DP, id), \ - SRI(DP_MSA_TIMING_PARAM3, DP, id), \ - SRI(DP_MSA_TIMING_PARAM4, DP, id), \ - SRI(DP_MSE_RATE_CNTL, DP, id), \ - SRI(DP_MSE_RATE_UPDATE, DP, id), \ - SRI(DP_PIXEL_FORMAT, DP, id), \ - SRI(DP_SEC_CNTL, DP, id), \ - SRI(DP_SEC_CNTL1, DP, id), \ - SRI(DP_SEC_CNTL2, DP, id), \ - SRI(DP_SEC_CNTL5, DP, id), \ - SRI(DP_SEC_CNTL6, DP, id), \ - SRI(DP_STEER_FIFO, DP, id), \ - SRI(DP_VID_M, DP, id), \ - SRI(DP_VID_N, DP, id), \ - SRI(DP_VID_STREAM_CNTL, DP, id), \ - SRI(DP_VID_TIMING, DP, id), \ - SRI(DP_SEC_AUD_N, DP, id), \ - SRI(DP_SEC_AUD_N_READBACK, DP, id), \ - SRI(DP_SEC_AUD_M_READBACK, DP, id), \ - SRI(DP_SEC_TIMESTAMP, DP, id), \ - SRI(DIG_CLOCK_PATTERN, DIG, id) - -#define SE_DCN_REG_LIST(id)\ - SE_COMMON_DCN_REG_LIST(id) - - -struct dcn10_stream_enc_registers { - uint32_t AFMT_CNTL; - uint32_t AFMT_AVI_INFO0; - uint32_t AFMT_AVI_INFO1; - uint32_t AFMT_AVI_INFO2; - uint32_t AFMT_AVI_INFO3; - uint32_t AFMT_GENERIC_0; - uint32_t AFMT_GENERIC_1; - uint32_t AFMT_GENERIC_2; - uint32_t AFMT_GENERIC_3; - uint32_t AFMT_GENERIC_4; - uint32_t AFMT_GENERIC_5; - uint32_t AFMT_GENERIC_6; - uint32_t AFMT_GENERIC_7; - uint32_t AFMT_GENERIC_HDR; - uint32_t AFMT_INFOFRAME_CONTROL0; - uint32_t AFMT_VBI_PACKET_CONTROL; - uint32_t AFMT_VBI_PACKET_CONTROL1; - uint32_t AFMT_AUDIO_PACKET_CONTROL; - uint32_t AFMT_AUDIO_PACKET_CONTROL2; - uint32_t AFMT_AUDIO_SRC_CONTROL; - uint32_t AFMT_60958_0; - uint32_t AFMT_60958_1; - uint32_t AFMT_60958_2; - uint32_t DIG_FE_CNTL; - uint32_t DIG_FIFO_STATUS; - uint32_t DP_MSE_RATE_CNTL; - uint32_t DP_MSE_RATE_UPDATE; - uint32_t DP_PIXEL_FORMAT; - uint32_t DP_SEC_CNTL; - uint32_t DP_SEC_CNTL1; - uint32_t DP_SEC_CNTL2; - uint32_t DP_SEC_CNTL5; - uint32_t DP_SEC_CNTL6; - uint32_t DP_STEER_FIFO; - uint32_t DP_VID_M; - uint32_t DP_VID_N; - uint32_t DP_VID_STREAM_CNTL; - uint32_t DP_VID_TIMING; - uint32_t DP_SEC_AUD_N; - uint32_t DP_SEC_AUD_N_READBACK; - uint32_t DP_SEC_AUD_M_READBACK; - uint32_t DP_SEC_TIMESTAMP; - uint32_t HDMI_CONTROL; - uint32_t HDMI_GC; - uint32_t HDMI_GENERIC_PACKET_CONTROL0; - uint32_t HDMI_GENERIC_PACKET_CONTROL1; - uint32_t HDMI_GENERIC_PACKET_CONTROL2; - uint32_t HDMI_GENERIC_PACKET_CONTROL3; - uint32_t HDMI_GENERIC_PACKET_CONTROL4; - uint32_t HDMI_GENERIC_PACKET_CONTROL5; - uint32_t HDMI_INFOFRAME_CONTROL0; - uint32_t HDMI_INFOFRAME_CONTROL1; - uint32_t HDMI_VBI_PACKET_CONTROL; - uint32_t HDMI_AUDIO_PACKET_CONTROL; - uint32_t HDMI_ACR_PACKET_CONTROL; - uint32_t HDMI_ACR_32_0; - uint32_t HDMI_ACR_32_1; - uint32_t HDMI_ACR_44_0; - uint32_t HDMI_ACR_44_1; - uint32_t HDMI_ACR_48_0; - uint32_t HDMI_ACR_48_1; - uint32_t DP_DB_CNTL; - uint32_t DP_MSA_MISC; - uint32_t DP_MSA_VBID_MISC; - uint32_t DP_MSA_COLORIMETRY; - uint32_t DP_MSA_TIMING_PARAM1; - uint32_t DP_MSA_TIMING_PARAM2; - uint32_t DP_MSA_TIMING_PARAM3; - uint32_t DP_MSA_TIMING_PARAM4; - uint32_t HDMI_DB_CONTROL; - uint32_t DP_DSC_CNTL; - uint32_t DP_DSC_BYTES_PER_PIXEL; - uint32_t DME_CONTROL; - uint32_t DP_SEC_METADATA_TRANSMISSION; - uint32_t HDMI_METADATA_PACKET_CONTROL; - uint32_t DP_SEC_FRAMING4; - uint32_t DP_GSP11_CNTL; - uint32_t HDMI_GENERIC_PACKET_CONTROL6; - uint32_t HDMI_GENERIC_PACKET_CONTROL7; - uint32_t HDMI_GENERIC_PACKET_CONTROL8; - uint32_t HDMI_GENERIC_PACKET_CONTROL9; - uint32_t HDMI_GENERIC_PACKET_CONTROL10; - uint32_t DIG_CLOCK_PATTERN; - uint32_t DIG_FIFO_CTRL0; - uint32_t DIG_FE_CLK_CNTL; - uint32_t DIG_FE_EN_CNTL; - uint32_t STREAM_MAPPER_CONTROL; -}; - - -#define SE_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix - -#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ - SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ - SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\ - SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\ - SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\ - SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\ - SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\ - SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ - SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ - SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ - SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ - SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ - SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\ - SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ - SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ - SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ - SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ - SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ - SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\ - SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\ - SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\ - SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\ - SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\ - SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ - SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\ - SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ - SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\ - SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\ - SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\ - SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\ - SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\ - SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\ - SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\ - SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\ - SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\ - SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ - SE_SF(DP0_DP_SEC_AUD_N_READBACK, DP_SEC_AUD_N_READBACK, mask_sh),\ - SE_SF(DP0_DP_SEC_AUD_M_READBACK, DP_SEC_AUD_M_READBACK, mask_sh),\ - SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ - SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\ - SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ - SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ - SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ - SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ - SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_PPS, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\ - SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\ - SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ - SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ - SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\ - SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\ - SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh) - -#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\ - SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh) - - -#define SE_REG_FIELD_LIST_DCN1_0(type) \ - type AFMT_GENERIC_INDEX;\ - type AFMT_GENERIC_HB0;\ - type AFMT_GENERIC_HB1;\ - type AFMT_GENERIC_HB2;\ - type AFMT_GENERIC_HB3;\ - type AFMT_GENERIC_LOCK_STATUS;\ - type AFMT_GENERIC_CONFLICT;\ - type AFMT_GENERIC_CONFLICT_CLR;\ - type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\ - type AFMT_GENERIC1_FRAME_UPDATE_PENDING;\ - type AFMT_GENERIC2_FRAME_UPDATE_PENDING;\ - type AFMT_GENERIC3_FRAME_UPDATE_PENDING;\ - type AFMT_GENERIC4_FRAME_UPDATE_PENDING;\ - type AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING;\ - type AFMT_GENERIC5_FRAME_UPDATE_PENDING;\ - type AFMT_GENERIC6_FRAME_UPDATE_PENDING;\ - type AFMT_GENERIC7_FRAME_UPDATE_PENDING;\ - type AFMT_GENERIC0_FRAME_UPDATE;\ - type AFMT_GENERIC1_FRAME_UPDATE;\ - type AFMT_GENERIC2_FRAME_UPDATE;\ - type AFMT_GENERIC3_FRAME_UPDATE;\ - type AFMT_GENERIC4_FRAME_UPDATE;\ - type AFMT_GENERIC0_IMMEDIATE_UPDATE;\ - type AFMT_GENERIC1_IMMEDIATE_UPDATE;\ - type AFMT_GENERIC2_IMMEDIATE_UPDATE;\ - type AFMT_GENERIC3_IMMEDIATE_UPDATE;\ - type AFMT_GENERIC4_IMMEDIATE_UPDATE;\ - type AFMT_GENERIC5_IMMEDIATE_UPDATE;\ - type AFMT_GENERIC6_IMMEDIATE_UPDATE;\ - type AFMT_GENERIC7_IMMEDIATE_UPDATE;\ - type AFMT_GENERIC5_FRAME_UPDATE;\ - type AFMT_GENERIC6_FRAME_UPDATE;\ - type AFMT_GENERIC7_FRAME_UPDATE;\ - type HDMI_GENERIC0_CONT;\ - type HDMI_GENERIC0_SEND;\ - type HDMI_GENERIC0_LINE;\ - type HDMI_GENERIC1_CONT;\ - type HDMI_GENERIC1_SEND;\ - type HDMI_GENERIC1_LINE;\ - type HDMI_GENERIC2_CONT;\ - type HDMI_GENERIC2_SEND;\ - type HDMI_GENERIC2_LINE;\ - type HDMI_GENERIC3_CONT;\ - type HDMI_GENERIC3_SEND;\ - type HDMI_GENERIC3_LINE;\ - type HDMI_GENERIC4_CONT;\ - type HDMI_GENERIC4_SEND;\ - type HDMI_GENERIC4_LINE;\ - type HDMI_GENERIC5_CONT;\ - type HDMI_GENERIC5_SEND;\ - type HDMI_GENERIC5_LINE;\ - type HDMI_GENERIC6_CONT;\ - type HDMI_GENERIC6_SEND;\ - type HDMI_GENERIC6_LINE;\ - type HDMI_GENERIC7_CONT;\ - type HDMI_GENERIC7_SEND;\ - type HDMI_GENERIC7_LINE;\ - type DP_PIXEL_ENCODING;\ - type DP_COMPONENT_DEPTH;\ - type HDMI_PACKET_GEN_VERSION;\ - type HDMI_KEEPOUT_MODE;\ - type HDMI_DEEP_COLOR_ENABLE;\ - type HDMI_CLOCK_CHANNEL_RATE;\ - type HDMI_DEEP_COLOR_DEPTH;\ - type HDMI_GC_CONT;\ - type HDMI_GC_SEND;\ - type HDMI_NULL_SEND;\ - type HDMI_DATA_SCRAMBLE_EN;\ - type HDMI_NO_EXTRA_NULL_PACKET_FILLED;\ - type HDMI_AUDIO_INFO_SEND;\ - type AFMT_AUDIO_INFO_UPDATE;\ - type HDMI_AUDIO_INFO_LINE;\ - type HDMI_GC_AVMUTE;\ - type DP_MSE_RATE_X;\ - type DP_MSE_RATE_Y;\ - type DP_MSE_RATE_UPDATE_PENDING;\ - type DP_SEC_GSP0_ENABLE;\ - type DP_SEC_STREAM_ENABLE;\ - type DP_SEC_GSP1_ENABLE;\ - type DP_SEC_GSP2_ENABLE;\ - type DP_SEC_GSP3_ENABLE;\ - type DP_SEC_GSP4_ENABLE;\ - type DP_SEC_GSP5_ENABLE;\ - type DP_SEC_GSP5_LINE_NUM;\ - type DP_SEC_GSP5_LINE_REFERENCE;\ - type DP_SEC_GSP6_ENABLE;\ - type DP_SEC_GSP7_ENABLE;\ - type DP_SEC_GSP7_PPS;\ - type DP_SEC_GSP7_SEND;\ - type DP_SEC_GSP4_SEND;\ - type DP_SEC_GSP4_SEND_PENDING;\ - type DP_SEC_GSP4_LINE_NUM;\ - type DP_SEC_GSP4_SEND_ANY_LINE;\ - type DP_SEC_MPG_ENABLE;\ - type DP_VID_STREAM_DIS_DEFER;\ - type DP_VID_STREAM_ENABLE;\ - type DP_VID_STREAM_STATUS;\ - type DP_STEER_FIFO_RESET;\ - type DP_VID_M_N_GEN_EN;\ - type DP_VID_N;\ - type DP_VID_M;\ - type DIG_START;\ - type AFMT_AUDIO_SRC_SELECT;\ - type AFMT_AUDIO_CHANNEL_ENABLE;\ - type HDMI_AUDIO_PACKETS_PER_LINE;\ - type HDMI_AUDIO_DELAY_EN;\ - type AFMT_60958_CS_UPDATE;\ - type AFMT_AUDIO_LAYOUT_OVRD;\ - type AFMT_60958_OSF_OVRD;\ - type HDMI_ACR_AUTO_SEND;\ - type HDMI_ACR_SOURCE;\ - type HDMI_ACR_AUDIO_PRIORITY;\ - type HDMI_ACR_CTS_32;\ - type HDMI_ACR_N_32;\ - type HDMI_ACR_CTS_44;\ - type HDMI_ACR_N_44;\ - type HDMI_ACR_CTS_48;\ - type HDMI_ACR_N_48;\ - type AFMT_60958_CS_CHANNEL_NUMBER_L;\ - type AFMT_60958_CS_CLOCK_ACCURACY;\ - type AFMT_60958_CS_CHANNEL_NUMBER_R;\ - type AFMT_60958_CS_CHANNEL_NUMBER_2;\ - type AFMT_60958_CS_CHANNEL_NUMBER_3;\ - type AFMT_60958_CS_CHANNEL_NUMBER_4;\ - type AFMT_60958_CS_CHANNEL_NUMBER_5;\ - type AFMT_60958_CS_CHANNEL_NUMBER_6;\ - type AFMT_60958_CS_CHANNEL_NUMBER_7;\ - type DP_SEC_AUD_N;\ - type DP_SEC_AUD_N_READBACK;\ - type DP_SEC_AUD_M_READBACK;\ - type DP_SEC_TIMESTAMP_MODE;\ - type DP_SEC_ASP_ENABLE;\ - type DP_SEC_ATP_ENABLE;\ - type DP_SEC_AIP_ENABLE;\ - type DP_SEC_ACM_ENABLE;\ - type DP_SEC_GSP7_LINE_NUM;\ - type AFMT_AUDIO_SAMPLE_SEND;\ - type AFMT_AUDIO_CLOCK_EN;\ - type TMDS_PIXEL_ENCODING;\ - type TMDS_COLOR_FORMAT;\ - type DIG_STEREOSYNC_SELECT;\ - type DIG_STEREOSYNC_GATE_EN;\ - type DP_DB_DISABLE;\ - type DP_MSA_MISC0;\ - type DP_MSA_HTOTAL;\ - type DP_MSA_VTOTAL;\ - type DP_MSA_HSTART;\ - type DP_MSA_VSTART;\ - type DP_MSA_HSYNCWIDTH;\ - type DP_MSA_HSYNCPOLARITY;\ - type DP_MSA_VSYNCWIDTH;\ - type DP_MSA_VSYNCPOLARITY;\ - type DP_MSA_HWIDTH;\ - type DP_MSA_VHEIGHT;\ - type HDMI_DB_DISABLE;\ - type DP_VID_N_MUL;\ - type DP_VID_M_DOUBLE_VALUE_EN;\ - type DIG_SOURCE_SELECT;\ - type DIG_FIFO_LEVEL_ERROR;\ - type DIG_FIFO_USE_OVERWRITE_LEVEL;\ - type DIG_FIFO_OVERWRITE_LEVEL;\ - type DIG_FIFO_ERROR_ACK;\ - type DIG_FIFO_CAL_AVERAGE_LEVEL;\ - type DIG_FIFO_MAXIMUM_LEVEL;\ - type DIG_FIFO_MINIMUM_LEVEL;\ - type DIG_FIFO_READ_CLOCK_SRC;\ - type DIG_FIFO_CALIBRATED;\ - type DIG_FIFO_FORCE_RECAL_AVERAGE;\ - type DIG_FIFO_FORCE_RECOMP_MINMAX;\ - type DIG_CLOCK_PATTERN - -#define SE_REG_FIELD_LIST_DCN2_0(type) \ - type DP_DSC_MODE;\ - type DP_DSC_SLICE_WIDTH;\ - type DP_DSC_BYTES_PER_PIXEL;\ - type DP_VBID6_LINE_REFERENCE;\ - type DP_VBID6_LINE_NUM;\ - type METADATA_ENGINE_EN;\ - type METADATA_HUBP_REQUESTOR_ID;\ - type METADATA_STREAM_TYPE;\ - type DP_SEC_METADATA_PACKET_ENABLE;\ - type DP_SEC_METADATA_PACKET_LINE_REFERENCE;\ - type DP_SEC_METADATA_PACKET_LINE;\ - type HDMI_METADATA_PACKET_ENABLE;\ - type HDMI_METADATA_PACKET_LINE_REFERENCE;\ - type HDMI_METADATA_PACKET_LINE;\ - type DOLBY_VISION_EN;\ - type DP_PIXEL_COMBINE;\ - type DP_SST_SDP_SPLITTING - -#define SE_REG_FIELD_LIST_DCN3_0(type) \ - type HDMI_GENERIC8_CONT;\ - type HDMI_GENERIC8_SEND;\ - type HDMI_GENERIC8_LINE;\ - type HDMI_GENERIC9_CONT;\ - type HDMI_GENERIC9_SEND;\ - type HDMI_GENERIC9_LINE;\ - type HDMI_GENERIC10_CONT;\ - type HDMI_GENERIC10_SEND;\ - type HDMI_GENERIC10_LINE;\ - type HDMI_GENERIC11_CONT;\ - type HDMI_GENERIC11_SEND;\ - type HDMI_GENERIC11_LINE;\ - type HDMI_GENERIC12_CONT;\ - type HDMI_GENERIC12_SEND;\ - type HDMI_GENERIC12_LINE;\ - type HDMI_GENERIC13_CONT;\ - type HDMI_GENERIC13_SEND;\ - type HDMI_GENERIC13_LINE;\ - type HDMI_GENERIC14_CONT;\ - type HDMI_GENERIC14_SEND;\ - type HDMI_GENERIC14_LINE;\ - type DP_SEC_GSP11_PPS;\ - type DP_SEC_GSP11_ENABLE;\ - type DP_SEC_GSP11_LINE_NUM - -#define SE_REG_FIELD_LIST_DCN3_1_COMMON(type) \ - type DIG_FIFO_OUTPUT_PIXEL_MODE;\ - type DP_PIXEL_PER_CYCLE_PROCESSING_MODE;\ - type DIG_SYMCLK_FE_ON;\ - type DIG_FIFO_READ_START_LEVEL;\ - type DIG_FIFO_ENABLE;\ - type DIG_FIFO_RESET;\ - type DIG_FIFO_RESET_DONE;\ - type PIXEL_ENCODING_TYPE;\ - type UNCOMPRESSED_PIXEL_FORMAT;\ - type UNCOMPRESSED_COMPONENT_DEPTH - -#define SE_REG_FIELD_LIST_DCN3_5_COMMON(type) \ - type DIG_FE_CLK_EN;\ - type DIG_FE_MODE;\ - type DIG_FE_SOFT_RESET;\ - type DIG_FE_ENABLE;\ - type DIG_FE_SYMCLK_FE_G_CLOCK_ON;\ - type DIG_FE_DISPCLK_G_CLOCK_ON;\ - type DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON;\ - type DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON;\ - type DIG_FE_SOCCLK_G_AFMT_CLOCK_ON;\ - type DIG_STREAM_LINK_TARGET - -struct dcn10_stream_encoder_shift { - SE_REG_FIELD_LIST_DCN1_0(uint8_t); - uint8_t HDMI_ACP_SEND; - SE_REG_FIELD_LIST_DCN2_0(uint8_t); - SE_REG_FIELD_LIST_DCN3_0(uint8_t); - SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t); - SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t); -}; - -struct dcn10_stream_encoder_mask { - SE_REG_FIELD_LIST_DCN1_0(uint32_t); - uint32_t HDMI_ACP_SEND; - SE_REG_FIELD_LIST_DCN2_0(uint32_t); - SE_REG_FIELD_LIST_DCN3_0(uint32_t); - SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t); - SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t); -}; - -struct dcn10_stream_encoder { - struct stream_encoder base; - const struct dcn10_stream_enc_registers *regs; - const struct dcn10_stream_encoder_shift *se_shift; - const struct dcn10_stream_encoder_mask *se_mask; -}; - -void dcn10_stream_encoder_construct( - struct dcn10_stream_encoder *enc1, - struct dc_context *ctx, - struct dc_bios *bp, - enum engine_id eng_id, - const struct dcn10_stream_enc_registers *regs, - const struct dcn10_stream_encoder_shift *se_shift, - const struct dcn10_stream_encoder_mask *se_mask); - -void enc1_update_generic_info_packet( - struct dcn10_stream_encoder *enc1, - uint32_t packet_index, - const struct dc_info_packet *info_packet); - -void enc1_stream_encoder_dp_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing, - enum dc_color_space output_color_space, - bool use_vsc_sdp_for_colorimetry, - uint32_t enable_sdp_splitting); - -void enc1_stream_encoder_hdmi_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing, - int actual_pix_clk_khz, - bool enable_audio); - -void enc1_stream_encoder_dvi_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing, - bool is_dual_link); - -void enc1_stream_encoder_set_throttled_vcp_size( - struct stream_encoder *enc, - struct fixed31_32 avg_time_slots_per_mtp); - -void enc1_stream_encoder_update_dp_info_packets( - struct stream_encoder *enc, - const struct encoder_info_frame *info_frame); - -void enc1_stream_encoder_send_immediate_sdp_message( - struct stream_encoder *enc, - const uint8_t *custom_sdp_message, - unsigned int sdp_message_size); - -void enc1_stream_encoder_stop_dp_info_packets( - struct stream_encoder *enc); - -void enc1_stream_encoder_dp_blank( - struct dc_link *link, - struct stream_encoder *enc); - -void enc1_stream_encoder_dp_unblank( - struct dc_link *link, - struct stream_encoder *enc, - const struct encoder_unblank_param *param); - -void enc1_setup_stereo_sync( - struct stream_encoder *enc, - int tg_inst, bool enable); - -void enc1_stream_encoder_set_avmute( - struct stream_encoder *enc, - bool enable); - -void enc1_se_audio_mute_control( - struct stream_encoder *enc, - bool mute); - -void enc1_se_dp_audio_setup( - struct stream_encoder *enc, - unsigned int az_inst, - struct audio_info *info); - -void enc1_se_dp_audio_enable( - struct stream_encoder *enc); - -void enc1_se_dp_audio_disable( - struct stream_encoder *enc); - -void enc1_se_hdmi_audio_setup( - struct stream_encoder *enc, - unsigned int az_inst, - struct audio_info *info, - struct audio_crtc_info *audio_crtc_info); - -void enc1_se_hdmi_audio_disable( - struct stream_encoder *enc); - -void enc1_dig_connect_to_otg( - struct stream_encoder *enc, - int tg_inst); - -unsigned int enc1_dig_source_otg( - struct stream_encoder *enc); - -void enc1_stream_encoder_set_stream_attribute_helper( - struct dcn10_stream_encoder *enc1, - struct dc_crtc_timing *crtc_timing); - -void enc1_se_enable_audio_clock( - struct stream_encoder *enc, - bool enable); - -void enc1_se_enable_dp_audio( - struct stream_encoder *enc); - -void get_audio_clock_info( - enum dc_color_depth color_depth, - uint32_t crtc_pixel_clock_100Hz, - uint32_t actual_pixel_clock_100Hz, - struct audio_clock_info *audio_clock_info); - -void enc1_reset_hdmi_stream_attribute( - struct stream_encoder *enc); - -bool enc1_stream_encoder_dp_get_pixel_format( - struct stream_encoder *enc, - enum dc_pixel_encoding *encoding, - enum dc_color_depth *depth); - -#endif /* __DC_STREAM_ENCODER_DCN10_H__ */ |