diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20')
22 files changed, 16 insertions, 9888 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile index 3dae3943b056..25ba0d310d46 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile @@ -1,11 +1,7 @@ # SPDX-License-Identifier: MIT -# -# Makefile for DCN. +# Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved. -DCN20 = dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \ - dcn20_mpc.o dcn20_opp.o dcn20_hubbub.o dcn20_mmhubbub.o \ - dcn20_stream_encoder.o dcn20_link_encoder.o dcn20_dccg.o \ - dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o +DCN20 = dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c deleted file mode 100644 index 5999b2da3a01..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include <linux/slab.h> - -#include "reg_helper.h" -#include "core_types.h" -#include "dcn20_dccg.h" - -#define TO_DCN_DCCG(dccg)\ - container_of(dccg, struct dcn_dccg, base) - -#define REG(reg) \ - (dccg_dcn->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name - -#define CTX \ - dccg_dcn->base.ctx -#define DC_LOGGER \ - dccg->ctx->logger - -void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - if (dccg->ref_dppclk && req_dppclk) { - int ref_dppclk = dccg->ref_dppclk; - int modulo, phase; - - // phase / modulo = dpp pipe clk / dpp global clk - modulo = 0xff; // use FF at the end - phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; - - if (phase > 0xff) { - ASSERT(false); - phase = 0xff; - } - - REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, - DPPCLK0_DTO_PHASE, phase, - DPPCLK0_DTO_MODULO, modulo); - REG_UPDATE(DPPCLK_DTO_CTRL, - DPPCLK_DTO_ENABLE[dpp_inst], 1); - } else { - REG_UPDATE(DPPCLK_DTO_CTRL, - DPPCLK_DTO_ENABLE[dpp_inst], 0); - } - - dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; -} - -void dccg2_get_dccg_ref_freq(struct dccg *dccg, - unsigned int xtalin_freq_inKhz, - unsigned int *dccg_ref_freq_inKhz) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - uint32_t clk_en = 0; - uint32_t clk_sel = 0; - - REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel); - - if (clk_en != 0) { - // DCN20 has never been validated for non-xtalin as reference - // frequency. There's actually no way for DC to determine what - // frequency a non-xtalin source is. - ASSERT_CRITICAL(false); - } - - *dccg_ref_freq_inKhz = xtalin_freq_inKhz; - - return; -} - -void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, - bool en) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, - DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0); -} - -void dccg2_otg_add_pixel(struct dccg *dccg, - uint32_t otg_inst) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], - OTG_ADD_PIXEL[otg_inst], 0, - OTG_DROP_PIXEL[otg_inst], 0); - REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], - OTG_ADD_PIXEL[otg_inst], 1); -} - -void dccg2_otg_drop_pixel(struct dccg *dccg, - uint32_t otg_inst) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], - OTG_ADD_PIXEL[otg_inst], 0, - OTG_DROP_PIXEL[otg_inst], 0); - REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], - OTG_DROP_PIXEL[otg_inst], 1); -} - -void dccg2_init(struct dccg *dccg) -{ -} - -static const struct dccg_funcs dccg2_funcs = { - .update_dpp_dto = dccg2_update_dpp_dto, - .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, - .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, - .otg_add_pixel = dccg2_otg_add_pixel, - .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init -}; - -struct dccg *dccg2_create( - struct dc_context *ctx, - const struct dccg_registers *regs, - const struct dccg_shift *dccg_shift, - const struct dccg_mask *dccg_mask) -{ - struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_ATOMIC); - struct dccg *base; - - if (dccg_dcn == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - base = &dccg_dcn->base; - base->ctx = ctx; - base->funcs = &dccg2_funcs; - - dccg_dcn->regs = regs; - dccg_dcn->dccg_shift = dccg_shift; - dccg_dcn->dccg_mask = dccg_mask; - - return &dccg_dcn->base; -} - -void dcn_dccg_destroy(struct dccg **dccg) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(*dccg); - - kfree(dccg_dcn); - *dccg = NULL; -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h deleted file mode 100644 index ef5c22f41563..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ /dev/null @@ -1,428 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DCN20_DCCG_H__ -#define __DCN20_DCCG_H__ - -#include "dccg.h" - -#define DCCG_COMMON_REG_LIST_DCN_BASE() \ - SR(DPPCLK_DTO_CTRL),\ - DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ - DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ - DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ - DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ - SR(REFCLK_CNTL),\ - DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ - DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\ - SR(DISPCLK_FREQ_CHANGE_CNTL) - -#define DCCG_REG_LIST_DCN2() \ - DCCG_COMMON_REG_LIST_DCN_BASE(),\ - DCCG_SRII(DTO_PARAM, DPPCLK, 4),\ - DCCG_SRII(DTO_PARAM, DPPCLK, 5),\ - DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ - DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ - DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\ - DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5) - -#define DCCG_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix - -#define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ - .field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix - -#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\ - .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix - -#define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\ - DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ - DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ - DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ - DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\ - DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\ - DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\ - DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\ - DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\ - DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\ - DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\ - DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\ - DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh) - - - - -#define DCCG_MASK_SH_LIST_DCN2(mask_sh) \ - DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh) - -#define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) \ - DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh) - - -#define DCCG_REG_FIELD_LIST(type) \ - type DPPCLK0_DTO_PHASE;\ - type DPPCLK0_DTO_MODULO;\ - type DPPCLK_DTO_ENABLE[6];\ - type DPPCLK_DTO_DB_EN[6];\ - type REFCLK_CLOCK_EN;\ - type REFCLK_SRC_SEL;\ - type DISPCLK_STEP_DELAY;\ - type DISPCLK_STEP_SIZE;\ - type DISPCLK_FREQ_RAMP_DONE;\ - type DISPCLK_MAX_ERRDET_CYCLES;\ - type DCCG_FIFO_ERRDET_RESET;\ - type DCCG_FIFO_ERRDET_STATE;\ - type DCCG_FIFO_ERRDET_OVR_EN;\ - type DISPCLK_CHG_FWD_CORR_DISABLE;\ - type DISPCLK_FREQ_CHANGE_CNTL;\ - type OTG_ADD_PIXEL[MAX_PIPES];\ - type OTG_DROP_PIXEL[MAX_PIPES]; - -#define DCCG3_REG_FIELD_LIST(type) \ - type HDMICHARCLK0_EN;\ - type HDMICHARCLK0_SRC_SEL;\ - type PHYASYMCLK_FORCE_EN;\ - type PHYASYMCLK_FORCE_SRC_SEL;\ - type PHYBSYMCLK_FORCE_EN;\ - type PHYBSYMCLK_FORCE_SRC_SEL;\ - type PHYCSYMCLK_FORCE_EN;\ - type PHYCSYMCLK_FORCE_SRC_SEL; - -#define DCCG31_REG_FIELD_LIST(type) \ - type PHYDSYMCLK_FORCE_EN;\ - type PHYDSYMCLK_FORCE_SRC_SEL;\ - type PHYESYMCLK_FORCE_EN;\ - type PHYESYMCLK_FORCE_SRC_SEL;\ - type DPSTREAMCLK_PIPE0_EN;\ - type DPSTREAMCLK_PIPE1_EN;\ - type DPSTREAMCLK_PIPE2_EN;\ - type DPSTREAMCLK_PIPE3_EN;\ - type HDMISTREAMCLK0_SRC_SEL;\ - type HDMISTREAMCLK0_DTO_FORCE_DIS;\ - type SYMCLK32_SE0_SRC_SEL;\ - type SYMCLK32_SE1_SRC_SEL;\ - type SYMCLK32_SE2_SRC_SEL;\ - type SYMCLK32_SE3_SRC_SEL;\ - type SYMCLK32_SE0_EN;\ - type SYMCLK32_SE1_EN;\ - type SYMCLK32_SE2_EN;\ - type SYMCLK32_SE3_EN;\ - type SYMCLK32_LE0_SRC_SEL;\ - type SYMCLK32_LE1_SRC_SEL;\ - type SYMCLK32_LE0_EN;\ - type SYMCLK32_LE1_EN;\ - type DTBCLK_DTO_ENABLE[MAX_PIPES];\ - type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\ - type PIPE_DTO_SRC_SEL[MAX_PIPES];\ - type DTBCLK_DTO_DIV[MAX_PIPES];\ - type DCCG_AUDIO_DTO_SEL;\ - type DCCG_AUDIO_DTO0_SOURCE_SEL;\ - type DENTIST_DISPCLK_CHG_MODE;\ - type DSCCLK0_DTO_PHASE;\ - type DSCCLK0_DTO_MODULO;\ - type DSCCLK1_DTO_PHASE;\ - type DSCCLK1_DTO_MODULO;\ - type DSCCLK2_DTO_PHASE;\ - type DSCCLK2_DTO_MODULO;\ - type DSCCLK0_DTO_ENABLE;\ - type DSCCLK1_DTO_ENABLE;\ - type DSCCLK2_DTO_ENABLE;\ - type SYMCLK32_ROOT_SE0_GATE_DISABLE;\ - type SYMCLK32_ROOT_SE1_GATE_DISABLE;\ - type SYMCLK32_ROOT_SE2_GATE_DISABLE;\ - type SYMCLK32_ROOT_SE3_GATE_DISABLE;\ - type SYMCLK32_SE0_GATE_DISABLE;\ - type SYMCLK32_SE1_GATE_DISABLE;\ - type SYMCLK32_SE2_GATE_DISABLE;\ - type SYMCLK32_SE3_GATE_DISABLE;\ - type SYMCLK32_ROOT_LE0_GATE_DISABLE;\ - type SYMCLK32_ROOT_LE1_GATE_DISABLE;\ - type SYMCLK32_LE0_GATE_DISABLE;\ - type SYMCLK32_LE1_GATE_DISABLE;\ - type DPSTREAMCLK_ROOT_GATE_DISABLE;\ - type DPSTREAMCLK_GATE_DISABLE;\ - type HDMISTREAMCLK0_DTO_PHASE;\ - type HDMISTREAMCLK0_DTO_MODULO;\ - type HDMICHARCLK0_GATE_DISABLE;\ - type HDMICHARCLK0_ROOT_GATE_DISABLE; \ - type PHYASYMCLK_GATE_DISABLE; \ - type PHYBSYMCLK_GATE_DISABLE; \ - type PHYCSYMCLK_GATE_DISABLE; \ - type PHYDSYMCLK_GATE_DISABLE; \ - type PHYESYMCLK_GATE_DISABLE; - -#define DCCG314_REG_FIELD_LIST(type) \ - type DSCCLK3_DTO_PHASE;\ - type DSCCLK3_DTO_MODULO;\ - type DSCCLK3_DTO_ENABLE;\ - type DENTIST_DISPCLK_RDIVIDER;\ - type DENTIST_DISPCLK_WDIVIDER; - -#define DCCG32_REG_FIELD_LIST(type) \ - type DPSTREAMCLK0_EN;\ - type DPSTREAMCLK1_EN;\ - type DPSTREAMCLK2_EN;\ - type DPSTREAMCLK3_EN;\ - type DPSTREAMCLK0_SRC_SEL;\ - type DPSTREAMCLK1_SRC_SEL;\ - type DPSTREAMCLK2_SRC_SEL;\ - type DPSTREAMCLK3_SRC_SEL;\ - type HDMISTREAMCLK0_EN;\ - type OTG0_PIXEL_RATE_DIVK1;\ - type OTG0_PIXEL_RATE_DIVK2;\ - type OTG1_PIXEL_RATE_DIVK1;\ - type OTG1_PIXEL_RATE_DIVK2;\ - type OTG2_PIXEL_RATE_DIVK1;\ - type OTG2_PIXEL_RATE_DIVK2;\ - type OTG3_PIXEL_RATE_DIVK1;\ - type OTG3_PIXEL_RATE_DIVK2;\ - type DTBCLK_P0_SRC_SEL;\ - type DTBCLK_P0_EN;\ - type DTBCLK_P1_SRC_SEL;\ - type DTBCLK_P1_EN;\ - type DTBCLK_P2_SRC_SEL;\ - type DTBCLK_P2_EN;\ - type DTBCLK_P3_SRC_SEL;\ - type DTBCLK_P3_EN;\ - type DENTIST_DISPCLK_CHG_DONE; - -#define DCCG35_REG_FIELD_LIST(type) \ - type DPPCLK0_EN;\ - type DPPCLK1_EN;\ - type DPPCLK2_EN;\ - type DPPCLK3_EN;\ - type DSCCLK0_EN;\ - type DSCCLK1_EN;\ - type DSCCLK2_EN;\ - type DSCCLK3_EN;\ - type DISPCLK_DCCG_GATE_DISABLE;\ - type DCCG_GLOBAL_FGCG_REP_DIS; \ - type PHYASYMCLK_EN;\ - type PHYASYMCLK_SRC_SEL;\ - type PHYBSYMCLK_EN;\ - type PHYBSYMCLK_SRC_SEL;\ - type PHYCSYMCLK_EN;\ - type PHYCSYMCLK_SRC_SEL;\ - type PHYDSYMCLK_EN;\ - type PHYDSYMCLK_SRC_SEL;\ - type PHYESYMCLK_EN;\ - type PHYESYMCLK_SRC_SEL;\ - type PHYASYMCLK_ROOT_GATE_DISABLE;\ - type PHYBSYMCLK_ROOT_GATE_DISABLE;\ - type PHYCSYMCLK_ROOT_GATE_DISABLE;\ - type PHYDSYMCLK_ROOT_GATE_DISABLE;\ - type PHYESYMCLK_ROOT_GATE_DISABLE;\ - type HDMISTREAMCLK0_GATE_DISABLE;\ - type HDMISTREAMCLK1_GATE_DISABLE;\ - type HDMISTREAMCLK2_GATE_DISABLE;\ - type HDMISTREAMCLK3_GATE_DISABLE;\ - type HDMISTREAMCLK4_GATE_DISABLE;\ - type HDMISTREAMCLK5_GATE_DISABLE;\ - type SYMCLKA_CLOCK_ENABLE;\ - type SYMCLKB_CLOCK_ENABLE;\ - type SYMCLKC_CLOCK_ENABLE;\ - type SYMCLKD_CLOCK_ENABLE;\ - type SYMCLKE_CLOCK_ENABLE;\ - type SYMCLKA_FE_EN;\ - type SYMCLKB_FE_EN;\ - type SYMCLKC_FE_EN;\ - type SYMCLKD_FE_EN;\ - type SYMCLKE_FE_EN;\ - type SYMCLKA_SRC_SEL;\ - type SYMCLKB_SRC_SEL;\ - type SYMCLKC_SRC_SEL;\ - type SYMCLKD_SRC_SEL;\ - type SYMCLKE_SRC_SEL;\ - type SYMCLKA_FE_SRC_SEL;\ - type SYMCLKB_FE_SRC_SEL;\ - type SYMCLKC_FE_SRC_SEL;\ - type SYMCLKD_FE_SRC_SEL;\ - type SYMCLKE_FE_SRC_SEL;\ - type DTBCLK_P0_GATE_DISABLE;\ - type DTBCLK_P1_GATE_DISABLE;\ - type DTBCLK_P2_GATE_DISABLE;\ - type DTBCLK_P3_GATE_DISABLE;\ - type DSCCLK0_ROOT_GATE_DISABLE;\ - type DSCCLK1_ROOT_GATE_DISABLE;\ - type DSCCLK2_ROOT_GATE_DISABLE;\ - type DSCCLK3_ROOT_GATE_DISABLE;\ - type SYMCLKA_FE_ROOT_GATE_DISABLE;\ - type SYMCLKB_FE_ROOT_GATE_DISABLE;\ - type SYMCLKC_FE_ROOT_GATE_DISABLE;\ - type SYMCLKD_FE_ROOT_GATE_DISABLE;\ - type SYMCLKE_FE_ROOT_GATE_DISABLE;\ - type DPPCLK0_ROOT_GATE_DISABLE;\ - type DPPCLK1_ROOT_GATE_DISABLE;\ - type DPPCLK2_ROOT_GATE_DISABLE;\ - type DPPCLK3_ROOT_GATE_DISABLE;\ - type HDMISTREAMCLK0_ROOT_GATE_DISABLE;\ - type SYMCLKA_ROOT_GATE_DISABLE;\ - type SYMCLKB_ROOT_GATE_DISABLE;\ - type SYMCLKC_ROOT_GATE_DISABLE;\ - type SYMCLKD_ROOT_GATE_DISABLE;\ - type SYMCLKE_ROOT_GATE_DISABLE;\ - type PHYA_REFCLK_ROOT_GATE_DISABLE;\ - type PHYB_REFCLK_ROOT_GATE_DISABLE;\ - type PHYC_REFCLK_ROOT_GATE_DISABLE;\ - type PHYD_REFCLK_ROOT_GATE_DISABLE;\ - type PHYE_REFCLK_ROOT_GATE_DISABLE;\ - type DPSTREAMCLK0_ROOT_GATE_DISABLE;\ - type DPSTREAMCLK1_ROOT_GATE_DISABLE;\ - type DPSTREAMCLK2_ROOT_GATE_DISABLE;\ - type DPSTREAMCLK3_ROOT_GATE_DISABLE;\ - type DPSTREAMCLK0_GATE_DISABLE;\ - type DPSTREAMCLK1_GATE_DISABLE;\ - type DPSTREAMCLK2_GATE_DISABLE;\ - type DPSTREAMCLK3_GATE_DISABLE;\ - -struct dccg_shift { - DCCG_REG_FIELD_LIST(uint8_t) - DCCG3_REG_FIELD_LIST(uint8_t) - DCCG31_REG_FIELD_LIST(uint8_t) - DCCG314_REG_FIELD_LIST(uint8_t) - DCCG32_REG_FIELD_LIST(uint8_t) - DCCG35_REG_FIELD_LIST(uint8_t) -}; - -struct dccg_mask { - DCCG_REG_FIELD_LIST(uint32_t) - DCCG3_REG_FIELD_LIST(uint32_t) - DCCG31_REG_FIELD_LIST(uint32_t) - DCCG314_REG_FIELD_LIST(uint32_t) - DCCG32_REG_FIELD_LIST(uint32_t) - DCCG35_REG_FIELD_LIST(uint32_t) -}; - -struct dccg_registers { - uint32_t DPPCLK_DTO_CTRL; - uint32_t DPPCLK_DTO_PARAM[6]; - uint32_t REFCLK_CNTL; - uint32_t DISPCLK_FREQ_CHANGE_CNTL; - uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; - uint32_t HDMICHARCLK_CLOCK_CNTL[6]; - uint32_t PHYASYMCLK_CLOCK_CNTL; - uint32_t PHYBSYMCLK_CLOCK_CNTL; - uint32_t PHYCSYMCLK_CLOCK_CNTL; - uint32_t PHYDSYMCLK_CLOCK_CNTL; - uint32_t PHYESYMCLK_CLOCK_CNTL; - uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; - uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; - uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO; - uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE; - uint32_t DCCG_AUDIO_DTO_SOURCE; - uint32_t DPSTREAMCLK_CNTL; - uint32_t HDMISTREAMCLK_CNTL; - uint32_t SYMCLK32_SE_CNTL; - uint32_t SYMCLK32_LE_CNTL; - uint32_t DENTIST_DISPCLK_CNTL; - uint32_t DSCCLK_DTO_CTRL; - uint32_t DSCCLK0_DTO_PARAM; - uint32_t DSCCLK1_DTO_PARAM; - uint32_t DSCCLK2_DTO_PARAM; - uint32_t DSCCLK3_DTO_PARAM; - uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE; - uint32_t DPSTREAMCLK_GATE_DISABLE; - uint32_t DCCG_GATE_DISABLE_CNTL; - uint32_t DCCG_GATE_DISABLE_CNTL2; - uint32_t DCCG_GATE_DISABLE_CNTL3; - uint32_t HDMISTREAMCLK0_DTO_PARAM; - uint32_t DCCG_GATE_DISABLE_CNTL4; - uint32_t OTG_PIXEL_RATE_DIV; - uint32_t DTBCLK_P_CNTL; - uint32_t DPPCLK_CTRL; - uint32_t DCCG_GATE_DISABLE_CNTL5; - uint32_t DCCG_GATE_DISABLE_CNTL6; - uint32_t DCCG_GLOBAL_FGCG_REP_CNTL; - uint32_t SYMCLKA_CLOCK_ENABLE; - uint32_t SYMCLKB_CLOCK_ENABLE; - uint32_t SYMCLKC_CLOCK_ENABLE; - uint32_t SYMCLKD_CLOCK_ENABLE; - uint32_t SYMCLKE_CLOCK_ENABLE; -}; - -struct dcn_dccg { - struct dccg base; - const struct dccg_registers *regs; - const struct dccg_shift *dccg_shift; - const struct dccg_mask *dccg_mask; -}; - -void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk); - -void dccg2_get_dccg_ref_freq(struct dccg *dccg, - unsigned int xtalin_freq_inKhz, - unsigned int *dccg_ref_freq_inKhz); - -void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, - bool en); -void dccg2_otg_add_pixel(struct dccg *dccg, - uint32_t otg_inst); -void dccg2_otg_drop_pixel(struct dccg *dccg, - uint32_t otg_inst); - - -void dccg2_init(struct dccg *dccg); - -struct dccg *dccg2_create( - struct dc_context *ctx, - const struct dccg_registers *regs, - const struct dccg_shift *dccg_shift, - const struct dccg_mask *dccg_mask); - -void dcn_dccg_destroy(struct dccg **dccg); - -#endif //__DCN20_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c deleted file mode 100644 index 1516c0a48726..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -#include "core_types.h" - -#include "reg_helper.h" -#include "dcn20_dpp.h" -#include "basics/conversion.h" - -#define NUM_PHASES 64 -#define HORZ_MAX_TAPS 8 -#define VERT_MAX_TAPS 8 - -#define BLACK_OFFSET_RGB_Y 0x0 -#define BLACK_OFFSET_CBCR 0x8000 - -#define REG(reg)\ - dpp->tf_regs->reg - -#define CTX \ - dpp->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - dpp->tf_shift->field_name, dpp->tf_mask->field_name - -void dpp20_read_state(struct dpp *dpp_base, - struct dcn_dpp_state *s) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_GET(DPP_CONTROL, - DPP_CLOCK_ENABLE, &s->is_enabled); - - // Degamma LUT (RAM) - REG_GET(CM_DGAM_CONTROL, - CM_DGAM_LUT_MODE, &s->dgam_lut_mode); - - // Shaper LUT (RAM), 3D LUT (mode, bit-depth, size) - REG_GET(CM_SHAPER_CONTROL, - CM_SHAPER_LUT_MODE, &s->shaper_lut_mode); - REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL, - CM_3DLUT_CONFIG_STATUS, &s->lut3d_mode, - CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth); - REG_GET(CM_3DLUT_MODE, - CM_3DLUT_SIZE, &s->lut3d_size); - - // Blend/Out Gamma (RAM) - REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK, - CM_BLNDGAM_CONFIG_STATUS, &s->rgam_lut_mode); -} - -void dpp2_power_on_obuf( - struct dpp *dpp_base, - bool power_on) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0); - - REG_UPDATE(OBUF_MEM_PWR_CTRL, - OBUF_MEM_PWR_FORCE, power_on == true ? 0:1); - - REG_UPDATE(DSCL_MEM_PWR_CTRL, - LUT_MEM_PWR_FORCE, power_on == true ? 0:1); -} - -void dpp2_dummy_program_input_lut( - struct dpp *dpp_base, - const struct dc_gamma *gamma) -{} - -static void dpp2_cnv_setup ( - struct dpp *dpp_base, - enum surface_pixel_format format, - enum expansion_mode mode, - struct dc_csc_transform input_csc_color_matrix, - enum dc_color_space input_color_space, - struct cnv_alpha_2bit_lut *alpha_2bit_lut) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - uint32_t pixel_format = 0; - uint32_t alpha_en = 1; - enum dc_color_space color_space = COLOR_SPACE_SRGB; - enum dcn20_input_csc_select select = DCN2_ICSC_SELECT_BYPASS; - bool force_disable_cursor = false; - struct out_csc_color_matrix tbl_entry; - uint32_t is_2bit = 0; - int i = 0; - - REG_SET_2(FORMAT_CONTROL, 0, - CNVC_BYPASS, 0, - FORMAT_EXPANSION_MODE, mode); - - //hardcode default - //FORMAT_CONTROL. FORMAT_CNV16 default 0: U0.16/S.1.15; 1: U1.15/ S.1.14 - //FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN default 0: disabled 1: enabled - //FORMAT_CONTROL. CLAMP_POSITIVE default 0: disabled 1: enabled - //FORMAT_CONTROL. CLAMP_POSITIVE_C default 0: disabled 1: enabled - REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); - REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); - REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); - REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); - - switch (format) { - case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: - pixel_format = 1; - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB565: - pixel_format = 3; - alpha_en = 0; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: - pixel_format = 8; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: - pixel_format = 10; - is_2bit = 1; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: - force_disable_cursor = false; - pixel_format = 65; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: - force_disable_cursor = true; - pixel_format = 64; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: - force_disable_cursor = true; - pixel_format = 67; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: - force_disable_cursor = true; - pixel_format = 66; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: - pixel_format = 26; /* ARGB16161616_UNORM */ - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: - pixel_format = 24; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: - pixel_format = 25; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: - pixel_format = 12; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: - pixel_format = 112; - alpha_en = 0; - break; - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: - pixel_format = 113; - alpha_en = 0; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: - pixel_format = 114; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - is_2bit = 1; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: - pixel_format = 115; - color_space = COLOR_SPACE_YCBCR709; - select = DCN2_ICSC_SELECT_ICSC_A; - is_2bit = 1; - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: - pixel_format = 118; - alpha_en = 0; - break; - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: - pixel_format = 119; - alpha_en = 0; - break; - default: - break; - } - - /* Set default color space based on format if none is given. */ - color_space = input_color_space ? input_color_space : color_space; - - if (is_2bit == 1 && alpha_2bit_lut != NULL) { - REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); - REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); - REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); - REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); - } - - REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, - CNVC_SURFACE_PIXEL_FORMAT, pixel_format); - REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); - - // if input adjustments exist, program icsc with those values - if (input_csc_color_matrix.enable_adjustment - == true) { - for (i = 0; i < 12; i++) - tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; - - tbl_entry.color_space = input_color_space; - - if (color_space >= COLOR_SPACE_YCBCR601) - select = DCN2_ICSC_SELECT_ICSC_A; - else - select = DCN2_ICSC_SELECT_BYPASS; - - dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry); - } else - dpp2_program_input_csc(dpp_base, color_space, select, NULL); - - if (force_disable_cursor) { - REG_UPDATE(CURSOR_CONTROL, - CURSOR_ENABLE, 0); - REG_UPDATE(CURSOR0_CONTROL, - CUR0_ENABLE, 0); - - } - dpp2_power_on_obuf(dpp_base, true); - -} - -/*compute the maximum number of lines that we can fit in the line buffer*/ -void dscl2_calc_lb_num_partitions( - const struct scaler_data *scl_data, - enum lb_memory_config lb_config, - int *num_part_y, - int *num_part_c) -{ - int memory_line_size_y, memory_line_size_c, memory_line_size_a, - lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a; - - int line_size = scl_data->viewport.width < scl_data->recout.width ? - scl_data->viewport.width : scl_data->recout.width; - int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? - scl_data->viewport_c.width : scl_data->recout.width; - - if (line_size == 0) - line_size = 1; - - if (line_size_c == 0) - line_size_c = 1; - - memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ - memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ - memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ - - if (lb_config == LB_MEMORY_CONFIG_1) { - lb_memory_size = 970; - lb_memory_size_c = 970; - lb_memory_size_a = 970; - } else if (lb_config == LB_MEMORY_CONFIG_2) { - lb_memory_size = 1290; - lb_memory_size_c = 1290; - lb_memory_size_a = 1290; - } else if (lb_config == LB_MEMORY_CONFIG_3) { - /* 420 mode: using 3rd mem from Y, Cr and Cb */ - lb_memory_size = 970 + 1290 + 484 + 484 + 484; - lb_memory_size_c = 970 + 1290; - lb_memory_size_a = 970 + 1290 + 484; - } else { - lb_memory_size = 970 + 1290 + 484; - lb_memory_size_c = 970 + 1290 + 484; - lb_memory_size_a = 970 + 1290 + 484; - } - *num_part_y = lb_memory_size / memory_line_size_y; - *num_part_c = lb_memory_size_c / memory_line_size_c; - num_partitions_a = lb_memory_size_a / memory_line_size_a; - - if (scl_data->lb_params.alpha_en - && (num_partitions_a < *num_part_y)) - *num_part_y = num_partitions_a; - - if (*num_part_y > 64) - *num_part_y = 64; - if (*num_part_c > 64) - *num_part_c = 64; -} - -void dpp2_cnv_set_alpha_keyer( - struct dpp *dpp_base, - struct cnv_color_keyer_params *color_keyer) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_EN, color_keyer->color_keyer_en); - - REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, color_keyer->color_keyer_mode); - - REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, color_keyer->color_keyer_alpha_low); - REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, color_keyer->color_keyer_alpha_high); - - REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low); - REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high); - - REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, color_keyer->color_keyer_green_low); - REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, color_keyer->color_keyer_green_high); - - REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low); - REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high); -} - -void dpp2_set_cursor_attributes( - struct dpp *dpp_base, - struct dc_cursor_attributes *cursor_attributes) -{ - enum dc_cursor_color_format color_format = cursor_attributes->color_format; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - int cur_rom_en = 0; - - if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || - color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { - if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) { - cur_rom_en = 1; - } - } - - REG_UPDATE_3(CURSOR0_CONTROL, - CUR0_MODE, color_format, - CUR0_EXPANSION_MODE, 0, - CUR0_ROM_EN, cur_rom_en); - - if (color_format == CURSOR_MODE_MONO) { - /* todo: clarify what to program these to */ - REG_UPDATE(CURSOR0_COLOR0, - CUR0_COLOR0, 0x00000000); - REG_UPDATE(CURSOR0_COLOR1, - CUR0_COLOR1, 0xFFFFFFFF); - } -} - -void oppn20_dummy_program_regamma_pwl( - struct dpp *dpp, - const struct pwl_params *params, - enum opp_regamma mode) -{} - -static struct dpp_funcs dcn20_dpp_funcs = { - .dpp_read_state = dpp20_read_state, - .dpp_reset = dpp_reset, - .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, - .dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps, - .dpp_set_gamut_remap = dpp2_cm_set_gamut_remap, - .dpp_set_csc_adjustment = NULL, - .dpp_set_csc_default = NULL, - .dpp_program_regamma_pwl = oppn20_dummy_program_regamma_pwl, - .dpp_set_degamma = dpp2_set_degamma, - .dpp_program_input_lut = dpp2_dummy_program_input_lut, - .dpp_full_bypass = dpp1_full_bypass, - .dpp_setup = dpp2_cnv_setup, - .dpp_program_degamma_pwl = dpp2_set_degamma_pwl, - .dpp_program_blnd_lut = dpp20_program_blnd_lut, - .dpp_program_shaper_lut = dpp20_program_shaper, - .dpp_program_3dlut = dpp20_program_3dlut, - .dpp_program_bias_and_scale = NULL, - .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer, - .set_cursor_attributes = dpp2_set_cursor_attributes, - .set_cursor_position = dpp1_set_cursor_position, - .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, - .dpp_dppclk_control = dpp1_dppclk_control, - .dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier, - .dpp_get_gamut_remap = dpp2_cm_get_gamut_remap, -}; - -static struct dpp_caps dcn20_dpp_cap = { - .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT, - .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions, -}; - -bool dpp2_construct( - struct dcn20_dpp *dpp, - struct dc_context *ctx, - uint32_t inst, - const struct dcn2_dpp_registers *tf_regs, - const struct dcn2_dpp_shift *tf_shift, - const struct dcn2_dpp_mask *tf_mask) -{ - dpp->base.ctx = ctx; - - dpp->base.inst = inst; - dpp->base.funcs = &dcn20_dpp_funcs; - dpp->base.caps = &dcn20_dpp_cap; - - dpp->tf_regs = tf_regs; - dpp->tf_shift = tf_shift; - dpp->tf_mask = tf_mask; - - dpp->lb_pixel_depth_supported = - LB_PIXEL_DEPTH_18BPP | - LB_PIXEL_DEPTH_24BPP | - LB_PIXEL_DEPTH_30BPP | - LB_PIXEL_DEPTH_36BPP; - - dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; - dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ - - return true; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h deleted file mode 100644 index 672cde46c4b9..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h +++ /dev/null @@ -1,781 +0,0 @@ -/* Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DCN20_DPP_H__ -#define __DCN20_DPP_H__ - -#include "dcn10/dcn10_dpp.h" - -#define TO_DCN20_DPP(dpp)\ - container_of(dpp, struct dcn20_dpp, base) - -#define TF_REG_LIST_DCN20_COMMON_UPDATED(id) \ - SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \ - SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \ - SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \ - SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \ - SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \ - SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \ - SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id) - -#define TF_REG_LIST_DCN20_COMMON(id) \ - SRI(CM_BLNDGAM_CONTROL, CM, id), \ - SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \ - SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \ - SRI(CM_BLNDGAM_RAMB_START_CNTL_R, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL1_B, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL2_B, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL1_G, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL2_G, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL1_R, CM, id), \ - SRI(CM_BLNDGAM_RAMB_END_CNTL2_R, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_0_1, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_2_3, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_4_5, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_6_7, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_8_9, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_10_11, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_12_13, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_14_15, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_16_17, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_18_19, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_20_21, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_22_23, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_24_25, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_26_27, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_28_29, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_30_31, CM, id), \ - SRI(CM_BLNDGAM_RAMB_REGION_32_33, CM, id), \ - SRI(CM_BLNDGAM_RAMA_START_CNTL_B, CM, id), \ - SRI(CM_BLNDGAM_RAMA_START_CNTL_G, CM, id), \ - SRI(CM_BLNDGAM_RAMA_START_CNTL_R, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL1_B, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL2_B, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL1_G, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL2_G, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL1_R, CM, id), \ - SRI(CM_BLNDGAM_RAMA_END_CNTL2_R, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_0_1, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_2_3, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_4_5, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_6_7, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_8_9, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_10_11, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_12_13, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_14_15, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_16_17, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_18_19, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_20_21, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_22_23, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_24_25, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_26_27, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_28_29, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_30_31, CM, id), \ - SRI(CM_BLNDGAM_RAMA_REGION_32_33, CM, id), \ - SRI(CM_BLNDGAM_LUT_INDEX, CM, id), \ - SRI(CM_BLNDGAM_LUT_DATA, CM, id), \ - SRI(CM_3DLUT_MODE, CM, id), \ - SRI(CM_3DLUT_INDEX, CM, id), \ - SRI(CM_3DLUT_DATA, CM, id), \ - SRI(CM_3DLUT_DATA_30BIT, CM, id), \ - SRI(CM_3DLUT_READ_WRITE_CONTROL, CM, id), \ - SRI(CM_SHAPER_LUT_WRITE_EN_MASK, CM, id), \ - SRI(CM_SHAPER_CONTROL, CM, id), \ - SRI(CM_SHAPER_RAMB_START_CNTL_B, CM, id), \ - SRI(CM_SHAPER_RAMB_START_CNTL_G, CM, id), \ - SRI(CM_SHAPER_RAMB_START_CNTL_R, CM, id), \ - SRI(CM_SHAPER_RAMB_END_CNTL_B, CM, id), \ - SRI(CM_SHAPER_RAMB_END_CNTL_G, CM, id), \ - SRI(CM_SHAPER_RAMB_END_CNTL_R, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_0_1, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_2_3, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_4_5, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_6_7, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_8_9, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_10_11, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_12_13, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_14_15, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_16_17, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_18_19, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_20_21, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_22_23, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_24_25, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_26_27, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_28_29, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_30_31, CM, id), \ - SRI(CM_SHAPER_RAMB_REGION_32_33, CM, id), \ - SRI(CM_SHAPER_RAMA_START_CNTL_B, CM, id), \ - SRI(CM_SHAPER_RAMA_START_CNTL_G, CM, id), \ - SRI(CM_SHAPER_RAMA_START_CNTL_R, CM, id), \ - SRI(CM_SHAPER_RAMA_END_CNTL_B, CM, id), \ - SRI(CM_SHAPER_RAMA_END_CNTL_G, CM, id), \ - SRI(CM_SHAPER_RAMA_END_CNTL_R, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_0_1, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_2_3, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_4_5, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_6_7, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_8_9, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_10_11, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_12_13, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_14_15, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_16_17, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_18_19, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_20_21, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_22_23, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_24_25, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_26_27, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_28_29, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_30_31, CM, id), \ - SRI(CM_SHAPER_RAMA_REGION_32_33, CM, id), \ - SRI(CM_SHAPER_LUT_INDEX, CM, id) - -#define TF_REG_LIST_DCN20_COMMON_APPEND(id) \ - SRI(CM_GAMUT_REMAP_B_C11_C12, CM, id),\ - SRI(CM_GAMUT_REMAP_B_C13_C14, CM, id),\ - SRI(CM_GAMUT_REMAP_B_C21_C22, CM, id),\ - SRI(CM_GAMUT_REMAP_B_C23_C24, CM, id),\ - SRI(CM_GAMUT_REMAP_B_C31_C32, CM, id),\ - SRI(CM_GAMUT_REMAP_B_C33_C34, CM, id),\ - SRI(CM_ICSC_B_C11_C12, CM, id), \ - SRI(CM_ICSC_B_C33_C34, CM, id) - -#define TF_REG_LIST_DCN20(id) \ - TF_REG_LIST_DCN(id), \ - TF_REG_LIST_DCN20_COMMON(id), \ - TF_REG_LIST_DCN20_COMMON_UPDATED(id), \ - SRI(CURSOR_CONTROL, CURSOR0_, id), \ - SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \ - SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \ - SRI(FCNV_FP_BIAS_G, CNVC_CFG, id), \ - SRI(FCNV_FP_BIAS_B, CNVC_CFG, id), \ - SRI(FCNV_FP_SCALE_R, CNVC_CFG, id), \ - SRI(FCNV_FP_SCALE_G, CNVC_CFG, id), \ - SRI(FCNV_FP_SCALE_B, CNVC_CFG, id), \ - SRI(COLOR_KEYER_CONTROL, CNVC_CFG, id), \ - SRI(COLOR_KEYER_ALPHA, CNVC_CFG, id), \ - SRI(COLOR_KEYER_RED, CNVC_CFG, id), \ - SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \ - SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \ - SRI(CM_SHAPER_LUT_DATA, CM, id), \ - SRI(CURSOR_CONTROL, CURSOR0_, id),\ - SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\ - SRI(DSCL_MEM_PWR_CTRL, DSCL, id) - - -#define TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh)\ - TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_LUT_MODE, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh) - - -#define TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh)\ - TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_LUT_INDEX, CM_BLNDGAM_LUT_INDEX, mask_sh), \ - TF_SF(CM0_CM_BLNDGAM_LUT_DATA, CM_BLNDGAM_LUT_DATA, mask_sh), \ - TF_SF(CM0_CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, mask_sh), \ - TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \ - TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_SIZE, mask_sh), \ - TF_SF(CM0_CM_3DLUT_INDEX, CM_3DLUT_INDEX, mask_sh), \ - TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA0, mask_sh), \ - TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA1, mask_sh), \ - TF_SF(CM0_CM_3DLUT_DATA_30BIT, CM_3DLUT_DATA_30BIT, mask_sh), \ - TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, mask_sh), \ - TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_RAM_SEL, mask_sh), \ - TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, mask_sh), \ - TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_READ_SEL, mask_sh), \ - TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ - TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ - TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_EN_MASK, mask_sh), \ - TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_SEL, mask_sh), \ - TF_SF(CM0_CM_SHAPER_LUT_INDEX, CM_SHAPER_LUT_INDEX, mask_sh), \ - TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh) - - -#define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\ - TF_REG_LIST_SH_MASK_DCN(mask_sh), \ - TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \ - TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), \ - TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, mask_sh), \ - TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \ - TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ - TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ - TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ - TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ - TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \ - TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \ - TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \ - TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \ - TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \ - TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \ - TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \ - TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \ - TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \ - TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \ - TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \ - TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \ - TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\ - TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\ - TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh) - -/* DPP CM debug status register: - * - * Status index including current ICSC, Gamut Remap Mode is 9 - * ICSC Mode: [4..3] - * Gamut Remap Mode: [10..9] - */ -#define CM_TEST_DEBUG_DATA_STATUS_IDX 9 - -#define TF_DEBUG_REG_LIST_SH_DCN20 \ - TF_DEBUG_REG_LIST_SH_DCN10, \ - .CM_TEST_DEBUG_DATA_ICSC_MODE = 3, \ - .CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE = 9 - -#define TF_DEBUG_REG_LIST_MASK_DCN20 \ - TF_DEBUG_REG_LIST_MASK_DCN10, \ - .CM_TEST_DEBUG_DATA_ICSC_MODE = 0x18, \ - .CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE = 0x600 - -#define TF_REG_FIELD_LIST_DCN2_0(type) \ - TF_REG_FIELD_LIST(type) \ - type CM_BLNDGAM_LUT_DATA; \ - type CM_TEST_DEBUG_DATA_ICSC_MODE; \ - type CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE; \ - type FORMAT_CNV16; \ - type CNVC_BYPASS_MSB_ALIGN; \ - type CLAMP_POSITIVE; \ - type CLAMP_POSITIVE_C; \ - type ALPHA_2BIT_LUT0; \ - type ALPHA_2BIT_LUT1; \ - type ALPHA_2BIT_LUT2; \ - type ALPHA_2BIT_LUT3; \ - type FCNV_FP_BIAS_R; \ - type FCNV_FP_BIAS_G; \ - type FCNV_FP_BIAS_B; \ - type FCNV_FP_SCALE_R; \ - type FCNV_FP_SCALE_G; \ - type FCNV_FP_SCALE_B; \ - type COLOR_KEYER_EN; \ - type COLOR_KEYER_MODE; \ - type COLOR_KEYER_ALPHA_LOW; \ - type COLOR_KEYER_ALPHA_HIGH; \ - type COLOR_KEYER_RED_LOW; \ - type COLOR_KEYER_RED_HIGH; \ - type COLOR_KEYER_GREEN_LOW; \ - type COLOR_KEYER_GREEN_HIGH; \ - type COLOR_KEYER_BLUE_LOW; \ - type COLOR_KEYER_BLUE_HIGH; \ - type CUR0_PIX_INV_MODE; \ - type CUR0_PIXEL_ALPHA_MOD_EN; \ - type CUR0_ROM_EN;\ - type OBUF_MEM_PWR_FORCE - - -struct dcn2_dpp_shift { - TF_REG_FIELD_LIST_DCN2_0(uint8_t); -}; - -struct dcn2_dpp_mask { - TF_REG_FIELD_LIST_DCN2_0(uint32_t); -}; - -#define DPP_DCN2_REG_VARIABLE_LIST \ - DPP_COMMON_REG_VARIABLE_LIST \ - uint32_t CM_BLNDGAM_LUT_DATA; \ - uint32_t ALPHA_2BIT_LUT; \ - uint32_t FCNV_FP_BIAS_R; \ - uint32_t FCNV_FP_BIAS_G; \ - uint32_t FCNV_FP_BIAS_B; \ - uint32_t FCNV_FP_SCALE_R; \ - uint32_t FCNV_FP_SCALE_G; \ - uint32_t FCNV_FP_SCALE_B; \ - uint32_t COLOR_KEYER_CONTROL; \ - uint32_t COLOR_KEYER_ALPHA; \ - uint32_t COLOR_KEYER_RED; \ - uint32_t COLOR_KEYER_GREEN; \ - uint32_t COLOR_KEYER_BLUE; \ - uint32_t OBUF_MEM_PWR_CTRL - -#define DPP_DCN2_REG_VARIABLE_LIST_CM_APPEND \ - uint32_t CM_GAMUT_REMAP_B_C11_C12; \ - uint32_t CM_GAMUT_REMAP_B_C13_C14; \ - uint32_t CM_GAMUT_REMAP_B_C21_C22; \ - uint32_t CM_GAMUT_REMAP_B_C23_C24; \ - uint32_t CM_GAMUT_REMAP_B_C31_C32; \ - uint32_t CM_GAMUT_REMAP_B_C33_C34; \ - uint32_t CM_ICSC_B_C11_C12; \ - uint32_t CM_ICSC_B_C33_C34 - -struct dcn2_dpp_registers { - DPP_DCN2_REG_VARIABLE_LIST; - DPP_DCN2_REG_VARIABLE_LIST_CM_APPEND; -}; - -struct dcn20_dpp { - struct dpp base; - - const struct dcn2_dpp_registers *tf_regs; - const struct dcn2_dpp_shift *tf_shift; - const struct dcn2_dpp_mask *tf_mask; - - const uint16_t *filter_v; - const uint16_t *filter_h; - const uint16_t *filter_v_c; - const uint16_t *filter_h_c; - int lb_pixel_depth_supported; - int lb_memory_size; - int lb_bits_per_entry; - bool is_write_to_ram_a_safe; - struct scaler_data scl_data; - struct pwl_params pwl_data; -}; - -enum dcn20_input_csc_select { - DCN2_ICSC_SELECT_BYPASS = 0, - DCN2_ICSC_SELECT_ICSC_A = 1, - DCN2_ICSC_SELECT_ICSC_B = 2 -}; - -enum dcn20_gamut_remap_select { - DCN2_GAMUT_REMAP_BYPASS = 0, - DCN2_GAMUT_REMAP_COEF_A = 1, - DCN2_GAMUT_REMAP_COEF_B = 2 -}; - -void dpp20_read_state(struct dpp *dpp_base, - struct dcn_dpp_state *s); - -void dpp2_set_degamma_pwl( - struct dpp *dpp_base, - const struct pwl_params *params); - -void dpp2_set_degamma( - struct dpp *dpp_base, - enum ipp_degamma_mode mode); - -void dpp2_cm_set_gamut_remap( - struct dpp *dpp_base, - const struct dpp_grph_csc_adjustment *adjust); - -void dpp2_program_input_csc( - struct dpp *dpp_base, - enum dc_color_space color_space, - enum dcn20_input_csc_select input_select, - const struct out_csc_color_matrix *tbl_entry); - -bool dpp20_program_blnd_lut( - struct dpp *dpp_base, const struct pwl_params *params); - -bool dpp20_program_shaper( - struct dpp *dpp_base, - const struct pwl_params *params); - -bool dpp20_program_3dlut( - struct dpp *dpp_base, - struct tetrahedral_params *params); - -void dpp2_cnv_set_alpha_keyer( - struct dpp *dpp_base, - struct cnv_color_keyer_params *color_keyer); - -void dscl2_calc_lb_num_partitions( - const struct scaler_data *scl_data, - enum lb_memory_config lb_config, - int *num_part_y, - int *num_part_c); - -void dpp2_set_cursor_attributes( - struct dpp *dpp_base, - struct dc_cursor_attributes *cursor_attributes); - -void dpp2_dummy_program_input_lut( - struct dpp *dpp_base, - const struct dc_gamma *gamma); - -void oppn20_dummy_program_regamma_pwl( - struct dpp *dpp, - const struct pwl_params *params, - enum opp_regamma mode); - -void dpp2_set_hdr_multiplier( - struct dpp *dpp_base, - uint32_t multiplier); - -bool dpp2_construct(struct dcn20_dpp *dpp2, - struct dc_context *ctx, - uint32_t inst, - const struct dcn2_dpp_registers *tf_regs, - const struct dcn2_dpp_shift *tf_shift, - const struct dcn2_dpp_mask *tf_mask); - -void dpp2_power_on_obuf( - struct dpp *dpp_base, - bool power_on); - -void dpp2_cm_get_gamut_remap(struct dpp *dpp_base, - struct dpp_grph_csc_adjustment *adjust); -#endif /* __DC_HWSS_DCN20_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c deleted file mode 100644 index 58dc69926e8a..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c +++ /dev/null @@ -1,1202 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" - -#include "core_types.h" - -#include "reg_helper.h" -#include "dcn20_dpp.h" -#include "basics/conversion.h" - -#include "dcn10/dcn10_cm_common.h" - -#define REG(reg)\ - dpp->tf_regs->reg - -#define IND_REG(index) \ - (index) - -#define CTX \ - dpp->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - dpp->tf_shift->field_name, dpp->tf_mask->field_name - - -static void dpp2_enable_cm_block( - struct dpp *dpp_base) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - unsigned int cm_bypass_mode = 0; - //Temp, put CM in bypass mode - if (dpp_base->ctx->dc->debug.cm_in_bypass) - cm_bypass_mode = 1; - - REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode); -} - - -static bool dpp2_degamma_ram_inuse( - struct dpp *dpp_base, - bool *ram_a_inuse) -{ - bool ret = false; - uint32_t status_reg = 0; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_GET(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, - &status_reg); - - if (status_reg == 3) { - *ram_a_inuse = true; - ret = true; - } else if (status_reg == 4) { - *ram_a_inuse = false; - ret = true; - } - return ret; -} - -static void dpp2_program_degamma_lut( - struct dpp *dpp_base, - const struct pwl_result_data *rgb, - uint32_t num, - bool is_ram_a) -{ - uint32_t i; - - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, - CM_DGAM_LUT_WRITE_EN_MASK, 7); - REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, - is_ram_a == true ? 0:1); - - REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0); - for (i = 0 ; i < num; i++) { - REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg); - - REG_SET(CM_DGAM_LUT_DATA, 0, - CM_DGAM_LUT_DATA, rgb[i].delta_red_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, - CM_DGAM_LUT_DATA, rgb[i].delta_green_reg); - REG_SET(CM_DGAM_LUT_DATA, 0, - CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg); - - } - -} - -void dpp2_set_degamma_pwl( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - bool is_ram_a = true; - - dpp1_power_on_degamma_lut(dpp_base, true); - dpp2_enable_cm_block(dpp_base); - dpp2_degamma_ram_inuse(dpp_base, &is_ram_a); - if (is_ram_a == true) - dpp1_program_degamma_lutb_settings(dpp_base, params); - else - dpp1_program_degamma_luta_settings(dpp_base, params); - - dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); - dpp1_degamma_ram_select(dpp_base, !is_ram_a); -} - -void dpp2_set_degamma( - struct dpp *dpp_base, - enum ipp_degamma_mode mode) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - dpp2_enable_cm_block(dpp_base); - - switch (mode) { - case IPP_DEGAMMA_MODE_BYPASS: - /* Setting de gamma bypass for now */ - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0); - break; - case IPP_DEGAMMA_MODE_HW_sRGB: - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1); - break; - case IPP_DEGAMMA_MODE_HW_xvYCC: - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2); - break; - case IPP_DEGAMMA_MODE_USER_PWL: - REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } -} - -static void program_gamut_remap( - struct dcn20_dpp *dpp, - const uint16_t *regval, - enum dcn20_gamut_remap_select select) -{ - uint32_t cur_select = 0; - struct color_matrices_reg gam_regs; - - if (regval == NULL || select == DCN2_GAMUT_REMAP_BYPASS) { - REG_SET(CM_GAMUT_REMAP_CONTROL, 0, - CM_GAMUT_REMAP_MODE, 0); - return; - } - - /* determine which gamut_remap coefficients (A or B) we are using - * currently. select the alternate set to double buffer - * the update so gamut_remap is updated on frame boundary - */ - IX_REG_GET(CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_DATA, - CM_TEST_DEBUG_DATA_STATUS_IDX, - CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE, &cur_select); - - /* value stored in dbg reg will be 1 greater than mode we want */ - if (cur_select != DCN2_GAMUT_REMAP_COEF_A) - select = DCN2_GAMUT_REMAP_COEF_A; - else - select = DCN2_GAMUT_REMAP_COEF_B; - - gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; - gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; - gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; - gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; - - if (select == DCN2_GAMUT_REMAP_COEF_A) { - gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); - gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); - } else { - gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12); - gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34); - } - - cm_helper_program_color_matrices( - dpp->base.ctx, - regval, - &gam_regs); - - REG_SET( - CM_GAMUT_REMAP_CONTROL, 0, - CM_GAMUT_REMAP_MODE, select); - -} - -void dpp2_cm_set_gamut_remap( - struct dpp *dpp_base, - const struct dpp_grph_csc_adjustment *adjust) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - int i = 0; - - if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) - /* Bypass if type is bypass or hw */ - program_gamut_remap(dpp, NULL, DCN2_GAMUT_REMAP_BYPASS); - else { - struct fixed31_32 arr_matrix[12]; - uint16_t arr_reg_val[12]; - - for (i = 0; i < 12; i++) - arr_matrix[i] = adjust->temperature_matrix[i]; - - convert_float_matrix( - arr_reg_val, arr_matrix, 12); - - program_gamut_remap(dpp, arr_reg_val, DCN2_GAMUT_REMAP_COEF_A); - } -} - -static void read_gamut_remap(struct dcn20_dpp *dpp, - uint16_t *regval, - enum dcn20_gamut_remap_select *select) -{ - struct color_matrices_reg gam_regs; - uint32_t selection; - - IX_REG_GET(CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_DATA, - CM_TEST_DEBUG_DATA_STATUS_IDX, - CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE, &selection); - - *select = selection; - - gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; - gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; - gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; - gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; - - if (*select == DCN2_GAMUT_REMAP_COEF_A) { - gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); - gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); - - cm_helper_read_color_matrices(dpp->base.ctx, - regval, - &gam_regs); - - } else if (*select == DCN2_GAMUT_REMAP_COEF_B) { - gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12); - gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34); - - cm_helper_read_color_matrices(dpp->base.ctx, - regval, - &gam_regs); - } -} - -void dpp2_cm_get_gamut_remap(struct dpp *dpp_base, - struct dpp_grph_csc_adjustment *adjust) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - uint16_t arr_reg_val[12]; - enum dcn20_gamut_remap_select select; - - read_gamut_remap(dpp, arr_reg_val, &select); - - if (select == DCN2_GAMUT_REMAP_BYPASS) { - adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - return; - } - - adjust->gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; - convert_hw_matrix(adjust->temperature_matrix, - arr_reg_val, ARRAY_SIZE(arr_reg_val)); -} - -void dpp2_program_input_csc( - struct dpp *dpp_base, - enum dc_color_space color_space, - enum dcn20_input_csc_select input_select, - const struct out_csc_color_matrix *tbl_entry) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - int i; - int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix); - const uint16_t *regval = NULL; - uint32_t cur_select = 0; - enum dcn20_input_csc_select select; - struct color_matrices_reg icsc_regs; - - if (input_select == DCN2_ICSC_SELECT_BYPASS) { - REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0); - return; - } - - if (tbl_entry == NULL) { - for (i = 0; i < arr_size; i++) - if (dpp_input_csc_matrix[i].color_space == color_space) { - regval = dpp_input_csc_matrix[i].regval; - break; - } - - if (regval == NULL) { - BREAK_TO_DEBUGGER(); - return; - } - } else { - regval = tbl_entry->regval; - } - - /* determine which CSC coefficients (A or B) we are using - * currently. select the alternate set to double buffer - * the CSC update so CSC is updated on frame boundary - */ - IX_REG_GET(CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_DATA, - CM_TEST_DEBUG_DATA_STATUS_IDX, - CM_TEST_DEBUG_DATA_ICSC_MODE, &cur_select); - - if (cur_select != DCN2_ICSC_SELECT_ICSC_A) - select = DCN2_ICSC_SELECT_ICSC_A; - else - select = DCN2_ICSC_SELECT_ICSC_B; - - icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; - icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; - icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; - icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; - - if (select == DCN2_ICSC_SELECT_ICSC_A) { - - icsc_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12); - icsc_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34); - - } else { - - icsc_regs.csc_c11_c12 = REG(CM_ICSC_B_C11_C12); - icsc_regs.csc_c33_c34 = REG(CM_ICSC_B_C33_C34); - - } - - cm_helper_program_color_matrices( - dpp->base.ctx, - regval, - &icsc_regs); - - REG_SET(CM_ICSC_CONTROL, 0, - CM_ICSC_MODE, select); -} - -static void dpp20_power_on_blnd_lut( - struct dpp *dpp_base, - bool power_on) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_SET(CM_MEM_PWR_CTRL, 0, - BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0:1); - -} - -static void dpp20_configure_blnd_lut( - struct dpp *dpp_base, - bool is_ram_a) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK, - CM_BLNDGAM_LUT_WRITE_EN_MASK, 7); - REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK, - CM_BLNDGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1); - REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); -} - -static void dpp20_program_blnd_pwl( - struct dpp *dpp_base, - const struct pwl_result_data *rgb, - uint32_t num) -{ - uint32_t i; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - for (i = 0 ; i < num; i++) { - REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); - REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg); - REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg); - - REG_SET(CM_BLNDGAM_LUT_DATA, 0, - CM_BLNDGAM_LUT_DATA, rgb[i].delta_red_reg); - REG_SET(CM_BLNDGAM_LUT_DATA, 0, - CM_BLNDGAM_LUT_DATA, rgb[i].delta_green_reg); - REG_SET(CM_BLNDGAM_LUT_DATA, 0, - CM_BLNDGAM_LUT_DATA, rgb[i].delta_blue_reg); - - } - -} - -static void dcn20_dpp_cm_get_reg_field( - struct dcn20_dpp *dpp, - struct xfer_func_reg *reg) -{ - reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; - reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; - reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; - reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; - reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; - reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; - reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; - reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; - - reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; - reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; - reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; - reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; - reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; - reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; - reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; - reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; - reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; - reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; - reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; - reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; -} - -/*program blnd lut RAM A*/ -static void dpp20_program_blnd_luta_settings( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - struct xfer_func_reg gam_regs; - - dcn20_dpp_cm_get_reg_field(dpp, &gam_regs); - - gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B); - gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G); - gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R); - gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_B); - gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_G); - gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_R); - gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B); - gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B); - gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G); - gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G); - gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R); - gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R); - gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1); - gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33); - - cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); -} - -/*program blnd lut RAM B*/ -static void dpp20_program_blnd_lutb_settings( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - struct xfer_func_reg gam_regs; - - dcn20_dpp_cm_get_reg_field(dpp, &gam_regs); - - gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B); - gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G); - gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R); - gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_B); - gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_G); - gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_R); - gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B); - gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B); - gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G); - gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G); - gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R); - gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R); - gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1); - gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33); - - cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); -} - -static enum dc_lut_mode dpp20_get_blndgam_current(struct dpp *dpp_base) -{ - enum dc_lut_mode mode; - uint32_t state_mode; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, &state_mode); - - switch (state_mode) { - case 0: - mode = LUT_BYPASS; - break; - case 1: - mode = LUT_RAM_A; - break; - case 2: - mode = LUT_RAM_B; - break; - default: - mode = LUT_BYPASS; - break; - } - - return mode; -} - -bool dpp20_program_blnd_lut( - struct dpp *dpp_base, const struct pwl_params *params) -{ - enum dc_lut_mode current_mode; - enum dc_lut_mode next_mode; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - if (params == NULL) { - REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_LUT_MODE, 0); - return false; - } - current_mode = dpp20_get_blndgam_current(dpp_base); - if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) - next_mode = LUT_RAM_B; - else - next_mode = LUT_RAM_A; - - dpp20_power_on_blnd_lut(dpp_base, true); - dpp20_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A); - - if (next_mode == LUT_RAM_A) - dpp20_program_blnd_luta_settings(dpp_base, params); - else - dpp20_program_blnd_lutb_settings(dpp_base, params); - - dpp20_program_blnd_pwl( - dpp_base, params->rgb_resulted, params->hw_points_num); - - REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_LUT_MODE, - next_mode == LUT_RAM_A ? 1:2); - - return true; -} - - -static void dpp20_program_shaper_lut( - struct dpp *dpp_base, - const struct pwl_result_data *rgb, - uint32_t num) -{ - uint32_t i, red, green, blue; - uint32_t red_delta, green_delta, blue_delta; - uint32_t red_value, green_value, blue_value; - - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - for (i = 0 ; i < num; i++) { - - red = rgb[i].red_reg; - green = rgb[i].green_reg; - blue = rgb[i].blue_reg; - - red_delta = rgb[i].delta_red_reg; - green_delta = rgb[i].delta_green_reg; - blue_delta = rgb[i].delta_blue_reg; - - red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); - green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); - blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); - - REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value); - REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value); - REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value); - } - -} - -static enum dc_lut_mode dpp20_get_shaper_current(struct dpp *dpp_base) -{ - enum dc_lut_mode mode; - uint32_t state_mode; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_GET(CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_CONFIG_STATUS, &state_mode); - - switch (state_mode) { - case 0: - mode = LUT_BYPASS; - break; - case 1: - mode = LUT_RAM_A; - break; - case 2: - mode = LUT_RAM_B; - break; - default: - mode = LUT_BYPASS; - break; - } - - return mode; -} - -static void dpp20_configure_shaper_lut( - struct dpp *dpp_base, - bool is_ram_a) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, - CM_SHAPER_LUT_WRITE_EN_MASK, 7); - REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK, - CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); - REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0); -} - -/*program shaper RAM A*/ - -static void dpp20_program_shaper_luta_settings( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - const struct gamma_curve *curve; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, - CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); - REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, - CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0); - REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, - CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0); - - REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, - CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); - - REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, - CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); - - REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, - CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, - CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); - - curve = params->arr_curve_points; - REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, - CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, - CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, - CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, - CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, - CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, - CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, - CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, - CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, - CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0, - CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0, - CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0, - CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0, - CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0, - CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0, - CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0, - CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0, - CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); -} - -/*program shaper RAM B*/ -static void dpp20_program_shaper_lutb_settings( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - const struct gamma_curve *curve; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, - CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); - REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, - CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0); - REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, - CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0); - - REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, - CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); - - REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0, - CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y); - - REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0, - CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x, - CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y); - - curve = params->arr_curve_points; - REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0, - CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0, - CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0, - CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0, - CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0, - CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0, - CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0, - CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0, - CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0, - CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0, - CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0, - CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0, - CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0, - CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0, - CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0, - CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0, - CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num); - - curve += 2; - REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0, - CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset, - CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num, - CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset, - CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num); - -} - - -bool dpp20_program_shaper( - struct dpp *dpp_base, - const struct pwl_params *params) -{ - enum dc_lut_mode current_mode; - enum dc_lut_mode next_mode; - - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - if (params == NULL) { - REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0); - return false; - } - current_mode = dpp20_get_shaper_current(dpp_base); - - if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) - next_mode = LUT_RAM_B; - else - next_mode = LUT_RAM_A; - - dpp20_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A); - - if (next_mode == LUT_RAM_A) - dpp20_program_shaper_luta_settings(dpp_base, params); - else - dpp20_program_shaper_lutb_settings(dpp_base, params); - - dpp20_program_shaper_lut( - dpp_base, params->rgb_resulted, params->hw_points_num); - - REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2); - - return true; - -} - -static enum dc_lut_mode get3dlut_config( - struct dpp *dpp_base, - bool *is_17x17x17, - bool *is_12bits_color_channel) -{ - uint32_t i_mode, i_enable_10bits, lut_size; - enum dc_lut_mode mode; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL, - CM_3DLUT_CONFIG_STATUS, &i_mode, - CM_3DLUT_30BIT_EN, &i_enable_10bits); - - switch (i_mode) { - case 0: - mode = LUT_BYPASS; - break; - case 1: - mode = LUT_RAM_A; - break; - case 2: - mode = LUT_RAM_B; - break; - default: - mode = LUT_BYPASS; - break; - } - if (i_enable_10bits > 0) - *is_12bits_color_channel = false; - else - *is_12bits_color_channel = true; - - REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size); - - if (lut_size == 0) - *is_17x17x17 = true; - else - *is_17x17x17 = false; - - return mode; -} -/* - * select ramA or ramB, or bypass - * select color channel size 10 or 12 bits - * select 3dlut size 17x17x17 or 9x9x9 - */ -static void dpp20_set_3dlut_mode( - struct dpp *dpp_base, - enum dc_lut_mode mode, - bool is_color_channel_12bits, - bool is_lut_size17x17x17) -{ - uint32_t lut_mode; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - if (mode == LUT_BYPASS) - lut_mode = 0; - else if (mode == LUT_RAM_A) - lut_mode = 1; - else - lut_mode = 2; - - REG_UPDATE_2(CM_3DLUT_MODE, - CM_3DLUT_MODE, lut_mode, - CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1); -} - -static void dpp20_select_3dlut_ram( - struct dpp *dpp_base, - enum dc_lut_mode mode, - bool is_color_channel_12bits) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL, - CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, - CM_3DLUT_30BIT_EN, - is_color_channel_12bits == true ? 0:1); -} - - - -static void dpp20_set3dlut_ram12( - struct dpp *dpp_base, - const struct dc_rgb *lut, - uint32_t entries) -{ - uint32_t i, red, green, blue, red1, green1, blue1; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - for (i = 0 ; i < entries; i += 2) { - red = lut[i].red<<4; - green = lut[i].green<<4; - blue = lut[i].blue<<4; - red1 = lut[i+1].red<<4; - green1 = lut[i+1].green<<4; - blue1 = lut[i+1].blue<<4; - - REG_SET_2(CM_3DLUT_DATA, 0, - CM_3DLUT_DATA0, red, - CM_3DLUT_DATA1, red1); - - REG_SET_2(CM_3DLUT_DATA, 0, - CM_3DLUT_DATA0, green, - CM_3DLUT_DATA1, green1); - - REG_SET_2(CM_3DLUT_DATA, 0, - CM_3DLUT_DATA0, blue, - CM_3DLUT_DATA1, blue1); - - } -} - -/* - * load selected lut with 10 bits color channels - */ -static void dpp20_set3dlut_ram10( - struct dpp *dpp_base, - const struct dc_rgb *lut, - uint32_t entries) -{ - uint32_t i, red, green, blue, value; - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - for (i = 0; i < entries; i++) { - red = lut[i].red; - green = lut[i].green; - blue = lut[i].blue; - - value = (red<<20) | (green<<10) | blue; - - REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value); - } - -} - - -static void dpp20_select_3dlut_ram_mask( - struct dpp *dpp_base, - uint32_t ram_selection_mask) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, - ram_selection_mask); - REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0); -} - -bool dpp20_program_3dlut( - struct dpp *dpp_base, - struct tetrahedral_params *params) -{ - enum dc_lut_mode mode; - bool is_17x17x17; - bool is_12bits_color_channel; - struct dc_rgb *lut0; - struct dc_rgb *lut1; - struct dc_rgb *lut2; - struct dc_rgb *lut3; - int lut_size0; - int lut_size; - - if (params == NULL) { - dpp20_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false); - return false; - } - mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel); - - if (mode == LUT_BYPASS || mode == LUT_RAM_B) - mode = LUT_RAM_A; - else - mode = LUT_RAM_B; - - is_17x17x17 = !params->use_tetrahedral_9; - is_12bits_color_channel = params->use_12bits; - if (is_17x17x17) { - lut0 = params->tetrahedral_17.lut0; - lut1 = params->tetrahedral_17.lut1; - lut2 = params->tetrahedral_17.lut2; - lut3 = params->tetrahedral_17.lut3; - lut_size0 = sizeof(params->tetrahedral_17.lut0)/ - sizeof(params->tetrahedral_17.lut0[0]); - lut_size = sizeof(params->tetrahedral_17.lut1)/ - sizeof(params->tetrahedral_17.lut1[0]); - } else { - lut0 = params->tetrahedral_9.lut0; - lut1 = params->tetrahedral_9.lut1; - lut2 = params->tetrahedral_9.lut2; - lut3 = params->tetrahedral_9.lut3; - lut_size0 = sizeof(params->tetrahedral_9.lut0)/ - sizeof(params->tetrahedral_9.lut0[0]); - lut_size = sizeof(params->tetrahedral_9.lut1)/ - sizeof(params->tetrahedral_9.lut1[0]); - } - - dpp20_select_3dlut_ram(dpp_base, mode, - is_12bits_color_channel); - dpp20_select_3dlut_ram_mask(dpp_base, 0x1); - if (is_12bits_color_channel) - dpp20_set3dlut_ram12(dpp_base, lut0, lut_size0); - else - dpp20_set3dlut_ram10(dpp_base, lut0, lut_size0); - - dpp20_select_3dlut_ram_mask(dpp_base, 0x2); - if (is_12bits_color_channel) - dpp20_set3dlut_ram12(dpp_base, lut1, lut_size); - else - dpp20_set3dlut_ram10(dpp_base, lut1, lut_size); - - dpp20_select_3dlut_ram_mask(dpp_base, 0x4); - if (is_12bits_color_channel) - dpp20_set3dlut_ram12(dpp_base, lut2, lut_size); - else - dpp20_set3dlut_ram10(dpp_base, lut2, lut_size); - - dpp20_select_3dlut_ram_mask(dpp_base, 0x8); - if (is_12bits_color_channel) - dpp20_set3dlut_ram12(dpp_base, lut3, lut_size); - else - dpp20_set3dlut_ram10(dpp_base, lut3, lut_size); - - - dpp20_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel, - is_17x17x17); - - return true; -} - -void dpp2_set_hdr_multiplier( - struct dpp *dpp_base, - uint32_t multiplier) -{ - struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); - - REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier); -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c index f8667be57046..80779e85e2c5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c @@ -299,6 +299,17 @@ void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params) } } + + if (dwbc20->dwbc_mask->WBSCL_COEF_RAM_SEL) { + /* Swap double buffered coefficient set */ + uint32_t wbscl_mode = REG_READ(WBSCL_MODE); + bool coef_ram_current = get_reg_field_value_ex( + wbscl_mode, dwbc20->dwbc_mask->WBSCL_COEF_RAM_SEL_CURRENT, + dwbc20->dwbc_shift->WBSCL_COEF_RAM_SEL_CURRENT); + + REG_UPDATE(WBSCL_MODE, WBSCL_COEF_RAM_SEL, !coef_ram_current); + } + } static const struct dwbc_funcs dcn20_dwbc_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c index 994fb732a7cb..a0d437f0ce2b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c @@ -690,6 +690,9 @@ static void wbscl_set_scaler_filter( int pair; uint16_t odd_coef, even_coef; + if (!filter) + return; + for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) { for (pair = 0; pair < tap_pairs; pair++) { even_coef = filter[phase * taps + 2 * pair]; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c deleted file mode 100644 index 6eebcb22e317..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c +++ /dev/null @@ -1,670 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - - -#include "dcn20_hubbub.h" -#include "reg_helper.h" -#include "clk_mgr.h" - -#define REG(reg)\ - hubbub1->regs->reg - -#define CTX \ - hubbub1->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - hubbub1->shifts->field_name, hubbub1->masks->field_name - -#define REG(reg)\ - hubbub1->regs->reg - -#define CTX \ - hubbub1->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - hubbub1->shifts->field_name, hubbub1->masks->field_name - -#ifdef NUM_VMID -#undef NUM_VMID -#endif -#define NUM_VMID 16 - -bool hubbub2_dcc_support_swizzle( - enum swizzle_mode_values swizzle, - unsigned int bytes_per_element, - enum segment_order *segment_order_horz, - enum segment_order *segment_order_vert) -{ - bool standard_swizzle = false; - bool display_swizzle = false; - bool render_swizzle = false; - - switch (swizzle) { - case DC_SW_4KB_S: - case DC_SW_64KB_S: - case DC_SW_VAR_S: - case DC_SW_4KB_S_X: - case DC_SW_64KB_S_X: - case DC_SW_VAR_S_X: - standard_swizzle = true; - break; - case DC_SW_64KB_R_X: - render_swizzle = true; - break; - case DC_SW_4KB_D: - case DC_SW_64KB_D: - case DC_SW_VAR_D: - case DC_SW_4KB_D_X: - case DC_SW_64KB_D_X: - case DC_SW_VAR_D_X: - display_swizzle = true; - break; - default: - break; - } - - if (standard_swizzle) { - if (bytes_per_element == 1) { - *segment_order_horz = segment_order__contiguous; - *segment_order_vert = segment_order__na; - return true; - } - if (bytes_per_element == 2) { - *segment_order_horz = segment_order__non_contiguous; - *segment_order_vert = segment_order__contiguous; - return true; - } - if (bytes_per_element == 4) { - *segment_order_horz = segment_order__non_contiguous; - *segment_order_vert = segment_order__contiguous; - return true; - } - if (bytes_per_element == 8) { - *segment_order_horz = segment_order__na; - *segment_order_vert = segment_order__contiguous; - return true; - } - } - if (render_swizzle) { - if (bytes_per_element == 2) { - *segment_order_horz = segment_order__contiguous; - *segment_order_vert = segment_order__contiguous; - return true; - } - if (bytes_per_element == 4) { - *segment_order_horz = segment_order__non_contiguous; - *segment_order_vert = segment_order__contiguous; - return true; - } - if (bytes_per_element == 8) { - *segment_order_horz = segment_order__contiguous; - *segment_order_vert = segment_order__non_contiguous; - return true; - } - } - if (display_swizzle && bytes_per_element == 8) { - *segment_order_horz = segment_order__contiguous; - *segment_order_vert = segment_order__non_contiguous; - return true; - } - - return false; -} - -bool hubbub2_dcc_support_pixel_format( - enum surface_pixel_format format, - unsigned int *bytes_per_element) -{ - /* DML: get_bytes_per_element */ - switch (format) { - case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: - case SURFACE_PIXEL_FORMAT_GRPH_RGB565: - *bytes_per_element = 2; - return true; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: - case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: - case SURFACE_PIXEL_FORMAT_GRPH_RGBE: - case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: - *bytes_per_element = 4; - return true; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: - *bytes_per_element = 8; - return true; - default: - return false; - } -} - -static void hubbub2_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height, - unsigned int bytes_per_element) -{ - /* copied from DML. might want to refactor DML to leverage from DML */ - /* DML : get_blk256_size */ - if (bytes_per_element == 1) { - *blk256_width = 16; - *blk256_height = 16; - } else if (bytes_per_element == 2) { - *blk256_width = 16; - *blk256_height = 8; - } else if (bytes_per_element == 4) { - *blk256_width = 8; - *blk256_height = 8; - } else if (bytes_per_element == 8) { - *blk256_width = 8; - *blk256_height = 4; - } -} - -static void hubbub2_det_request_size( - unsigned int detile_buf_size, - unsigned int height, - unsigned int width, - unsigned int bpe, - bool *req128_horz_wc, - bool *req128_vert_wc) -{ - unsigned int blk256_height = 0; - unsigned int blk256_width = 0; - unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc; - - hubbub2_get_blk256_size(&blk256_width, &blk256_height, bpe); - - swath_bytes_horz_wc = width * blk256_height * bpe; - swath_bytes_vert_wc = height * blk256_width * bpe; - - *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ? - false : /* full 256B request */ - true; /* half 128b request */ - - *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ? - false : /* full 256B request */ - true; /* half 128b request */ -} - -bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub, - const struct dc_dcc_surface_param *input, - struct dc_surface_dcc_cap *output) -{ - struct dc *dc = hubbub->ctx->dc; - /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */ - enum dcc_control dcc_control; - unsigned int bpe; - enum segment_order segment_order_horz, segment_order_vert; - bool req128_horz_wc, req128_vert_wc; - - memset(output, 0, sizeof(*output)); - - if (dc->debug.disable_dcc == DCC_DISABLE) - return false; - - if (!hubbub->funcs->dcc_support_pixel_format(input->format, - &bpe)) - return false; - - if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe, - &segment_order_horz, &segment_order_vert)) - return false; - - hubbub2_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size, - input->surface_size.height, input->surface_size.width, - bpe, &req128_horz_wc, &req128_vert_wc); - - if (!req128_horz_wc && !req128_vert_wc) { - dcc_control = dcc_control__256_256_xxx; - } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) { - if (!req128_horz_wc) - dcc_control = dcc_control__256_256_xxx; - else if (segment_order_horz == segment_order__contiguous) - dcc_control = dcc_control__128_128_xxx; - else - dcc_control = dcc_control__256_64_64; - } else if (input->scan == SCAN_DIRECTION_VERTICAL) { - if (!req128_vert_wc) - dcc_control = dcc_control__256_256_xxx; - else if (segment_order_vert == segment_order__contiguous) - dcc_control = dcc_control__128_128_xxx; - else - dcc_control = dcc_control__256_64_64; - } else { - if ((req128_horz_wc && - segment_order_horz == segment_order__non_contiguous) || - (req128_vert_wc && - segment_order_vert == segment_order__non_contiguous)) - /* access_dir not known, must use most constraining */ - dcc_control = dcc_control__256_64_64; - else - /* reg128 is true for either horz and vert - * but segment_order is contiguous - */ - dcc_control = dcc_control__128_128_xxx; - } - - /* Exception for 64KB_R_X */ - if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X)) - dcc_control = dcc_control__128_128_xxx; - - if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE && - dcc_control != dcc_control__256_256_xxx) - return false; - - switch (dcc_control) { - case dcc_control__256_256_xxx: - output->grph.rgb.max_uncompressed_blk_size = 256; - output->grph.rgb.max_compressed_blk_size = 256; - output->grph.rgb.independent_64b_blks = false; - break; - case dcc_control__128_128_xxx: - output->grph.rgb.max_uncompressed_blk_size = 128; - output->grph.rgb.max_compressed_blk_size = 128; - output->grph.rgb.independent_64b_blks = false; - break; - case dcc_control__256_64_64: - output->grph.rgb.max_uncompressed_blk_size = 256; - output->grph.rgb.max_compressed_blk_size = 64; - output->grph.rgb.independent_64b_blks = true; - break; - default: - ASSERT(false); - break; - } - output->capable = true; - output->const_color_support = true; - - return true; -} - -static enum dcn_hubbub_page_table_depth page_table_depth_to_hw(unsigned int page_table_depth) -{ - enum dcn_hubbub_page_table_depth depth = 0; - - switch (page_table_depth) { - case 1: - depth = DCN_PAGE_TABLE_DEPTH_1_LEVEL; - break; - case 2: - depth = DCN_PAGE_TABLE_DEPTH_2_LEVEL; - break; - case 3: - depth = DCN_PAGE_TABLE_DEPTH_3_LEVEL; - break; - case 4: - depth = DCN_PAGE_TABLE_DEPTH_4_LEVEL; - break; - default: - ASSERT(false); - break; - } - - return depth; -} - -static enum dcn_hubbub_page_table_block_size page_table_block_size_to_hw(unsigned int page_table_block_size) -{ - enum dcn_hubbub_page_table_block_size block_size = 0; - - switch (page_table_block_size) { - case 4096: - block_size = DCN_PAGE_TABLE_BLOCK_SIZE_4KB; - break; - case 65536: - block_size = DCN_PAGE_TABLE_BLOCK_SIZE_64KB; - break; - case 32768: - block_size = DCN_PAGE_TABLE_BLOCK_SIZE_32KB; - break; - default: - ASSERT(false); - block_size = page_table_block_size; - break; - } - - return block_size; -} - -void hubbub2_init_vm_ctx(struct hubbub *hubbub, - struct dcn_hubbub_virt_addr_config *va_config, - int vmid) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - struct dcn_vmid_page_table_config virt_config; - - virt_config.page_table_start_addr = va_config->page_table_start_addr >> 12; - virt_config.page_table_end_addr = va_config->page_table_end_addr >> 12; - virt_config.depth = page_table_depth_to_hw(va_config->page_table_depth); - virt_config.block_size = page_table_block_size_to_hw(va_config->page_table_block_size); - virt_config.page_table_base_addr = va_config->page_table_base_addr; - - dcn20_vmid_setup(&hubbub1->vmid[vmid], &virt_config); -} - -int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub, - struct dcn_hubbub_phys_addr_config *pa_config) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - struct dcn_vmid_page_table_config phys_config; - - REG_SET(DCN_VM_FB_LOCATION_BASE, 0, - FB_BASE, pa_config->system_aperture.fb_base >> 24); - REG_SET(DCN_VM_FB_LOCATION_TOP, 0, - FB_TOP, pa_config->system_aperture.fb_top >> 24); - REG_SET(DCN_VM_FB_OFFSET, 0, - FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); - REG_SET(DCN_VM_AGP_BOT, 0, - AGP_BOT, pa_config->system_aperture.agp_bot >> 24); - REG_SET(DCN_VM_AGP_TOP, 0, - AGP_TOP, pa_config->system_aperture.agp_top >> 24); - REG_SET(DCN_VM_AGP_BASE, 0, - AGP_BASE, pa_config->system_aperture.agp_base >> 24); - - REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, - DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF); - REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, - DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, (pa_config->page_table_default_page_addr >> 12) & 0xFFFFFFFF); - - if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { - phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; - phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12; - phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; - phys_config.depth = 0; - phys_config.block_size = 0; - // Init VMID 0 based on PA config - dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config); - } - - return NUM_VMID; -} - -void hubbub2_update_dchub(struct hubbub *hubbub, - struct dchub_init_data *dh_data) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - - if (REG(DCN_VM_FB_LOCATION_TOP) == 0) - return; - - switch (dh_data->fb_mode) { - case FRAME_BUFFER_MODE_ZFB_ONLY: - /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ - REG_UPDATE(DCN_VM_FB_LOCATION_TOP, - FB_TOP, 0); - - REG_UPDATE(DCN_VM_FB_LOCATION_BASE, - FB_BASE, 0xFFFFFF); - - /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ - REG_UPDATE(DCN_VM_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 24); - - /*This field defines the bottom range of the AGP aperture and represents the 24*/ - /*MSBs, bits [47:24] of the 48 address bits*/ - REG_UPDATE(DCN_VM_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 24); - - /*This field defines the top range of the AGP aperture and represents the 24*/ - /*MSBs, bits [47:24] of the 48 address bits*/ - REG_UPDATE(DCN_VM_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 24); - break; - case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - - /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ - REG_UPDATE(DCN_VM_AGP_BASE, - AGP_BASE, dh_data->zfb_phys_addr_base >> 24); - - /*This field defines the bottom range of the AGP aperture and represents the 24*/ - /*MSBs, bits [47:24] of the 48 address bits*/ - REG_UPDATE(DCN_VM_AGP_BOT, - AGP_BOT, dh_data->zfb_mc_base_addr >> 24); - - /*This field defines the top range of the AGP aperture and represents the 24*/ - /*MSBs, bits [47:24] of the 48 address bits*/ - REG_UPDATE(DCN_VM_AGP_TOP, - AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 24); - break; - case FRAME_BUFFER_MODE_LOCAL_ONLY: - /*Should not touch FB LOCATION (should be done by VBIOS)*/ - - /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ - REG_UPDATE(DCN_VM_AGP_BASE, - AGP_BASE, 0); - - /*This field defines the bottom range of the AGP aperture and represents the 24*/ - /*MSBs, bits [47:24] of the 48 address bits*/ - REG_UPDATE(DCN_VM_AGP_BOT, - AGP_BOT, 0xFFFFFF); - - /*This field defines the top range of the AGP aperture and represents the 24*/ - /*MSBs, bits [47:24] of the 48 address bits*/ - REG_UPDATE(DCN_VM_AGP_TOP, - AGP_TOP, 0); - break; - default: - break; - } - - dh_data->dchub_initialzied = true; - dh_data->dchub_info_valid = false; -} - -void hubbub2_wm_read_state(struct hubbub *hubbub, - struct dcn_hubbub_wm *wm) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - - struct dcn_hubbub_wm_set *s; - - memset(wm, 0, sizeof(struct dcn_hubbub_wm)); - - s = &wm->sets[0]; - s->wm_set = 0; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); - if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A)) - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); - } - s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); - - s = &wm->sets[1]; - s->wm_set = 1; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); - if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B)) - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); - } - s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); - - s = &wm->sets[2]; - s->wm_set = 2; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); - if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C)) - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C); - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); - } - s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); - - s = &wm->sets[3]; - s->wm_set = 3; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); - if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)) - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D); - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); - } - s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); -} - -void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub, - unsigned int dccg_ref_freq_inKhz, - unsigned int *dchub_ref_freq_inKhz) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - uint32_t ref_div = 0; - uint32_t ref_en = 0; - - REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div, - DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en); - - if (ref_en) { - if (ref_div == 2) - *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz / 2; - else - *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz; - - // DC hub reference frequency must be around 50Mhz, otherwise there may be - // overflow/underflow issues when doing HUBBUB programming - if (*dchub_ref_freq_inKhz < 40000 || *dchub_ref_freq_inKhz > 60000) - ASSERT_CRITICAL(false); - - return; - } else { - *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz; - - // HUBBUB global timer must be enabled. - ASSERT_CRITICAL(false); - return; - } -} - -static bool hubbub2_program_watermarks( - struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - bool wm_pending = false; - /* - * Need to clamp to max of the register values (i.e. no wrap) - * for dcn1, all wm registers are 21-bit wide - */ - if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - if (hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - /* - * There's a special case when going from p-state support to p-state unsupported - * here we are going to LOWER watermarks to go to dummy p-state only, but this has - * to be done prepare_bandwidth, not optimize - */ - if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true && - hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false) - safe_to_lower = true; - - hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); - - REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, - DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); - REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 180); - - hubbub->funcs->allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); - return wm_pending; -} - -void hubbub2_read_state(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - - if (REG(DCN_VM_FAULT_ADDR_MSB)) - hubbub_state->vm_fault_addr_msb = REG_READ(DCN_VM_FAULT_ADDR_MSB); - - if (REG(DCN_VM_FAULT_ADDR_LSB)) - hubbub_state->vm_fault_addr_msb = REG_READ(DCN_VM_FAULT_ADDR_LSB); - - if (REG(DCN_VM_FAULT_CNTL)) - REG_GET(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, &hubbub_state->vm_error_mode); - - if (REG(DCN_VM_FAULT_STATUS)) { - REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, &hubbub_state->vm_error_status); - REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, &hubbub_state->vm_error_vmid); - REG_GET(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, &hubbub_state->vm_error_pipe); - } - - if (REG(DCHUBBUB_TEST_DEBUG_INDEX) && REG(DCHUBBUB_TEST_DEBUG_DATA)) { - REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, 0x6); - hubbub_state->test_debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA); - } - - if (REG(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL)) - hubbub_state->watermark_change_cntl = REG_READ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL); - - if (REG(DCHUBBUB_ARB_DRAM_STATE_CNTL)) - hubbub_state->dram_state_cntl = REG_READ(DCHUBBUB_ARB_DRAM_STATE_CNTL); -} - -static const struct hubbub_funcs hubbub2_funcs = { - .update_dchub = hubbub2_update_dchub, - .init_dchub_sys_ctx = hubbub2_init_dchub_sys_ctx, - .init_vm_ctx = hubbub2_init_vm_ctx, - .dcc_support_swizzle = hubbub2_dcc_support_swizzle, - .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format, - .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap, - .wm_read_state = hubbub2_wm_read_state, - .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq, - .program_watermarks = hubbub2_program_watermarks, - .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, - .allow_self_refresh_control = hubbub1_allow_self_refresh_control, - .hubbub_read_state = hubbub2_read_state, -}; - -void hubbub2_construct(struct dcn20_hubbub *hubbub, - struct dc_context *ctx, - const struct dcn_hubbub_registers *hubbub_regs, - const struct dcn_hubbub_shift *hubbub_shift, - const struct dcn_hubbub_mask *hubbub_mask) -{ - hubbub->base.ctx = ctx; - - hubbub->base.funcs = &hubbub2_funcs; - - hubbub->regs = hubbub_regs; - hubbub->shifts = hubbub_shift; - hubbub->masks = hubbub_mask; - - hubbub->debug_test_index_pstate = 0xB; - hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */ -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h deleted file mode 100644 index 2f6146bf1d32..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright 2016 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_HUBBUB_DCN20_H__ -#define __DC_HUBBUB_DCN20_H__ - -#include "dcn10/dcn10_hubbub.h" -#include "dcn20_vmid.h" - -#define TO_DCN20_HUBBUB(hubbub)\ - container_of(hubbub, struct dcn20_hubbub, base) - -#define HUBBUB_REG_LIST_DCN20_COMMON()\ - HUBBUB_REG_LIST_DCN_COMMON(), \ - SR(DCHUBBUB_CRC_CTRL), \ - SR(DCN_VM_FB_LOCATION_BASE),\ - SR(DCN_VM_FB_LOCATION_TOP),\ - SR(DCN_VM_FB_OFFSET),\ - SR(DCN_VM_AGP_BOT),\ - SR(DCN_VM_AGP_TOP),\ - SR(DCN_VM_AGP_BASE),\ - SR(DCN_VM_FAULT_ADDR_MSB), \ - SR(DCN_VM_FAULT_ADDR_LSB), \ - SR(DCN_VM_FAULT_CNTL), \ - SR(DCN_VM_FAULT_STATUS) - -#define HUBBUB_REG_LIST_DCN20(id)\ - HUBBUB_REG_LIST_DCN20_COMMON(), \ - HUBBUB_SR_WATERMARK_REG_LIST(), \ - HUBBUB_VM_REG_LIST(),\ - SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB),\ - SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB) - - -#define HUBBUB_MASK_SH_LIST_DCN20(mask_sh)\ - HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ - HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ - HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ - HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ - HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ - HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ - HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ - HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ - HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \ - HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh), \ - HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh) - -struct dcn20_hubbub { - struct hubbub base; - const struct dcn_hubbub_registers *regs; - const struct dcn_hubbub_shift *shifts; - const struct dcn_hubbub_mask *masks; - unsigned int debug_test_index_pstate; - struct dcn_watermark_set watermarks; - int num_vmid; - struct dcn20_vmid vmid[16]; - unsigned int detile_buf_size; - unsigned int crb_size_segs; - unsigned int compbuf_size_segments; - unsigned int pixel_chunk_size; - unsigned int det0_size; - unsigned int det1_size; - unsigned int det2_size; - unsigned int det3_size; -}; - -void hubbub2_construct(struct dcn20_hubbub *hubbub, - struct dc_context *ctx, - const struct dcn_hubbub_registers *hubbub_regs, - const struct dcn_hubbub_shift *hubbub_shift, - const struct dcn_hubbub_mask *hubbub_mask); - -bool hubbub2_dcc_support_swizzle( - enum swizzle_mode_values swizzle, - unsigned int bytes_per_element, - enum segment_order *segment_order_horz, - enum segment_order *segment_order_vert); - -bool hubbub2_dcc_support_pixel_format( - enum surface_pixel_format format, - unsigned int *bytes_per_element); - -bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub, - const struct dc_dcc_surface_param *input, - struct dc_surface_dcc_cap *output); - -bool hubbub2_initialize_vmids(struct hubbub *hubbub, - const struct dc_dcc_surface_param *input, - struct dc_surface_dcc_cap *output); - -int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub, - struct dcn_hubbub_phys_addr_config *pa_config); -void hubbub2_init_vm_ctx(struct hubbub *hubbub, - struct dcn_hubbub_virt_addr_config *va_config, - int vmid); -void hubbub2_update_dchub(struct hubbub *hubbub, - struct dchub_init_data *dh_data); - -void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub, - unsigned int dccg_ref_freq_inKhz, - unsigned int *dchub_ref_freq_inKhz); - -void hubbub2_wm_read_state(struct hubbub *hubbub, - struct dcn_hubbub_wm *wm); - -void hubbub2_read_state(struct hubbub *hubbub, - struct dcn_hubbub_state *hubbub_state); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c deleted file mode 100644 index 89c3bf0fe0c9..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c +++ /dev/null @@ -1,1693 +0,0 @@ -/* - * Copyright 2012-2021 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dcn20_hubp.h" - -#include "dm_services.h" -#include "dce_calcs.h" -#include "reg_helper.h" -#include "basics/conversion.h" - -#define DC_LOGGER \ - ctx->logger -#define DC_LOGGER_INIT(logger) - -#define REG(reg)\ - hubp2->hubp_regs->reg - -#define CTX \ - hubp2->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name - -void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, - struct vm_system_aperture_param *apt) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - PHYSICAL_ADDRESS_LOC mc_vm_apt_default; - PHYSICAL_ADDRESS_LOC mc_vm_apt_low; - PHYSICAL_ADDRESS_LOC mc_vm_apt_high; - - // The format of default addr is 48:12 of the 48 bit addr - mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; - - // The format of high/low are 48:18 of the 48 bit addr - mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; - mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; - - REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, - DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */ - DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); - - REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, - DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); - - REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, - MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); - - REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); - - REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, - ENABLE_L1_TLB, 1, - SYSTEM_ACCESS_MODE, 0x3); -} - -void hubp2_program_deadline( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - /* DLG - Per hubp */ - REG_SET_2(BLANK_OFFSET_0, 0, - REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, - DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); - - REG_SET(BLANK_OFFSET_1, 0, - MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); - - REG_SET(DST_DIMENSIONS, 0, - REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); - - REG_SET_2(DST_AFTER_SCALER, 0, - REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, - DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); - - REG_SET(REF_FREQ_TO_PIX_FREQ, 0, - REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); - - /* DLG - Per luma/chroma */ - REG_SET(VBLANK_PARAMETERS_1, 0, - REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); - - if (REG(NOM_PARAMETERS_0)) - REG_SET(NOM_PARAMETERS_0, 0, - DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); - - if (REG(NOM_PARAMETERS_1)) - REG_SET(NOM_PARAMETERS_1, 0, - REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); - - REG_SET(NOM_PARAMETERS_4, 0, - DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); - - REG_SET(NOM_PARAMETERS_5, 0, - REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); - - REG_SET_2(PER_LINE_DELIVERY, 0, - REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, - REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); - - REG_SET(VBLANK_PARAMETERS_2, 0, - REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); - - if (REG(NOM_PARAMETERS_2)) - REG_SET(NOM_PARAMETERS_2, 0, - DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); - - if (REG(NOM_PARAMETERS_3)) - REG_SET(NOM_PARAMETERS_3, 0, - REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); - - REG_SET(NOM_PARAMETERS_6, 0, - DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); - - REG_SET(NOM_PARAMETERS_7, 0, - REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); - - /* TTU - per hubp */ - REG_SET_2(DCN_TTU_QOS_WM, 0, - QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, - QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); - - /* TTU - per luma/chroma */ - /* Assumed surf0 is luma and 1 is chroma */ - - REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, - REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, - QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, - QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); - - REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, - REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, - QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, - QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); - - REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, - REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, - QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, - QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); - - REG_SET(FLIP_PARAMETERS_1, 0, - REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); -} - -void hubp2_vready_at_or_After_vsync(struct hubp *hubp, - struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) -{ - uint32_t value = 0; - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */ - REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8); - /* - if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) - <= OTG_V_BLANK_END - Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1 - else - Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0 - */ - if (pipe_dest->htotal != 0) { - if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width - + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { - value = 1; - } else - value = 0; - } - - REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); -} - -static void hubp2_program_requestor(struct hubp *hubp, - struct _vcs_dpi_display_rq_regs_st *rq_regs) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_UPDATE(HUBPRET_CONTROL, - DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); - REG_SET_4(DCN_EXPANSION_MODE, 0, - DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, - PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, - MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, - CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); - REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, - CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, - MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, - META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, - MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, - DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, - MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, - SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, - PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); - REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, - CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, - MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, - META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, - MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, - DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, - MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, - SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, - PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); -} - -static void hubp2_setup( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr, - struct _vcs_dpi_display_rq_regs_st *rq_regs, - struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) -{ - /* otg is locked when this func is called. Register are double buffered. - * disable the requestors is not needed - */ - - hubp2_vready_at_or_After_vsync(hubp, pipe_dest); - hubp2_program_requestor(hubp, rq_regs); - hubp2_program_deadline(hubp, dlg_attr, ttu_attr); - -} - -void hubp2_setup_interdependent( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_SET_2(PREFETCH_SETTINGS, 0, - DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, - VRATIO_PREFETCH, dlg_attr->vratio_prefetch); - - REG_SET(PREFETCH_SETTINGS_C, 0, - VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); - - REG_SET_2(VBLANK_PARAMETERS_0, 0, - DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, - DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); - - REG_SET_2(FLIP_PARAMETERS_0, 0, - DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip, - DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip); - - REG_SET(VBLANK_PARAMETERS_3, 0, - REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); - - REG_SET(VBLANK_PARAMETERS_4, 0, - REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); - - REG_SET(FLIP_PARAMETERS_2, 0, - REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l); - - REG_SET_2(PER_LINE_DELIVERY_PRE, 0, - REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, - REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); - - REG_SET(DCN_SURF0_TTU_CNTL1, 0, - REFCYC_PER_REQ_DELIVERY_PRE, - ttu_attr->refcyc_per_req_delivery_pre_l); - REG_SET(DCN_SURF1_TTU_CNTL1, 0, - REFCYC_PER_REQ_DELIVERY_PRE, - ttu_attr->refcyc_per_req_delivery_pre_c); - REG_SET(DCN_CUR0_TTU_CNTL1, 0, - REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); - REG_SET(DCN_CUR1_TTU_CNTL1, 0, - REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1); - - REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, - MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, - QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); -} - -/* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used: - * NUM_BANKS - * NUM_SE - * NUM_RB_PER_SE - * RB_ALIGNED - * Other things can be defaulted, since they never change: - * PIPE_ALIGNED = 0 - * META_LINEAR = 0 - * In GFX10, only these apply: - * PIPE_INTERLEAVE - * NUM_PIPES - * MAX_COMPRESSED_FRAGS - * SW_MODE - */ -static void hubp2_program_tiling( - struct dcn20_hubp *hubp2, - const union dc_tiling_info *info, - const enum surface_pixel_format pixel_format) -{ - REG_UPDATE_3(DCSURF_ADDR_CONFIG, - NUM_PIPES, log_2(info->gfx9.num_pipes), - PIPE_INTERLEAVE, info->gfx9.pipe_interleave, - MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); - - REG_UPDATE_4(DCSURF_TILING_CONFIG, - SW_MODE, info->gfx9.swizzle, - META_LINEAR, 0, - RB_ALIGNED, 0, - PIPE_ALIGNED, 0); -} - -void hubp2_program_size( - struct hubp *hubp, - enum surface_pixel_format format, - const struct plane_size *plane_size, - struct dc_plane_dcc_param *dcc) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; - bool use_pitch_c = false; - - /* Program data and meta surface pitch (calculation from addrlib) - * 444 or 420 luma - */ - use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN - && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END; - use_pitch_c = use_pitch_c - || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); - if (use_pitch_c) { - ASSERT(plane_size->chroma_pitch != 0); - /* Chroma pitch zero can cause system hang! */ - - pitch = plane_size->surface_pitch - 1; - meta_pitch = dcc->meta_pitch - 1; - pitch_c = plane_size->chroma_pitch - 1; - meta_pitch_c = dcc->meta_pitch_c - 1; - } else { - pitch = plane_size->surface_pitch - 1; - meta_pitch = dcc->meta_pitch - 1; - pitch_c = 0; - meta_pitch_c = 0; - } - - if (!dcc->enable) { - meta_pitch = 0; - meta_pitch_c = 0; - } - - REG_UPDATE_2(DCSURF_SURFACE_PITCH, - PITCH, pitch, META_PITCH, meta_pitch); - - use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN; - use_pitch_c = use_pitch_c - || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); - if (use_pitch_c) - REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, - PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); -} - -void hubp2_program_rotation( - struct hubp *hubp, - enum dc_rotation_angle rotation, - bool horizontal_mirror) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - uint32_t mirror; - - - if (horizontal_mirror) - mirror = 1; - else - mirror = 0; - - /* Program rotation angle and horz mirror - no mirror */ - if (rotation == ROTATION_ANGLE_0) - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - ROTATION_ANGLE, 0, - H_MIRROR_EN, mirror); - else if (rotation == ROTATION_ANGLE_90) - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - ROTATION_ANGLE, 1, - H_MIRROR_EN, mirror); - else if (rotation == ROTATION_ANGLE_180) - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - ROTATION_ANGLE, 2, - H_MIRROR_EN, mirror); - else if (rotation == ROTATION_ANGLE_270) - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - ROTATION_ANGLE, 3, - H_MIRROR_EN, mirror); -} - -void hubp2_dcc_control(struct hubp *hubp, bool enable, - enum hubp_ind_block_size independent_64b_blks) -{ - uint32_t dcc_en = enable ? 1 : 0; - uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_UPDATE_4(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_DCC_EN, dcc_en, - PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, - SECONDARY_SURFACE_DCC_EN, dcc_en, - SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); -} - -void hubp2_program_pixel_format( - struct hubp *hubp, - enum surface_pixel_format format) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - uint32_t red_bar = 3; - uint32_t blue_bar = 2; - - /* swap for ABGR format */ - if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { - red_bar = 2; - blue_bar = 3; - } - - REG_UPDATE_2(HUBPRET_CONTROL, - CROSSBAR_SRC_CB_B, blue_bar, - CROSSBAR_SRC_CR_R, red_bar); - - /* Mapping is same as ipp programming (cnvc) */ - - switch (format) { - case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 1); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB565: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 3); - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 8); - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 10); - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 24); - break; - - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 65); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 64); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 67); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 66); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 12); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 112); - break; - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 113); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 114); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 118); - break; - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 119); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGBE: - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 116, - ALPHA_PLANE_EN, 0); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 116, - ALPHA_PLANE_EN, 1); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - /* don't see the need of program the xbar in DCN 1.0 */ -} - -void hubp2_program_surface_config( - struct hubp *hubp, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - struct plane_size *plane_size, - enum dc_rotation_angle rotation, - struct dc_plane_dcc_param *dcc, - bool horizontal_mirror, - unsigned int compat_level) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); - hubp2_program_tiling(hubp2, tiling_info, format); - hubp2_program_size(hubp, format, plane_size, dcc); - hubp2_program_rotation(hubp, rotation, horizontal_mirror); - hubp2_program_pixel_format(hubp, format); -} - -enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( - unsigned int cursor_width, - enum dc_cursor_color_format cursor_mode) -{ - enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16; - - if (cursor_mode == CURSOR_MODE_MONO) - line_per_chunk = CURSOR_LINE_PER_CHUNK_16; - else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND || - cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || - cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { - if (cursor_width >= 1 && cursor_width <= 32) - line_per_chunk = CURSOR_LINE_PER_CHUNK_16; - else if (cursor_width >= 33 && cursor_width <= 64) - line_per_chunk = CURSOR_LINE_PER_CHUNK_8; - else if (cursor_width >= 65 && cursor_width <= 128) - line_per_chunk = CURSOR_LINE_PER_CHUNK_4; - else if (cursor_width >= 129 && cursor_width <= 256) - line_per_chunk = CURSOR_LINE_PER_CHUNK_2; - } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED || - cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) { - if (cursor_width >= 1 && cursor_width <= 16) - line_per_chunk = CURSOR_LINE_PER_CHUNK_16; - else if (cursor_width >= 17 && cursor_width <= 32) - line_per_chunk = CURSOR_LINE_PER_CHUNK_8; - else if (cursor_width >= 33 && cursor_width <= 64) - line_per_chunk = CURSOR_LINE_PER_CHUNK_4; - else if (cursor_width >= 65 && cursor_width <= 128) - line_per_chunk = CURSOR_LINE_PER_CHUNK_2; - else if (cursor_width >= 129 && cursor_width <= 256) - line_per_chunk = CURSOR_LINE_PER_CHUNK_1; - } - - return line_per_chunk; -} - -void hubp2_cursor_set_attributes( - struct hubp *hubp, - const struct dc_cursor_attributes *attr) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); - enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( - attr->width, attr->color_format); - - hubp->curs_attr = *attr; - - REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, - CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); - REG_UPDATE(CURSOR_SURFACE_ADDRESS, - CURSOR_SURFACE_ADDRESS, attr->address.low_part); - - REG_UPDATE_2(CURSOR_SIZE, - CURSOR_WIDTH, attr->width, - CURSOR_HEIGHT, attr->height); - - REG_UPDATE_4(CURSOR_CONTROL, - CURSOR_MODE, attr->color_format, - CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, - CURSOR_PITCH, hw_pitch, - CURSOR_LINES_PER_CHUNK, lpc); - - REG_SET_2(CURSOR_SETTINGS, 0, - /* no shift of the cursor HDL schedule */ - CURSOR0_DST_Y_OFFSET, 0, - /* used to shift the cursor chunk request deadline */ - CURSOR0_CHUNK_HDL_ADJUST, 3); - - hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part; - hubp->att.SURFACE_ADDR = attr->address.low_part; - hubp->att.size.bits.width = attr->width; - hubp->att.size.bits.height = attr->height; - hubp->att.cur_ctl.bits.mode = attr->color_format; - - hubp->cur_rect.w = attr->width; - hubp->cur_rect.h = attr->height; - - hubp->att.cur_ctl.bits.pitch = hw_pitch; - hubp->att.cur_ctl.bits.line_per_chunk = lpc; - hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION; - hubp->att.settings.bits.dst_y_offset = 0; - hubp->att.settings.bits.chunk_hdl_adjust = 3; -} - -void hubp2_dmdata_set_attributes( - struct hubp *hubp, - const struct dc_dmdata_attributes *attr) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - if (attr->dmdata_mode == DMDATA_HW_MODE) { - /* set to HW mode */ - REG_UPDATE(DMDATA_CNTL, - DMDATA_MODE, 1); - - /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */ - REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); - - /* toggle DMDATA_UPDATED and set repeat and size */ - REG_UPDATE(DMDATA_CNTL, - DMDATA_UPDATED, 0); - REG_UPDATE_3(DMDATA_CNTL, - DMDATA_UPDATED, 1, - DMDATA_REPEAT, attr->dmdata_repeat, - DMDATA_SIZE, attr->dmdata_size); - - /* set DMDATA address */ - REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part); - REG_UPDATE(DMDATA_ADDRESS_HIGH, - DMDATA_ADDRESS_HIGH, attr->address.high_part); - - REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); - - } else { - /* set to SW mode before loading data */ - REG_SET(DMDATA_CNTL, 0, - DMDATA_MODE, 0); - /* toggle DMDATA_SW_UPDATED to start loading sequence */ - REG_UPDATE(DMDATA_SW_CNTL, - DMDATA_SW_UPDATED, 0); - REG_UPDATE_3(DMDATA_SW_CNTL, - DMDATA_SW_UPDATED, 1, - DMDATA_SW_REPEAT, attr->dmdata_repeat, - DMDATA_SW_SIZE, attr->dmdata_size); - /* load data into hubp dmdata buffer */ - hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data); - } - - /* Note that DL_DELTA must be programmed if we want to use TTU mode */ - REG_SET_3(DMDATA_QOS_CNTL, 0, - DMDATA_QOS_MODE, attr->dmdata_qos_mode, - DMDATA_QOS_LEVEL, attr->dmdata_qos_level, - DMDATA_DL_DELTA, attr->dmdata_dl_delta); -} - -void hubp2_dmdata_load( - struct hubp *hubp, - uint32_t dmdata_sw_size, - const uint32_t *dmdata_sw_data) -{ - int i; - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - /* load dmdata into HUBP buffer in SW mode */ - for (i = 0; i < dmdata_sw_size / 4; i++) - REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]); -} - -bool hubp2_dmdata_status_done(struct hubp *hubp) -{ - uint32_t status; - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); - return (status == 1); -} - -bool hubp2_program_surface_flip_and_addr( - struct hubp *hubp, - const struct dc_plane_address *address, - bool flip_immediate) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - //program flip type - REG_UPDATE(DCSURF_FLIP_CONTROL, - SURFACE_FLIP_TYPE, flip_immediate); - - // Program VMID reg - REG_UPDATE(VMID_SETTINGS_0, - VMID, address->vmid); - - - /* HW automatically latch rest of address register on write to - * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used - * - * program high first and then the low addr, order matters! - */ - switch (address->type) { - case PLN_ADDR_TYPE_GRAPHICS: - /* DCN1.0 does not support const color - * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 - * base on address->grph.dcc_const_color - * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma - * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma - */ - - if (address->grph.addr.quad_part == 0) - break; - - REG_UPDATE_2(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_TMZ, address->tmz_surface, - PRIMARY_META_SURFACE_TMZ, address->tmz_surface); - - if (address->grph.meta_addr.quad_part != 0) { - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_META_SURFACE_ADDRESS_HIGH, - address->grph.meta_addr.high_part); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, - PRIMARY_META_SURFACE_ADDRESS, - address->grph.meta_addr.low_part); - } - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_SURFACE_ADDRESS_HIGH, - address->grph.addr.high_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, - PRIMARY_SURFACE_ADDRESS, - address->grph.addr.low_part); - break; - case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: - if (address->video_progressive.luma_addr.quad_part == 0 - || address->video_progressive.chroma_addr.quad_part == 0) - break; - - REG_UPDATE_4(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_TMZ, address->tmz_surface, - PRIMARY_SURFACE_TMZ_C, address->tmz_surface, - PRIMARY_META_SURFACE_TMZ, address->tmz_surface, - PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); - - if (address->video_progressive.luma_meta_addr.quad_part != 0) { - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, - PRIMARY_META_SURFACE_ADDRESS_HIGH_C, - address->video_progressive.chroma_meta_addr.high_part); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, - PRIMARY_META_SURFACE_ADDRESS_C, - address->video_progressive.chroma_meta_addr.low_part); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_META_SURFACE_ADDRESS_HIGH, - address->video_progressive.luma_meta_addr.high_part); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, - PRIMARY_META_SURFACE_ADDRESS, - address->video_progressive.luma_meta_addr.low_part); - } - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, - PRIMARY_SURFACE_ADDRESS_HIGH_C, - address->video_progressive.chroma_addr.high_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, - PRIMARY_SURFACE_ADDRESS_C, - address->video_progressive.chroma_addr.low_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_SURFACE_ADDRESS_HIGH, - address->video_progressive.luma_addr.high_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, - PRIMARY_SURFACE_ADDRESS, - address->video_progressive.luma_addr.low_part); - break; - case PLN_ADDR_TYPE_GRPH_STEREO: - if (address->grph_stereo.left_addr.quad_part == 0) - break; - if (address->grph_stereo.right_addr.quad_part == 0) - break; - - REG_UPDATE_8(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_TMZ, address->tmz_surface, - PRIMARY_SURFACE_TMZ_C, address->tmz_surface, - PRIMARY_META_SURFACE_TMZ, address->tmz_surface, - PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, - SECONDARY_SURFACE_TMZ, address->tmz_surface, - SECONDARY_SURFACE_TMZ_C, address->tmz_surface, - SECONDARY_META_SURFACE_TMZ, address->tmz_surface, - SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); - - if (address->grph_stereo.right_meta_addr.quad_part != 0) { - - REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, - SECONDARY_META_SURFACE_ADDRESS_HIGH, - address->grph_stereo.right_meta_addr.high_part); - - REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, - SECONDARY_META_SURFACE_ADDRESS, - address->grph_stereo.right_meta_addr.low_part); - } - if (address->grph_stereo.left_meta_addr.quad_part != 0) { - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_META_SURFACE_ADDRESS_HIGH, - address->grph_stereo.left_meta_addr.high_part); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, - PRIMARY_META_SURFACE_ADDRESS, - address->grph_stereo.left_meta_addr.low_part); - } - - REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, - SECONDARY_SURFACE_ADDRESS_HIGH, - address->grph_stereo.right_addr.high_part); - - REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, - SECONDARY_SURFACE_ADDRESS, - address->grph_stereo.right_addr.low_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_SURFACE_ADDRESS_HIGH, - address->grph_stereo.left_addr.high_part); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, - PRIMARY_SURFACE_ADDRESS, - address->grph_stereo.left_addr.low_part); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - hubp->request_address = *address; - - return true; -} - -void hubp2_enable_triplebuffer( - struct hubp *hubp, - bool enable) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - uint32_t triple_buffer_en = 0; - bool tri_buffer_en; - - REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); - tri_buffer_en = (triple_buffer_en == 1); - if (tri_buffer_en != enable) { - REG_UPDATE(DCSURF_FLIP_CONTROL2, - SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE); - } -} - -bool hubp2_is_triplebuffer_enabled( - struct hubp *hubp) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - uint32_t triple_buffer_en = 0; - - REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); - - return (bool)triple_buffer_en; -} - -void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0); -} - -bool hubp2_is_flip_pending(struct hubp *hubp) -{ - uint32_t flip_pending = 0; - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - struct dc_plane_address earliest_inuse_address; - - if (hubp && hubp->power_gated) - return false; - - REG_GET(DCSURF_FLIP_CONTROL, - SURFACE_FLIP_PENDING, &flip_pending); - - REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, - SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); - - REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, - SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); - - if (flip_pending) - return true; - - if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) - return true; - - return false; -} - -void hubp2_set_blank(struct hubp *hubp, bool blank) -{ - hubp2_set_blank_regs(hubp, blank); - - if (blank) { - hubp->mpcc_id = 0xf; - hubp->opp_id = OPP_ID_INVALID; - } -} - -void hubp2_set_blank_regs(struct hubp *hubp, bool blank) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - uint32_t blank_en = blank ? 1 : 0; - - if (blank) { - uint32_t reg_val = REG_READ(DCHUBP_CNTL); - - if (reg_val) { - /* init sequence workaround: in case HUBP is - * power gated, this wait would timeout. - * - * we just wrote reg_val to non-0, if it stay 0 - * it means HUBP is gated - */ - REG_WAIT(DCHUBP_CNTL, - HUBP_NO_OUTSTANDING_REQ, 1, - 1, 100000); - } - } - - REG_UPDATE_2(DCHUBP_CNTL, - HUBP_BLANK_EN, blank_en, - HUBP_TTU_DISABLE, 0); -} - -void hubp2_cursor_set_position( - struct hubp *hubp, - const struct dc_cursor_position *pos, - const struct dc_cursor_mi_param *param) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - int x_pos = pos->x - param->viewport.x; - int y_pos = pos->y - param->viewport.y; - int x_hotspot = pos->x_hotspot; - int y_hotspot = pos->y_hotspot; - int src_x_offset = x_pos - pos->x_hotspot; - int src_y_offset = y_pos - pos->y_hotspot; - int cursor_height = (int)hubp->curs_attr.height; - int cursor_width = (int)hubp->curs_attr.width; - uint32_t dst_x_offset; - uint32_t cur_en = pos->enable ? 1 : 0; - - hubp->curs_pos = *pos; - - /* - * Guard aganst cursor_set_position() from being called with invalid - * attributes - * - * TODO: Look at combining cursor_set_position() and - * cursor_set_attributes() into cursor_update() - */ - if (hubp->curs_attr.address.quad_part == 0) - return; - - // Transform cursor width / height and hotspots for offset calculations - if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { - swap(cursor_height, cursor_width); - swap(x_hotspot, y_hotspot); - - if (param->rotation == ROTATION_ANGLE_90) { - // hotspot = (-y, x) - src_x_offset = x_pos - (cursor_width - x_hotspot); - src_y_offset = y_pos - y_hotspot; - } else if (param->rotation == ROTATION_ANGLE_270) { - // hotspot = (y, -x) - src_x_offset = x_pos - x_hotspot; - src_y_offset = y_pos - (cursor_height - y_hotspot); - } - } else if (param->rotation == ROTATION_ANGLE_180) { - // hotspot = (-x, -y) - if (!param->mirror) - src_x_offset = x_pos - (cursor_width - x_hotspot); - - src_y_offset = y_pos - (cursor_height - y_hotspot); - } - - dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; - dst_x_offset *= param->ref_clk_khz; - dst_x_offset /= param->pixel_clk_khz; - - ASSERT(param->h_scale_ratio.value); - - if (param->h_scale_ratio.value) - dst_x_offset = dc_fixpt_floor(dc_fixpt_div( - dc_fixpt_from_int(dst_x_offset), - param->h_scale_ratio)); - - if (src_x_offset >= (int)param->viewport.width) - cur_en = 0; /* not visible beyond right edge*/ - - if (src_x_offset + cursor_width <= 0) - cur_en = 0; /* not visible beyond left edge*/ - - if (src_y_offset >= (int)param->viewport.height) - cur_en = 0; /* not visible beyond bottom edge*/ - - if (src_y_offset + cursor_height <= 0) - cur_en = 0; /* not visible beyond top edge*/ - - if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) - hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); - - REG_UPDATE(CURSOR_CONTROL, - CURSOR_ENABLE, cur_en); - - REG_SET_2(CURSOR_POSITION, 0, - CURSOR_X_POSITION, pos->x, - CURSOR_Y_POSITION, pos->y); - - REG_SET_2(CURSOR_HOT_SPOT, 0, - CURSOR_HOT_SPOT_X, pos->x_hotspot, - CURSOR_HOT_SPOT_Y, pos->y_hotspot); - - REG_SET(CURSOR_DST_OFFSET, 0, - CURSOR_DST_X_OFFSET, dst_x_offset); - /* TODO Handle surface pixel formats other than 4:4:4 */ - /* Cursor Position Register Config */ - hubp->pos.cur_ctl.bits.cur_enable = cur_en; - hubp->pos.position.bits.x_pos = pos->x; - hubp->pos.position.bits.y_pos = pos->y; - hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot; - hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot; - hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset; - /* Cursor Rectangle Cache - * Cursor bitmaps have different hotspot values - * There's a possibility that the above logic returns a negative value, - * so we clamp them to 0 - */ - if (src_x_offset < 0) - src_x_offset = 0; - if (src_y_offset < 0) - src_y_offset = 0; - /* Save necessary cursor info x, y position. w, h is saved in attribute func. */ - if (param->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && - param->rotation != ROTATION_ANGLE_0) { - hubp->cur_rect.x = 0; - hubp->cur_rect.y = 0; - hubp->cur_rect.w = param->stream->timing.h_addressable; - hubp->cur_rect.h = param->stream->timing.v_addressable; - } else { - hubp->cur_rect.x = src_x_offset + param->viewport.x; - hubp->cur_rect.y = src_y_offset + param->viewport.y; - } -} - -void hubp2_clk_cntl(struct hubp *hubp, bool enable) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - uint32_t clk_enable = enable ? 1 : 0; - - REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); -} - -void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); -} - -void hubp2_clear_underflow(struct hubp *hubp) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); -} - -void hubp2_read_state_common(struct hubp *hubp) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - struct dcn_hubp_state *s = &hubp2->state; - struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; - struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; - struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; - - /* Requester */ - REG_GET(HUBPRET_CONTROL, - DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); - REG_GET_4(DCN_EXPANSION_MODE, - DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, - PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, - MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, - CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); - - REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr); - - REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, - MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr); - - /* DLG - Per hubp */ - REG_GET_2(BLANK_OFFSET_0, - REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, - DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); - - REG_GET(BLANK_OFFSET_1, - MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); - - REG_GET(DST_DIMENSIONS, - REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); - - REG_GET_2(DST_AFTER_SCALER, - REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, - DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); - - if (REG(PREFETCH_SETTINS)) - REG_GET_2(PREFETCH_SETTINS, - DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, - VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); - else - REG_GET_2(PREFETCH_SETTINGS, - DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, - VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); - - REG_GET_2(VBLANK_PARAMETERS_0, - DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, - DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); - - REG_GET(REF_FREQ_TO_PIX_FREQ, - REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); - - /* DLG - Per luma/chroma */ - REG_GET(VBLANK_PARAMETERS_1, - REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); - - REG_GET(VBLANK_PARAMETERS_3, - REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); - - if (REG(NOM_PARAMETERS_0)) - REG_GET(NOM_PARAMETERS_0, - DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); - - if (REG(NOM_PARAMETERS_1)) - REG_GET(NOM_PARAMETERS_1, - REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); - - REG_GET(NOM_PARAMETERS_4, - DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); - - REG_GET(NOM_PARAMETERS_5, - REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); - - REG_GET_2(PER_LINE_DELIVERY_PRE, - REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, - REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); - - REG_GET_2(PER_LINE_DELIVERY, - REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, - REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); - - if (REG(PREFETCH_SETTINS_C)) - REG_GET(PREFETCH_SETTINS_C, - VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); - else - REG_GET(PREFETCH_SETTINGS_C, - VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); - - REG_GET(VBLANK_PARAMETERS_2, - REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); - - REG_GET(VBLANK_PARAMETERS_4, - REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); - - if (REG(NOM_PARAMETERS_2)) - REG_GET(NOM_PARAMETERS_2, - DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); - - if (REG(NOM_PARAMETERS_3)) - REG_GET(NOM_PARAMETERS_3, - REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); - - REG_GET(NOM_PARAMETERS_6, - DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); - - REG_GET(NOM_PARAMETERS_7, - REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); - - /* TTU - per hubp */ - REG_GET_2(DCN_TTU_QOS_WM, - QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, - QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); - - REG_GET_2(DCN_GLOBAL_TTU_CNTL, - MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, - QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); - - /* TTU - per luma/chroma */ - /* Assumed surf0 is luma and 1 is chroma */ - - REG_GET_3(DCN_SURF0_TTU_CNTL0, - REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, - QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, - QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); - - REG_GET(DCN_SURF0_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, - &ttu_attr->refcyc_per_req_delivery_pre_l); - - REG_GET_3(DCN_SURF1_TTU_CNTL0, - REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, - QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, - QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); - - REG_GET(DCN_SURF1_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, - &ttu_attr->refcyc_per_req_delivery_pre_c); - - /* Rest of hubp */ - REG_GET(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, &s->pixel_format); - - REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, - SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); - - REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, - SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); - - REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, - PRI_VIEWPORT_WIDTH, &s->viewport_width, - PRI_VIEWPORT_HEIGHT, &s->viewport_height); - - REG_GET_2(DCSURF_SURFACE_CONFIG, - ROTATION_ANGLE, &s->rotation_angle, - H_MIRROR_EN, &s->h_mirror_en); - - REG_GET(DCSURF_TILING_CONFIG, - SW_MODE, &s->sw_mode); - - REG_GET(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_DCC_EN, &s->dcc_en); - - REG_GET_3(DCHUBP_CNTL, - HUBP_BLANK_EN, &s->blank_en, - HUBP_TTU_DISABLE, &s->ttu_disable, - HUBP_UNDERFLOW_STATUS, &s->underflow_status); - - REG_GET(HUBP_CLK_CNTL, - HUBP_CLOCK_ENABLE, &s->clock_en); - - REG_GET(DCN_GLOBAL_TTU_CNTL, - MIN_TTU_VBLANK, &s->min_ttu_vblank); - - REG_GET_2(DCN_TTU_QOS_WM, - QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, - QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); - - REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, - PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); - - REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, - PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); - - REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, - PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo); - - REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, - PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi); -} - -void hubp2_read_state(struct hubp *hubp) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - struct dcn_hubp_state *s = &hubp2->state; - struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; - - hubp2_read_state_common(hubp); - - REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, - CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, - MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, - META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, - MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, - DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, - MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, - SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, - PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); - - REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, - CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, - MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, - META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, - MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, - DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, - MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, - SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, - PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); - -} - -static void hubp2_validate_dml_output(struct hubp *hubp, - struct dc_context *ctx, - struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, - struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; - struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; - struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; - DC_LOGGER_INIT(ctx->logger); - DC_LOG_DEBUG("DML Validation | Running Validation"); - - /* Requestor Regs */ - REG_GET(HUBPRET_CONTROL, - DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); - REG_GET_4(DCN_EXPANSION_MODE, - DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, - PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, - MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, - CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); - REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, - CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, - MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, - META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, - MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, - DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, - MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, - SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, - PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); - REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, - CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, - MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, - META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, - MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, - DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, - MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size, - SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, - PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); - - if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) - DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", - dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); - if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) - DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", - dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); - if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) - DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", - dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); - if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) - DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", - dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); - if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) - DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", - dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); - - if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); - if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); - if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); - if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); - if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); - if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); - if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); - if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); - - if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); - if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); - if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); - if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); - if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); - if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size); - if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); - if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); - - /* DLG - Per hubp */ - REG_GET_2(BLANK_OFFSET_0, - REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, - DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); - REG_GET(BLANK_OFFSET_1, - MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); - REG_GET(DST_DIMENSIONS, - REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); - REG_GET_2(DST_AFTER_SCALER, - REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, - DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); - REG_GET(REF_FREQ_TO_PIX_FREQ, - REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); - - if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) - DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); - if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) - DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", - dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); - if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) - DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", - dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); - if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) - DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); - if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) - DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); - if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) - DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", - dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); - if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) - DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", - dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); - - /* DLG - Per luma/chroma */ - REG_GET(VBLANK_PARAMETERS_1, - REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); - if (REG(NOM_PARAMETERS_0)) - REG_GET(NOM_PARAMETERS_0, - DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); - if (REG(NOM_PARAMETERS_1)) - REG_GET(NOM_PARAMETERS_1, - REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); - REG_GET(NOM_PARAMETERS_4, - DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); - REG_GET(NOM_PARAMETERS_5, - REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); - REG_GET_2(PER_LINE_DELIVERY, - REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, - REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); - REG_GET_2(PER_LINE_DELIVERY_PRE, - REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, - REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); - REG_GET(VBLANK_PARAMETERS_2, - REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); - if (REG(NOM_PARAMETERS_2)) - REG_GET(NOM_PARAMETERS_2, - DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); - if (REG(NOM_PARAMETERS_3)) - REG_GET(NOM_PARAMETERS_3, - REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); - REG_GET(NOM_PARAMETERS_6, - DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); - REG_GET(NOM_PARAMETERS_7, - REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); - REG_GET(VBLANK_PARAMETERS_3, - REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); - REG_GET(VBLANK_PARAMETERS_4, - REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); - - if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) - DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); - if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", - dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); - if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); - if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", - dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); - if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); - if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) - DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); - if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) - DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); - if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) - DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); - if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", - dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); - if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); - if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", - dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); - if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); - if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) - DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); - if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) - DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); - if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) - DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); - if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) - DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); - - /* TTU - per hubp */ - REG_GET_2(DCN_TTU_QOS_WM, - QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, - QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); - - if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) - DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); - if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) - DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); - - /* TTU - per luma/chroma */ - /* Assumed surf0 is luma and 1 is chroma */ - REG_GET_3(DCN_SURF0_TTU_CNTL0, - REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, - QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, - QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); - REG_GET_3(DCN_SURF1_TTU_CNTL0, - REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, - QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, - QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); - REG_GET_3(DCN_CUR0_TTU_CNTL0, - REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, - QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, - QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); - REG_GET(FLIP_PARAMETERS_1, - REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); - REG_GET(DCN_CUR0_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); - REG_GET(DCN_CUR1_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); - REG_GET(DCN_SURF0_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); - REG_GET(DCN_SURF1_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); - - if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) - DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); - if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) - DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); - if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) - DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); - if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) - DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); - if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) - DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); - if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) - DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); - if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) - DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); - if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) - DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); - if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) - DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); - if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) - DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); - if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) - DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); - if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) - DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); - if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) - DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); - if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) - DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); -} - -static struct hubp_funcs dcn20_hubp_funcs = { - .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, - .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, - .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, - .hubp_program_surface_config = hubp2_program_surface_config, - .hubp_is_flip_pending = hubp2_is_flip_pending, - .hubp_setup = hubp2_setup, - .hubp_setup_interdependent = hubp2_setup_interdependent, - .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings, - .set_blank = hubp2_set_blank, - .set_blank_regs = hubp2_set_blank_regs, - .dcc_control = hubp2_dcc_control, - .mem_program_viewport = min_set_viewport, - .set_cursor_attributes = hubp2_cursor_set_attributes, - .set_cursor_position = hubp2_cursor_set_position, - .hubp_clk_cntl = hubp2_clk_cntl, - .hubp_vtg_sel = hubp2_vtg_sel, - .dmdata_set_attributes = hubp2_dmdata_set_attributes, - .dmdata_load = hubp2_dmdata_load, - .dmdata_status_done = hubp2_dmdata_status_done, - .hubp_read_state = hubp2_read_state, - .hubp_clear_underflow = hubp2_clear_underflow, - .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, - .hubp_init = hubp1_init, - .validate_dml_output = hubp2_validate_dml_output, - .hubp_in_blank = hubp1_in_blank, - .hubp_soft_reset = hubp1_soft_reset, - .hubp_set_flip_int = hubp1_set_flip_int, -}; - - -bool hubp2_construct( - struct dcn20_hubp *hubp2, - struct dc_context *ctx, - uint32_t inst, - const struct dcn_hubp2_registers *hubp_regs, - const struct dcn_hubp2_shift *hubp_shift, - const struct dcn_hubp2_mask *hubp_mask) -{ - hubp2->base.funcs = &dcn20_hubp_funcs; - hubp2->base.ctx = ctx; - hubp2->hubp_regs = hubp_regs; - hubp2->hubp_shift = hubp_shift; - hubp2->hubp_mask = hubp_mask; - hubp2->base.inst = inst; - hubp2->base.opp_id = OPP_ID_INVALID; - hubp2->base.mpcc_id = 0xf; - - return true; -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h deleted file mode 100644 index efa2adf4f83d..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h +++ /dev/null @@ -1,371 +0,0 @@ -/* - * Copyright 2012-17 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_MEM_INPUT_DCN20_H__ -#define __DC_MEM_INPUT_DCN20_H__ - -#include "../dcn10/dcn10_hubp.h" - -#define TO_DCN20_HUBP(hubp)\ - container_of(hubp, struct dcn20_hubp, base) - -#define HUBP_REG_LIST_DCN2_COMMON(id)\ - HUBP_REG_LIST_DCN(id),\ - HUBP_REG_LIST_DCN_VM(id),\ - SRI(PREFETCH_SETTINGS, HUBPREQ, id),\ - SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\ - SRI(CURSOR_SETTINGS, HUBPREQ, id), \ - SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \ - SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \ - SRI(CURSOR_SIZE, CURSOR0_, id), \ - SRI(CURSOR_CONTROL, CURSOR0_, id), \ - SRI(CURSOR_POSITION, CURSOR0_, id), \ - SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \ - SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \ - SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \ - SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \ - SRI(DMDATA_CNTL, CURSOR0_, id), \ - SRI(DMDATA_SW_CNTL, CURSOR0_, id), \ - SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \ - SRI(DMDATA_SW_DATA, CURSOR0_, id), \ - SRI(DMDATA_STATUS, CURSOR0_, id),\ - SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\ - SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\ - SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\ - SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\ - SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\ - SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \ - SRI(VMID_SETTINGS_0, HUBPREQ, id) - -#define HUBP_REG_LIST_DCN20(id)\ - HUBP_REG_LIST_DCN2_COMMON(id),\ - SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ - SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB) - -#define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\ - HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ - HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ - HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ - HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ - HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ - HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ - HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ - HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh) - -/*DCN2.x and DCN1.x*/ -#define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\ - HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\ - HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) - -/*DCN2.0 specific*/ -#define HUBP_MASK_SH_LIST_DCN20(mask_sh)\ - HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\ - HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ - HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ - HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh) - -/*DCN2.x */ -#define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \ - HUBP_COMMON_REG_VARIABLE_LIST; \ - uint32_t DMDATA_ADDRESS_HIGH; \ - uint32_t DMDATA_ADDRESS_LOW; \ - uint32_t DMDATA_CNTL; \ - uint32_t DMDATA_SW_CNTL; \ - uint32_t DMDATA_QOS_CNTL; \ - uint32_t DMDATA_SW_DATA; \ - uint32_t DMDATA_STATUS;\ - uint32_t DCSURF_FLIP_CONTROL2;\ - uint32_t FLIP_PARAMETERS_0;\ - uint32_t FLIP_PARAMETERS_1;\ - uint32_t FLIP_PARAMETERS_2;\ - uint32_t DCN_CUR1_TTU_CNTL0;\ - uint32_t DCN_CUR1_TTU_CNTL1;\ - uint32_t VMID_SETTINGS_0 - - -#define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \ - DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \ - uint32_t FLIP_PARAMETERS_3;\ - uint32_t FLIP_PARAMETERS_4;\ - uint32_t FLIP_PARAMETERS_5;\ - uint32_t FLIP_PARAMETERS_6;\ - uint32_t VBLANK_PARAMETERS_5;\ - uint32_t VBLANK_PARAMETERS_6 - -#define DCN30_HUBP_REG_COMMON_VARIABLE_LIST \ - DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\ - uint32_t DCN_DMDATA_VM_CNTL - -#define DCN32_HUBP_REG_COMMON_VARIABLE_LIST \ - DCN30_HUBP_REG_COMMON_VARIABLE_LIST;\ - uint32_t DCHUBP_MALL_CONFIG;\ - uint32_t DCHUBP_VMPG_CONFIG;\ - uint32_t UCLK_PSTATE_FORCE - -#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ - DCN_HUBP_REG_FIELD_BASE_LIST(type); \ - type DMDATA_ADDRESS_HIGH;\ - type DMDATA_MODE;\ - type DMDATA_UPDATED;\ - type DMDATA_REPEAT;\ - type DMDATA_SIZE;\ - type DMDATA_SW_UPDATED;\ - type DMDATA_SW_REPEAT;\ - type DMDATA_SW_SIZE;\ - type DMDATA_QOS_MODE;\ - type DMDATA_QOS_LEVEL;\ - type DMDATA_DL_DELTA;\ - type DMDATA_DONE;\ - type DST_Y_PER_VM_FLIP;\ - type DST_Y_PER_ROW_FLIP;\ - type REFCYC_PER_PTE_GROUP_FLIP_L;\ - type REFCYC_PER_META_CHUNK_FLIP_L;\ - type HUBP_VREADY_AT_OR_AFTER_VSYNC;\ - type HUBP_DISABLE_STOP_DATA_DURING_VM;\ - type HUBPREQ_MASTER_UPDATE_LOCK_STATUS;\ - type SURFACE_GSL_ENABLE;\ - type SURFACE_TRIPLE_BUFFER_ENABLE;\ - type VMID - -#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \ - DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\ - type REFCYC_PER_VM_GROUP_FLIP;\ - type REFCYC_PER_VM_REQ_FLIP;\ - type REFCYC_PER_VM_GROUP_VBLANK;\ - type REFCYC_PER_VM_REQ_VBLANK;\ - type REFCYC_PER_PTE_GROUP_FLIP_C; \ - type REFCYC_PER_META_CHUNK_FLIP_C; \ - type VM_GROUP_SIZE - -#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \ - DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ - type PRIMARY_SURFACE_DCC_IND_BLK;\ - type SECONDARY_SURFACE_DCC_IND_BLK;\ - type PRIMARY_SURFACE_DCC_IND_BLK_C;\ - type SECONDARY_SURFACE_DCC_IND_BLK_C;\ - type ALPHA_PLANE_EN;\ - type REFCYC_PER_VM_DMDATA;\ - type DMDATA_VM_FAULT_STATUS;\ - type DMDATA_VM_FAULT_STATUS_CLEAR; \ - type DMDATA_VM_UNDERFLOW_STATUS;\ - type DMDATA_VM_LATE_STATUS;\ - type DMDATA_VM_UNDERFLOW_STATUS_CLEAR; \ - type DMDATA_VM_DONE; \ - type CROSSBAR_SRC_Y_G; \ - type CROSSBAR_SRC_ALPHA; \ - type PACK_3TO2_ELEMENT_DISABLE; \ - type ROW_TTU_MODE; \ - type NUM_PKRS - -#define DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type) \ - DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type);\ - type HUBP_UNBOUNDED_REQ_MODE;\ - type CURSOR_REQ_MODE;\ - type HUBP_SOFT_RESET - -#define DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type) \ - DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type);\ - type USE_MALL_SEL; \ - type USE_MALL_FOR_CURSOR;\ - type VMPG_SIZE; \ - type PTE_BUFFER_MODE; \ - type BIGK_FRAGMENT_SIZE; \ - type FORCE_ONE_ROW_FOR_FRAME; \ - type DATA_UCLK_PSTATE_FORCE_EN; \ - type DATA_UCLK_PSTATE_FORCE_VALUE; \ - type CURSOR_UCLK_PSTATE_FORCE_EN; \ - type CURSOR_UCLK_PSTATE_FORCE_VALUE - -struct dcn_hubp2_registers { - DCN32_HUBP_REG_COMMON_VARIABLE_LIST; -}; - -struct dcn_hubp2_shift { - DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); -}; - -struct dcn_hubp2_mask { - DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); -}; - -struct dcn20_hubp { - struct hubp base; - struct dcn_hubp_state state; - const struct dcn_hubp2_registers *hubp_regs; - const struct dcn_hubp2_shift *hubp_shift; - const struct dcn_hubp2_mask *hubp_mask; -}; - -bool hubp2_construct( - struct dcn20_hubp *hubp2, - struct dc_context *ctx, - uint32_t inst, - const struct dcn_hubp2_registers *hubp_regs, - const struct dcn_hubp2_shift *hubp_shift, - const struct dcn_hubp2_mask *hubp_mask); - -void hubp2_setup_interdependent( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr); - -void hubp2_vready_at_or_After_vsync(struct hubp *hubp, - struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); - -void hubp2_cursor_set_attributes( - struct hubp *hubp, - const struct dc_cursor_attributes *attr); - -void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, - struct vm_system_aperture_param *apt); - -enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( - unsigned int cursor_width, - enum dc_cursor_color_format cursor_mode); - -void hubp2_dmdata_set_attributes( - struct hubp *hubp, - const struct dc_dmdata_attributes *attr); - -void hubp2_dmdata_load( - struct hubp *hubp, - uint32_t dmdata_sw_size, - const uint32_t *dmdata_sw_data); - -bool hubp2_dmdata_status_done(struct hubp *hubp); - -void hubp2_enable_triplebuffer( - struct hubp *hubp, - bool enable); - -bool hubp2_is_triplebuffer_enabled( - struct hubp *hubp); - -void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable); - -void hubp2_program_deadline( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr); - -bool hubp2_program_surface_flip_and_addr( - struct hubp *hubp, - const struct dc_plane_address *address, - bool flip_immediate); - -void hubp2_dcc_control(struct hubp *hubp, bool enable, - enum hubp_ind_block_size independent_64b_blks); - -void hubp2_program_size( - struct hubp *hubp, - enum surface_pixel_format format, - const struct plane_size *plane_size, - struct dc_plane_dcc_param *dcc); - -void hubp2_program_rotation( - struct hubp *hubp, - enum dc_rotation_angle rotation, - bool horizontal_mirror); - -void hubp2_program_pixel_format( - struct hubp *hubp, - enum surface_pixel_format format); - -void hubp2_program_surface_config( - struct hubp *hubp, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - struct plane_size *plane_size, - enum dc_rotation_angle rotation, - struct dc_plane_dcc_param *dcc, - bool horizontal_mirror, - unsigned int compat_level); - -bool hubp2_is_flip_pending(struct hubp *hubp); - -void hubp2_set_blank(struct hubp *hubp, bool blank); -void hubp2_set_blank_regs(struct hubp *hubp, bool blank); - -void hubp2_cursor_set_position( - struct hubp *hubp, - const struct dc_cursor_position *pos, - const struct dc_cursor_mi_param *param); - -void hubp2_clk_cntl(struct hubp *hubp, bool enable); - -void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst); - -void hubp2_clear_underflow(struct hubp *hubp); - -void hubp2_read_state_common(struct hubp *hubp); - -void hubp2_read_state(struct hubp *hubp); - -#endif /* __DC_MEM_INPUT_DCN20_H__ */ - - diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c deleted file mode 100644 index 51a57dae1811..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c +++ /dev/null @@ -1,502 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "reg_helper.h" - -#include "core_types.h" -#include "link_encoder.h" -#include "dcn20_link_encoder.h" -#include "stream_encoder.h" -#include "dc_bios_types.h" - -#include "gpio_service_interface.h" - -#define CTX \ - enc10->base.ctx -#define DC_LOGGER \ - enc10->base.ctx->logger - -#define REG(reg)\ - (enc10->link_regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - enc10->link_shift->field_name, enc10->link_mask->field_name - -#define IND_REG(index) \ - (enc10->link_regs->index) - -#ifndef MAX -#define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) -#endif -#ifndef MIN -#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) -#endif - -static struct mpll_cfg dcn2_mpll_cfg[] = { - // RBR - { - .hdmimode_enable = 1, - .ref_range = 3, - .ref_clk_mpllb_div = 2, - .mpllb_ssc_en = 1, - .mpllb_div5_clk_en = 1, - .mpllb_multiplier = 226, - .mpllb_fracn_en = 1, - .mpllb_fracn_quot = 39321, - .mpllb_fracn_rem = 3, - .mpllb_fracn_den = 5, - .mpllb_ssc_up_spread = 0, - .mpllb_ssc_peak = 38221, - .mpllb_ssc_stepsize = 49314, - .mpllb_div_clk_en = 0, - .mpllb_div_multiplier = 0, - .mpllb_hdmi_div = 0, - .mpllb_tx_clk_div = 2, - .tx_vboost_lvl = 4, - .mpllb_pmix_en = 1, - .mpllb_word_div2_en = 0, - .mpllb_ana_v2i = 2, - .mpllb_ana_freq_vco = 2, - .mpllb_ana_cp_int = 7, - .mpllb_ana_cp_prop = 18, - .hdmi_pixel_clk_div = 0, - }, - // HBR - { - .hdmimode_enable = 1, - .ref_range = 3, - .ref_clk_mpllb_div = 2, - .mpllb_ssc_en = 1, - .mpllb_div5_clk_en = 1, - .mpllb_multiplier = 184, - .mpllb_fracn_en = 0, - .mpllb_fracn_quot = 0, - .mpllb_fracn_rem = 0, - .mpllb_fracn_den = 1, - .mpllb_ssc_up_spread = 0, - .mpllb_ssc_peak = 31850, - .mpllb_ssc_stepsize = 41095, - .mpllb_div_clk_en = 0, - .mpllb_div_multiplier = 0, - .mpllb_hdmi_div = 0, - .mpllb_tx_clk_div = 1, - .tx_vboost_lvl = 4, - .mpllb_pmix_en = 1, - .mpllb_word_div2_en = 0, - .mpllb_ana_v2i = 2, - .mpllb_ana_freq_vco = 3, - .mpllb_ana_cp_int = 7, - .mpllb_ana_cp_prop = 18, - .hdmi_pixel_clk_div = 0, - }, - //HBR2 - { - .hdmimode_enable = 1, - .ref_range = 3, - .ref_clk_mpllb_div = 2, - .mpllb_ssc_en = 1, - .mpllb_div5_clk_en = 1, - .mpllb_multiplier = 184, - .mpllb_fracn_en = 0, - .mpllb_fracn_quot = 0, - .mpllb_fracn_rem = 0, - .mpllb_fracn_den = 1, - .mpllb_ssc_up_spread = 0, - .mpllb_ssc_peak = 31850, - .mpllb_ssc_stepsize = 41095, - .mpllb_div_clk_en = 0, - .mpllb_div_multiplier = 0, - .mpllb_hdmi_div = 0, - .mpllb_tx_clk_div = 0, - .tx_vboost_lvl = 4, - .mpllb_pmix_en = 1, - .mpllb_word_div2_en = 0, - .mpllb_ana_v2i = 2, - .mpllb_ana_freq_vco = 3, - .mpllb_ana_cp_int = 7, - .mpllb_ana_cp_prop = 18, - .hdmi_pixel_clk_div = 0, - }, - //HBR3 - { - .hdmimode_enable = 1, - .ref_range = 3, - .ref_clk_mpllb_div = 2, - .mpllb_ssc_en = 1, - .mpllb_div5_clk_en = 1, - .mpllb_multiplier = 292, - .mpllb_fracn_en = 0, - .mpllb_fracn_quot = 0, - .mpllb_fracn_rem = 0, - .mpllb_fracn_den = 1, - .mpllb_ssc_up_spread = 0, - .mpllb_ssc_peak = 47776, - .mpllb_ssc_stepsize = 61642, - .mpllb_div_clk_en = 0, - .mpllb_div_multiplier = 0, - .mpllb_hdmi_div = 0, - .mpllb_tx_clk_div = 0, - .tx_vboost_lvl = 4, - .mpllb_pmix_en = 1, - .mpllb_word_div2_en = 0, - .mpllb_ana_v2i = 2, - .mpllb_ana_freq_vco = 0, - .mpllb_ana_cp_int = 7, - .mpllb_ana_cp_prop = 18, - .hdmi_pixel_clk_div = 0, - }, -}; - -void enc2_fec_set_enable(struct link_encoder *enc, bool enable) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - DC_LOG_DSC("%s FEC at link encoder inst %d", - enable ? "Enabling" : "Disabling", enc->id.enum_id); - REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable); -} - -void enc2_fec_set_ready(struct link_encoder *enc, bool ready) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, ready); -} - -bool enc2_fec_is_active(struct link_encoder *enc) -{ - uint32_t active = 0; - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active); - - return (active != 0); -} - -/* this function reads dsc related register fields to be logged later in dcn10_log_hw_state - * into a dcn_dsc_state struct. - */ -void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); - REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); - REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); - REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); -} - -static bool update_cfg_data( - struct dcn10_link_encoder *enc10, - const struct dc_link_settings *link_settings, - struct dpcssys_phy_seq_cfg *cfg) -{ - int i; - - cfg->load_sram_fw = false; - - for (i = 0; i < link_settings->lane_count; i++) - cfg->lane_en[i] = true; - - switch (link_settings->link_rate) { - case LINK_RATE_LOW: - cfg->mpll_cfg = dcn2_mpll_cfg[0]; - break; - case LINK_RATE_HIGH: - cfg->mpll_cfg = dcn2_mpll_cfg[1]; - break; - case LINK_RATE_HIGH2: - cfg->mpll_cfg = dcn2_mpll_cfg[2]; - break; - case LINK_RATE_HIGH3: - cfg->mpll_cfg = dcn2_mpll_cfg[3]; - break; - default: - DC_LOG_ERROR("%s: No supported link rate found %X!\n", - __func__, link_settings->link_rate); - return false; - } - - return true; -} - -void dcn20_link_encoder_enable_dp_output( - struct link_encoder *enc, - const struct dc_link_settings *link_settings, - enum clock_source_id clock_source) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - struct dcn20_link_encoder *enc20 = (struct dcn20_link_encoder *) enc10; - struct dpcssys_phy_seq_cfg *cfg = &enc20->phy_seq_cfg; - - if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { - dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); - return; - } - - if (!update_cfg_data(enc10, link_settings, cfg)) - return; - - enc1_configure_encoder(enc10, link_settings); - - dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT); - -} - -void dcn20_link_encoder_get_max_link_cap(struct link_encoder *enc, - struct dc_link_settings *link_settings) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - uint32_t is_in_usb_c_dp4_mode = 0; - - dcn10_link_encoder_get_max_link_cap(enc, link_settings); - - /* in usb c dp2 mode, max lane count is 2 */ - if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) { - REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); - if (!is_in_usb_c_dp4_mode) - link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); - } - -} - -bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - uint32_t dp_alt_mode_disable = 0; - bool is_usb_c_alt_mode = false; - - if (enc->features.flags.bits.DP_IS_USB_C) { - /* if value == 1 alt mode is disabled, otherwise it is enabled */ - REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); - is_usb_c_alt_mode = (dp_alt_mode_disable == 0); - } - - return is_usb_c_alt_mode; -} - -#define AUX_REG(reg)\ - (enc10->aux_regs->reg) - -#define AUX_REG_READ(reg_name) \ - dm_read_reg(CTX, AUX_REG(reg_name)) - -#define AUX_REG_WRITE(reg_name, val) \ - dm_write_reg(CTX, AUX_REG(reg_name), val) -void enc2_hw_init(struct link_encoder *enc) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); -/* - 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2 - 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4 - 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8 - 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16 - 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32 - 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64 - 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128 - 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256 -*/ - -/* - AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0, - AUX_RX_START_WINDOW = 1 [6:4] - AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8] - AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1 - AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1 - AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0 - AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1 - AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1 - AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 - AUX_RX_DETECTION_THRESHOLD [30:28] = 1 -*/ - if (enc->ctx->dc_bios->golden_table.dc_golden_table_ver > 0) { - AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, enc->ctx->dc_bios->golden_table.aux_dphy_rx_control0_val); - - AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, enc->ctx->dc_bios->golden_table.aux_dphy_tx_control_val); - - AUX_REG_WRITE(AUX_DPHY_RX_CONTROL1, enc->ctx->dc_bios->golden_table.aux_dphy_rx_control1_val); - } else { - AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); - - AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); - } - - //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; - // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk - // 27MHz -> 0xd - // 100MHz -> 0x32 - // 48MHz -> 0x18 - - // Set TMDS_CTL0 to 1. This is a legacy setting. - REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1); - - dcn10_aux_initialize(enc10); -} - -static const struct link_encoder_funcs dcn20_link_enc_funcs = { - .read_state = link_enc2_read_state, - .validate_output_with_stream = - dcn10_link_encoder_validate_output_with_stream, - .hw_init = enc2_hw_init, - .setup = dcn10_link_encoder_setup, - .enable_tmds_output = dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa, - .enable_dp_output = dcn20_link_encoder_enable_dp_output, - .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output, - .disable_output = dcn10_link_encoder_disable_output, - .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, - .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, - .update_mst_stream_allocation_table = - dcn10_link_encoder_update_mst_stream_allocation_table, - .psr_program_dp_dphy_fast_training = - dcn10_psr_program_dp_dphy_fast_training, - .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, - .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, - .enable_hpd = dcn10_link_encoder_enable_hpd, - .disable_hpd = dcn10_link_encoder_disable_hpd, - .is_dig_enabled = dcn10_is_dig_enabled, - .destroy = dcn10_link_encoder_destroy, - .fec_set_enable = enc2_fec_set_enable, - .fec_set_ready = enc2_fec_set_ready, - .fec_is_active = enc2_fec_is_active, - .get_dig_mode = dcn10_get_dig_mode, - .get_dig_frontend = dcn10_get_dig_frontend, - .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode, - .get_max_link_cap = dcn20_link_encoder_get_max_link_cap, -}; - -void dcn20_link_encoder_construct( - struct dcn20_link_encoder *enc20, - const struct encoder_init_data *init_data, - const struct encoder_feature_support *enc_features, - const struct dcn10_link_enc_registers *link_regs, - const struct dcn10_link_enc_aux_registers *aux_regs, - const struct dcn10_link_enc_hpd_registers *hpd_regs, - const struct dcn10_link_enc_shift *link_shift, - const struct dcn10_link_enc_mask *link_mask) -{ - struct bp_encoder_cap_info bp_cap_info = {0}; - const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; - enum bp_result result = BP_RESULT_OK; - struct dcn10_link_encoder *enc10 = &enc20->enc10; - - enc10->base.funcs = &dcn20_link_enc_funcs; - enc10->base.ctx = init_data->ctx; - enc10->base.id = init_data->encoder; - - enc10->base.hpd_source = init_data->hpd_source; - enc10->base.connector = init_data->connector; - - enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; - - enc10->base.features = *enc_features; - - enc10->base.transmitter = init_data->transmitter; - - /* set the flag to indicate whether driver poll the I2C data pin - * while doing the DP sink detect - */ - -/* if (dal_adapter_service_is_feature_supported(as, - FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) - enc10->base.features.flags.bits. - DP_SINK_DETECT_POLL_DATA_PIN = true;*/ - - enc10->base.output_signals = - SIGNAL_TYPE_DVI_SINGLE_LINK | - SIGNAL_TYPE_DVI_DUAL_LINK | - SIGNAL_TYPE_LVDS | - SIGNAL_TYPE_DISPLAY_PORT | - SIGNAL_TYPE_DISPLAY_PORT_MST | - SIGNAL_TYPE_EDP | - SIGNAL_TYPE_HDMI_TYPE_A; - - /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. - * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. - * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer - * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. - * Prefer DIG assignment is decided by board design. - * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design - * and VBIOS will filter out 7 UNIPHY for DCE 8.0. - * By this, adding DIGG should not hurt DCE 8.0. - * This will let DCE 8.1 share DCE 8.0 as much as possible - */ - - enc10->link_regs = link_regs; - enc10->aux_regs = aux_regs; - enc10->hpd_regs = hpd_regs; - enc10->link_shift = link_shift; - enc10->link_mask = link_mask; - - switch (enc10->base.transmitter) { - case TRANSMITTER_UNIPHY_A: - enc10->base.preferred_engine = ENGINE_ID_DIGA; - break; - case TRANSMITTER_UNIPHY_B: - enc10->base.preferred_engine = ENGINE_ID_DIGB; - break; - case TRANSMITTER_UNIPHY_C: - enc10->base.preferred_engine = ENGINE_ID_DIGC; - break; - case TRANSMITTER_UNIPHY_D: - enc10->base.preferred_engine = ENGINE_ID_DIGD; - break; - case TRANSMITTER_UNIPHY_E: - enc10->base.preferred_engine = ENGINE_ID_DIGE; - break; - case TRANSMITTER_UNIPHY_F: - enc10->base.preferred_engine = ENGINE_ID_DIGF; - break; - case TRANSMITTER_UNIPHY_G: - enc10->base.preferred_engine = ENGINE_ID_DIGG; - break; - default: - ASSERT_CRITICAL(false); - enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; - } - - /* default to one to mirror Windows behavior */ - enc10->base.features.flags.bits.HDMI_6GB_EN = 1; - - result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios, - enc10->base.id, &bp_cap_info); - - /* Override features with DCE-specific values */ - if (result == BP_RESULT_OK) { - enc10->base.features.flags.bits.IS_HBR2_CAPABLE = - bp_cap_info.DP_HBR2_EN; - enc10->base.features.flags.bits.IS_HBR3_CAPABLE = - bp_cap_info.DP_HBR3_EN; - enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; - enc10->base.features.flags.bits.DP_IS_USB_C = - bp_cap_info.DP_IS_USB_C; - } else { - DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", - __func__, - result); - } - if (enc10->base.ctx->dc->debug.hdmi20_disable) { - enc10->base.features.flags.bits.HDMI_6GB_EN = 0; - } -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h deleted file mode 100644 index b2b266953d18..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h +++ /dev/null @@ -1,364 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_LINK_ENCODER__DCN20_H__ -#define __DC_LINK_ENCODER__DCN20_H__ - -#include "dcn10/dcn10_link_encoder.h" - -#define DCN2_AUX_REG_LIST(id)\ - AUX_REG_LIST(id), \ - SRI(AUX_DPHY_TX_CONTROL, DP_AUX, id) - -#define UNIPHY_MASK_SH_LIST(mask_sh)\ - LE_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\ - LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh),\ - LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL0_XBAR_SOURCE, mask_sh),\ - LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL1_XBAR_SOURCE, mask_sh),\ - LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL2_XBAR_SOURCE, mask_sh),\ - LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_CHANNEL3_XBAR_SOURCE, mask_sh) - -#define DPCS_MASK_SH_LIST(mask_sh)\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA, RDPCS_PLL_UPDATE_DATA, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\ - LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\ - LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh),\ - LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_CLOCK_ON, mask_sh),\ - LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_GATE_DIS, mask_sh),\ - LE_SF(DPCSTX0_DPCSTX_TX_CLOCK_CNTL, DPCS_SYMCLK_EN, mask_sh),\ - LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP, mask_sh),\ - LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT, mask_sh),\ - LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_EN, mask_sh),\ - LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh) - -#define DPCS_DCN2_MASK_SH_LIST(mask_sh)\ - DPCS_MASK_SH_LIST(mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL, RDPCS_PHY_RX_REF_LD_VAL, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL, RDPCS_PHY_RX_VCO_LD_VAL, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE_ACK, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX0_PSTATE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX1_PSTATE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX0_MPLL_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX1_MPLL_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX2_WIDTH, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX2_RATE, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX3_WIDTH, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX3_RATE, mask_sh),\ - LE_SF(DCIO_SOFT_RESET, UNIPHYA_SOFT_RESET, mask_sh),\ - LE_SF(DCIO_SOFT_RESET, UNIPHYB_SOFT_RESET, mask_sh),\ - LE_SF(DCIO_SOFT_RESET, UNIPHYC_SOFT_RESET, mask_sh),\ - LE_SF(DCIO_SOFT_RESET, UNIPHYD_SOFT_RESET, mask_sh),\ - LE_SF(DCIO_SOFT_RESET, UNIPHYE_SOFT_RESET, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\ - LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh) - -#define LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)\ - LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\ - LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE0EN, mask_sh),\ - LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE1EN, mask_sh),\ - LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE2EN, mask_sh),\ - LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE3EN, mask_sh),\ - LE_SF(DIG0_DIG_LANE_ENABLE, DIG_CLK_EN, mask_sh),\ - LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ - UNIPHY_MASK_SH_LIST(mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \ - LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh) - -#define UNIPHY_DCN2_REG_LIST(id) \ - SRI(CLOCK_ENABLE, SYMCLK, id), \ - SRI(CHANNEL_XBAR_CNTL, UNIPHY, id) - -#define DPCS_DCN2_CMN_REG_LIST(id) \ - SRI(DIG_LANE_ENABLE, DIG, id), \ - SRI(TMDS_CTL_BITS, DIG, id), \ - SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \ - SRI(RDPCSTX_CNTL, RDPCSTX, id), \ - SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \ - SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \ - SRI(RDPCSTX_PLL_UPDATE_DATA, RDPCSTX, id), \ - SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \ - SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \ - SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \ - SRI(DPCSTX_TX_CLOCK_CNTL, DPCSTX, id), \ - SRI(DPCSTX_TX_CNTL, DPCSTX, id), \ - SR(RDPCSTX0_RDPCSTX_SCRATCH) - - -#define DPCS_DCN2_REG_LIST(id) \ - DPCS_DCN2_CMN_REG_LIST(id), \ - SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\ - SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id) - -#define LE_DCN2_REG_LIST(id) \ - LE_DCN10_REG_LIST(id), \ - SR(DCIO_SOFT_RESET) - -struct mpll_cfg { - uint32_t mpllb_ana_v2i; - uint32_t mpllb_ana_freq_vco; - uint32_t mpllb_ana_cp_int; - uint32_t mpllb_ana_cp_prop; - uint32_t mpllb_multiplier; - uint32_t ref_clk_mpllb_div; - bool mpllb_word_div2_en; - bool mpllb_ssc_en; - bool mpllb_div5_clk_en; - bool mpllb_div_clk_en; - bool mpllb_fracn_en; - bool mpllb_pmix_en; - uint32_t mpllb_div_multiplier; - uint32_t mpllb_tx_clk_div; - uint32_t mpllb_fracn_quot; - uint32_t mpllb_fracn_den; - uint32_t mpllb_ssc_peak; - uint32_t mpllb_ssc_stepsize; - uint32_t mpllb_ssc_up_spread; - uint32_t mpllb_fracn_rem; - uint32_t mpllb_hdmi_div; - // TODO: May not mpll params, need to figure out. - uint32_t tx_vboost_lvl; - uint32_t hdmi_pixel_clk_div; - uint32_t ref_range; - uint32_t ref_clk; - bool hdmimode_enable; - bool sup_pre_hp; - bool dp_tx0_vergdrv_byp; - bool dp_tx1_vergdrv_byp; - bool dp_tx2_vergdrv_byp; - bool dp_tx3_vergdrv_byp; - uint32_t tx_peaking_lvl; - uint32_t ctr_reqs_pll; - - -}; - -struct dpcssys_phy_seq_cfg { - bool program_fuse; - bool bypass_sram; - bool lane_en[4]; - bool use_calibration_setting; - struct mpll_cfg mpll_cfg; - bool load_sram_fw; -#if 0 - - bool hdmimode_enable; - bool silver2; - bool ext_refclk_en; - uint32_t dp_tx0_term_ctrl; - uint32_t dp_tx1_term_ctrl; - uint32_t dp_tx2_term_ctrl; - uint32_t dp_tx3_term_ctrl; - uint32_t fw_data[0x1000]; - uint32_t dp_tx0_width; - uint32_t dp_tx1_width; - uint32_t dp_tx2_width; - uint32_t dp_tx3_width; - uint32_t dp_tx0_rate; - uint32_t dp_tx1_rate; - uint32_t dp_tx2_rate; - uint32_t dp_tx3_rate; - uint32_t dp_tx0_eq_main; - uint32_t dp_tx0_eq_pre; - uint32_t dp_tx0_eq_post; - uint32_t dp_tx1_eq_main; - uint32_t dp_tx1_eq_pre; - uint32_t dp_tx1_eq_post; - uint32_t dp_tx2_eq_main; - uint32_t dp_tx2_eq_pre; - uint32_t dp_tx2_eq_post; - uint32_t dp_tx3_eq_main; - uint32_t dp_tx3_eq_pre; - uint32_t dp_tx3_eq_post; - bool data_swap_en; - bool data_order_invert_en; - uint32_t ldpcs_fifo_start_delay; - uint32_t rdpcs_fifo_start_delay; - bool rdpcs_reg_fifo_error_mask; - bool rdpcs_tx_fifo_error_mask; - bool rdpcs_dpalt_disable_mask; - bool rdpcs_dpalt_4lane_mask; -#endif -}; - -struct dcn20_link_encoder { - struct dcn10_link_encoder enc10; - struct dpcssys_phy_seq_cfg phy_seq_cfg; -}; - -void enc2_fec_set_enable(struct link_encoder *enc, bool enable); -void enc2_fec_set_ready(struct link_encoder *enc, bool ready); -bool enc2_fec_is_active(struct link_encoder *enc); -void enc2_hw_init(struct link_encoder *enc); - -void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s); - -void dcn20_link_encoder_enable_dp_output( - struct link_encoder *enc, - const struct dc_link_settings *link_settings, - enum clock_source_id clock_source); - -bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc); -void dcn20_link_encoder_get_max_link_cap(struct link_encoder *enc, - struct dc_link_settings *link_settings); - -void dcn20_link_encoder_construct( - struct dcn20_link_encoder *enc20, - const struct encoder_init_data *init_data, - const struct encoder_feature_support *enc_features, - const struct dcn10_link_enc_registers *link_regs, - const struct dcn10_link_enc_aux_registers *aux_regs, - const struct dcn10_link_enc_hpd_registers *hpd_regs, - const struct dcn10_link_enc_shift *link_shift, - const struct dcn10_link_enc_mask *link_mask); - -#endif /* __DC_LINK_ENCODER__DCN20_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c deleted file mode 100644 index 259a98e4ee2c..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - - -#include "reg_helper.h" -#include "resource.h" -#include "mcif_wb.h" -#include "dcn20_mmhubbub.h" - - -#define REG(reg)\ - mcif_wb20->mcif_wb_regs->reg - -#define CTX \ - mcif_wb20->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - mcif_wb20->mcif_wb_shift->field_name, mcif_wb20->mcif_wb_mask->field_name - -#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8 -#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40 - -/* wbif programming guide: - * 1. set up wbif parameter: - * unsigned long long luma_address[4]; //4 frame buffer - * unsigned long long chroma_address[4]; - * unsigned int luma_pitch; - * unsigned int chroma_pitch; - * unsigned int warmup_pitch=0x10; //256B align, the page size is 4KB when it is 0x10 - * unsigned int slice_lines; //slice size - * unsigned int time_per_pixel; // time per pixel, in ns - * unsigned int arbitration_slice; // 0: 512 bytes 1: 1024 bytes 2: 2048 Bytes - * unsigned int max_scaled_time; // used for QOS generation - * unsigned int swlock=0x0; - * unsigned int cli_watermark[4]; //4 group urgent watermark - * unsigned int pstate_watermark[4]; //4 group pstate watermark - * unsigned int sw_int_en; // Software interrupt enable, frame end and overflow - * unsigned int sw_slice_int_en; // slice end interrupt enable - * unsigned int sw_overrun_int_en; // overrun error interrupt enable - * unsigned int vce_int_en; // VCE interrupt enable, frame end and overflow - * unsigned int vce_slice_int_en; // VCE slice end interrupt enable, frame end and overflow - * - * 2. configure wbif register - * a. call mmhubbub_config_wbif() - * - * 3. Enable wbif - * call set_wbif_bufmgr_enable(); - * - * 4. wbif_dump_status(), option, for debug purpose - * the bufmgr status can show the progress of write back, can be used for debug purpose - */ - -static void mmhubbub2_config_mcif_buf(struct mcif_wb *mcif_wb, - struct mcif_buf_params *params, - unsigned int dest_height) -{ - struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb); - - /* sw lock buffer0~buffer3, default is 0 */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock); - - /* buffer address for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); - REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0])); - /* right eye sub-buffer address offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0); - - /* buffer address for Chroma in planar mode (unused in packing mode) */ - REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); - REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0])); - /* right eye offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0); - - /* buffer address for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); - REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1])); - /* right eye sub-buffer address offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0); - - /* buffer address for Chroma in planar mode (unused in packing mode) */ - REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); - REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1])); - /* right eye offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, 0); - - /* buffer address for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2])); - REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2])); - /* right eye sub-buffer address offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, 0); - - /* buffer address for Chroma in planar mode (unused in packing mode) */ - REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2])); - REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2])); - /* right eye offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, 0); - - /* buffer address for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3])); - REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3])); - /* right eye sub-buffer address offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, 0); - - /* buffer address for Chroma in planar mode (unused in packing mode) */ - REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3])); - REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3])); - /* right eye offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, 0); - - /* setup luma & chroma size - * should be enough to contain a whole frame Luma data, - * the programmed value is frame buffer size [27:8], 256-byte aligned - */ - REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height); - REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height); - - /* enable address fence */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1); - - /* setup pitch, the programmed value is [15:8], 256B align */ - REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, params->luma_pitch >> 8, - MCIF_WB_BUF_CHROMA_PITCH, params->chroma_pitch >> 8); - - /* Set pitch for MC cache warm up mode */ - /* Pitch is 256 bytes aligned. The default pitch is 4K */ - /* default is 0x10 */ - REG_UPDATE(MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, params->warmup_pitch); -} - -static void mmhubbub2_config_mcif_arb(struct mcif_wb *mcif_wb, - struct mcif_arb_params *params) -{ - struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb); - - /* Programmed by the video driver based on the CRTC timing (for DWB) */ - REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel); - - /* Programming dwb watermark */ - /* Watermark to generate urgent in MCIF_WB_CLI, value is determined by MCIF_WB_CLI_WATERMARK_MASK. */ - /* Program in ns. A formula will be provided in the pseudo code to calculate the value. */ - REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x0); - /* urgent_watermarkA */ - REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[0]); - REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x1); - /* urgent_watermarkB */ - REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[1]); - REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x2); - /* urgent_watermarkC */ - REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[2]); - REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x3); - /* urgent_watermarkD */ - REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[3]); - - /* Programming nb pstate watermark */ - /* nbp_state_change_watermarkA */ - REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0); - REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, - NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[0]); - /* nbp_state_change_watermarkB */ - REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1); - REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, - NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[1]); - /* nbp_state_change_watermarkC */ - REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2); - REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, - NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[2]); - /* nbp_state_change_watermarkD */ - REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3); - REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, - NB_PSTATE_CHANGE_REFRESH_WATERMARK, params->pstate_watermark[3]); - - /* max_scaled_time */ - REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time); - - /* slice_lines */ - REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1); - - /* Set arbitration unit for Luma/Chroma */ - /* arb_unit=2 should be chosen for more efficiency */ - /* Arbitration size, 0: 512 bytes 1: 1024 bytes 2: 2048 Bytes */ - REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, params->arbitration_slice); -} - -void mmhubbub2_config_mcif_irq(struct mcif_wb *mcif_wb, - struct mcif_irq_params *params) -{ - struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb); - - /* Set interrupt mask */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, params->sw_int_en); - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, params->sw_slice_int_en); - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, params->sw_overrun_int_en); - - REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, params->vce_int_en); - if (mcif_wb20->mcif_wb_mask->MCIF_WB_BUFMGR_VCE_SLICE_INT_EN) - REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, params->vce_slice_int_en); -} - -void mmhubbub2_enable_mcif(struct mcif_wb *mcif_wb) -{ - struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb); - - /* Enable Mcifwb */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 1); -} - -void mmhubbub2_disable_mcif(struct mcif_wb *mcif_wb) -{ - struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb); - - /* disable buffer manager */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 0); -} - -/* set which group of pstate watermark to use and set wbif watermark change request */ -/* -static void mmhubbub2_wbif_watermark_change_req(struct mcif_wb *mcif_wb, unsigned int wm_set) -{ - struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb); - uint32_t change_req; - - REG_GET(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, &change_req); - change_req = (change_req == 0) ? 1 : 0; - REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, wm_set); - REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, change_req); -} -*/ -/* Set watermark change interrupt disable bit */ -/* -static void mmhubbub2_set_wbif_watermark_change_int_disable(struct mcif_wb *mcif_wb, unsigned int ack_int_dis) -{ - struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb); - - REG_UPDATE(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, ack_int_dis); -} -*/ -/* Read watermark change interrupt status */ -/* -unsigned int mmhubbub2_get_wbif_watermark_change_int_status(struct mcif_wb *mcif_wb) -{ - struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb); - uint32_t irq_status; - - REG_GET(SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, &irq_status); - return irq_status; -} -*/ - -void mcifwb2_dump_frame(struct mcif_wb *mcif_wb, - struct mcif_buf_params *mcif_params, - enum dwb_scaler_mode out_format, - unsigned int dest_width, - unsigned int dest_height, - struct mcif_wb_frame_dump_info *dump_info, - unsigned char *luma_buffer, - unsigned char *chroma_buffer, - unsigned char *dest_luma_buffer, - unsigned char *dest_chroma_buffer) -{ - struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb); - - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf); - - memcpy(dest_luma_buffer, luma_buffer, mcif_params->luma_pitch * dest_height); - memcpy(dest_chroma_buffer, chroma_buffer, mcif_params->chroma_pitch * dest_height / 2); - - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0); - - dump_info->format = out_format; - dump_info->width = dest_width; - dump_info->height = dest_height; - dump_info->luma_pitch = mcif_params->luma_pitch; - dump_info->chroma_pitch = mcif_params->chroma_pitch; - dump_info->size = dest_height * (mcif_params->luma_pitch + mcif_params->chroma_pitch); -} - -static const struct mcif_wb_funcs dcn20_mmhubbub_funcs = { - .enable_mcif = mmhubbub2_enable_mcif, - .disable_mcif = mmhubbub2_disable_mcif, - .config_mcif_buf = mmhubbub2_config_mcif_buf, - .config_mcif_arb = mmhubbub2_config_mcif_arb, - .config_mcif_irq = mmhubbub2_config_mcif_irq, - .dump_frame = mcifwb2_dump_frame, -}; - -void dcn20_mmhubbub_construct(struct dcn20_mmhubbub *mcif_wb20, - struct dc_context *ctx, - const struct dcn20_mmhubbub_registers *mcif_wb_regs, - const struct dcn20_mmhubbub_shift *mcif_wb_shift, - const struct dcn20_mmhubbub_mask *mcif_wb_mask, - int inst) -{ - mcif_wb20->base.ctx = ctx; - - mcif_wb20->base.inst = inst; - mcif_wb20->base.funcs = &dcn20_mmhubbub_funcs; - - mcif_wb20->mcif_wb_regs = mcif_wb_regs; - mcif_wb20->mcif_wb_shift = mcif_wb_shift; - mcif_wb20->mcif_wb_mask = mcif_wb_mask; -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h deleted file mode 100644 index 5ab32aa51e13..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_MCIF_WB_DCN20_H__ -#define __DC_MCIF_WB_DCN20_H__ - -#define TO_DCN20_MMHUBBUB(mcif_wb_base) \ - container_of(mcif_wb_base, struct dcn20_mmhubbub, base) - -#define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \ - SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\ - SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\ - SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\ - SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\ - SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\ - SRI(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\ - SRI(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\ - SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\ - SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\ - SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\ - SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\ - SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\ - SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\ - SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\ - SRI(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\ - SRI(SMU_WM_CONTROL, WBIF, inst) - -#define MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_LONG_LINE_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SHORT_LINE_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FRAME_LENGTH_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_CUR_LINE_R, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FIELD, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_LONG_LINE_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SHORT_LINE_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FRAME_LENGTH_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_CUR_LINE_R, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FIELD, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_LONG_LINE_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SHORT_LINE_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FRAME_LENGTH_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_CUR_LINE_R, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FIELD, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_LONG_LINE_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SHORT_LINE_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FRAME_LENGTH_ERROR, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_CUR_LINE_R, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB_TEST_DEBUG_INDEX, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA, MCIF_WB_TEST_DEBUG_DATA, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, DIS_REFRESH_UNDER_NBPREQ, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\ - SF(MCIF_WB0_MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_SECURITY_LEVEL, MCIF_WB_SECURITY_LEVEL, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\ - SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\ - SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, mask_sh),\ - SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, mask_sh),\ - SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, mask_sh) - -#define MCIF_WB_REG_FIELD_LIST_DCN2_0(type) \ - type MCIF_WB_BUFMGR_ENABLE;\ - type MCIF_WB_BUFMGR_SW_INT_EN;\ - type MCIF_WB_BUFMGR_SW_INT_ACK;\ - type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\ - type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\ - type MCIF_WB_BUFMGR_SW_LOCK;\ - type MCIF_WB_P_VMID;\ - type MCIF_WB_BUF_ADDR_FENCE_EN;\ - type MCIF_WB_BUFMGR_CUR_LINE_R;\ - type MCIF_WB_BUFMGR_VCE_INT_STATUS;\ - type MCIF_WB_BUFMGR_SW_INT_STATUS;\ - type MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS;\ - type MCIF_WB_BUFMGR_CUR_BUF;\ - type MCIF_WB_BUFMGR_BUFTAG;\ - type MCIF_WB_BUFMGR_CUR_LINE_L;\ - type MCIF_WB_BUFMGR_NEXT_BUF;\ - type MCIF_WB_BUF_LUMA_PITCH;\ - type MCIF_WB_BUF_CHROMA_PITCH;\ - type MCIF_WB_BUF_1_ACTIVE;\ - type MCIF_WB_BUF_1_SW_LOCKED;\ - type MCIF_WB_BUF_1_VCE_LOCKED;\ - type MCIF_WB_BUF_1_OVERFLOW;\ - type MCIF_WB_BUF_1_DISABLE;\ - type MCIF_WB_BUF_1_MODE;\ - type MCIF_WB_BUF_1_BUFTAG;\ - type MCIF_WB_BUF_1_NXT_BUF;\ - type MCIF_WB_BUF_1_FIELD;\ - type MCIF_WB_BUF_1_CUR_LINE_L;\ - type MCIF_WB_BUF_1_LONG_LINE_ERROR;\ - type MCIF_WB_BUF_1_SHORT_LINE_ERROR;\ - type MCIF_WB_BUF_1_FRAME_LENGTH_ERROR;\ - type MCIF_WB_BUF_1_CUR_LINE_R;\ - type MCIF_WB_BUF_1_NEW_CONTENT;\ - type MCIF_WB_BUF_1_COLOR_DEPTH;\ - type MCIF_WB_BUF_1_TMZ_BLACK_PIXEL;\ - type MCIF_WB_BUF_1_TMZ;\ - type MCIF_WB_BUF_1_Y_OVERRUN;\ - type MCIF_WB_BUF_1_C_OVERRUN;\ - type MCIF_WB_BUF_2_ACTIVE;\ - type MCIF_WB_BUF_2_SW_LOCKED;\ - type MCIF_WB_BUF_2_VCE_LOCKED;\ - type MCIF_WB_BUF_2_OVERFLOW;\ - type MCIF_WB_BUF_2_DISABLE;\ - type MCIF_WB_BUF_2_MODE;\ - type MCIF_WB_BUF_2_BUFTAG;\ - type MCIF_WB_BUF_2_NXT_BUF;\ - type MCIF_WB_BUF_2_FIELD;\ - type MCIF_WB_BUF_2_CUR_LINE_L;\ - type MCIF_WB_BUF_2_LONG_LINE_ERROR;\ - type MCIF_WB_BUF_2_SHORT_LINE_ERROR;\ - type MCIF_WB_BUF_2_FRAME_LENGTH_ERROR;\ - type MCIF_WB_BUF_2_CUR_LINE_R;\ - type MCIF_WB_BUF_2_NEW_CONTENT;\ - type MCIF_WB_BUF_2_COLOR_DEPTH;\ - type MCIF_WB_BUF_2_TMZ_BLACK_PIXEL;\ - type MCIF_WB_BUF_2_TMZ;\ - type MCIF_WB_BUF_2_Y_OVERRUN;\ - type MCIF_WB_BUF_2_C_OVERRUN;\ - type MCIF_WB_BUF_3_ACTIVE;\ - type MCIF_WB_BUF_3_SW_LOCKED;\ - type MCIF_WB_BUF_3_VCE_LOCKED;\ - type MCIF_WB_BUF_3_OVERFLOW;\ - type MCIF_WB_BUF_3_DISABLE;\ - type MCIF_WB_BUF_3_MODE;\ - type MCIF_WB_BUF_3_BUFTAG;\ - type MCIF_WB_BUF_3_NXT_BUF;\ - type MCIF_WB_BUF_3_FIELD;\ - type MCIF_WB_BUF_3_CUR_LINE_L;\ - type MCIF_WB_BUF_3_LONG_LINE_ERROR;\ - type MCIF_WB_BUF_3_SHORT_LINE_ERROR;\ - type MCIF_WB_BUF_3_FRAME_LENGTH_ERROR;\ - type MCIF_WB_BUF_3_CUR_LINE_R;\ - type MCIF_WB_BUF_3_NEW_CONTENT;\ - type MCIF_WB_BUF_3_COLOR_DEPTH;\ - type MCIF_WB_BUF_3_TMZ_BLACK_PIXEL;\ - type MCIF_WB_BUF_3_TMZ;\ - type MCIF_WB_BUF_3_Y_OVERRUN;\ - type MCIF_WB_BUF_3_C_OVERRUN;\ - type MCIF_WB_BUF_4_ACTIVE;\ - type MCIF_WB_BUF_4_SW_LOCKED;\ - type MCIF_WB_BUF_4_VCE_LOCKED;\ - type MCIF_WB_BUF_4_OVERFLOW;\ - type MCIF_WB_BUF_4_DISABLE;\ - type MCIF_WB_BUF_4_MODE;\ - type MCIF_WB_BUF_4_BUFTAG;\ - type MCIF_WB_BUF_4_NXT_BUF;\ - type MCIF_WB_BUF_4_FIELD;\ - type MCIF_WB_BUF_4_CUR_LINE_L;\ - type MCIF_WB_BUF_4_LONG_LINE_ERROR;\ - type MCIF_WB_BUF_4_SHORT_LINE_ERROR;\ - type MCIF_WB_BUF_4_FRAME_LENGTH_ERROR;\ - type MCIF_WB_BUF_4_CUR_LINE_R;\ - type MCIF_WB_BUF_4_NEW_CONTENT;\ - type MCIF_WB_BUF_4_COLOR_DEPTH;\ - type MCIF_WB_BUF_4_TMZ_BLACK_PIXEL;\ - type MCIF_WB_BUF_4_TMZ;\ - type MCIF_WB_BUF_4_Y_OVERRUN;\ - type MCIF_WB_BUF_4_C_OVERRUN;\ - type MCIF_WB_CLIENT_ARBITRATION_SLICE;\ - type MCIF_WB_TIME_PER_PIXEL;\ - type WM_CHANGE_ACK_FORCE_ON;\ - type MCIF_WB_CLI_WATERMARK_MASK;\ - type MCIF_WB_TEST_DEBUG_INDEX;\ - type MCIF_WB_TEST_DEBUG_DATA;\ - type MCIF_WB_BUF_1_ADDR_Y;\ - type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\ - type MCIF_WB_BUF_1_ADDR_C;\ - type MCIF_WB_BUF_1_ADDR_C_OFFSET;\ - type MCIF_WB_BUF_2_ADDR_Y;\ - type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\ - type MCIF_WB_BUF_2_ADDR_C;\ - type MCIF_WB_BUF_2_ADDR_C_OFFSET;\ - type MCIF_WB_BUF_3_ADDR_Y;\ - type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\ - type MCIF_WB_BUF_3_ADDR_C;\ - type MCIF_WB_BUF_3_ADDR_C_OFFSET;\ - type MCIF_WB_BUF_4_ADDR_Y;\ - type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\ - type MCIF_WB_BUF_4_ADDR_C;\ - type MCIF_WB_BUF_4_ADDR_C_OFFSET;\ - type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\ - type MCIF_WB_BUFMGR_VCE_INT_EN;\ - type MCIF_WB_BUFMGR_VCE_INT_ACK;\ - type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\ - type MCIF_WB_BUFMGR_VCE_LOCK;\ - type MCIF_WB_BUFMGR_SLICE_SIZE;\ - type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\ - type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\ - type NB_PSTATE_CHANGE_FORCE_ON;\ - type NB_PSTATE_ALLOW_FOR_URGENT;\ - type NB_PSTATE_CHANGE_WATERMARK_MASK;\ - type MCIF_WB_CLI_WATERMARK;\ - type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\ - type MCIF_WB_PITCH_SIZE_WARMUP;\ - type DIS_REFRESH_UNDER_NBPREQ;\ - type PERFRAME_SELF_REFRESH;\ - type MAX_SCALED_TIME_TO_URGENT;\ - type MCIF_WB_SECURITY_LEVEL;\ - type MCIF_WB_BUF_LUMA_SIZE;\ - type MCIF_WB_BUF_CHROMA_SIZE;\ - type MCIF_WB_BUF_1_ADDR_Y_HIGH;\ - type MCIF_WB_BUF_1_ADDR_C_HIGH;\ - type MCIF_WB_BUF_2_ADDR_Y_HIGH;\ - type MCIF_WB_BUF_2_ADDR_C_HIGH;\ - type MCIF_WB_BUF_3_ADDR_Y_HIGH;\ - type MCIF_WB_BUF_3_ADDR_C_HIGH;\ - type MCIF_WB_BUF_4_ADDR_Y_HIGH;\ - type MCIF_WB_BUF_4_ADDR_C_HIGH;\ - type MCIF_WB_BUF_1_RESOLUTION_WIDTH;\ - type MCIF_WB_BUF_1_RESOLUTION_HEIGHT;\ - type MCIF_WB_BUF_2_RESOLUTION_WIDTH;\ - type MCIF_WB_BUF_2_RESOLUTION_HEIGHT;\ - type MCIF_WB_BUF_3_RESOLUTION_WIDTH;\ - type MCIF_WB_BUF_3_RESOLUTION_HEIGHT;\ - type MCIF_WB_BUF_4_RESOLUTION_WIDTH;\ - type MCIF_WB_BUF_4_RESOLUTION_HEIGHT;\ - type MCIF_WB0_WM_CHG_SEL;\ - type MCIF_WB0_WM_CHG_REQ;\ - type MCIF_WB0_WM_CHG_ACK_INT_DIS;\ - type MCIF_WB0_WM_CHG_ACK_INT_STATUS - -#define MCIF_WB_REG_VARIABLE_LIST_DCN2_0 \ - uint32_t MCIF_WB_BUFMGR_SW_CONTROL;\ - uint32_t MCIF_WB_BUFMGR_CUR_LINE_R;\ - uint32_t MCIF_WB_BUFMGR_STATUS;\ - uint32_t MCIF_WB_BUF_PITCH;\ - uint32_t MCIF_WB_BUF_1_STATUS;\ - uint32_t MCIF_WB_BUF_1_STATUS2;\ - uint32_t MCIF_WB_BUF_2_STATUS;\ - uint32_t MCIF_WB_BUF_2_STATUS2;\ - uint32_t MCIF_WB_BUF_3_STATUS;\ - uint32_t MCIF_WB_BUF_3_STATUS2;\ - uint32_t MCIF_WB_BUF_4_STATUS;\ - uint32_t MCIF_WB_BUF_4_STATUS2;\ - uint32_t MCIF_WB_ARBITRATION_CONTROL;\ - uint32_t MCIF_WB_SCLK_CHANGE;\ - uint32_t MCIF_WB_TEST_DEBUG_INDEX;\ - uint32_t MCIF_WB_TEST_DEBUG_DATA;\ - uint32_t MCIF_WB_BUF_1_ADDR_Y;\ - uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;\ - uint32_t MCIF_WB_BUF_1_ADDR_C;\ - uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;\ - uint32_t MCIF_WB_BUF_2_ADDR_Y;\ - uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;\ - uint32_t MCIF_WB_BUF_2_ADDR_C;\ - uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;\ - uint32_t MCIF_WB_BUF_3_ADDR_Y;\ - uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;\ - uint32_t MCIF_WB_BUF_3_ADDR_C;\ - uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;\ - uint32_t MCIF_WB_BUF_4_ADDR_Y;\ - uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;\ - uint32_t MCIF_WB_BUF_4_ADDR_C;\ - uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;\ - uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;\ - uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;\ - uint32_t MCIF_WB_NB_PSTATE_CONTROL;\ - uint32_t MCIF_WB_WATERMARK;\ - uint32_t MCIF_WB_CLOCK_GATER_CONTROL;\ - uint32_t MCIF_WB_WARM_UP_CNTL;\ - uint32_t MCIF_WB_SELF_REFRESH_CONTROL;\ - uint32_t MULTI_LEVEL_QOS_CTRL;\ - uint32_t MCIF_WB_SECURITY_LEVEL;\ - uint32_t MCIF_WB_BUF_LUMA_SIZE;\ - uint32_t MCIF_WB_BUF_CHROMA_SIZE;\ - uint32_t MCIF_WB_BUF_1_ADDR_Y_HIGH;\ - uint32_t MCIF_WB_BUF_1_ADDR_C_HIGH;\ - uint32_t MCIF_WB_BUF_2_ADDR_Y_HIGH;\ - uint32_t MCIF_WB_BUF_2_ADDR_C_HIGH;\ - uint32_t MCIF_WB_BUF_3_ADDR_Y_HIGH;\ - uint32_t MCIF_WB_BUF_3_ADDR_C_HIGH;\ - uint32_t MCIF_WB_BUF_4_ADDR_Y_HIGH;\ - uint32_t MCIF_WB_BUF_4_ADDR_C_HIGH;\ - uint32_t MCIF_WB_BUF_1_RESOLUTION;\ - uint32_t MCIF_WB_BUF_2_RESOLUTION;\ - uint32_t MCIF_WB_BUF_3_RESOLUTION;\ - uint32_t MCIF_WB_BUF_4_RESOLUTION;\ - uint32_t SMU_WM_CONTROL - -struct dcn20_mmhubbub_registers { - MCIF_WB_REG_VARIABLE_LIST_DCN2_0; -}; - - -struct dcn20_mmhubbub_mask { - MCIF_WB_REG_FIELD_LIST_DCN2_0(uint32_t); -}; - -struct dcn20_mmhubbub_shift { - MCIF_WB_REG_FIELD_LIST_DCN2_0(uint8_t); -}; - -struct dcn20_mmhubbub { - struct mcif_wb base; - const struct dcn20_mmhubbub_registers *mcif_wb_regs; - const struct dcn20_mmhubbub_shift *mcif_wb_shift; - const struct dcn20_mmhubbub_mask *mcif_wb_mask; -}; - -void mmhubbub2_config_mcif_irq(struct mcif_wb *mcif_wb, - struct mcif_irq_params *params); - -void mmhubbub2_enable_mcif(struct mcif_wb *mcif_wb); - -void mmhubbub2_disable_mcif(struct mcif_wb *mcif_wb); - -void mcifwb2_dump_frame(struct mcif_wb *mcif_wb, - struct mcif_buf_params *mcif_params, - enum dwb_scaler_mode out_format, - unsigned int dest_width, - unsigned int dest_height, - struct mcif_wb_frame_dump_info *dump_info, - unsigned char *luma_buffer, - unsigned char *chroma_buffer, - unsigned char *dest_luma_buffer, - unsigned char *dest_chroma_buffer); - -void dcn20_mmhubbub_construct(struct dcn20_mmhubbub *mcif_wb20, - struct dc_context *ctx, - const struct dcn20_mmhubbub_registers *mcif_wb_regs, - const struct dcn20_mmhubbub_shift *mcif_wb_shift, - const struct dcn20_mmhubbub_mask *mcif_wb_mask, - int inst); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c deleted file mode 100644 index 16b5ff208d14..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dcn20_mpc.h" - -#include "reg_helper.h" -#include "dc.h" -#include "mem_input.h" -#include "dcn10/dcn10_cm_common.h" - -#define REG(reg)\ - mpc20->mpc_regs->reg - -#define IND_REG(index) \ - (index) - -#define CTX \ - mpc20->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name - -#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) - -void mpc2_update_blending( - struct mpc *mpc, - struct mpcc_blnd_cfg *blnd_cfg, - int mpcc_id) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - - struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); - - REG_UPDATE_7(MPCC_CONTROL[mpcc_id], - MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, - MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha, - MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only, - MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha, - MPCC_GLOBAL_GAIN, blnd_cfg->global_gain, - MPCC_BG_BPC, blnd_cfg->background_color_bpc, - MPCC_BOT_GAIN_MODE, blnd_cfg->bottom_gain_mode); - - REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); - REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); - REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); - - mpcc->blnd_cfg = *blnd_cfg; -} - -void mpc2_set_denorm( - struct mpc *mpc, - int opp_id, - enum dc_color_depth output_depth) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - int denorm_mode = 0; - - switch (output_depth) { - case COLOR_DEPTH_666: - denorm_mode = 1; - break; - case COLOR_DEPTH_888: - denorm_mode = 2; - break; - case COLOR_DEPTH_999: - denorm_mode = 3; - break; - case COLOR_DEPTH_101010: - denorm_mode = 4; - break; - case COLOR_DEPTH_111111: - denorm_mode = 5; - break; - case COLOR_DEPTH_121212: - denorm_mode = 6; - break; - case COLOR_DEPTH_141414: - case COLOR_DEPTH_161616: - default: - /* not valid used case! */ - break; - } - - REG_UPDATE(DENORM_CONTROL[opp_id], - MPC_OUT_DENORM_MODE, denorm_mode); -} - -void mpc2_set_denorm_clamp( - struct mpc *mpc, - int opp_id, - struct mpc_denorm_clamp denorm_clamp) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - - REG_UPDATE_2(DENORM_CONTROL[opp_id], - MPC_OUT_DENORM_CLAMP_MAX_R_CR, denorm_clamp.clamp_max_r_cr, - MPC_OUT_DENORM_CLAMP_MIN_R_CR, denorm_clamp.clamp_min_r_cr); - REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], - MPC_OUT_DENORM_CLAMP_MAX_G_Y, denorm_clamp.clamp_max_g_y, - MPC_OUT_DENORM_CLAMP_MIN_G_Y, denorm_clamp.clamp_min_g_y); - REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], - MPC_OUT_DENORM_CLAMP_MAX_B_CB, denorm_clamp.clamp_max_b_cb, - MPC_OUT_DENORM_CLAMP_MIN_B_CB, denorm_clamp.clamp_min_b_cb); -} - - - -void mpc2_set_output_csc( - struct mpc *mpc, - int opp_id, - const uint16_t *regval, - enum mpc_output_csc_mode ocsc_mode) -{ - uint32_t cur_mode; - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - struct color_matrices_reg ocsc_regs; - - if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) { - REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); - return; - } - - if (regval == NULL) { - BREAK_TO_DEBUGGER(); - return; - } - - /* determine which CSC coefficients (A or B) we are using - * currently. select the alternate set to double buffer - * the CSC update so CSC is updated on frame boundary - */ - IX_REG_GET(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_DATA, - MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX, - MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE, &cur_mode); - - if (cur_mode != MPC_OUTPUT_CSC_COEF_A) - ocsc_mode = MPC_OUTPUT_CSC_COEF_A; - else - ocsc_mode = MPC_OUTPUT_CSC_COEF_B; - - ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; - ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; - ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; - ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; - - if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { - ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); - ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); - } else { - ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); - ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); - } - - cm_helper_program_color_matrices( - mpc20->base.ctx, - regval, - &ocsc_regs); - - REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); -} - -void mpc2_set_ocsc_default( - struct mpc *mpc, - int opp_id, - enum dc_color_space color_space, - enum mpc_output_csc_mode ocsc_mode) -{ - uint32_t cur_mode; - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - uint32_t arr_size; - struct color_matrices_reg ocsc_regs; - const uint16_t *regval = NULL; - - if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) { - REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); - return; - } - - regval = find_color_matrix(color_space, &arr_size); - - if (regval == NULL) { - BREAK_TO_DEBUGGER(); - return; - } - - /* determine which CSC coefficients (A or B) we are using - * currently. select the alternate set to double buffer - * the CSC update so CSC is updated on frame boundary - */ - IX_REG_GET(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_DATA, - MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX, - MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE, &cur_mode); - - if (cur_mode != MPC_OUTPUT_CSC_COEF_A) - ocsc_mode = MPC_OUTPUT_CSC_COEF_A; - else - ocsc_mode = MPC_OUTPUT_CSC_COEF_B; - - ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; - ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; - ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; - ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; - - - if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { - ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); - ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); - } else { - ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); - ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); - } - - cm_helper_program_color_matrices( - mpc20->base.ctx, - regval, - &ocsc_regs); - - REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); -} - -static void mpc2_ogam_get_reg_field( - struct mpc *mpc, - struct xfer_func_reg *reg) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - - reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; - reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; - reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; - reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; - reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; - reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; - reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; - reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; - reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; - reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; - reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; - reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; - reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; - reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; - reg->shifts.field_region_linear_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; - reg->masks.field_region_linear_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; - reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B; - reg->masks.exp_region_start = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B; - reg->shifts.exp_resion_start_segment = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; - reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; -} - -void mpc20_power_on_ogam_lut( - struct mpc *mpc, int mpcc_id, - bool power_on) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - - REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, - MPCC_OGAM_MEM_PWR_DIS, power_on == true ? 1:0); - -} - -static void mpc20_configure_ogam_lut( - struct mpc *mpc, int mpcc_id, - bool is_ram_a) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - - REG_UPDATE_2(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], - MPCC_OGAM_LUT_WRITE_EN_MASK, 7, - MPCC_OGAM_LUT_RAM_SEL, is_ram_a == true ? 0:1); - - REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); -} - -static enum dc_lut_mode mpc20_get_ogam_current(struct mpc *mpc, int mpcc_id) -{ - enum dc_lut_mode mode; - uint32_t state_mode; - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - - REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], MPCC_OGAM_CONFIG_STATUS, &state_mode); - - switch (state_mode) { - case 0: - mode = LUT_BYPASS; - break; - case 1: - mode = LUT_RAM_A; - break; - case 2: - mode = LUT_RAM_B; - break; - default: - mode = LUT_BYPASS; - break; - } - - return mode; -} - -static void mpc2_program_lutb(struct mpc *mpc, int mpcc_id, - const struct pwl_params *params) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - struct xfer_func_reg gam_regs; - - mpc2_ogam_get_reg_field(mpc, &gam_regs); - - gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]); - gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]); - gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]); - gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_B[mpcc_id]); - gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_G[mpcc_id]); - gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]); - gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]); - gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]); - gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]); - gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]); - gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]); - gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]); - gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]); - gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]); - - cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs); - -} - -static void mpc2_program_luta(struct mpc *mpc, int mpcc_id, - const struct pwl_params *params) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - struct xfer_func_reg gam_regs; - - mpc2_ogam_get_reg_field(mpc, &gam_regs); - - gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]); - gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]); - gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]); - gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_B[mpcc_id]); - gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_G[mpcc_id]); - gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_R[mpcc_id]); - gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]); - gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]); - gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]); - gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]); - gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]); - gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]); - gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]); - gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]); - - cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs); - -} - -static void mpc20_program_ogam_pwl( - struct mpc *mpc, int mpcc_id, - const struct pwl_result_data *rgb, - uint32_t num) -{ - uint32_t i; - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - - PERF_TRACE(); - REG_SEQ_START(); - - for (i = 0 ; i < num; i++) { - REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg); - REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg); - REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].blue_reg); - - REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, - MPCC_OGAM_LUT_DATA, rgb[i].delta_red_reg); - REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, - MPCC_OGAM_LUT_DATA, rgb[i].delta_green_reg); - REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, - MPCC_OGAM_LUT_DATA, rgb[i].delta_blue_reg); - - } - -} - -static void apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id, - enum dc_lut_mode current_mode, - enum dc_lut_mode next_mode) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - - if (mpc->ctx->dc->debug.cm_in_bypass) { - REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); - return; - } - - if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) { - /*hw fixed in new review*/ - return; - } - if (current_mode == LUT_BYPASS) - /*this will only work if OTG is locked. - *if we were to support OTG unlock case, - *the workaround will be more complex - */ - REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, - next_mode == LUT_RAM_A ? 1:2); -} - -void mpc2_set_output_gamma( - struct mpc *mpc, - int mpcc_id, - const struct pwl_params *params) -{ - enum dc_lut_mode current_mode; - enum dc_lut_mode next_mode; - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - - if (mpc->ctx->dc->debug.cm_in_bypass) { - REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); - return; - } - - if (params == NULL) { - REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); - return; - } - - current_mode = mpc20_get_ogam_current(mpc, mpcc_id); - if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) - next_mode = LUT_RAM_B; - else - next_mode = LUT_RAM_A; - - mpc20_power_on_ogam_lut(mpc, mpcc_id, true); - mpc20_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A); - - if (next_mode == LUT_RAM_A) - mpc2_program_luta(mpc, mpcc_id, params); - else - mpc2_program_lutb(mpc, mpcc_id, params); - - apply_DEDCN20_305_wa(mpc, mpcc_id, current_mode, next_mode); - - mpc20_program_ogam_pwl( - mpc, mpcc_id, params->rgb_resulted, params->hw_points_num); - - REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, - next_mode == LUT_RAM_A ? 1:2); -} -void mpc2_assert_idle_mpcc(struct mpc *mpc, int id) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - unsigned int mpc_disabled; - - ASSERT(!(mpc20->mpcc_in_use_mask & 1 << id)); - REG_GET(MPCC_STATUS[id], MPCC_DISABLED, &mpc_disabled); - if (mpc_disabled) - return; - - REG_WAIT(MPCC_STATUS[id], - MPCC_IDLE, 1, - 1, 100000); -} - -void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - unsigned int top_sel, mpc_busy, mpc_idle, mpc_disabled; - - REG_GET(MPCC_TOP_SEL[mpcc_id], - MPCC_TOP_SEL, &top_sel); - - REG_GET_3(MPCC_STATUS[mpcc_id], - MPCC_BUSY, &mpc_busy, - MPCC_IDLE, &mpc_idle, - MPCC_DISABLED, &mpc_disabled); - - if (top_sel == 0xf) { - ASSERT(!mpc_busy); - ASSERT(mpc_idle); - ASSERT(mpc_disabled); - } else { - ASSERT(!mpc_disabled); - ASSERT(!mpc_idle); - } - - REG_SEQ_SUBMIT(); - PERF_TRACE(); - REG_SEQ_WAIT_DONE(); - PERF_TRACE(); -} - -static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) -{ - mpcc->mpcc_id = mpcc_inst; - mpcc->dpp_id = 0xf; - mpcc->mpcc_bot = NULL; - mpcc->blnd_cfg.overlap_only = false; - mpcc->blnd_cfg.global_alpha = 0xff; - mpcc->blnd_cfg.global_gain = 0xff; - mpcc->blnd_cfg.background_color_bpc = 4; - mpcc->blnd_cfg.bottom_gain_mode = 0; - mpcc->blnd_cfg.top_gain = 0x1f000; - mpcc->blnd_cfg.bottom_inside_gain = 0x1f000; - mpcc->blnd_cfg.bottom_outside_gain = 0x1f000; - mpcc->sm_cfg.enable = false; -} - -static struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) -{ - struct mpcc *tmp_mpcc = tree->opp_list; - - while (tmp_mpcc != NULL) { - if (tmp_mpcc->dpp_id == 0xf || tmp_mpcc->dpp_id == dpp_id) - return tmp_mpcc; - - /* avoid circular linked list */ - ASSERT(tmp_mpcc != tmp_mpcc->mpcc_bot); - if (tmp_mpcc == tmp_mpcc->mpcc_bot) - break; - - tmp_mpcc = tmp_mpcc->mpcc_bot; - } - return NULL; -} - -static void mpc2_read_mpcc_state( - struct mpc *mpc, - int mpcc_inst, - struct mpcc_state *s) -{ - struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc); - - REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); - REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); - REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); - REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, - MPCC_ALPHA_BLND_MODE, &s->alpha_mode, - MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha, - MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only); - REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, - MPCC_BUSY, &s->busy); - - /* Gamma block state */ - REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_inst], - MPCC_OGAM_CONFIG_STATUS, &s->rgam_mode); -} - -static const struct mpc_funcs dcn20_mpc_funcs = { - .read_mpcc_state = mpc2_read_mpcc_state, - .insert_plane = mpc1_insert_plane, - .remove_mpcc = mpc1_remove_mpcc, - .mpc_init = mpc1_mpc_init, - .mpc_init_single_inst = mpc1_mpc_init_single_inst, - .update_blending = mpc2_update_blending, - .cursor_lock = mpc1_cursor_lock, - .get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp, - .wait_for_idle = mpc2_assert_idle_mpcc, - .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect, - .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, - .set_denorm = mpc2_set_denorm, - .set_denorm_clamp = mpc2_set_denorm_clamp, - .set_output_csc = mpc2_set_output_csc, - .set_ocsc_default = mpc2_set_ocsc_default, - .set_output_gamma = mpc2_set_output_gamma, - .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut, - .get_mpc_out_mux = mpc1_get_mpc_out_mux, - .set_bg_color = mpc1_set_bg_color, -}; - -void dcn20_mpc_construct(struct dcn20_mpc *mpc20, - struct dc_context *ctx, - const struct dcn20_mpc_registers *mpc_regs, - const struct dcn20_mpc_shift *mpc_shift, - const struct dcn20_mpc_mask *mpc_mask, - int num_mpcc) -{ - int i; - - mpc20->base.ctx = ctx; - - mpc20->base.funcs = &dcn20_mpc_funcs; - - mpc20->mpc_regs = mpc_regs; - mpc20->mpc_shift = mpc_shift; - mpc20->mpc_mask = mpc_mask; - - mpc20->mpcc_in_use_mask = 0; - mpc20->num_mpcc = num_mpcc; - - for (i = 0; i < MAX_MPCC; i++) - mpc2_init_mpcc(&mpc20->base.mpcc_array[i], i); -} - diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h deleted file mode 100644 index 496658f420db..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h +++ /dev/null @@ -1,312 +0,0 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_MPCC_DCN20_H__ -#define __DC_MPCC_DCN20_H__ - -#include "dcn10/dcn10_mpc.h" - -#define TO_DCN20_MPC(mpc_base) \ - container_of(mpc_base, struct dcn20_mpc, base) - -#define MPC_REG_LIST_DCN2_0(inst)\ - MPC_COMMON_REG_LIST_DCN1_0(inst),\ - SRII(MPCC_TOP_GAIN, MPCC, inst),\ - SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\ - SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\ - SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_G, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_R, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\ - SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\ - SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),\ - SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst) - -#define MPC_OUT_MUX_REG_LIST_DCN2_0(inst) \ - MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\ - SRII(CSC_MODE, MPC_OUT, inst),\ - SRII(CSC_C11_C12_A, MPC_OUT, inst),\ - SRII(CSC_C33_C34_A, MPC_OUT, inst),\ - SRII(CSC_C11_C12_B, MPC_OUT, inst),\ - SRII(CSC_C33_C34_B, MPC_OUT, inst),\ - SRII(DENORM_CONTROL, MPC_OUT, inst),\ - SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\ - SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst) - -#define MPC_DBG_REG_LIST_DCN2_0() \ - SR(MPC_OCSC_TEST_DEBUG_DATA),\ - SR(MPC_OCSC_TEST_DEBUG_INDEX) - -#define MPC_REG_VARIABLE_LIST_DCN2_0 \ - MPC_COMMON_REG_VARIABLE_LIST \ - uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \ - uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \ - uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_END_CNTL2_B[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_END_CNTL1_G[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_END_CNTL2_G[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_END_CNTL1_R[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_END_CNTL2_R[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_REGION_0_1[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMA_REGION_32_33[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_START_CNTL_B[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_START_CNTL_G[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_START_CNTL_R[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_B[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_G[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_R[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_END_CNTL1_B[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_END_CNTL2_B[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_END_CNTL1_G[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_END_CNTL2_G[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_END_CNTL1_R[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_END_CNTL2_R[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_REGION_0_1[MAX_MPCC]; \ - uint32_t MPCC_OGAM_RAMB_REGION_32_33[MAX_MPCC];\ - uint32_t MPCC_MEM_PWR_CTRL[MAX_MPCC];\ - uint32_t MPCC_OGAM_LUT_INDEX[MAX_MPCC];\ - uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\ - uint32_t MPCC_OGAM_LUT_DATA[MAX_MPCC];\ - uint32_t MPCC_OGAM_MODE[MAX_MPCC];\ - uint32_t MPC_OCSC_TEST_DEBUG_DATA;\ - uint32_t MPC_OCSC_TEST_DEBUG_INDEX;\ - uint32_t CSC_MODE[MAX_OPP]; \ - uint32_t CSC_C11_C12_A[MAX_OPP]; \ - uint32_t CSC_C33_C34_A[MAX_OPP]; \ - uint32_t CSC_C11_C12_B[MAX_OPP]; \ - uint32_t CSC_C33_C34_B[MAX_OPP]; \ - uint32_t DENORM_CONTROL[MAX_OPP]; \ - uint32_t DENORM_CLAMP_G_Y[MAX_OPP]; \ - uint32_t DENORM_CLAMP_B_CB[MAX_OPP]; - -#define MPC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \ - MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\ - SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ - SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ - SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ - SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ - SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ - SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\ - SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ - SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ - SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ - SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\ - SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ - SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_CONFIG_STATUS, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ - SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\ - SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ - SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ - SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ - SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ - SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ - SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ - SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\ - SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh) - -/* - * DCN2 MPC_OCSC debug status register: - * - * Status index including current OCSC Mode is 1 - * OCSC Mode: [1..0] - */ -#define MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX 1 - -#define MPC_DEBUG_REG_LIST_SH_DCN20 \ - .MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0 - -#define MPC_DEBUG_REG_LIST_MASK_DCN20 \ - .MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0x3 - -#define MPC_REG_FIELD_LIST_DCN2_0(type) \ - MPC_REG_FIELD_LIST(type)\ - type MPCC_BG_BPC;\ - type MPCC_BOT_GAIN_MODE;\ - type MPCC_TOP_GAIN;\ - type MPCC_BOT_GAIN_INSIDE;\ - type MPCC_BOT_GAIN_OUTSIDE;\ - type MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE;\ - type MPC_OCSC_TEST_DEBUG_INDEX;\ - type MPC_OCSC_MODE;\ - type MPC_OCSC_C11_A;\ - type MPC_OCSC_C12_A;\ - type MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;\ - type MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;\ - type MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;\ - type MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;\ - type MPCC_OGAM_RAMA_EXP_REGION_END_B;\ - type MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;\ - type MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;\ - type MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;\ - type MPCC_OGAM_RAMA_EXP_REGION_START_B;\ - type MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;\ - type MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET;\ - type MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS;\ - type MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET;\ - type MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS;\ - type MPCC_OGAM_RAMB_EXP_REGION_END_B;\ - type MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B;\ - type MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B;\ - type MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;\ - type MPCC_OGAM_RAMB_EXP_REGION_START_B;\ - type MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B;\ - type MPCC_OGAM_MEM_PWR_FORCE;\ - type MPCC_OGAM_LUT_INDEX;\ - type MPCC_OGAM_LUT_WRITE_EN_MASK;\ - type MPCC_OGAM_LUT_RAM_SEL;\ - type MPCC_OGAM_CONFIG_STATUS;\ - type MPCC_OGAM_LUT_DATA;\ - type MPCC_OGAM_MODE;\ - type MPC_OUT_DENORM_MODE;\ - type MPC_OUT_DENORM_CLAMP_MAX_R_CR;\ - type MPC_OUT_DENORM_CLAMP_MIN_R_CR;\ - type MPC_OUT_DENORM_CLAMP_MAX_G_Y;\ - type MPC_OUT_DENORM_CLAMP_MIN_G_Y;\ - type MPC_OUT_DENORM_CLAMP_MAX_B_CB;\ - type MPC_OUT_DENORM_CLAMP_MIN_B_CB;\ - type MPCC_DISABLED;\ - type MPCC_OGAM_MEM_PWR_DIS; - -struct dcn20_mpc_registers { - MPC_REG_VARIABLE_LIST_DCN2_0 -}; - -struct dcn20_mpc_shift { - MPC_REG_FIELD_LIST_DCN2_0(uint8_t) -}; - -struct dcn20_mpc_mask { - MPC_REG_FIELD_LIST_DCN2_0(uint32_t) -}; - -struct dcn20_mpc { - struct mpc base; - - int mpcc_in_use_mask; - int num_mpcc; - const struct dcn20_mpc_registers *mpc_regs; - const struct dcn20_mpc_shift *mpc_shift; - const struct dcn20_mpc_mask *mpc_mask; -}; - -void dcn20_mpc_construct(struct dcn20_mpc *mpcc20, - struct dc_context *ctx, - const struct dcn20_mpc_registers *mpc_regs, - const struct dcn20_mpc_shift *mpc_shift, - const struct dcn20_mpc_mask *mpc_mask, - int num_mpcc); - -void mpc2_update_blending( - struct mpc *mpc, - struct mpcc_blnd_cfg *blnd_cfg, - int mpcc_id); - -void mpc2_set_denorm( - struct mpc *mpc, - int opp_id, - enum dc_color_depth output_depth); - -void mpc2_set_denorm_clamp( - struct mpc *mpc, - int opp_id, - struct mpc_denorm_clamp denorm_clamp); - -void mpc2_set_output_csc( - struct mpc *mpc, - int opp_id, - const uint16_t *regval, - enum mpc_output_csc_mode ocsc_mode); - -void mpc2_set_ocsc_default( - struct mpc *mpc, - int opp_id, - enum dc_color_space color_space, - enum mpc_output_csc_mode ocsc_mode); - -void mpc2_set_output_gamma( - struct mpc *mpc, - int mpcc_id, - const struct pwl_params *params); - -void mpc2_assert_idle_mpcc(struct mpc *mpc, int id); -void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id); -void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on); -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c deleted file mode 100644 index fbf1b6370eb2..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "dcn20_opp.h" -#include "reg_helper.h" - -#define REG(reg) \ - (oppn20->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - oppn20->opp_shift->field_name, oppn20->opp_mask->field_name - -#define CTX \ - oppn20->base.ctx - - -void opp2_set_disp_pattern_generator( - struct output_pixel_processor *opp, - enum controller_dp_test_pattern test_pattern, - enum controller_dp_color_space color_space, - enum dc_color_depth color_depth, - const struct tg_color *solid_color, - int width, - int height, - int offset) -{ - struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); - enum test_pattern_color_format bit_depth; - enum test_pattern_dyn_range dyn_range; - enum test_pattern_mode mode; - - /* color ramp generator mixes 16-bits color */ - uint32_t src_bpc = 16; - /* requested bpc */ - uint32_t dst_bpc; - uint32_t index; - /* RGB values of the color bars. - * Produce two RGB colors: RGB0 - white (all Fs) - * and RGB1 - black (all 0s) - * (three RGB components for two colors) - */ - uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, - 0x0000, 0x0000}; - /* dest color (converted to the specified color format) */ - uint16_t dst_color[6]; - uint32_t inc_base; - - /* translate to bit depth */ - switch (color_depth) { - case COLOR_DEPTH_666: - bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; - break; - case COLOR_DEPTH_888: - bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; - break; - case COLOR_DEPTH_101010: - bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; - break; - case COLOR_DEPTH_121212: - bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; - break; - default: - bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; - break; - } - - /* set DPG dimentions */ - REG_SET_2(DPG_DIMENSIONS, 0, - DPG_ACTIVE_WIDTH, width, - DPG_ACTIVE_HEIGHT, height); - - /* set DPG offset */ - REG_SET_2(DPG_OFFSET_SEGMENT, 0, - DPG_X_OFFSET, offset, - DPG_SEGMENT_WIDTH, 0); - - switch (test_pattern) { - case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: - case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: - { - dyn_range = (test_pattern == - CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? - TEST_PATTERN_DYN_RANGE_CEA : - TEST_PATTERN_DYN_RANGE_VESA); - - switch (color_space) { - case CONTROLLER_DP_COLOR_SPACE_YCBCR601: - mode = TEST_PATTERN_MODE_COLORSQUARES_YCBCR601; - break; - case CONTROLLER_DP_COLOR_SPACE_YCBCR709: - mode = TEST_PATTERN_MODE_COLORSQUARES_YCBCR709; - break; - case CONTROLLER_DP_COLOR_SPACE_RGB: - default: - mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; - break; - } - - REG_UPDATE_6(DPG_CONTROL, - DPG_EN, 1, - DPG_MODE, mode, - DPG_DYNAMIC_RANGE, dyn_range, - DPG_BIT_DEPTH, bit_depth, - DPG_VRES, 6, - DPG_HRES, 6); - } - break; - - case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: - case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: - { - mode = (test_pattern == - CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? - TEST_PATTERN_MODE_VERTICALBARS : - TEST_PATTERN_MODE_HORIZONTALBARS); - - switch (bit_depth) { - case TEST_PATTERN_COLOR_FORMAT_BPC_6: - dst_bpc = 6; - break; - case TEST_PATTERN_COLOR_FORMAT_BPC_8: - dst_bpc = 8; - break; - case TEST_PATTERN_COLOR_FORMAT_BPC_10: - dst_bpc = 10; - break; - default: - dst_bpc = 8; - break; - } - - /* adjust color to the required colorFormat */ - for (index = 0; index < 6; index++) { - /* dst = 2^dstBpc * src / 2^srcBpc = src >> - * (srcBpc - dstBpc); - */ - dst_color[index] = - src_color[index] >> (src_bpc - dst_bpc); - /* DPG_COLOUR registers are 16-bit MSB aligned value with bits 3:0 hardwired to ZERO. - * XXXXXXXXXX000000 for 10 bit, - * XXXXXXXX00000000 for 8 bit, - * XXXXXX0000000000 for 6 bits - */ - dst_color[index] <<= (16 - dst_bpc); - } - - REG_SET_2(DPG_COLOUR_R_CR, 0, - DPG_COLOUR1_R_CR, dst_color[0], - DPG_COLOUR0_R_CR, dst_color[3]); - REG_SET_2(DPG_COLOUR_G_Y, 0, - DPG_COLOUR1_G_Y, dst_color[1], - DPG_COLOUR0_G_Y, dst_color[4]); - REG_SET_2(DPG_COLOUR_B_CB, 0, - DPG_COLOUR1_B_CB, dst_color[2], - DPG_COLOUR0_B_CB, dst_color[5]); - - /* enable test pattern */ - REG_UPDATE_6(DPG_CONTROL, - DPG_EN, 1, - DPG_MODE, mode, - DPG_DYNAMIC_RANGE, 0, - DPG_BIT_DEPTH, bit_depth, - DPG_VRES, 0, - DPG_HRES, 0); - } - break; - - case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: - { - mode = (bit_depth == - TEST_PATTERN_COLOR_FORMAT_BPC_10 ? - TEST_PATTERN_MODE_DUALRAMP_RGB : - TEST_PATTERN_MODE_SINGLERAMP_RGB); - - switch (bit_depth) { - case TEST_PATTERN_COLOR_FORMAT_BPC_6: - dst_bpc = 6; - break; - case TEST_PATTERN_COLOR_FORMAT_BPC_8: - dst_bpc = 8; - break; - case TEST_PATTERN_COLOR_FORMAT_BPC_10: - dst_bpc = 10; - break; - default: - dst_bpc = 8; - break; - } - - /* increment for the first ramp for one color gradation - * 1 gradation for 6-bit color is 2^10 - * gradations in 16-bit color - */ - inc_base = (src_bpc - dst_bpc); - - switch (bit_depth) { - case TEST_PATTERN_COLOR_FORMAT_BPC_6: - { - REG_SET_3(DPG_RAMP_CONTROL, 0, - DPG_RAMP0_OFFSET, 0, - DPG_INC0, inc_base, - DPG_INC1, 0); - REG_UPDATE_2(DPG_CONTROL, - DPG_VRES, 6, - DPG_HRES, 6); - } - break; - case TEST_PATTERN_COLOR_FORMAT_BPC_8: - { - REG_SET_3(DPG_RAMP_CONTROL, 0, - DPG_RAMP0_OFFSET, 0, - DPG_INC0, inc_base, - DPG_INC1, 0); - REG_UPDATE_2(DPG_CONTROL, - DPG_VRES, 6, - DPG_HRES, 8); - } - break; - case TEST_PATTERN_COLOR_FORMAT_BPC_10: - { - REG_SET_3(DPG_RAMP_CONTROL, 0, - DPG_RAMP0_OFFSET, 384 << 6, - DPG_INC0, inc_base, - DPG_INC1, inc_base + 2); - REG_UPDATE_2(DPG_CONTROL, - DPG_VRES, 5, - DPG_HRES, 8); - } - break; - default: - break; - } - - /* enable test pattern */ - REG_UPDATE_4(DPG_CONTROL, - DPG_EN, 1, - DPG_MODE, mode, - DPG_DYNAMIC_RANGE, 0, - DPG_BIT_DEPTH, bit_depth); - } - break; - case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: - { - REG_WRITE(DPG_CONTROL, 0); - REG_WRITE(DPG_COLOUR_R_CR, 0); - REG_WRITE(DPG_COLOUR_G_Y, 0); - REG_WRITE(DPG_COLOUR_B_CB, 0); - REG_WRITE(DPG_RAMP_CONTROL, 0); - } - break; - case CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR: - { - opp2_dpg_set_blank_color(opp, solid_color); - REG_UPDATE_2(DPG_CONTROL, - DPG_EN, 1, - DPG_MODE, TEST_PATTERN_MODE_HORIZONTALBARS); - - REG_SET_2(DPG_DIMENSIONS, 0, - DPG_ACTIVE_WIDTH, width, - DPG_ACTIVE_HEIGHT, height); - } - break; - default: - break; - - } -} - -void opp2_program_dpg_dimensions( - struct output_pixel_processor *opp, - int width, int height) -{ - struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); - - REG_SET_2(DPG_DIMENSIONS, 0, - DPG_ACTIVE_WIDTH, width, - DPG_ACTIVE_HEIGHT, height); -} - -void opp2_dpg_set_blank_color( - struct output_pixel_processor *opp, - const struct tg_color *color) -{ - struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); - - /* 16-bit MSB aligned value. Bits 3:0 of this field are hardwired to ZERO */ - ASSERT(color); - REG_SET_2(DPG_COLOUR_B_CB, 0, - DPG_COLOUR1_B_CB, color->color_b_cb << 6, - DPG_COLOUR0_B_CB, color->color_b_cb << 6); - REG_SET_2(DPG_COLOUR_G_Y, 0, - DPG_COLOUR1_G_Y, color->color_g_y << 6, - DPG_COLOUR0_G_Y, color->color_g_y << 6); - REG_SET_2(DPG_COLOUR_R_CR, 0, - DPG_COLOUR1_R_CR, color->color_r_cr << 6, - DPG_COLOUR0_R_CR, color->color_r_cr << 6); -} - -bool opp2_dpg_is_blanked(struct output_pixel_processor *opp) -{ - struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); - uint32_t dpg_en, dpg_mode; - uint32_t double_buffer_pending; - - REG_GET_2(DPG_CONTROL, - DPG_EN, &dpg_en, - DPG_MODE, &dpg_mode); - - REG_GET(DPG_STATUS, - DPG_DOUBLE_BUFFER_PENDING, &double_buffer_pending); - - return (dpg_en == 1) && - (double_buffer_pending == 0); -} - -bool opp2_dpg_is_pending(struct output_pixel_processor *opp) -{ - struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); - uint32_t double_buffer_pending; - uint32_t dpg_en; - - REG_GET(DPG_CONTROL, DPG_EN, &dpg_en); - - REG_GET(DPG_STATUS, DPG_DOUBLE_BUFFER_PENDING, &double_buffer_pending); - - return (dpg_en == 1 && double_buffer_pending == 1); -} - -void opp2_program_left_edge_extra_pixel ( - struct output_pixel_processor *opp, - bool count) -{ - struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); - - /* Specifies the number of extra left edge pixels that are supplied to - * the 422 horizontal chroma sub-sample filter. - * Note that when left edge pixel is not "0", fmt pixel encoding can be in either 420 or 422 mode - * */ - REG_UPDATE(FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, count); -} - -/*****************************************/ -/* Constructor, Destructor */ -/*****************************************/ - -static struct opp_funcs dcn20_opp_funcs = { - .opp_set_dyn_expansion = opp1_set_dyn_expansion, - .opp_program_fmt = opp1_program_fmt, - .opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction, - .opp_program_stereo = opp1_program_stereo, - .opp_pipe_clock_control = opp1_pipe_clock_control, - .opp_set_disp_pattern_generator = opp2_set_disp_pattern_generator, - .opp_program_dpg_dimensions = opp2_program_dpg_dimensions, - .dpg_is_blanked = opp2_dpg_is_blanked, - .dpg_is_pending = opp2_dpg_is_pending, - .opp_dpg_set_blank_color = opp2_dpg_set_blank_color, - .opp_destroy = opp1_destroy, - .opp_program_left_edge_extra_pixel = opp2_program_left_edge_extra_pixel, -}; - -void dcn20_opp_construct(struct dcn20_opp *oppn20, - struct dc_context *ctx, - uint32_t inst, - const struct dcn20_opp_registers *regs, - const struct dcn20_opp_shift *opp_shift, - const struct dcn20_opp_mask *opp_mask) -{ - oppn20->base.ctx = ctx; - oppn20->base.inst = inst; - oppn20->base.funcs = &dcn20_opp_funcs; - - oppn20->regs = regs; - oppn20->opp_shift = opp_shift; - oppn20->opp_mask = opp_mask; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h deleted file mode 100644 index 8f186abd558d..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h +++ /dev/null @@ -1,172 +0,0 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_OPP_DCN20_H__ -#define __DC_OPP_DCN20_H__ - -#include "dcn10/dcn10_opp.h" - -#define TO_DCN20_OPP(opp)\ - container_of(opp, struct dcn20_opp, base) - -#define OPP_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix - -#define OPP_DPG_REG_LIST(id) \ - SRI(DPG_CONTROL, DPG, id), \ - SRI(DPG_DIMENSIONS, DPG, id), \ - SRI(DPG_OFFSET_SEGMENT, DPG, id), \ - SRI(DPG_COLOUR_B_CB, DPG, id), \ - SRI(DPG_COLOUR_G_Y, DPG, id), \ - SRI(DPG_COLOUR_R_CR, DPG, id), \ - SRI(DPG_RAMP_CONTROL, DPG, id), \ - SRI(DPG_STATUS, DPG, id) - -#define OPP_REG_LIST_DCN20(id) \ - OPP_REG_LIST_DCN10(id), \ - OPP_DPG_REG_LIST(id), \ - SRI(FMT_422_CONTROL, FMT, id), \ - SRI(OPPBUF_CONTROL1, OPPBUF, id) - -#define OPP_REG_VARIABLE_LIST_DCN2_0 \ - OPP_COMMON_REG_VARIABLE_LIST; \ - uint32_t FMT_422_CONTROL; \ - uint32_t DPG_CONTROL; \ - uint32_t DPG_DIMENSIONS; \ - uint32_t DPG_OFFSET_SEGMENT; \ - uint32_t DPG_COLOUR_B_CB; \ - uint32_t DPG_COLOUR_G_Y; \ - uint32_t DPG_COLOUR_R_CR; \ - uint32_t DPG_RAMP_CONTROL; \ - uint32_t DPG_STATUS - -#define OPP_DPG_MASK_SH_LIST(mask_sh) \ - OPP_SF(DPG0_DPG_CONTROL, DPG_EN, mask_sh), \ - OPP_SF(DPG0_DPG_CONTROL, DPG_MODE, mask_sh), \ - OPP_SF(DPG0_DPG_CONTROL, DPG_DYNAMIC_RANGE, mask_sh), \ - OPP_SF(DPG0_DPG_CONTROL, DPG_BIT_DEPTH, mask_sh), \ - OPP_SF(DPG0_DPG_CONTROL, DPG_VRES, mask_sh), \ - OPP_SF(DPG0_DPG_CONTROL, DPG_HRES, mask_sh), \ - OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_WIDTH, mask_sh), \ - OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_HEIGHT, mask_sh), \ - OPP_SF(DPG0_DPG_OFFSET_SEGMENT, DPG_X_OFFSET, mask_sh), \ - OPP_SF(DPG0_DPG_OFFSET_SEGMENT, DPG_SEGMENT_WIDTH, mask_sh), \ - OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR0_R_CR, mask_sh), \ - OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR1_R_CR, mask_sh), \ - OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR0_B_CB, mask_sh), \ - OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR1_B_CB, mask_sh), \ - OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR0_G_Y, mask_sh), \ - OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR1_G_Y, mask_sh), \ - OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_RAMP0_OFFSET, mask_sh), \ - OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC0, mask_sh), \ - OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC1, mask_sh), \ - OPP_SF(DPG0_DPG_STATUS, DPG_DOUBLE_BUFFER_PENDING, mask_sh) - -#define OPP_MASK_SH_LIST_DCN20(mask_sh) \ - OPP_MASK_SH_LIST_DCN(mask_sh), \ - OPP_DPG_MASK_SH_LIST(mask_sh), \ - OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\ - OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh), \ - OPP_SF(FMT0_FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, mask_sh) - -#define OPP_DCN20_REG_FIELD_LIST(type) \ - OPP_DCN10_REG_FIELD_LIST(type); \ - type FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT; \ - type DPG_EN; \ - type DPG_MODE; \ - type DPG_DYNAMIC_RANGE; \ - type DPG_BIT_DEPTH; \ - type DPG_VRES; \ - type DPG_HRES; \ - type DPG_ACTIVE_WIDTH; \ - type DPG_ACTIVE_HEIGHT; \ - type DPG_X_OFFSET; \ - type DPG_SEGMENT_WIDTH; \ - type DPG_COLOUR0_R_CR; \ - type DPG_COLOUR1_R_CR; \ - type DPG_COLOUR0_B_CB; \ - type DPG_COLOUR1_B_CB; \ - type DPG_COLOUR0_G_Y; \ - type DPG_COLOUR1_G_Y; \ - type DPG_RAMP0_OFFSET; \ - type DPG_INC0; \ - type DPG_INC1; \ - type DPG_DOUBLE_BUFFER_PENDING - -struct dcn20_opp_registers { - OPP_REG_VARIABLE_LIST_DCN2_0; -}; - -struct dcn20_opp_shift { - OPP_DCN20_REG_FIELD_LIST(uint8_t); -}; - -struct dcn20_opp_mask { - OPP_DCN20_REG_FIELD_LIST(uint32_t); -}; - -struct dcn20_opp { - struct output_pixel_processor base; - - const struct dcn20_opp_registers *regs; - const struct dcn20_opp_shift *opp_shift; - const struct dcn20_opp_mask *opp_mask; - - bool is_write_to_ram_a_safe; -}; - -void dcn20_opp_construct(struct dcn20_opp *oppn20, - struct dc_context *ctx, - uint32_t inst, - const struct dcn20_opp_registers *regs, - const struct dcn20_opp_shift *opp_shift, - const struct dcn20_opp_mask *opp_mask); - -void opp2_set_disp_pattern_generator( - struct output_pixel_processor *opp, - enum controller_dp_test_pattern test_pattern, - enum controller_dp_color_space color_space, - enum dc_color_depth color_depth, - const struct tg_color *solid_color, - int width, - int height, - int offset); - -void opp2_program_dpg_dimensions( - struct output_pixel_processor *opp, - int width, int height); - -bool opp2_dpg_is_blanked(struct output_pixel_processor *opp); - -bool opp2_dpg_is_pending(struct output_pixel_processor *opp); - -void opp2_dpg_set_blank_color( - struct output_pixel_processor *opp, - const struct tg_color *color); - -void opp2_program_left_edge_extra_pixel ( - struct output_pixel_processor *opp, - bool count); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c deleted file mode 100644 index 0b47aeb60e79..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +++ /dev/null @@ -1,661 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include <linux/delay.h> - -#include "dc_bios_types.h" -#include "dcn20_stream_encoder.h" -#include "reg_helper.h" -#include "hw_shared.h" -#include "link.h" -#include "dpcd_defs.h" - -#define DC_LOGGER \ - enc1->base.ctx->logger - -#define REG(reg)\ - (enc1->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - enc1->se_shift->field_name, enc1->se_mask->field_name - - -#define CTX \ - enc1->base.ctx - - -static void enc2_update_hdmi_info_packet( - struct dcn10_stream_encoder *enc1, - uint32_t packet_index, - const struct dc_info_packet *info_packet) -{ - uint32_t cont, send, line; - - if (info_packet->valid) { - enc1_update_generic_info_packet( - enc1, - packet_index, - info_packet); - - /* enable transmission of packet(s) - - * packet transmission begins on the next frame */ - cont = 1; - /* send packet(s) every frame */ - send = 1; - /* select line number to send packets on */ - line = 2; - } else { - cont = 0; - send = 0; - line = 0; - } - - /* DP_SEC_GSP[x]_LINE_REFERENCE - keep default value REFER_TO_DP_SOF */ - - /* choose which generic packet control to use */ - switch (packet_index) { - case 0: - REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, - HDMI_GENERIC0_CONT, cont, - HDMI_GENERIC0_SEND, send); - REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, - HDMI_GENERIC0_LINE, line); - break; - case 1: - REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, - HDMI_GENERIC1_CONT, cont, - HDMI_GENERIC1_SEND, send); - REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, - HDMI_GENERIC1_LINE, line); - break; - case 2: - REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, - HDMI_GENERIC2_CONT, cont, - HDMI_GENERIC2_SEND, send); - REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, - HDMI_GENERIC2_LINE, line); - break; - case 3: - REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, - HDMI_GENERIC3_CONT, cont, - HDMI_GENERIC3_SEND, send); - REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, - HDMI_GENERIC3_LINE, line); - break; - case 4: - REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, - HDMI_GENERIC4_CONT, cont, - HDMI_GENERIC4_SEND, send); - REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, - HDMI_GENERIC4_LINE, line); - break; - case 5: - REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, - HDMI_GENERIC5_CONT, cont, - HDMI_GENERIC5_SEND, send); - REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, - HDMI_GENERIC5_LINE, line); - break; - case 6: - REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, - HDMI_GENERIC6_CONT, cont, - HDMI_GENERIC6_SEND, send); - REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, - HDMI_GENERIC6_LINE, line); - break; - case 7: - REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, - HDMI_GENERIC7_CONT, cont, - HDMI_GENERIC7_SEND, send); - REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, - HDMI_GENERIC7_LINE, line); - break; - default: - /* invalid HW packet index */ - DC_LOG_WARNING( - "Invalid HW packet index: %s()\n", - __func__); - return; - } -} - -static void enc2_stream_encoder_update_hdmi_info_packets( - struct stream_encoder *enc, - const struct encoder_info_frame *info_frame) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - /* for bring up, disable dp double TODO */ - REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); - - /*Always add mandatory packets first followed by optional ones*/ - enc2_update_hdmi_info_packet(enc1, 0, &info_frame->avi); - enc2_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif); - enc2_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); - enc2_update_hdmi_info_packet(enc1, 3, &info_frame->vendor); - enc2_update_hdmi_info_packet(enc1, 4, &info_frame->spd); - enc2_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd); - enc2_update_hdmi_info_packet(enc1, 6, &info_frame->vtem); -} - -static void enc2_stream_encoder_stop_hdmi_info_packets( - struct stream_encoder *enc) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - /* stop generic packets 0,1 on HDMI */ - REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, - HDMI_GENERIC0_CONT, 0, - HDMI_GENERIC0_SEND, 0, - HDMI_GENERIC1_CONT, 0, - HDMI_GENERIC1_SEND, 0); - REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, - HDMI_GENERIC0_LINE, 0, - HDMI_GENERIC1_LINE, 0); - - /* stop generic packets 2,3 on HDMI */ - REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, - HDMI_GENERIC2_CONT, 0, - HDMI_GENERIC2_SEND, 0, - HDMI_GENERIC3_CONT, 0, - HDMI_GENERIC3_SEND, 0); - REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, - HDMI_GENERIC2_LINE, 0, - HDMI_GENERIC3_LINE, 0); - - /* stop generic packets 4,5 on HDMI */ - REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, - HDMI_GENERIC4_CONT, 0, - HDMI_GENERIC4_SEND, 0, - HDMI_GENERIC5_CONT, 0, - HDMI_GENERIC5_SEND, 0); - REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, - HDMI_GENERIC4_LINE, 0, - HDMI_GENERIC5_LINE, 0); - - /* stop generic packets 6,7 on HDMI */ - REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, - HDMI_GENERIC6_CONT, 0, - HDMI_GENERIC6_SEND, 0, - HDMI_GENERIC7_CONT, 0, - HDMI_GENERIC7_SEND, 0); - REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, - HDMI_GENERIC6_LINE, 0, - HDMI_GENERIC7_LINE, 0); -} - - -/* Update GSP7 SDP 128 byte long */ -static void enc2_update_gsp7_128_info_packet( - struct dcn10_stream_encoder *enc1, - const struct dc_info_packet_128 *info_packet, - bool immediate_update) -{ - uint32_t i; - - /* TODOFPGA Figure out a proper number for max_retries polling for lock - * use 50 for now. - */ - uint32_t max_retries = 50; - const uint32_t *content = (const uint32_t *) &info_packet->sb[0]; - - ASSERT(info_packet->hb1 == DC_DP_INFOFRAME_TYPE_PPS); - - /* Configure for PPS packet size (128 bytes) */ - REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1); - - /* We need turn on clock before programming AFMT block*/ - REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); - - /* Poll dig_update_lock is not locked -> asic internal signal - * assumes otg master lock will unlock it - */ - /*REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 0, 10, max_retries);*/ - - /* Wait for HW/SW GSP memory access conflict to go away */ - REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, - 0, 10, max_retries); - - /* Clear HW/SW memory access conflict flag */ - REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); - - /* write generic packet header */ - REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, 7); - REG_SET_4(AFMT_GENERIC_HDR, 0, - AFMT_GENERIC_HB0, info_packet->hb0, - AFMT_GENERIC_HB1, info_packet->hb1, - AFMT_GENERIC_HB2, info_packet->hb2, - AFMT_GENERIC_HB3, info_packet->hb3); - - /* Write generic packet content 128 bytes long. Four sets are used (indexes 7 - * through 10) to fit 128 bytes. - */ - for (i = 0; i < 4; i++) { - uint32_t packet_index = 7 + i; - REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, packet_index); - - REG_WRITE(AFMT_GENERIC_0, *content++); - REG_WRITE(AFMT_GENERIC_1, *content++); - REG_WRITE(AFMT_GENERIC_2, *content++); - REG_WRITE(AFMT_GENERIC_3, *content++); - REG_WRITE(AFMT_GENERIC_4, *content++); - REG_WRITE(AFMT_GENERIC_5, *content++); - REG_WRITE(AFMT_GENERIC_6, *content++); - REG_WRITE(AFMT_GENERIC_7, *content++); - } - - REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL1, - AFMT_GENERIC7_FRAME_UPDATE, !immediate_update, - AFMT_GENERIC7_IMMEDIATE_UPDATE, immediate_update); -} - -/* Set DSC-related configuration. - * dsc_mode: 0 disables DSC, other values enable DSC in specified format - * sc_bytes_per_pixel: Bytes per pixel in u3.28 format - * dsc_slice_width: Slice width in pixels - */ -static void enc2_dp_set_dsc_config(struct stream_encoder *enc, - enum optc_dsc_mode dsc_mode, - uint32_t dsc_bytes_per_pixel, - uint32_t dsc_slice_width) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - REG_UPDATE_2(DP_DSC_CNTL, - DP_DSC_MODE, dsc_mode, - DP_DSC_SLICE_WIDTH, dsc_slice_width); - - REG_SET(DP_DSC_BYTES_PER_PIXEL, 0, - DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel); -} - - -static void enc2_dp_set_dsc_pps_info_packet(struct stream_encoder *enc, - bool enable, - uint8_t *dsc_packed_pps, - bool immediate_update) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - if (enable) { - struct dc_info_packet_128 pps_sdp; - - ASSERT(dsc_packed_pps); - - /* Load PPS into infoframe (SDP) registers */ - pps_sdp.valid = true; - pps_sdp.hb0 = 0; - pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS; - pps_sdp.hb2 = 127; - pps_sdp.hb3 = 0; - memcpy(&pps_sdp.sb[0], dsc_packed_pps, sizeof(pps_sdp.sb)); - enc2_update_gsp7_128_info_packet(enc1, &pps_sdp, immediate_update); - - /* Enable Generic Stream Packet 7 (GSP) transmission */ - //REG_UPDATE(DP_SEC_CNTL, - // DP_SEC_GSP7_ENABLE, 1); - - /* SW should make sure VBID[6] update line number is bigger - * than PPS transmit line number - */ - REG_UPDATE(DP_SEC_CNTL6, - DP_SEC_GSP7_LINE_NUM, 2); - REG_UPDATE_2(DP_MSA_VBID_MISC, - DP_VBID6_LINE_REFERENCE, 0, - DP_VBID6_LINE_NUM, 3); - - /* Send PPS data at the line number specified above. - * DP spec requires PPS to be sent only when it changes, however since - * decoder has to be able to handle its change on every frame, we're - * sending it always (i.e. on every frame) to reduce the chance it'd be - * missed by decoder. If it turns out required to send PPS only when it - * changes, we can use DP_SEC_GSP7_SEND register. - */ - REG_UPDATE_2(DP_SEC_CNTL, - DP_SEC_GSP7_ENABLE, 1, - DP_SEC_STREAM_ENABLE, 1); - } else { - /* Disable Generic Stream Packet 7 (GSP) transmission */ - REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, 0); - REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 0); - } -} - - -/* this function read dsc related register fields to be logged later in dcn10_log_hw_state - * into a dcn_dsc_state struct. - */ -static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - //if dsc is enabled, continue to read - REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); - if (s->dsc_mode) { - REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); - REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num); - - REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); - REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); - - REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable); - REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); - } -} - -/* Set Dynamic Metadata-configuration. - * enable_dme: TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME - * hubp_requestor_id: HUBP physical instance that is the source of dynamic metadata - * only needs to be set when enable_dme is TRUE - * dmdata_mode: dynamic metadata packet type: DP, HDMI, or Dolby Vision - * - * Ensure the OTG master update lock is set when changing DME configuration. - */ -void enc2_set_dynamic_metadata(struct stream_encoder *enc, - bool enable_dme, - uint32_t hubp_requestor_id, - enum dynamic_metadata_mode dmdata_mode) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - if (enable_dme) { - REG_UPDATE_2(DME_CONTROL, - METADATA_HUBP_REQUESTOR_ID, hubp_requestor_id, - METADATA_STREAM_TYPE, (dmdata_mode == dmdata_dolby_vision) ? 1 : 0); - - /* Use default line reference DP_SOF for bringup. - * Should use OTG_SOF for DRR cases - */ - if (dmdata_mode == dmdata_dp) - REG_UPDATE_3(DP_SEC_METADATA_TRANSMISSION, - DP_SEC_METADATA_PACKET_ENABLE, 1, - DP_SEC_METADATA_PACKET_LINE_REFERENCE, 0, - DP_SEC_METADATA_PACKET_LINE, 20); - else { - REG_UPDATE_3(HDMI_METADATA_PACKET_CONTROL, - HDMI_METADATA_PACKET_ENABLE, 1, - HDMI_METADATA_PACKET_LINE_REFERENCE, 0, - HDMI_METADATA_PACKET_LINE, 2); - - if (dmdata_mode == dmdata_dolby_vision) - REG_UPDATE(DIG_FE_CNTL, - DOLBY_VISION_EN, 1); - } - - REG_UPDATE(DME_CONTROL, - METADATA_ENGINE_EN, 1); - } else { - REG_UPDATE(DME_CONTROL, - METADATA_ENGINE_EN, 0); - - if (dmdata_mode == dmdata_dp) - REG_UPDATE(DP_SEC_METADATA_TRANSMISSION, - DP_SEC_METADATA_PACKET_ENABLE, 0); - else { - REG_UPDATE(HDMI_METADATA_PACKET_CONTROL, - HDMI_METADATA_PACKET_ENABLE, 0); - REG_UPDATE(DIG_FE_CNTL, - DOLBY_VISION_EN, 0); - } - } -} - -static void enc2_stream_encoder_update_dp_info_packets_sdp_line_num( - struct stream_encoder *enc, - struct encoder_info_frame *info_frame) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - if (info_frame->adaptive_sync.valid == true && - info_frame->sdp_line_num.adaptive_sync_line_num_valid == true) { - //00: REFER_TO_DP_SOF, 01: REFER_TO_OTG_SOF - REG_UPDATE(DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, 1); - - REG_UPDATE(DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, - info_frame->sdp_line_num.adaptive_sync_line_num); - } -} - -static void enc2_stream_encoder_update_dp_info_packets( - struct stream_encoder *enc, - const struct encoder_info_frame *info_frame) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t dmdata_packet_enabled = 0; - - enc1_stream_encoder_update_dp_info_packets(enc, info_frame); - - /* check if dynamic metadata packet transmission is enabled */ - REG_GET(DP_SEC_METADATA_TRANSMISSION, - DP_SEC_METADATA_PACKET_ENABLE, &dmdata_packet_enabled); - - if (dmdata_packet_enabled) - REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); -} - -static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) -{ - bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; - - two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 - && !timing->dsc_cfg.ycbcr422_simple); - return two_pix; -} - -void enc2_stream_encoder_dp_unblank( - struct dc_link *link, - struct stream_encoder *enc, - const struct encoder_unblank_param *param) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { - uint32_t n_vid = 0x8000; - uint32_t m_vid; - uint32_t n_multiply = 0; - uint64_t m_vid_l = n_vid; - - /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ - if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) { - /*this logic should be the same in get_pixel_clock_parameters() */ - n_multiply = 1; - } - /* M / N = Fstream / Flink - * m_vid / n_vid = pixel rate / link rate - */ - - m_vid_l *= param->timing.pix_clk_100hz / 10; - m_vid_l = div_u64(m_vid_l, - param->link_settings.link_rate - * LINK_RATE_REF_FREQ_IN_KHZ); - - m_vid = (uint32_t) m_vid_l; - - /* enable auto measurement */ - - REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); - - /* auto measurement need 1 full 0x8000 symbol cycle to kick in, - * therefore program initial value for Mvid and Nvid - */ - - REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); - - REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); - - REG_UPDATE_2(DP_VID_TIMING, - DP_VID_M_N_GEN_EN, 1, - DP_VID_N_MUL, n_multiply); - } - - /* make sure stream is disabled before resetting steer fifo */ - REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); - REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); - - /* set DIG_START to 0x1 to reset FIFO */ - REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); - udelay(1); - - /* write 0 to take the FIFO out of reset */ - - REG_UPDATE(DIG_FE_CNTL, DIG_START, 0); - - /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen - * that it overflows during mode transition, and sometimes doesn't recover. - */ - REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); - udelay(10); - - REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); - - /* wait 100us for DIG/DP logic to prime - * (i.e. a few video lines) - */ - udelay(100); - - /* the hardware would start sending video at the start of the next DP - * frame (i.e. rising edge of the vblank). - * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this - * register has no effect on enable transition! HW always guarantees - * VID_STREAM enable at start of next frame, and this is not - * programmable - */ - - REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); - - link->dc->link_srv->dp_trace_source_sequence(link, - DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); -} - -static void enc2_dp_set_odm_combine( - struct stream_encoder *enc, - bool odm_combine) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine); -} - -void enc2_stream_encoder_dp_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing, - enum dc_color_space output_color_space, - bool use_vsc_sdp_for_colorimetry, - uint32_t enable_sdp_splitting) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - enc1_stream_encoder_dp_set_stream_attribute(enc, - crtc_timing, - output_color_space, - use_vsc_sdp_for_colorimetry, - enable_sdp_splitting); - - REG_UPDATE(DP_SEC_FRAMING4, - DP_SST_SDP_SPLITTING, enable_sdp_splitting); -} - -uint32_t enc2_get_fifo_cal_average_level( - struct stream_encoder *enc) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t fifo_level; - - REG_GET(DIG_FIFO_STATUS, - DIG_FIFO_CAL_AVERAGE_LEVEL, &fifo_level); - return fifo_level; -} - -static const struct stream_encoder_funcs dcn20_str_enc_funcs = { - .dp_set_odm_combine = - enc2_dp_set_odm_combine, - .dp_set_stream_attribute = - enc2_stream_encoder_dp_set_stream_attribute, - .hdmi_set_stream_attribute = - enc1_stream_encoder_hdmi_set_stream_attribute, - .dvi_set_stream_attribute = - enc1_stream_encoder_dvi_set_stream_attribute, - .set_throttled_vcp_size = - enc1_stream_encoder_set_throttled_vcp_size, - .update_hdmi_info_packets = - enc2_stream_encoder_update_hdmi_info_packets, - .stop_hdmi_info_packets = - enc2_stream_encoder_stop_hdmi_info_packets, - .update_dp_info_packets_sdp_line_num = - enc2_stream_encoder_update_dp_info_packets_sdp_line_num, - .update_dp_info_packets = - enc2_stream_encoder_update_dp_info_packets, - .send_immediate_sdp_message = - enc1_stream_encoder_send_immediate_sdp_message, - .stop_dp_info_packets = - enc1_stream_encoder_stop_dp_info_packets, - .dp_blank = - enc1_stream_encoder_dp_blank, - .dp_unblank = - enc2_stream_encoder_dp_unblank, - .audio_mute_control = enc1_se_audio_mute_control, - - .dp_audio_setup = enc1_se_dp_audio_setup, - .dp_audio_enable = enc1_se_dp_audio_enable, - .dp_audio_disable = enc1_se_dp_audio_disable, - - .hdmi_audio_setup = enc1_se_hdmi_audio_setup, - .hdmi_audio_disable = enc1_se_hdmi_audio_disable, - .setup_stereo_sync = enc1_setup_stereo_sync, - .set_avmute = enc1_stream_encoder_set_avmute, - .dig_connect_to_otg = enc1_dig_connect_to_otg, - .dig_source_otg = enc1_dig_source_otg, - - .dp_get_pixel_format = - enc1_stream_encoder_dp_get_pixel_format, - - .enc_read_state = enc2_read_state, - .dp_set_dsc_config = enc2_dp_set_dsc_config, - .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet, - .set_dynamic_metadata = enc2_set_dynamic_metadata, - .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, - .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level, -}; - -void dcn20_stream_encoder_construct( - struct dcn10_stream_encoder *enc1, - struct dc_context *ctx, - struct dc_bios *bp, - enum engine_id eng_id, - const struct dcn10_stream_enc_registers *regs, - const struct dcn10_stream_encoder_shift *se_shift, - const struct dcn10_stream_encoder_mask *se_mask) -{ - enc1->base.funcs = &dcn20_str_enc_funcs; - enc1->base.ctx = ctx; - enc1->base.id = eng_id; - enc1->base.bp = bp; - enc1->regs = regs; - enc1->se_shift = se_shift; - enc1->se_mask = se_mask; - enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h deleted file mode 100644 index baa1e539f341..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_STREAM_ENCODER_DCN20_H__ -#define __DC_STREAM_ENCODER_DCN20_H__ - -#include "stream_encoder.h" -#include "dcn10/dcn10_stream_encoder.h" - - -#define SE_DCN2_REG_LIST(id)\ - SE_COMMON_DCN_REG_LIST(id),\ - SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \ - SRI(DP_DSC_CNTL, DP, id), \ - SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \ - SRI(DME_CONTROL, DIG, id),\ - SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ - SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ - SRI(DP_SEC_FRAMING4, DP, id) - -#define SE_COMMON_MASK_SH_LIST_DCN20(mask_sh)\ - SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\ - SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\ - SE_SF(DP0_DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, mask_sh),\ - SE_SF(DP0_DP_DSC_BYTES_PER_PIXEL, DP_DSC_BYTES_PER_PIXEL, mask_sh),\ - SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\ - SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\ - SE_SF(DIG0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\ - SE_SF(DIG0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\ - SE_SF(DIG0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\ - SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ - SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\ - SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ - SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\ - SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\ - SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\ - SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh) - -void dcn20_stream_encoder_construct( - struct dcn10_stream_encoder *enc1, - struct dc_context *ctx, - struct dc_bios *bp, - enum engine_id eng_id, - const struct dcn10_stream_enc_registers *regs, - const struct dcn10_stream_encoder_shift *se_shift, - const struct dcn10_stream_encoder_mask *se_mask); - -void enc2_stream_encoder_dp_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing, - enum dc_color_space output_color_space, - bool use_vsc_sdp_for_colorimetry, - uint32_t enable_sdp_splitting); - -void enc2_stream_encoder_dp_unblank( - struct dc_link *link, - struct stream_encoder *enc, - const struct encoder_unblank_param *param); - -void enc2_set_dynamic_metadata(struct stream_encoder *enc, - bool enable_dme, - uint32_t hubp_requestor_id, - enum dynamic_metadata_mode dmdata_mode); - -uint32_t enc2_get_fifo_cal_average_level( - struct stream_encoder *enc); - -#endif /* __DC_STREAM_ENCODER_DCN20_H__ */ |