diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn21')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c | 132 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.h | 36 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 723 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h | 158 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 860 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h | 134 |
7 files changed, 2 insertions, 2047 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile index ca92f5c8e7fb..c215f3cc6e44 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile @@ -1,9 +1,7 @@ # SPDX-License-Identifier: MIT -# -# Makefile for DCN21. +# Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved. -DCN21 = dcn21_hubp.o dcn21_hubbub.o \ - dcn21_link_encoder.o dcn21_dccg.o +DCN21 = dcn21_link_encoder.o AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c deleted file mode 100644 index d07c04458d31..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "reg_helper.h" -#include "core_types.h" -#include "dcn20/dcn20_dccg.h" -#include "dcn21_dccg.h" - -#define TO_DCN_DCCG(dccg)\ - container_of(dccg, struct dcn_dccg, base) - -#define REG(reg) \ - (dccg_dcn->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name - -#define CTX \ - dccg_dcn->base.ctx -#define DC_LOGGER \ - dccg->ctx->logger - -static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - if (dccg->ref_dppclk) { - int ref_dppclk = dccg->ref_dppclk; - int modulo = ref_dppclk / 10000; - int phase; - - if (req_dppclk) { - /* - * program DPP DTO phase and modulo as below - * phase = ceiling(dpp_pipe_clk_mhz / 10) - * module = trunc(dpp_global_clk_mhz / 10) - * - * storing frequencies in registers allow dmcub fw - * to run time lower clocks when possible for power saving - * - * ceiling phase and truncate modulo guarentees the divided - * down per pipe dpp clock has high enough frequency - */ - phase = (req_dppclk + 9999) / 10000; - - if (phase > modulo) { - /* phase > modulo result in screen corruption - * ie phase = 30, mod = 29 for 4k@60 HDMI - * in these case we don't want pipe clock to be divided - */ - phase = modulo; - } - } else { - /* - * set phase to 10 if dpp isn't used to - * prevent hard hang if access dpp register - * on unused pipe - * - * DTO should be on to divide down un-used - * pipe clock for power saving - */ - phase = 10; - } - - REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, - DPPCLK0_DTO_PHASE, phase, - DPPCLK0_DTO_MODULO, modulo); - - REG_UPDATE(DPPCLK_DTO_CTRL, - DPPCLK_DTO_ENABLE[dpp_inst], 1); - } - - dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; -} - - -static const struct dccg_funcs dccg21_funcs = { - .update_dpp_dto = dccg21_update_dpp_dto, - .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, - .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, - .otg_add_pixel = dccg2_otg_add_pixel, - .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init -}; - -struct dccg *dccg21_create( - struct dc_context *ctx, - const struct dccg_registers *regs, - const struct dccg_shift *dccg_shift, - const struct dccg_mask *dccg_mask) -{ - struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); - struct dccg *base; - - if (dccg_dcn == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - base = &dccg_dcn->base; - base->ctx = ctx; - base->funcs = &dccg21_funcs; - - dccg_dcn->regs = regs; - dccg_dcn->dccg_shift = dccg_shift; - dccg_dcn->dccg_mask = dccg_mask; - - return &dccg_dcn->base; -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.h deleted file mode 100644 index b7efa777ec73..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DCN21_DCCG_H__ -#define __DCN21_DCCG_H__ - -struct dccg *dccg21_create( - struct dc_context *ctx, - const struct dccg_registers *regs, - const struct dccg_shift *dccg_shift, - const struct dccg_mask *dccg_mask); - - -#endif /* __DCN21_DCCG_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c deleted file mode 100644 index aeb0e0d9b70a..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c +++ /dev/null @@ -1,723 +0,0 @@ -/* -* Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ -#include <linux/delay.h> -#include "dm_services.h" -#include "dcn20/dcn20_hubbub.h" -#include "dcn21_hubbub.h" -#include "reg_helper.h" - -#define REG(reg)\ - hubbub1->regs->reg -#define DC_LOGGER \ - hubbub1->base.ctx->logger -#define CTX \ - hubbub1->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - hubbub1->shifts->field_name, hubbub1->masks->field_name - -#define REG(reg)\ - hubbub1->regs->reg - -#define CTX \ - hubbub1->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - hubbub1->shifts->field_name, hubbub1->masks->field_name - -static uint32_t convert_and_clamp( - uint32_t wm_ns, - uint32_t refclk_mhz, - uint32_t clamp_value) -{ - uint32_t ret_val = 0; - ret_val = wm_ns * refclk_mhz; - ret_val /= 1000; - - if (ret_val > clamp_value) - ret_val = clamp_value; - - return ret_val; -} - -void dcn21_dchvm_init(struct hubbub *hubbub) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - uint32_t riommu_active; - int i; - - //Init DCHVM block - REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1); - - //Poll until RIOMMU_ACTIVE = 1 - for (i = 0; i < 100; i++) { - REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &riommu_active); - - if (riommu_active) - break; - else - udelay(5); - } - - if (riommu_active) { - //Reflect the power status of DCHUBBUB - REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1); - - //Start rIOMMU prefetching - REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1); - - // Enable dynamic clock gating - REG_UPDATE_4(DCHVM_CLK_CTRL, - HVM_DISPCLK_R_GATE_DIS, 0, - HVM_DISPCLK_G_GATE_DIS, 0, - HVM_DCFCLK_R_GATE_DIS, 0, - HVM_DCFCLK_G_GATE_DIS, 0); - - //Poll until HOSTVM_PREFETCH_DONE = 1 - REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100); - - hubbub->riommu_active = true; - } -} - -int hubbub21_init_dchub(struct hubbub *hubbub, - struct dcn_hubbub_phys_addr_config *pa_config) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - struct dcn_vmid_page_table_config phys_config; - - REG_SET(DCN_VM_FB_LOCATION_BASE, 0, - FB_BASE, pa_config->system_aperture.fb_base >> 24); - REG_SET(DCN_VM_FB_LOCATION_TOP, 0, - FB_TOP, pa_config->system_aperture.fb_top >> 24); - REG_SET(DCN_VM_FB_OFFSET, 0, - FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); - REG_SET(DCN_VM_AGP_BOT, 0, - AGP_BOT, pa_config->system_aperture.agp_bot >> 24); - REG_SET(DCN_VM_AGP_TOP, 0, - AGP_TOP, pa_config->system_aperture.agp_top >> 24); - REG_SET(DCN_VM_AGP_BASE, 0, - AGP_BASE, pa_config->system_aperture.agp_base >> 24); - - if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { - phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; - phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12; - phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr | 1; //Note: hack - phys_config.depth = 0; - phys_config.block_size = 0; - // Init VMID 0 based on PA config - dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config); - } - - dcn21_dchvm_init(hubbub); - - return hubbub1->num_vmid; -} - -bool hubbub21_program_urgent_watermarks( - struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - uint32_t prog_wm_value; - bool wm_pending = false; - - /* Repeat for water mark set A, B, C and D. */ - /* clock state A */ - if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) { - hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value); - - DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.urgent_ns, prog_wm_value); - } else if (watermarks->a.urgent_ns < hubbub1->watermarks.a.urgent_ns) - wm_pending = true; - - /* determine the transfer time for a quantity of data for a particular requestor.*/ - if (safe_to_lower || watermarks->a.frac_urg_bw_flip - > hubbub1->watermarks.a.frac_urg_bw_flip) { - hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; - - REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, - DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip); - } else if (watermarks->a.frac_urg_bw_flip - < hubbub1->watermarks.a.frac_urg_bw_flip) - wm_pending = true; - - if (safe_to_lower || watermarks->a.frac_urg_bw_nom - > hubbub1->watermarks.a.frac_urg_bw_nom) { - hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; - - REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, - DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom); - } else if (watermarks->a.frac_urg_bw_nom - < hubbub1->watermarks.a.frac_urg_bw_nom) - wm_pending = true; - - if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub1->watermarks.a.urgent_latency_ns) { - hubbub1->watermarks.a.urgent_latency_ns = watermarks->a.urgent_latency_ns; - prog_wm_value = convert_and_clamp(watermarks->a.urgent_latency_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0, - DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, prog_wm_value); - } else if (watermarks->a.urgent_latency_ns < hubbub1->watermarks.a.urgent_latency_ns) - wm_pending = true; - - /* clock state B */ - if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) { - hubbub1->watermarks.b.urgent_ns = watermarks->b.urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, prog_wm_value); - - DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.urgent_ns, prog_wm_value); - } else if (watermarks->b.urgent_ns < hubbub1->watermarks.b.urgent_ns) - wm_pending = true; - - /* determine the transfer time for a quantity of data for a particular requestor.*/ - if (safe_to_lower || watermarks->a.frac_urg_bw_flip - > hubbub1->watermarks.a.frac_urg_bw_flip) { - hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; - - REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, - DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->a.frac_urg_bw_flip); - } else if (watermarks->a.frac_urg_bw_flip - < hubbub1->watermarks.a.frac_urg_bw_flip) - wm_pending = true; - - if (safe_to_lower || watermarks->a.frac_urg_bw_nom - > hubbub1->watermarks.a.frac_urg_bw_nom) { - hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; - - REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, - DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->a.frac_urg_bw_nom); - } else if (watermarks->a.frac_urg_bw_nom - < hubbub1->watermarks.a.frac_urg_bw_nom) - wm_pending = true; - - if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub1->watermarks.b.urgent_latency_ns) { - hubbub1->watermarks.b.urgent_latency_ns = watermarks->b.urgent_latency_ns; - prog_wm_value = convert_and_clamp(watermarks->b.urgent_latency_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0, - DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, prog_wm_value); - } else if (watermarks->b.urgent_latency_ns < hubbub1->watermarks.b.urgent_latency_ns) - wm_pending = true; - - /* clock state C */ - if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) { - hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, prog_wm_value); - - DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.urgent_ns, prog_wm_value); - } else if (watermarks->c.urgent_ns < hubbub1->watermarks.c.urgent_ns) - wm_pending = true; - - /* determine the transfer time for a quantity of data for a particular requestor.*/ - if (safe_to_lower || watermarks->a.frac_urg_bw_flip - > hubbub1->watermarks.a.frac_urg_bw_flip) { - hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; - - REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0, - DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->a.frac_urg_bw_flip); - } else if (watermarks->a.frac_urg_bw_flip - < hubbub1->watermarks.a.frac_urg_bw_flip) - wm_pending = true; - - if (safe_to_lower || watermarks->a.frac_urg_bw_nom - > hubbub1->watermarks.a.frac_urg_bw_nom) { - hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; - - REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, - DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->a.frac_urg_bw_nom); - } else if (watermarks->a.frac_urg_bw_nom - < hubbub1->watermarks.a.frac_urg_bw_nom) - wm_pending = true; - - if (safe_to_lower || watermarks->c.urgent_latency_ns > hubbub1->watermarks.c.urgent_latency_ns) { - hubbub1->watermarks.c.urgent_latency_ns = watermarks->c.urgent_latency_ns; - prog_wm_value = convert_and_clamp(watermarks->c.urgent_latency_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0, - DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, prog_wm_value); - } else if (watermarks->c.urgent_latency_ns < hubbub1->watermarks.c.urgent_latency_ns) - wm_pending = true; - - /* clock state D */ - if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) { - hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns; - prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, prog_wm_value); - - DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.urgent_ns, prog_wm_value); - } else if (watermarks->d.urgent_ns < hubbub1->watermarks.d.urgent_ns) - wm_pending = true; - - /* determine the transfer time for a quantity of data for a particular requestor.*/ - if (safe_to_lower || watermarks->a.frac_urg_bw_flip - > hubbub1->watermarks.a.frac_urg_bw_flip) { - hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; - - REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0, - DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->a.frac_urg_bw_flip); - } else if (watermarks->a.frac_urg_bw_flip - < hubbub1->watermarks.a.frac_urg_bw_flip) - wm_pending = true; - - if (safe_to_lower || watermarks->a.frac_urg_bw_nom - > hubbub1->watermarks.a.frac_urg_bw_nom) { - hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom; - - REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0, - DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->a.frac_urg_bw_nom); - } else if (watermarks->a.frac_urg_bw_nom - < hubbub1->watermarks.a.frac_urg_bw_nom) - wm_pending = true; - - if (safe_to_lower || watermarks->d.urgent_latency_ns > hubbub1->watermarks.d.urgent_latency_ns) { - hubbub1->watermarks.d.urgent_latency_ns = watermarks->d.urgent_latency_ns; - prog_wm_value = convert_and_clamp(watermarks->d.urgent_latency_ns, - refclk_mhz, 0x1fffff); - REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0, - DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, prog_wm_value); - } else if (watermarks->d.urgent_latency_ns < hubbub1->watermarks.d.urgent_latency_ns) - wm_pending = true; - - return wm_pending; -} - -bool hubbub21_program_stutter_watermarks( - struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - uint32_t prog_wm_value; - bool wm_pending = false; - - /* clock state A */ - if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns - > hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) { - hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - } else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns - < hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns - > hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) { - hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns = - watermarks->a.cstate_pstate.cstate_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); - } else if (watermarks->a.cstate_pstate.cstate_exit_ns - < hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) - wm_pending = true; - - /* clock state B */ - if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns - > hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) { - hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - } else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns - < hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns - > hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) { - hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns = - watermarks->b.cstate_pstate.cstate_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); - } else if (watermarks->b.cstate_pstate.cstate_exit_ns - < hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) - wm_pending = true; - - /* clock state C */ - if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns - > hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) { - hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - } else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns - < hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns - > hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) { - hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns = - watermarks->c.cstate_pstate.cstate_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); - } else if (watermarks->c.cstate_pstate.cstate_exit_ns - < hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) - wm_pending = true; - - /* clock state D */ - if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns - > hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) { - hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - } else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns - < hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns - > hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) { - hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns = - watermarks->d.cstate_pstate.cstate_exit_ns; - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); - } else if (watermarks->d.cstate_pstate.cstate_exit_ns - < hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) - wm_pending = true; - - return wm_pending; -} - -bool hubbub21_program_pstate_watermarks( - struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - uint32_t prog_wm_value; - - bool wm_pending = false; - - /* clock state A */ - if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns - > hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) { - hubbub1->watermarks.a.cstate_pstate.pstate_change_ns = - watermarks->a.cstate_pstate.pstate_change_ns; - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); - } else if (watermarks->a.cstate_pstate.pstate_change_ns - < hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) - wm_pending = true; - - /* clock state B */ - if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns - > hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) { - hubbub1->watermarks.b.cstate_pstate.pstate_change_ns = - watermarks->b.cstate_pstate.pstate_change_ns; - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); - } else if (watermarks->b.cstate_pstate.pstate_change_ns - < hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) - wm_pending = false; - - /* clock state C */ - if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns - > hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) { - hubbub1->watermarks.c.cstate_pstate.pstate_change_ns = - watermarks->c.cstate_pstate.pstate_change_ns; - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); - } else if (watermarks->c.cstate_pstate.pstate_change_ns - < hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) - wm_pending = true; - - /* clock state D */ - if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns - > hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) { - hubbub1->watermarks.d.cstate_pstate.pstate_change_ns = - watermarks->d.cstate_pstate.pstate_change_ns; - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value, - DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); - } else if (watermarks->d.cstate_pstate.pstate_change_ns - < hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) - wm_pending = true; - - return wm_pending; -} - -bool hubbub21_program_watermarks( - struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - bool wm_pending = false; - - if (hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - if (hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - if (hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - /* - * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric. - * If the memory controller is fully utilized and the DCHub requestors are - * well ahead of their amortized schedule, then it is safe to prevent the next winner - * from being committed and sent to the fabric. - * The utilization of the memory controller is approximated by ensuring that - * the number of outstanding requests is greater than a threshold specified - * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule, - * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles. - * - * TODO: Revisit request limit after figure out right number. request limit for Renoir isn't decided yet, set maximum value (0x1FF) - * to turn off it for now. - */ - REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, - DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); - REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND, - DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF, - DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA); - REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, - DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF); - - hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); - - return wm_pending; -} - -void hubbub21_wm_read_state(struct hubbub *hubbub, - struct dcn_hubbub_wm *wm) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - struct dcn_hubbub_wm_set *s; - - memset(wm, 0, sizeof(struct dcn_hubbub_wm)); - - s = &wm->sets[0]; - s->wm_set = 0; - REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &s->data_urgent); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit); - - REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_change); - - s = &wm->sets[1]; - s->wm_set = 1; - REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &s->data_urgent); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit); - - REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_change); - - s = &wm->sets[2]; - s->wm_set = 2; - REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, &s->data_urgent); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit); - - REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_change); - - s = &wm->sets[3]; - s->wm_set = 3; - REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, &s->data_urgent); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit); - - REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, - DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_change); -} - -static void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - uint32_t prog_wm_value; - - prog_wm_value = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); -} - -static const struct hubbub_funcs hubbub21_funcs = { - .update_dchub = hubbub2_update_dchub, - .init_dchub_sys_ctx = hubbub21_init_dchub, - .init_vm_ctx = hubbub2_init_vm_ctx, - .dcc_support_swizzle = hubbub2_dcc_support_swizzle, - .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format, - .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap, - .wm_read_state = hubbub21_wm_read_state, - .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq, - .program_watermarks = hubbub21_program_watermarks, - .allow_self_refresh_control = hubbub1_allow_self_refresh_control, - .apply_DEDCN21_147_wa = hubbub21_apply_DEDCN21_147_wa, - .hubbub_read_state = hubbub2_read_state, -}; - -void hubbub21_construct(struct dcn20_hubbub *hubbub, - struct dc_context *ctx, - const struct dcn_hubbub_registers *hubbub_regs, - const struct dcn_hubbub_shift *hubbub_shift, - const struct dcn_hubbub_mask *hubbub_mask) -{ - hubbub->base.ctx = ctx; - - hubbub->base.funcs = &hubbub21_funcs; - - hubbub->regs = hubbub_regs; - hubbub->shifts = hubbub_shift; - hubbub->masks = hubbub_mask; - - hubbub->debug_test_index_pstate = 0xB; - hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */ -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h deleted file mode 100644 index d8eb2bb7282c..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h +++ /dev/null @@ -1,158 +0,0 @@ -/* -* Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ -#ifndef DAL_DC_DCN21_DCN21_HUBBUB_H_ -#define DAL_DC_DCN21_DCN21_HUBBUB_H_ - -#include "dcn20/dcn20_hubbub.h" - -#define HUBBUB_HVM_REG_LIST() \ - SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ - SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ - SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ - SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\ - SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\ - SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ - SR(DCHVM_CTRL0), \ - SR(DCHVM_MEM_CTRL), \ - SR(DCHVM_CLK_CTRL), \ - SR(DCHVM_RIOMMU_CTRL0), \ - SR(DCHVM_RIOMMU_STAT0) - -#define HUBBUB_REG_LIST_DCN21()\ - HUBBUB_REG_LIST_DCN20_COMMON(), \ - HUBBUB_SR_WATERMARK_REG_LIST(), \ - HUBBUB_HVM_REG_LIST() - -#define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \ - HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh), \ - HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \ - HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh), \ - HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh), \ - HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh), \ - HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh), \ - HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh), \ - HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh), \ - HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh), \ - HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh), \ - HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh), \ - HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh), \ - HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh), \ - HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh), \ - HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh) - -#define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\ - HUBBUB_MASK_SH_LIST_HVM(mask_sh), \ - HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \ - HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \ - HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ - HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ - HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ - HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ - HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ - HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ - HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \ - HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh) - -void dcn21_dchvm_init(struct hubbub *hubbub); -int hubbub21_init_dchub(struct hubbub *hubbub, - struct dcn_hubbub_phys_addr_config *pa_config); -bool hubbub21_program_watermarks( - struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower); -bool hubbub21_program_urgent_watermarks( - struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower); -bool hubbub21_program_stutter_watermarks( - struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower); -bool hubbub21_program_pstate_watermarks( - struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower); - -void hubbub21_wm_read_state(struct hubbub *hubbub, - struct dcn_hubbub_wm *wm); - -void hubbub21_construct(struct dcn20_hubbub *hubbub, - struct dc_context *ctx, - const struct dcn_hubbub_registers *hubbub_regs, - const struct dcn_hubbub_shift *hubbub_shift, - const struct dcn_hubbub_mask *hubbub_mask); - -#endif /* DAL_DC_DCN21_DCN21_HUBBUB_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c deleted file mode 100644 index e13d69a22c1c..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c +++ /dev/null @@ -1,860 +0,0 @@ -/* -* Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dcn10/dcn10_hubp.h" -#include "dcn21_hubp.h" - -#include "dm_services.h" -#include "reg_helper.h" - -#include "dc_dmub_srv.h" - -#define DC_LOGGER \ - ctx->logger -#define DC_LOGGER_INIT(logger) - -#define REG(reg)\ - hubp21->hubp_regs->reg - -#define CTX \ - hubp21->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name - -/* - * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL. - * As a result, if S/W updates any of these registers during a mode change, - * the current frame before the mode change will use the new value right away - * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior. - * - * REFCYC_PER_VM_GROUP_FLIP[22:0] - * REFCYC_PER_VM_GROUP_VBLANK[22:0] - * REFCYC_PER_VM_REQ_FLIP[22:0] - * REFCYC_PER_VM_REQ_VBLANK[22:0] - * - * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated - * when flipping to a new surface - * - * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated - * during prefetch period of a frame. The prefetch starts at a pre-determined - * number of lines before the display active per frame - * - * DCN may underflow due to incorrectly programming these registers - * during VM stage of prefetch/iflip. First lines of display active - * or a sub-region of active using a new surface will be corrupted - * until the VM data returns at flip/mode change transitions - * - * Work around: - * workaround is always opt to use the more aggressive settings. - * On any mode switch, if the new reg values are smaller than the current values, - * then update the regs with the new values. - * - * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 - * - */ -void apply_DEDCN21_142_wa_for_hostvm_deadline( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr) -{ - struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); - uint32_t refcyc_per_vm_group_vblank; - uint32_t refcyc_per_vm_req_vblank; - uint32_t refcyc_per_vm_group_flip; - uint32_t refcyc_per_vm_req_flip; - const uint32_t uninitialized_hw_default = 0; - - REG_GET(VBLANK_PARAMETERS_5, - REFCYC_PER_VM_GROUP_VBLANK, &refcyc_per_vm_group_vblank); - - if (refcyc_per_vm_group_vblank == uninitialized_hw_default || - refcyc_per_vm_group_vblank > dlg_attr->refcyc_per_vm_group_vblank) - REG_SET(VBLANK_PARAMETERS_5, 0, - REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank); - - REG_GET(VBLANK_PARAMETERS_6, - REFCYC_PER_VM_REQ_VBLANK, &refcyc_per_vm_req_vblank); - - if (refcyc_per_vm_req_vblank == uninitialized_hw_default || - refcyc_per_vm_req_vblank > dlg_attr->refcyc_per_vm_req_vblank) - REG_SET(VBLANK_PARAMETERS_6, 0, - REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank); - - REG_GET(FLIP_PARAMETERS_3, - REFCYC_PER_VM_GROUP_FLIP, &refcyc_per_vm_group_flip); - - if (refcyc_per_vm_group_flip == uninitialized_hw_default || - refcyc_per_vm_group_flip > dlg_attr->refcyc_per_vm_group_flip) - REG_SET(FLIP_PARAMETERS_3, 0, - REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip); - - REG_GET(FLIP_PARAMETERS_4, - REFCYC_PER_VM_REQ_FLIP, &refcyc_per_vm_req_flip); - - if (refcyc_per_vm_req_flip == uninitialized_hw_default || - refcyc_per_vm_req_flip > dlg_attr->refcyc_per_vm_req_flip) - REG_SET(FLIP_PARAMETERS_4, 0, - REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip); - - REG_SET(FLIP_PARAMETERS_5, 0, - REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c); - - REG_SET(FLIP_PARAMETERS_6, 0, - REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c); -} - -void hubp21_program_deadline( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr) -{ - hubp2_program_deadline(hubp, dlg_attr, ttu_attr); - - apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); -} - -void hubp21_program_requestor( - struct hubp *hubp, - struct _vcs_dpi_display_rq_regs_st *rq_regs) -{ - struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); - - REG_UPDATE(HUBPRET_CONTROL, - DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); - REG_SET_4(DCN_EXPANSION_MODE, 0, - DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, - PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, - MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, - CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); - REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, - CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, - MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, - META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, - MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, - DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, - VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, - SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, - PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); - REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, - CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, - MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, - META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, - MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, - DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, - SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, - PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); -} - -static void hubp21_setup( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr, - struct _vcs_dpi_display_rq_regs_st *rq_regs, - struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) -{ - /* otg is locked when this func is called. Register are double buffered. - * disable the requestors is not needed - */ - - hubp2_vready_at_or_After_vsync(hubp, pipe_dest); - hubp21_program_requestor(hubp, rq_regs); - hubp21_program_deadline(hubp, dlg_attr, ttu_attr); - -} - -static void hubp21_set_viewport( - struct hubp *hubp, - const struct rect *viewport, - const struct rect *viewport_c) -{ - struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); - - REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, - PRI_VIEWPORT_WIDTH, viewport->width, - PRI_VIEWPORT_HEIGHT, viewport->height); - - REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, - PRI_VIEWPORT_X_START, viewport->x, - PRI_VIEWPORT_Y_START, viewport->y); - - /*for stereo*/ - REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, - SEC_VIEWPORT_WIDTH, viewport->width, - SEC_VIEWPORT_HEIGHT, viewport->height); - - REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, - SEC_VIEWPORT_X_START, viewport->x, - SEC_VIEWPORT_Y_START, viewport->y); - - /* DC supports NV12 only at the moment */ - REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, - PRI_VIEWPORT_WIDTH_C, viewport_c->width, - PRI_VIEWPORT_HEIGHT_C, viewport_c->height); - - REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, - PRI_VIEWPORT_X_START_C, viewport_c->x, - PRI_VIEWPORT_Y_START_C, viewport_c->y); - - REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, - SEC_VIEWPORT_WIDTH_C, viewport_c->width, - SEC_VIEWPORT_HEIGHT_C, viewport_c->height); - - REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, - SEC_VIEWPORT_X_START_C, viewport_c->x, - SEC_VIEWPORT_Y_START_C, viewport_c->y); -} - -static void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, - struct vm_system_aperture_param *apt) -{ - struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); - - PHYSICAL_ADDRESS_LOC mc_vm_apt_low; - PHYSICAL_ADDRESS_LOC mc_vm_apt_high; - - // The format of high/low are 48:18 of the 48 bit addr - mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; - mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; - - REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, - MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); - - REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, - MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); - - REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, - ENABLE_L1_TLB, 1, - SYSTEM_ACCESS_MODE, 0x3); -} - -static void hubp21_validate_dml_output(struct hubp *hubp, - struct dc_context *ctx, - struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, - struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) -{ - struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); - struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; - struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; - struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; - DC_LOGGER_INIT(ctx->logger); - DC_LOG_DEBUG("DML Validation | Running Validation"); - - /* Requester - Per hubp */ - REG_GET(HUBPRET_CONTROL, - DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); - REG_GET_4(DCN_EXPANSION_MODE, - DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, - PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, - MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, - CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); - REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, - CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, - MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, - META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, - MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, - DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, - VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, - SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, - PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); - REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C, - CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, - MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, - META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, - MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, - DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, - SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, - PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); - - if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) - DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", - dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); - if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) - DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", - dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); - if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) - DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", - dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); - if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) - DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", - dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); - if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) - DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", - dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); - - if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); - if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); - if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); - if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); - if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); - if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); - if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); - if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); - - if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); - if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); - if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); - if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); - if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); - if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); - if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) - DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", - dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); - - - /* DLG - Per hubp */ - REG_GET_2(BLANK_OFFSET_0, - REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, - DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); - REG_GET(BLANK_OFFSET_1, - MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); - REG_GET(DST_DIMENSIONS, - REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); - REG_GET_2(DST_AFTER_SCALER, - REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, - DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); - REG_GET(REF_FREQ_TO_PIX_FREQ, - REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); - - if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) - DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); - if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) - DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", - dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); - if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) - DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", - dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); - if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) - DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); - if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) - DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); - if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) - DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", - dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); - if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) - DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", - dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); - - /* DLG - Per luma/chroma */ - REG_GET(VBLANK_PARAMETERS_1, - REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); - if (REG(NOM_PARAMETERS_0)) - REG_GET(NOM_PARAMETERS_0, - DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); - if (REG(NOM_PARAMETERS_1)) - REG_GET(NOM_PARAMETERS_1, - REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); - REG_GET(NOM_PARAMETERS_4, - DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); - REG_GET(NOM_PARAMETERS_5, - REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); - REG_GET_2(PER_LINE_DELIVERY, - REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, - REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); - REG_GET_2(PER_LINE_DELIVERY_PRE, - REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, - REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); - REG_GET(VBLANK_PARAMETERS_2, - REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); - if (REG(NOM_PARAMETERS_2)) - REG_GET(NOM_PARAMETERS_2, - DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); - if (REG(NOM_PARAMETERS_3)) - REG_GET(NOM_PARAMETERS_3, - REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); - REG_GET(NOM_PARAMETERS_6, - DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); - REG_GET(NOM_PARAMETERS_7, - REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); - REG_GET(VBLANK_PARAMETERS_3, - REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); - REG_GET(VBLANK_PARAMETERS_4, - REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); - - if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) - DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); - if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", - dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); - if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); - if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", - dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); - if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); - if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) - DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); - if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) - DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); - if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) - DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); - if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", - dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); - if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); - if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", - dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); - if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) - DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); - if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) - DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); - if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) - DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); - if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) - DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); - if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) - DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); - - /* TTU - per hubp */ - REG_GET_2(DCN_TTU_QOS_WM, - QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, - QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); - - if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) - DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); - if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) - DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); - - /* TTU - per luma/chroma */ - /* Assumed surf0 is luma and 1 is chroma */ - REG_GET_3(DCN_SURF0_TTU_CNTL0, - REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, - QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, - QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); - REG_GET_3(DCN_SURF1_TTU_CNTL0, - REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, - QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, - QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); - REG_GET_3(DCN_CUR0_TTU_CNTL0, - REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, - QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, - QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); - REG_GET(FLIP_PARAMETERS_1, - REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); - REG_GET(DCN_CUR0_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); - REG_GET(DCN_CUR1_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); - REG_GET(DCN_SURF0_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); - REG_GET(DCN_SURF1_TTU_CNTL1, - REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); - - if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) - DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); - if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) - DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); - if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) - DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); - if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) - DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); - if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) - DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); - if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) - DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); - if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) - DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); - if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) - DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); - if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) - DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", - dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); - if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) - DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); - if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) - DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); - if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) - DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); - if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) - DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); - if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) - DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", - dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); - - /* Host VM deadline regs */ - REG_GET(VBLANK_PARAMETERS_5, - REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank); - REG_GET(VBLANK_PARAMETERS_6, - REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank); - REG_GET(FLIP_PARAMETERS_3, - REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip); - REG_GET(FLIP_PARAMETERS_4, - REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip); - REG_GET(FLIP_PARAMETERS_5, - REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c); - REG_GET(FLIP_PARAMETERS_6, - REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c); - REG_GET(FLIP_PARAMETERS_2, - REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l); - - if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank) - DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank); - if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank) - DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank); - if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip) - DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip); - if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip) - DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip); - if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c) - DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c); - if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c) - DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c); - if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l) - DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n", - dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l); -} - -static void program_surface_flip_and_addr(struct hubp *hubp, struct surface_flip_registers *flip_regs) -{ - struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); - - REG_UPDATE_3(DCSURF_FLIP_CONTROL, - SURFACE_FLIP_TYPE, flip_regs->immediate, - SURFACE_FLIP_MODE_FOR_STEREOSYNC, flip_regs->grph_stereo, - SURFACE_FLIP_IN_STEREOSYNC, flip_regs->grph_stereo); - - REG_UPDATE(VMID_SETTINGS_0, - VMID, flip_regs->vmid); - - REG_UPDATE_8(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_TMZ, flip_regs->tmz_surface, - PRIMARY_SURFACE_TMZ_C, flip_regs->tmz_surface, - PRIMARY_META_SURFACE_TMZ, flip_regs->tmz_surface, - PRIMARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface, - SECONDARY_SURFACE_TMZ, flip_regs->tmz_surface, - SECONDARY_SURFACE_TMZ_C, flip_regs->tmz_surface, - SECONDARY_META_SURFACE_TMZ, flip_regs->tmz_surface, - SECONDARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, - PRIMARY_META_SURFACE_ADDRESS_HIGH_C, - flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, - PRIMARY_META_SURFACE_ADDRESS_C, - flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_C); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_META_SURFACE_ADDRESS_HIGH, - flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH); - - REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, - PRIMARY_META_SURFACE_ADDRESS, - flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS); - - REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, - SECONDARY_META_SURFACE_ADDRESS_HIGH, - flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH); - - REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, - SECONDARY_META_SURFACE_ADDRESS, - flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS); - - - REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, - SECONDARY_SURFACE_ADDRESS_HIGH, - flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH); - - REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, - SECONDARY_SURFACE_ADDRESS, - flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS); - - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, - PRIMARY_SURFACE_ADDRESS_HIGH_C, - flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, - PRIMARY_SURFACE_ADDRESS_C, - flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, - PRIMARY_SURFACE_ADDRESS_HIGH, - flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH); - - REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, - PRIMARY_SURFACE_ADDRESS, - flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS); -} - -static void dmcub_PLAT_54186_wa(struct hubp *hubp, - struct surface_flip_registers *flip_regs) -{ - struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); - union dmub_rb_cmd cmd; - - memset(&cmd, 0, sizeof(cmd)); - - cmd.PLAT_54186_wa.header.type = DMUB_CMD__PLAT_54186_WA; - cmd.PLAT_54186_wa.header.payload_bytes = sizeof(cmd.PLAT_54186_wa.flip); - cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS = - flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS; - cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_C = - flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C; - cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = - flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; - cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = - flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; - cmd.PLAT_54186_wa.flip.flip_params.grph_stereo = flip_regs->grph_stereo; - cmd.PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst; - cmd.PLAT_54186_wa.flip.flip_params.immediate = flip_regs->immediate; - cmd.PLAT_54186_wa.flip.flip_params.tmz_surface = flip_regs->tmz_surface; - cmd.PLAT_54186_wa.flip.flip_params.vmid = flip_regs->vmid; - - PERF_TRACE(); // TODO: remove after performance is stable. - dc_wake_and_execute_dmub_cmd(hubp->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); - PERF_TRACE(); // TODO: remove after performance is stable. -} - -static bool hubp21_program_surface_flip_and_addr( - struct hubp *hubp, - const struct dc_plane_address *address, - bool flip_immediate) -{ - struct surface_flip_registers flip_regs = { 0 }; - - flip_regs.vmid = address->vmid; - - switch (address->type) { - case PLN_ADDR_TYPE_GRAPHICS: - if (address->grph.addr.quad_part == 0) { - BREAK_TO_DEBUGGER(); - break; - } - - if (address->grph.meta_addr.quad_part != 0) { - flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = - address->grph.meta_addr.low_part; - flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = - address->grph.meta_addr.high_part; - } - - flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = - address->grph.addr.low_part; - flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = - address->grph.addr.high_part; - break; - case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: - if (address->video_progressive.luma_addr.quad_part == 0 - || address->video_progressive.chroma_addr.quad_part == 0) - break; - - if (address->video_progressive.luma_meta_addr.quad_part != 0) { - flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = - address->video_progressive.luma_meta_addr.low_part; - flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = - address->video_progressive.luma_meta_addr.high_part; - - flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = - address->video_progressive.chroma_meta_addr.low_part; - flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = - address->video_progressive.chroma_meta_addr.high_part; - } - - flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = - address->video_progressive.luma_addr.low_part; - flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = - address->video_progressive.luma_addr.high_part; - - flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C = - address->video_progressive.chroma_addr.low_part; - - flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = - address->video_progressive.chroma_addr.high_part; - - break; - case PLN_ADDR_TYPE_GRPH_STEREO: - if (address->grph_stereo.left_addr.quad_part == 0) - break; - if (address->grph_stereo.right_addr.quad_part == 0) - break; - - flip_regs.grph_stereo = true; - - if (address->grph_stereo.right_meta_addr.quad_part != 0) { - flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS = - address->grph_stereo.right_meta_addr.low_part; - flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = - address->grph_stereo.right_meta_addr.high_part; - } - - if (address->grph_stereo.left_meta_addr.quad_part != 0) { - flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS = - address->grph_stereo.left_meta_addr.low_part; - flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = - address->grph_stereo.left_meta_addr.high_part; - } - - flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS = - address->grph_stereo.left_addr.low_part; - flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = - address->grph_stereo.left_addr.high_part; - - flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS = - address->grph_stereo.right_addr.low_part; - flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = - address->grph_stereo.right_addr.high_part; - - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - flip_regs.tmz_surface = address->tmz_surface; - flip_regs.immediate = flip_immediate; - - if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) - dmcub_PLAT_54186_wa(hubp, &flip_regs); - else - program_surface_flip_and_addr(hubp, &flip_regs); - - hubp->request_address = *address; - - return true; -} - -static void hubp21_init(struct hubp *hubp) -{ - // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta - // This is a chicken bit to enable the ECO fix. - - struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); - //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1; - REG_WRITE(HUBPREQ_DEBUG, 1 << 26); -} -static struct hubp_funcs dcn21_hubp_funcs = { - .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, - .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, - .hubp_program_surface_flip_and_addr = hubp21_program_surface_flip_and_addr, - .hubp_program_surface_config = hubp1_program_surface_config, - .hubp_is_flip_pending = hubp1_is_flip_pending, - .hubp_setup = hubp21_setup, - .hubp_setup_interdependent = hubp2_setup_interdependent, - .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings, - .set_blank = hubp1_set_blank, - .dcc_control = hubp1_dcc_control, - .mem_program_viewport = hubp21_set_viewport, - .set_cursor_attributes = hubp2_cursor_set_attributes, - .set_cursor_position = hubp1_cursor_set_position, - .hubp_clk_cntl = hubp1_clk_cntl, - .hubp_vtg_sel = hubp1_vtg_sel, - .dmdata_set_attributes = hubp2_dmdata_set_attributes, - .dmdata_load = hubp2_dmdata_load, - .dmdata_status_done = hubp2_dmdata_status_done, - .hubp_read_state = hubp2_read_state, - .hubp_clear_underflow = hubp1_clear_underflow, - .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, - .hubp_init = hubp21_init, - .validate_dml_output = hubp21_validate_dml_output, - .hubp_set_flip_int = hubp1_set_flip_int, -}; - -bool hubp21_construct( - struct dcn21_hubp *hubp21, - struct dc_context *ctx, - uint32_t inst, - const struct dcn_hubp2_registers *hubp_regs, - const struct dcn_hubp2_shift *hubp_shift, - const struct dcn_hubp2_mask *hubp_mask) -{ - hubp21->base.funcs = &dcn21_hubp_funcs; - hubp21->base.ctx = ctx; - hubp21->hubp_regs = hubp_regs; - hubp21->hubp_shift = hubp_shift; - hubp21->hubp_mask = hubp_mask; - hubp21->base.inst = inst; - hubp21->base.opp_id = OPP_ID_INVALID; - hubp21->base.mpcc_id = 0xf; - - return true; -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h deleted file mode 100644 index 9873b6cbc5ba..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h +++ /dev/null @@ -1,134 +0,0 @@ -/* -* Copyright 2018 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef DAL_DC_DCN21_DCN21_HUBP_H_ -#define DAL_DC_DCN21_DCN21_HUBP_H_ - -#include "../dcn20/dcn20_hubp.h" -#include "../dcn10/dcn10_hubp.h" - -#define TO_DCN21_HUBP(hubp)\ - container_of(hubp, struct dcn21_hubp, base) - -#define HUBP_REG_LIST_DCN21(id)\ - HUBP_REG_LIST_DCN2_COMMON(id),\ - SRI(FLIP_PARAMETERS_3, HUBPREQ, id),\ - SRI(FLIP_PARAMETERS_4, HUBPREQ, id),\ - SRI(FLIP_PARAMETERS_5, HUBPREQ, id),\ - SRI(FLIP_PARAMETERS_6, HUBPREQ, id),\ - SRI(VBLANK_PARAMETERS_5, HUBPREQ, id),\ - SRI(VBLANK_PARAMETERS_6, HUBPREQ, id) - -#define HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh)\ - HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ - HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ - HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ - HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ - HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ - HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ - HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ - HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ - HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ - HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ - HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ - HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ - HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\ - HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\ - HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\ - HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh) - -#define HUBP_MASK_SH_LIST_DCN21(mask_sh)\ - HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh),\ - HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh) - - -struct dcn21_hubp { - struct hubp base; - struct dcn_hubp_state state; - const struct dcn_hubp2_registers *hubp_regs; - const struct dcn_hubp2_shift *hubp_shift; - const struct dcn_hubp2_mask *hubp_mask; - int PLAT_54186_wa_chroma_addr_offset; -}; - -bool hubp21_construct( - struct dcn21_hubp *hubp21, - struct dc_context *ctx, - uint32_t inst, - const struct dcn_hubp2_registers *hubp_regs, - const struct dcn_hubp2_shift *hubp_shift, - const struct dcn_hubp2_mask *hubp_mask); - -void apply_DEDCN21_142_wa_for_hostvm_deadline( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr); - -void hubp21_program_deadline( - struct hubp *hubp, - struct _vcs_dpi_display_dlg_regs_st *dlg_attr, - struct _vcs_dpi_display_ttu_regs_st *ttu_attr); - -void hubp21_program_requestor( - struct hubp *hubp, - struct _vcs_dpi_display_rq_regs_st *rq_regs); -#endif /* DAL_DC_DCN21_DCN21_HUBP_H_ */ |