diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw')
28 files changed, 7298 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h new file mode 100644 index 000000000000..3f0161d64675 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h @@ -0,0 +1,71 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_ABM_H__ +#define __DC_ABM_H__ + +#include "dm_services_types.h" + +struct abm_save_restore; + +struct abm { + struct dc_context *ctx; + const struct abm_funcs *funcs; + bool dmcu_is_running; +}; + +struct abm_funcs { + void (*abm_init)(struct abm *abm, uint32_t back_light, uint32_t user_level); + bool (*set_abm_level)(struct abm *abm, unsigned int abm_level); + bool (*set_abm_immediate_disable)(struct abm *abm, unsigned int panel_inst); + bool (*set_pipe)(struct abm *abm, unsigned int controller_id, unsigned int panel_inst); + + /* backlight_pwm_u16_16 is unsigned 32 bit, + * 16 bit integer + 16 fractional, where 1.0 is max backlight value. + */ + bool (*set_backlight_level_pwm)(struct abm *abm, + unsigned int backlight_pwm_u16_16, + unsigned int frame_ramp, + unsigned int controller_id, + unsigned int panel_inst); + + unsigned int (*get_current_backlight)(struct abm *abm); + unsigned int (*get_target_backlight)(struct abm *abm); + bool (*init_abm_config)(struct abm *abm, + const char *src, + unsigned int bytes, + unsigned int inst); + bool (*set_abm_pause)(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int otg_inst); + bool (*save_restore)( + struct abm *abm, + unsigned int panel_inst, + struct abm_save_restore *pData); + bool (*set_pipe_ex)(struct abm *abm, + unsigned int otg_inst, + unsigned int option, + unsigned int panel_inst, + unsigned int pwrseq_inst); +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h b/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h new file mode 100644 index 000000000000..8c18efc2aa70 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h @@ -0,0 +1,66 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_AUDIO_H__ +#define __DAL_AUDIO_H__ + +#include "audio_types.h" + +struct audio; + +struct audio_funcs { + + bool (*endpoint_valid)(struct audio *audio); + + void (*hw_init)(struct audio *audio); + + void (*az_enable)(struct audio *audio); + + void (*az_disable)(struct audio *audio); + + void (*az_configure)(struct audio *audio, + enum signal_type signal, + const struct audio_crtc_info *crtc_info, + const struct audio_info *audio_info, + const struct audio_dp_link_info *dp_link_info); + + void (*az_disable_hbr_audio)(struct audio *audio); + + void (*wall_dto_setup)(struct audio *audio, + enum signal_type signal, + const struct audio_crtc_info *crtc_info, + const struct audio_pll_info *pll_info); + + void (*destroy)(struct audio **audio); +}; + +struct audio { + const struct audio_funcs *funcs; + struct dc_context *ctx; + unsigned int inst; + bool enabled; +}; + +#endif /* __DAL_AUDIO__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h b/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h new file mode 100644 index 000000000000..af6b9509d09d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h @@ -0,0 +1,187 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_AUX_ENGINE_H__ +#define __DAL_AUX_ENGINE_H__ + +#include "dc_ddc_types.h" + +enum aux_return_code_type; + +enum i2caux_transaction_operation { + I2CAUX_TRANSACTION_READ, + I2CAUX_TRANSACTION_WRITE +}; + +enum i2caux_transaction_address_space { + I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C = 1, + I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD +}; + +struct i2caux_transaction_payload { + enum i2caux_transaction_address_space address_space; + uint32_t address; + uint32_t length; + uint8_t *data; +}; + +enum i2caux_transaction_status { + I2CAUX_TRANSACTION_STATUS_UNKNOWN = (-1L), + I2CAUX_TRANSACTION_STATUS_SUCCEEDED, + I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY, + I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT, + I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR, + I2CAUX_TRANSACTION_STATUS_FAILED_NACK, + I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE, + I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION, + I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION, + I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW, + I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON +}; + +struct i2caux_transaction_request { + enum i2caux_transaction_operation operation; + struct i2caux_transaction_payload payload; + enum i2caux_transaction_status status; +}; + +enum i2caux_engine_type { + I2CAUX_ENGINE_TYPE_UNKNOWN = (-1L), + I2CAUX_ENGINE_TYPE_AUX, + I2CAUX_ENGINE_TYPE_I2C_DDC_HW, + I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW, + I2CAUX_ENGINE_TYPE_I2C_SW +}; + +enum i2c_default_speed { + I2CAUX_DEFAULT_I2C_HW_SPEED = 50, + I2CAUX_DEFAULT_I2C_SW_SPEED = 50 +}; + +union aux_config { + struct { + uint32_t ALLOW_AUX_WHEN_HPD_LOW:1; + } bits; + uint32_t raw; +}; + +struct aux_engine { + uint32_t inst; + struct ddc *ddc; + struct dc_context *ctx; + const struct aux_engine_funcs *funcs; + /* following values are expressed in milliseconds */ + uint32_t delay; + uint32_t max_defer_write_retry; + bool acquire_reset; +}; + +struct read_command_context { + uint8_t *buffer; + uint32_t current_read_length; + uint32_t offset; + enum i2caux_transaction_status status; + + struct aux_request_transaction_data request; + struct aux_reply_transaction_data reply; + + uint8_t returned_byte; + + uint32_t timed_out_retry_aux; + uint32_t invalid_reply_retry_aux; + uint32_t defer_retry_aux; + uint32_t defer_retry_i2c; + uint32_t invalid_reply_retry_aux_on_ack; + + bool transaction_complete; + bool operation_succeeded; +}; + +struct write_command_context { + bool mot; + + uint8_t *buffer; + uint32_t current_write_length; + enum i2caux_transaction_status status; + + struct aux_request_transaction_data request; + struct aux_reply_transaction_data reply; + + uint8_t returned_byte; + + uint32_t timed_out_retry_aux; + uint32_t invalid_reply_retry_aux; + uint32_t defer_retry_aux; + uint32_t defer_retry_i2c; + uint32_t max_defer_retry; + uint32_t ack_m_retry; + + uint8_t reply_data[DEFAULT_AUX_MAX_DATA_SIZE]; + + bool transaction_complete; + bool operation_succeeded; +}; + + +struct aux_engine_funcs { + bool (*configure_timeout)( + struct ddc_service *ddc, + uint32_t timeout); + void (*destroy)( + struct aux_engine **ptr); + bool (*acquire_engine)( + struct aux_engine *engine); + void (*configure)( + struct aux_engine *engine, + union aux_config cfg); + void (*submit_channel_request)( + struct aux_engine *engine, + struct aux_request_transaction_data *request); + void (*process_channel_reply)( + struct aux_engine *engine, + struct aux_reply_transaction_data *reply); + int (*read_channel_reply)( + struct aux_engine *engine, + uint32_t size, + uint8_t *buffer, + uint8_t *reply_result, + uint32_t *sw_status); + enum aux_return_code_type (*get_channel_status)( + struct aux_engine *engine, + uint8_t *returned_bytes); + bool (*is_engine_available)(struct aux_engine *engine); + bool (*acquire)( + struct aux_engine *engine, + struct ddc *ddc); + bool (*submit_request)( + struct aux_engine *engine, + struct i2caux_transaction_request *request, + bool middle_of_transaction); + void (*release_engine)( + struct aux_engine *engine); + void (*destroy_engine)( + struct aux_engine **engine); +}; +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h new file mode 100644 index 000000000000..2c9a4a12bd8a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -0,0 +1,371 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_CLK_MGR_H__ +#define __DAL_CLK_MGR_H__ + +#include "dc.h" +#include "dm_pp_smu.h" + +/* Constants */ +#define DDR4_DRAM_WIDTH 64 +#define WM_A 0 +#define WM_B 1 +#define WM_C 2 +#define WM_D 3 +#define WM_SET_COUNT 4 +#define WM_1A 2 +#define WM_1B 3 + +#define DCN_MINIMUM_DISPCLK_Khz 100000 +#define DCN_MINIMUM_DPPCLK_Khz 100000 + +struct dcn3_clk_internal { + int dummy; +// TODO: + uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk + uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk + uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk + uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk + uint32_t CLK1_CLK4_CURRENT_CNT; + uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider + uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow + + uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass + uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass + uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass + uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass + + uint32_t CLK4_CLK0_CURRENT_CNT; //fclk +}; + +struct dcn35_clk_internal { + int dummy; + uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk + uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk + uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk + uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk + uint32_t CLK1_CLK4_CURRENT_CNT; //dtbclk + //uint32_t CLK1_CLK5_CURRENT_CNT; //dpiaclk + //uint32_t CLK1_CLK6_CURRENT_CNT; //srdbgclk + uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider + uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow + + uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass + uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass + uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass + uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass + uint32_t CLK1_CLK4_BYPASS_CNTL; //dtbclk bypass +}; + +struct dcn301_clk_internal { + int dummy; + uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk + uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk + uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk + uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk + uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider + uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow + + uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass + uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass + uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass + uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass +}; + +/* Will these bw structures be ASIC specific? */ + +#define MAX_NUM_DPM_LVL 8 +#define WM_SET_COUNT 4 + +enum clk_type { + CLK_TYPE_DCFCLK, + CLK_TYPE_FCLK, + CLK_TYPE_MCLK, + CLK_TYPE_SOCCLK, + CLK_TYPE_DTBCLK, + CLK_TYPE_DISPCLK, + CLK_TYPE_DPPCLK, + CLK_TYPE_DSCCLK, + CLK_TYPE_COUNT +}; + +struct clk_limit_table_entry { + unsigned int voltage; /* milivolts withh 2 fractional bits */ + unsigned int dcfclk_mhz; + unsigned int fclk_mhz; + unsigned int memclk_mhz; + unsigned int socclk_mhz; + unsigned int dtbclk_mhz; + unsigned int dispclk_mhz; + unsigned int dppclk_mhz; + unsigned int phyclk_mhz; + unsigned int phyclk_d18_mhz; + unsigned int wck_ratio; +}; + +struct clk_limit_num_entries { + unsigned int num_dcfclk_levels; + unsigned int num_fclk_levels; + unsigned int num_memclk_levels; + unsigned int num_socclk_levels; + unsigned int num_dtbclk_levels; + unsigned int num_dispclk_levels; + unsigned int num_dppclk_levels; + unsigned int num_phyclk_levels; + unsigned int num_phyclk_d18_levels; +}; + +/* This table is contiguous */ +struct clk_limit_table { + struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL]; + struct clk_limit_num_entries num_entries_per_clk; + unsigned int num_entries; /* highest populated dpm level for back compatibility */ +}; + +struct wm_range_table_entry { + unsigned int wm_inst; + unsigned int wm_type; + double pstate_latency_us; + double sr_exit_time_us; + double sr_enter_plus_exit_time_us; + bool valid; +}; + +struct nv_wm_range_entry { + bool valid; + + struct { + uint8_t wm_type; + uint16_t min_dcfclk; + uint16_t max_dcfclk; + uint16_t min_uclk; + uint16_t max_uclk; + } pmfw_breakdown; + + struct { + double pstate_latency_us; + double sr_exit_time_us; + double sr_enter_plus_exit_time_us; + double fclk_change_latency_us; + } dml_input; +}; + +struct clk_log_info { + bool enabled; + char *pBuf; + unsigned int bufSize; + unsigned int *sum_chars_printed; +}; + +struct clk_state_registers_and_bypass { + uint32_t dcfclk; + uint32_t dcf_deep_sleep_divider; + uint32_t dcf_deep_sleep_allow; + uint32_t dprefclk; + uint32_t dispclk; + uint32_t dppclk; + uint32_t dtbclk; + uint32_t fclk; + + uint32_t dppclk_bypass; + uint32_t dcfclk_bypass; + uint32_t dprefclk_bypass; + uint32_t dispclk_bypass; +}; + +struct rv1_clk_internal { + uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk + uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider + uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow + uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk + uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk + + uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass + uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass + uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass +}; + +struct rn_clk_internal { + uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk + uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk + uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk + uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk + uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider + uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow + + uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass + uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass + uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass + uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass + +}; + +/* For dtn logging and debugging */ +struct clk_state_registers { + uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk + uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider + uint32_t CLK0_CLK8_ALLOW_DS; //dcf_deep_sleep_allow + uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk + uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk +}; + +/* TODO: combine this with the above */ +struct clk_bypass { + uint32_t dcfclk_bypass; + uint32_t dispclk_pypass; + uint32_t dprefclk_bypass; +}; +/* + * This table is not contiguous, can have holes, each + * entry correspond to one set of WM. For example if + * we have 2 DPM and LPDDR, we will WM set A, B and + * D occupied, C will be emptry. + */ +struct wm_table { + union { + struct nv_wm_range_entry nv_entries[WM_SET_COUNT]; + struct wm_range_table_entry entries[WM_SET_COUNT]; + }; +}; + +struct dummy_pstate_entry { + unsigned int dram_speed_mts; + unsigned int dummy_pstate_latency_us; +}; + +struct clk_bw_params { + unsigned int vram_type; + unsigned int num_channels; + unsigned int dram_channel_width_bytes; + unsigned int dispclk_vco_khz; + unsigned int dc_mode_softmax_memclk; + unsigned int max_memclk_mhz; + struct clk_limit_table clk_table; + struct wm_table wm_table; + struct dummy_pstate_entry dummy_pstate_table[4]; + struct clk_limit_table_entry dc_mode_limit; +}; +/* Public interfaces */ + +struct clk_states { + uint32_t dprefclk_khz; +}; + +struct clk_mgr_funcs { + /* + * This function should set new clocks based on the input "safe_to_lower". + * If safe_to_lower == false, then only clocks which are to be increased + * should changed. + * If safe_to_lower == true, then only clocks which are to be decreased + * should be changed. + */ + void (*update_clocks)(struct clk_mgr *clk_mgr, + struct dc_state *context, + bool safe_to_lower); + + int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr); + int (*get_dtb_ref_clk_frequency)(struct clk_mgr *clk_mgr); + + void (*set_low_power_state)(struct clk_mgr *clk_mgr); + void (*exit_low_power_state)(struct clk_mgr *clk_mgr); + bool (*is_ips_supported)(struct clk_mgr *clk_mgr); + + void (*init_clocks)(struct clk_mgr *clk_mgr); + + void (*dump_clk_registers)(struct clk_state_registers_and_bypass *regs_and_bypass, + struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info); + + void (*enable_pme_wa) (struct clk_mgr *clk_mgr); + void (*get_clock)(struct clk_mgr *clk_mgr, + struct dc_state *context, + enum dc_clock_type clock_type, + struct dc_clock_config *clock_cfg); + + bool (*are_clock_states_equal) (struct dc_clocks *a, + struct dc_clocks *b); + void (*notify_wm_ranges)(struct clk_mgr *clk_mgr); + + /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ + void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link); + /* + * Send message to PMFW to set hard min memclk frequency + * When current_mode = false, set DPM0 + * When current_mode = true, set required clock for current mode + */ + void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode); + + int (*get_hard_min_memclk)(struct clk_mgr *clk_mgr); + int (*get_hard_min_fclk)(struct clk_mgr *clk_mgr); + + /* Send message to PMFW to set hard max memclk frequency to highest DPM */ + void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr); + + /* Custom set a memclk freq range*/ + void (*set_max_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); + void (*set_min_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz); + + /* Get current memclk states from PMFW, update relevant structures */ + void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr); + + /* Get SMU present */ + bool (*is_smu_present)(struct clk_mgr *clk_mgr); + + int (*get_dispclk_from_dentist)(struct clk_mgr *clk_mgr_base); + + bool (*is_dc_mode_present)(struct clk_mgr *clk_mgr); + + uint32_t (*set_smartmux_switch)(struct clk_mgr *clk_mgr, uint32_t pins_to_set); + + unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type); +}; + +struct clk_mgr { + struct dc_context *ctx; + struct clk_mgr_funcs *funcs; + struct dc_clocks clks; + bool psr_allow_active_cache; + bool force_smu_not_present; + bool dc_mode_softmax_enabled; + int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes + int dp_dto_source_clock_in_khz; // Used to program DP DTO with ss adjustment on DCN314 + int dentist_vco_freq_khz; + struct clk_state_registers_and_bypass boot_snapshot; + struct clk_bw_params *bw_params; + struct pp_smu_wm_range_sets ranges; +}; + +/* forward declarations */ +struct dccg; + +struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); + +void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr); + +void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); + +void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); + +#endif /* __DAL_CLK_MGR_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h new file mode 100644 index 000000000000..bac8febad69a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -0,0 +1,474 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_CLK_MGR_INTERNAL_H__ +#define __DAL_CLK_MGR_INTERNAL_H__ + +#include "clk_mgr.h" +#include "dc.h" + +/* + * only thing needed from here is MEMORY_TYPE_MULTIPLIER_CZ, which is also + * used in resource, perhaps this should be defined somewhere more common. + */ +#include "resource.h" + + +/* Starting DID for each range */ +enum dentist_base_divider_id { + DENTIST_BASE_DID_1 = 0x08, + DENTIST_BASE_DID_2 = 0x40, + DENTIST_BASE_DID_3 = 0x60, + DENTIST_BASE_DID_4 = 0x7e, + DENTIST_MAX_DID = 0x7f +}; + +/* Starting point and step size for each divider range.*/ +enum dentist_divider_range { + DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */ + DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */ + DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */ + DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */ + DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */ + DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */ + DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */ + DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */ + DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4 +}; + +/* + *************************************************************************************** + ****************** Clock Manager Private Macros and Defines *************************** + *************************************************************************************** + */ + +/* Macros */ + +#define TO_CLK_MGR_INTERNAL(clk_mgr)\ + container_of(clk_mgr, struct clk_mgr_internal, base) + +#define CTX \ + clk_mgr->base.ctx + +#define DC_LOGGER \ + dc->ctx->logger + + + + +#define CLK_BASE(inst) \ + CLK_BASE_INNER(inst) + +#define CLK_SRI(reg_name, block, inst)\ + .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ + mm ## block ## _ ## inst ## _ ## reg_name + +#define CLK_COMMON_REG_LIST_DCE_BASE() \ + .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \ + .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL + +#if defined(CONFIG_DRM_AMD_DC_SI) +#define CLK_COMMON_REG_LIST_DCE60_BASE() \ + SR(DENTIST_DISPCLK_CNTL) +#endif + +#define CLK_COMMON_REG_LIST_DCN_BASE() \ + SR(DENTIST_DISPCLK_CNTL) + +#define CLK_COMMON_REG_LIST_DCN_201() \ + SR(DENTIST_DISPCLK_CNTL), \ + CLK_SRI(CLK4_CLK_PLL_REQ, CLK4, 0), \ + CLK_SRI(CLK4_CLK2_CURRENT_CNT, CLK4, 0) + +#define CLK_REG_LIST_NV10() \ + SR(DENTIST_DISPCLK_CNTL), \ + CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \ + CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0) + +#define CLK_REG_LIST_DCN3() \ + SR(DENTIST_DISPCLK_CNTL), \ + CLK_SRI(CLK0_CLK_PLL_REQ, CLK02, 0), \ + CLK_SRI(CLK0_CLK2_DFS_CNTL, CLK02, 0) + +#define CLK_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +#define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ + CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ + CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh) + +#if defined(CONFIG_DRM_AMD_DC_SI) +#define CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \ + CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ + CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh) +#endif + +#define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ + CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ + CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh) + +#define CLK_MASK_SH_LIST_RV1(mask_sh) \ + CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ + CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\ + CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\ + CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh), + +#define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \ + CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ + CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\ + CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh) + +#define CLK_MASK_SH_LIST_NV10(mask_sh) \ + CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\ + CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\ + CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh) + +#define CLK_COMMON_MASK_SH_LIST_DCN201_BASE(mask_sh) \ + CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ + CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\ + CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh),\ + CLK_SF(CLK4_0_CLK4_CLK_PLL_REQ, FbMult_int, mask_sh) + +#define CLK_REG_LIST_DCN32() \ + SR(DENTIST_DISPCLK_CNTL), \ + CLK_SR_DCN32(CLK1_CLK_PLL_REQ), \ + CLK_SR_DCN32(CLK1_CLK0_DFS_CNTL), \ + CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \ + CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \ + CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \ + CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL), \ + CLK_SR_DCN32(CLK1_CLK0_CURRENT_CNT), \ + CLK_SR_DCN32(CLK1_CLK1_CURRENT_CNT), \ + CLK_SR_DCN32(CLK1_CLK2_CURRENT_CNT), \ + CLK_SR_DCN32(CLK1_CLK3_CURRENT_CNT), \ + CLK_SR_DCN32(CLK1_CLK4_CURRENT_CNT), \ + CLK_SR_DCN32(CLK4_CLK0_CURRENT_CNT) + +#define CLK_REG_LIST_DCN35() \ + CLK_SR_DCN35(CLK1_CLK_PLL_REQ), \ + CLK_SR_DCN35(CLK1_CLK0_DFS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK1_DFS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK2_DFS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK3_DFS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK4_DFS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK5_DFS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK0_CURRENT_CNT), \ + CLK_SR_DCN35(CLK1_CLK1_CURRENT_CNT), \ + CLK_SR_DCN35(CLK1_CLK2_CURRENT_CNT), \ + CLK_SR_DCN35(CLK1_CLK3_CURRENT_CNT), \ + CLK_SR_DCN35(CLK1_CLK4_CURRENT_CNT), \ + CLK_SR_DCN35(CLK1_CLK5_CURRENT_CNT), \ + CLK_SR_DCN35(CLK1_CLK0_BYPASS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK1_BYPASS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK2_BYPASS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK3_BYPASS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK4_BYPASS_CNTL),\ + CLK_SR_DCN35(CLK1_CLK5_BYPASS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK0_DS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK1_DS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK2_DS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK3_DS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK4_DS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK5_DS_CNTL), \ + CLK_SR_DCN35(CLK1_CLK0_ALLOW_DS), \ + CLK_SR_DCN35(CLK1_CLK1_ALLOW_DS), \ + CLK_SR_DCN35(CLK1_CLK2_ALLOW_DS), \ + CLK_SR_DCN35(CLK1_CLK3_ALLOW_DS), \ + CLK_SR_DCN35(CLK1_CLK4_ALLOW_DS), \ + CLK_SR_DCN35(CLK1_CLK5_ALLOW_DS), \ + CLK_SR_DCN35(CLK5_spll_field_8), \ + CLK_SR_DCN35(CLK6_spll_field_8), \ + SR(DENTIST_DISPCLK_CNTL), \ + +#define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \ + CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\ + CLK_SF(CLK1_CLK_PLL_REQ, FbMult_int, mask_sh),\ + CLK_SF(CLK1_CLK_PLL_REQ, FbMult_frac, mask_sh) + +#define CLK_REG_LIST_DCN321() \ + SR(DENTIST_DISPCLK_CNTL), \ + CLK_SR_DCN321(CLK0_CLK_PLL_REQ, CLK01, 0), \ + CLK_SR_DCN321(CLK0_CLK0_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN321(CLK0_CLK1_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN321(CLK0_CLK2_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN321(CLK0_CLK3_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN321(CLK0_CLK4_DFS_CNTL, CLK01, 0) + +#define CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) \ + CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\ + CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\ + CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh) + +#define CLK_REG_LIST_DCN401() \ + SR(DENTIST_DISPCLK_CNTL), \ + CLK_SR_DCN401(CLK0_CLK_PLL_REQ, CLK01, 0), \ + CLK_SR_DCN401(CLK0_CLK0_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN401(CLK0_CLK1_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN401(CLK0_CLK2_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN401(CLK0_CLK3_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN401(CLK0_CLK4_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN401(CLK2_CLK2_DFS_CNTL, CLK20, 0) + +#define CLK_COMMON_MASK_SH_LIST_DCN401(mask_sh) \ + CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) + +#define CLK_REG_FIELD_LIST(type) \ + type DPREFCLK_SRC_SEL; \ + type DENTIST_DPREFCLK_WDIVIDER; \ + type DENTIST_DISPCLK_WDIVIDER; \ + type DENTIST_DISPCLK_CHG_DONE; + +#define CLK20_REG_FIELD_LIST(type) \ + type DENTIST_DPPCLK_WDIVIDER; \ + type DENTIST_DPPCLK_CHG_DONE; \ + type FbMult_int; \ + type FbMult_frac; + +/* + *************************************************************************************** + ****************** Clock Manager Private Structures *********************************** + *************************************************************************************** + */ + +struct clk_mgr_registers { + uint32_t DPREFCLK_CNTL; + uint32_t DENTIST_DISPCLK_CNTL; + + uint32_t CLK4_CLK2_CURRENT_CNT; + uint32_t CLK4_CLK_PLL_REQ; + + uint32_t CLK4_CLK0_CURRENT_CNT; + + uint32_t CLK3_CLK2_DFS_CNTL; + uint32_t CLK3_CLK_PLL_REQ; + + uint32_t CLK0_CLK2_DFS_CNTL; + uint32_t CLK0_CLK_PLL_REQ; + + uint32_t CLK1_CLK_PLL_REQ; + uint32_t CLK1_CLK0_DFS_CNTL; + uint32_t CLK1_CLK1_DFS_CNTL; + uint32_t CLK1_CLK2_DFS_CNTL; + uint32_t CLK1_CLK3_DFS_CNTL; + uint32_t CLK1_CLK4_DFS_CNTL; + uint32_t CLK1_CLK5_DFS_CNTL; + uint32_t CLK2_CLK2_DFS_CNTL; + + uint32_t CLK1_CLK0_CURRENT_CNT; + uint32_t CLK1_CLK1_CURRENT_CNT; + uint32_t CLK1_CLK2_CURRENT_CNT; + uint32_t CLK1_CLK3_CURRENT_CNT; + uint32_t CLK1_CLK4_CURRENT_CNT; + uint32_t CLK1_CLK5_CURRENT_CNT; + + uint32_t CLK0_CLK0_DFS_CNTL; + uint32_t CLK0_CLK1_DFS_CNTL; + uint32_t CLK0_CLK3_DFS_CNTL; + uint32_t CLK0_CLK4_DFS_CNTL; + uint32_t CLK1_CLK0_BYPASS_CNTL; + uint32_t CLK1_CLK1_BYPASS_CNTL; + uint32_t CLK1_CLK2_BYPASS_CNTL; + uint32_t CLK1_CLK3_BYPASS_CNTL; + uint32_t CLK1_CLK4_BYPASS_CNTL; + uint32_t CLK1_CLK5_BYPASS_CNTL; + + uint32_t CLK1_CLK0_DS_CNTL; + uint32_t CLK1_CLK1_DS_CNTL; + uint32_t CLK1_CLK2_DS_CNTL; + uint32_t CLK1_CLK3_DS_CNTL; + uint32_t CLK1_CLK4_DS_CNTL; + uint32_t CLK1_CLK5_DS_CNTL; + + uint32_t CLK1_CLK0_ALLOW_DS; + uint32_t CLK1_CLK1_ALLOW_DS; + uint32_t CLK1_CLK2_ALLOW_DS; + uint32_t CLK1_CLK3_ALLOW_DS; + uint32_t CLK1_CLK4_ALLOW_DS; + uint32_t CLK1_CLK5_ALLOW_DS; + uint32_t CLK5_spll_field_8; + uint32_t CLK6_spll_field_8; +}; + +struct clk_mgr_shift { + CLK_REG_FIELD_LIST(uint8_t) + CLK20_REG_FIELD_LIST(uint8_t) +}; + +struct clk_mgr_mask { + CLK_REG_FIELD_LIST(uint32_t) + CLK20_REG_FIELD_LIST(uint32_t) +}; + +enum clock_type { + clock_type_dispclk = 1, + clock_type_dcfclk, + clock_type_socclk, + clock_type_pixelclk, + clock_type_phyclk, + clock_type_dppclk, + clock_type_fclk, + clock_type_dcfdsclk, + clock_type_dscclk, + clock_type_uclk, + clock_type_dramclk, +}; + + +struct state_dependent_clocks { + int display_clk_khz; + int pixel_clk_khz; +}; + +struct clk_mgr_internal { + struct clk_mgr base; + int smu_ver; + struct pp_smu_funcs *pp_smu; + struct clk_mgr_internal_funcs *funcs; + + struct dccg *dccg; + + /* + * For backwards compatbility with previous implementation + * TODO: remove these after everything transitions to new pattern + * Rationale is that clk registers change a lot across DCE versions + * and a shared data structure doesn't really make sense. + */ + const struct clk_mgr_registers *regs; + const struct clk_mgr_shift *clk_mgr_shift; + const struct clk_mgr_mask *clk_mgr_mask; + + struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES]; + + /*TODO: figure out which of the below fields should be here vs in asic specific portion */ + /* Cache the status of DFS-bypass feature*/ + bool dfs_bypass_enabled; + /* True if the DFS-bypass feature is enabled and active. */ + bool dfs_bypass_active; + + uint32_t dfs_ref_freq_khz; + /* + * Cache the display clock returned by VBIOS if DFS-bypass is enabled. + * This is basically "Crystal Frequency In KHz" (XTALIN) frequency + */ + int dfs_bypass_disp_clk; + + /** + * @ss_on_dprefclk: + * + * True if spread spectrum is enabled on the DP ref clock. + */ + bool ss_on_dprefclk; + + /** + * @xgmi_enabled: + * + * True if xGMI is enabled. On VG20, both audio and display clocks need + * to be adjusted with the WAFL link's SS info if xGMI is enabled. + */ + bool xgmi_enabled; + + /** + * @dprefclk_ss_percentage: + * + * DPREFCLK SS percentage (if down-spread enabled). + * + * Note that if XGMI is enabled, the SS info (percentage and divider) + * from the WAFL link is used instead. This is decided during + * dce_clk_mgr initialization. + */ + int dprefclk_ss_percentage; + + /** + * @dprefclk_ss_divider: + * + * DPREFCLK SS percentage Divider (100 or 1000). + */ + int dprefclk_ss_divider; + + enum dm_pp_clocks_state max_clks_state; + enum dm_pp_clocks_state cur_min_clks_state; + bool periodic_retraining_disabled; + + unsigned int cur_phyclk_req_table[MAX_LINKS]; + + bool smu_present; + void *wm_range_table; + long long wm_range_table_addr; + + bool dpm_present; + bool pme_trigger_pending; +}; + +struct clk_mgr_internal_funcs { + int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); + int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr); +}; + + +/* + *************************************************************************************** + ****************** Clock Manager Level Helper functions ******************************* + *************************************************************************************** + */ + + +static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk) +{ + return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk); +} + +static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support) +{ + if (cur_support != calc_support) { + if (calc_support && safe_to_lower) + return true; + else if (!calc_support && !safe_to_lower) + return true; + } + + return false; +} + +static inline int khz_to_mhz_ceil(int khz) +{ + return (khz + 999) / 1000; +} + +static inline int khz_to_mhz_floor(int khz) +{ + return khz / 1000; +} + +int clk_mgr_helper_get_active_display_cnt( + struct dc *dc, + struct dc_state *context); + +int clk_mgr_helper_get_active_plane_cnt( + struct dc *dc, + struct dc_state *context); + + + +#endif //__DAL_CLK_MGR_INTERNAL_H__ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h b/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h new file mode 100644 index 000000000000..7ce2f417f86a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2022 Advanced Micro Devices, Inc. All rights reserved. */ + +#ifndef __DAL_CURSOR_CACHE_H__ +#define __DAL_CURSOR_CACHE_H__ + +union reg_cursor_control_cfg { + struct { + uint32_t cur_enable: 1; + uint32_t reser0: 3; + uint32_t cur_2x_magnify: 1; + uint32_t reser1: 3; + uint32_t mode: 3; + uint32_t reser2: 5; + uint32_t pitch: 2; + uint32_t reser3: 6; + uint32_t line_per_chunk: 5; + uint32_t reser4: 3; + } bits; + uint32_t raw; +}; +struct cursor_position_cache_hubp { + union reg_cursor_control_cfg cur_ctl; + union reg_position_cfg { + struct { + uint32_t x_pos: 16; + uint32_t y_pos: 16; + } bits; + uint32_t raw; + } position; + union reg_hot_spot_cfg { + struct { + uint32_t x_hot: 16; + uint32_t y_hot: 16; + } bits; + uint32_t raw; + } hot_spot; + union reg_dst_offset_cfg { + struct { + uint32_t dst_x_offset: 13; + uint32_t reserved: 19; + } bits; + uint32_t raw; + } dst_offset; +}; + +struct cursor_attribute_cache_hubp { + uint32_t SURFACE_ADDR_HIGH; + uint32_t SURFACE_ADDR; + union reg_cursor_control_cfg cur_ctl; + union reg_cursor_size_cfg { + struct { + uint32_t width: 16; + uint32_t height: 16; + } bits; + uint32_t raw; + } size; + union reg_cursor_settings_cfg { + struct { + uint32_t dst_y_offset: 8; + uint32_t chunk_hdl_adjust: 2; + uint32_t reserved: 22; + } bits; + uint32_t raw; + } settings; +}; + +struct cursor_rect { + uint32_t x; + uint32_t y; + uint32_t w; + uint32_t h; +}; + +union reg_cur0_control_cfg { + struct { + uint32_t cur0_enable: 1; + uint32_t expansion_mode: 1; + uint32_t reser0: 1; + uint32_t cur0_rom_en: 1; + uint32_t mode: 3; + uint32_t reserved: 25; + } bits; + uint32_t raw; +}; + +struct cursor_position_cache_dpp { + union reg_cur0_control_cfg cur0_ctl; +}; + +struct cursor_attribute_cache_dpp { + union reg_cur0_control_cfg cur0_ctl; + union reg_cur0_fp_scale_bias { + struct { + uint32_t fp_bias: 16; + uint32_t fp_scale: 16; + } bits; + uint32_t raw; + } fp_scale_bias; + union reg_cur0_fp_scale_bias_g_y { + struct { + uint32_t fp_bias_g_y: 16; + uint32_t fp_scale_g_y: 16; + } bits; + uint32_t raw; + } fp_scale_bias_g_y; + union reg_cur0_fp_scale_bias_rb_crcb { + struct { + uint32_t fp_bias_rb_crcb: 16; + uint32_t fp_scale_rb_crcb: 16; + } bits; + uint32_t raw; + } fp_scale_bias_rb_crcb; +}; + +struct cursor_attributes_cfg { + struct cursor_attribute_cache_hubp aHubp; + struct cursor_attribute_cache_dpp aDpp; +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h new file mode 100644 index 000000000000..500a601e99b5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -0,0 +1,338 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_DCCG_H__ +#define __DAL_DCCG_H__ + +#include "dc_types.h" +#include "hw_shared.h" + +enum phyd32clk_clock_source { + PHYD32CLKA, + PHYD32CLKB, + PHYD32CLKC, + PHYD32CLKD, + PHYD32CLKE, + PHYD32CLKF, + PHYD32CLKG, +}; + +enum physymclk_clock_source { + PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through DCIO. + PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO. + PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO. +}; + +enum streamclk_source { + REFCLK, // Selects REFCLK as source for hdmistreamclk. + DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk. + DPREFCLK, // Selects DPREFCLK as source for hdmistreamclk +}; + +enum dentist_dispclk_change_mode { + DISPCLK_CHANGE_MODE_IMMEDIATE, + DISPCLK_CHANGE_MODE_RAMPING, +}; + +struct dp_dto_params { + int otg_inst; + enum signal_type signal; + enum streamclk_source clk_src; + uint64_t pixclk_hz; + uint64_t refclk_hz; +}; + +enum pixel_rate_div { + PIXEL_RATE_DIV_BY_1 = 0, + PIXEL_RATE_DIV_BY_2 = 1, + PIXEL_RATE_DIV_BY_4 = 3, + PIXEL_RATE_DIV_NA = 0xF +}; + +struct dcn_dccg_reg_state { + uint32_t dc_mem_global_pwr_req_cntl; + uint32_t dccg_audio_dtbclk_dto_modulo; + uint32_t dccg_audio_dtbclk_dto_phase; + uint32_t dccg_audio_dto_source; + uint32_t dccg_audio_dto0_module; + uint32_t dccg_audio_dto0_phase; + uint32_t dccg_audio_dto1_module; + uint32_t dccg_audio_dto1_phase; + uint32_t dccg_cac_status; + uint32_t dccg_cac_status2; + uint32_t dccg_disp_cntl_reg; + uint32_t dccg_ds_cntl; + uint32_t dccg_ds_dto_incr; + uint32_t dccg_ds_dto_modulo; + uint32_t dccg_ds_hw_cal_interval; + uint32_t dccg_gate_disable_cntl; + uint32_t dccg_gate_disable_cntl2; + uint32_t dccg_gate_disable_cntl3; + uint32_t dccg_gate_disable_cntl4; + uint32_t dccg_gate_disable_cntl5; + uint32_t dccg_gate_disable_cntl6; + uint32_t dccg_global_fgcg_rep_cntl; + uint32_t dccg_gtc_cntl; + uint32_t dccg_gtc_current; + uint32_t dccg_gtc_dto_incr; + uint32_t dccg_gtc_dto_modulo; + uint32_t dccg_perfmon_cntl; + uint32_t dccg_perfmon_cntl2; + uint32_t dccg_soft_reset; + uint32_t dccg_test_clk_sel; + uint32_t dccg_vsync_cnt_ctrl; + uint32_t dccg_vsync_cnt_int_ctrl; + uint32_t dccg_vsync_otg0_latch_value; + uint32_t dccg_vsync_otg1_latch_value; + uint32_t dccg_vsync_otg2_latch_value; + uint32_t dccg_vsync_otg3_latch_value; + uint32_t dccg_vsync_otg4_latch_value; + uint32_t dccg_vsync_otg5_latch_value; + uint32_t dispclk_cgtt_blk_ctrl_reg; + uint32_t dispclk_freq_change_cntl; + uint32_t dp_dto_dbuf_en; + uint32_t dp_dto0_modulo; + uint32_t dp_dto0_phase; + uint32_t dp_dto1_modulo; + uint32_t dp_dto1_phase; + uint32_t dp_dto2_modulo; + uint32_t dp_dto2_phase; + uint32_t dp_dto3_modulo; + uint32_t dp_dto3_phase; + uint32_t dpiaclk_540m_dto_modulo; + uint32_t dpiaclk_540m_dto_phase; + uint32_t dpiaclk_810m_dto_modulo; + uint32_t dpiaclk_810m_dto_phase; + uint32_t dpiaclk_dto_cntl; + uint32_t dpiasymclk_cntl; + uint32_t dppclk_cgtt_blk_ctrl_reg; + uint32_t dppclk_ctrl; + uint32_t dppclk_dto_ctrl; + uint32_t dppclk0_dto_param; + uint32_t dppclk1_dto_param; + uint32_t dppclk2_dto_param; + uint32_t dppclk3_dto_param; + uint32_t dprefclk_cgtt_blk_ctrl_reg; + uint32_t dprefclk_cntl; + uint32_t dpstreamclk_cntl; + uint32_t dscclk_dto_ctrl; + uint32_t dscclk0_dto_param; + uint32_t dscclk1_dto_param; + uint32_t dscclk2_dto_param; + uint32_t dscclk3_dto_param; + uint32_t dtbclk_dto_dbuf_en; + uint32_t dtbclk_dto0_modulo; + uint32_t dtbclk_dto0_phase; + uint32_t dtbclk_dto1_modulo; + uint32_t dtbclk_dto1_phase; + uint32_t dtbclk_dto2_modulo; + uint32_t dtbclk_dto2_phase; + uint32_t dtbclk_dto3_modulo; + uint32_t dtbclk_dto3_phase; + uint32_t dtbclk_p_cntl; + uint32_t force_symclk_disable; + uint32_t hdmicharclk0_clock_cntl; + uint32_t hdmistreamclk_cntl; + uint32_t hdmistreamclk0_dto_param; + uint32_t microsecond_time_base_div; + uint32_t millisecond_time_base_div; + uint32_t otg_pixel_rate_div; + uint32_t otg0_phypll_pixel_rate_cntl; + uint32_t otg0_pixel_rate_cntl; + uint32_t otg1_phypll_pixel_rate_cntl; + uint32_t otg1_pixel_rate_cntl; + uint32_t otg2_phypll_pixel_rate_cntl; + uint32_t otg2_pixel_rate_cntl; + uint32_t otg3_phypll_pixel_rate_cntl; + uint32_t otg3_pixel_rate_cntl; + uint32_t phyasymclk_clock_cntl; + uint32_t phybsymclk_clock_cntl; + uint32_t phycsymclk_clock_cntl; + uint32_t phydsymclk_clock_cntl; + uint32_t phyesymclk_clock_cntl; + uint32_t phyplla_pixclk_resync_cntl; + uint32_t phypllb_pixclk_resync_cntl; + uint32_t phypllc_pixclk_resync_cntl; + uint32_t phyplld_pixclk_resync_cntl; + uint32_t phyplle_pixclk_resync_cntl; + uint32_t refclk_cgtt_blk_ctrl_reg; + uint32_t socclk_cgtt_blk_ctrl_reg; + uint32_t symclk_cgtt_blk_ctrl_reg; + uint32_t symclk_psp_cntl; + uint32_t symclk32_le_cntl; + uint32_t symclk32_se_cntl; + uint32_t symclka_clock_enable; + uint32_t symclkb_clock_enable; + uint32_t symclkc_clock_enable; + uint32_t symclkd_clock_enable; + uint32_t symclke_clock_enable; +}; + +struct dccg { + struct dc_context *ctx; + const struct dccg_funcs *funcs; + int pipe_dppclk_khz[MAX_PIPES]; + int ref_dppclk; + bool dpp_clock_gated[MAX_PIPES]; + //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */ + //int audio_dtbclk_khz;/* TODO needs to be removed */ + //int ref_dtbclk_khz;/* TODO needs to be removed */ +}; +struct dtbclk_dto_params { + const struct dc_crtc_timing *timing; + int otg_inst; + int pixclk_khz; + int req_audio_dtbclk_khz; + int num_odm_segments; + int ref_dtbclk_khz; + bool is_hdmi; +}; + +struct dccg_funcs { + void (*update_dpp_dto)(struct dccg *dccg, + int dpp_inst, + int req_dppclk); + void (*get_dccg_ref_freq)(struct dccg *dccg, + unsigned int xtalin_freq_inKhz, + unsigned int *dccg_ref_freq_inKhz); + void (*set_fifo_errdet_ovr_en)(struct dccg *dccg, + bool en); + void (*otg_add_pixel)(struct dccg *dccg, + uint32_t otg_inst); + void (*otg_drop_pixel)(struct dccg *dccg, + uint32_t otg_inst); + void (*dccg_init)(struct dccg *dccg); + void (*set_dpstreamclk_root_clock_gating)( + struct dccg *dccg, + int dp_hpo_inst, + bool enable); + + void (*set_dpstreamclk)( + struct dccg *dccg, + enum streamclk_source src, + int otg_inst, + int dp_hpo_inst); + + void (*enable_symclk32_se)( + struct dccg *dccg, + int hpo_se_inst, + enum phyd32clk_clock_source phyd32clk); + + void (*disable_symclk32_se)( + struct dccg *dccg, + int hpo_se_inst); + + void (*enable_symclk32_le)( + struct dccg *dccg, + int hpo_le_inst, + enum phyd32clk_clock_source phyd32clk); + + void (*disable_symclk32_le)( + struct dccg *dccg, + int hpo_le_inst); + + void (*set_symclk32_le_root_clock_gating)( + struct dccg *dccg, + int hpo_le_inst, + bool enable); + + void (*set_physymclk)( + struct dccg *dccg, + int phy_inst, + enum physymclk_clock_source clk_src, + bool force_enable); + + void (*set_physymclk_root_clock_gating)( + struct dccg *dccg, + int phy_inst, + bool enable); + + void (*set_dtbclk_dto)( + struct dccg *dccg, + const struct dtbclk_dto_params *params); + + void (*set_audio_dtbclk_dto)( + struct dccg *dccg, + const struct dtbclk_dto_params *params); + + void (*set_dispclk_change_mode)( + struct dccg *dccg, + enum dentist_dispclk_change_mode change_mode); + + void (*disable_dsc)( + struct dccg *dccg, + int inst); + + void (*enable_dsc)( + struct dccg *dccg, + int inst); + + void (*set_pixel_rate_div)(struct dccg *dccg, + uint32_t otg_inst, + enum pixel_rate_div k1, + enum pixel_rate_div k2); + + void (*get_pixel_rate_div)(struct dccg *dccg, + uint32_t otg_inst, + uint32_t *div_factor1, + uint32_t *div_factor2); + + void (*set_valid_pixel_rate)( + struct dccg *dccg, + int ref_dtbclk_khz, + int otg_inst, + int pixclk_khz); + + void (*trigger_dio_fifo_resync)( + struct dccg *dccg); + + void (*dpp_root_clock_control)( + struct dccg *dccg, + unsigned int dpp_inst, + bool clock_on); + + void (*enable_symclk_se)( + struct dccg *dccg, + uint32_t stream_enc_inst, + uint32_t link_enc_inst); + + void (*disable_symclk_se)( + struct dccg *dccg, + uint32_t stream_enc_inst, + uint32_t link_enc_inst); + void (*set_dp_dto)( + struct dccg *dccg, + const struct dp_dto_params *params); + void (*set_dtbclk_p_src)( + struct dccg *dccg, + enum streamclk_source src, + uint32_t otg_inst); + void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h); + void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst); + void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); + void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state); +}; + +#endif //__DAL_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h new file mode 100644 index 000000000000..1ddfa30411c8 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -0,0 +1,296 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_DCHUBBUB_H__ +#define __DAL_DCHUBBUB_H__ + +/** + * DOC: overview + * + * There is only one common DCHUBBUB. It contains the common request and return + * blocks for the Data Fabric Interface that are not clock/power gated. + */ + +#include "dc/dc_hw_types.h" + +enum dcc_control { + dcc_control__256_256_xxx, + dcc_control__128_128_xxx, + dcc_control__256_64_64, + dcc_control__256_128_128, + dcc_control__256_256, + dcc_control__256_128, + dcc_control__256_64, + +}; + +enum segment_order { + segment_order__na, + segment_order__contiguous, + segment_order__non_contiguous, +}; + +struct dcn_hubbub_wm_set { + uint32_t wm_set; + uint32_t data_urgent; + uint32_t pte_meta_urgent; + uint32_t sr_enter; + uint32_t sr_exit; + uint32_t dram_clk_change; + uint32_t usr_retrain; + uint32_t fclk_pstate_change; + uint32_t sr_enter_exit_Z8; + uint32_t sr_enter_Z8; +}; + +struct dcn_hubbub_wm { + struct dcn_hubbub_wm_set sets[4]; +}; + +enum dcn_hubbub_page_table_depth { + DCN_PAGE_TABLE_DEPTH_1_LEVEL, + DCN_PAGE_TABLE_DEPTH_2_LEVEL, + DCN_PAGE_TABLE_DEPTH_3_LEVEL, + DCN_PAGE_TABLE_DEPTH_4_LEVEL +}; + +enum dcn_hubbub_page_table_block_size { + DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0, + DCN_PAGE_TABLE_BLOCK_SIZE_8KB = 1, + DCN_PAGE_TABLE_BLOCK_SIZE_16KB = 2, + DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3, + DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4, + DCN_PAGE_TABLE_BLOCK_SIZE_128KB = 5, + DCN_PAGE_TABLE_BLOCK_SIZE_256KB = 6, + DCN_PAGE_TABLE_BLOCK_SIZE_512KB = 7, + DCN_PAGE_TABLE_BLOCK_SIZE_1024KB = 8, + DCN_PAGE_TABLE_BLOCK_SIZE_2048KB = 9 +}; + +struct dcn_hubbub_phys_addr_config { + struct { + uint64_t fb_top; + uint64_t fb_offset; + uint64_t fb_base; + uint64_t agp_top; + uint64_t agp_bot; + uint64_t agp_base; + } system_aperture; + + struct { + uint64_t page_table_start_addr; + uint64_t page_table_end_addr; + uint64_t page_table_base_addr; + } gart_config; + + uint64_t page_table_default_page_addr; +}; + +struct dcn_hubbub_virt_addr_config { + uint64_t page_table_start_addr; + uint64_t page_table_end_addr; + enum dcn_hubbub_page_table_block_size page_table_block_size; + enum dcn_hubbub_page_table_depth page_table_depth; + uint64_t page_table_base_addr; +}; + +struct hubbub_addr_config { + struct dcn_hubbub_phys_addr_config pa_config; + struct dcn_hubbub_virt_addr_config va_config; + struct { + uint64_t aperture_check_fault; + uint64_t generic_fault; + } default_addrs; +}; + +struct dcn_hubbub_state { + uint32_t vm_fault_addr_msb; + uint32_t vm_fault_addr_lsb; + uint32_t vm_error_status; + uint32_t vm_error_vmid; + uint32_t vm_error_pipe; + uint32_t vm_error_mode; + uint32_t test_debug_data; + uint32_t watermark_change_cntl; + uint32_t dram_state_cntl; +}; + +struct dcn_hubbub_reg_state { + uint32_t det0_ctrl; + uint32_t det1_ctrl; + uint32_t det2_ctrl; + uint32_t det3_ctrl; + uint32_t compbuf_ctrl; +}; + +struct hubbub_system_latencies { + uint32_t max_latency_ns; + uint32_t avg_latency_ns; + uint32_t min_latency_ns; +}; + +struct hubbub_urgent_latency_params { + uint32_t refclk_mhz; + uint32_t t_win_ns; + uint32_t bandwidth_mbps; + uint32_t bw_factor_x1000; +}; + +struct hubbub_funcs { + void (*update_dchub)( + struct hubbub *hubbub, + struct dchub_init_data *dh_data); + + int (*init_dchub_sys_ctx)( + struct hubbub *hubbub, + struct dcn_hubbub_phys_addr_config *pa_config); + void (*init_vm_ctx)( + struct hubbub *hubbub, + struct dcn_hubbub_virt_addr_config *va_config, + int vmid); + + bool (*get_dcc_compression_cap)(struct hubbub *hubbub, + const struct dc_dcc_surface_param *input, + struct dc_surface_dcc_cap *output); + + bool (*dcc_support_swizzle)( + enum swizzle_mode_values swizzle, + unsigned int bytes_per_element, + enum segment_order *segment_order_horz, + enum segment_order *segment_order_vert); + + bool (*dcc_support_swizzle_addr3)( + enum swizzle_mode_addr3_values swizzle, + unsigned int plane_pitch, + unsigned int bytes_per_element, + enum segment_order *segment_order_horz, + enum segment_order *segment_order_vert); + + bool (*dcc_support_pixel_format_plane0_plane1)( + enum surface_pixel_format format, + unsigned int *plane0_bpe, + unsigned int *plane1_bpe); + bool (*dcc_support_pixel_format)( + enum surface_pixel_format format, + unsigned int *bytes_per_element); + + void (*wm_read_state)(struct hubbub *hubbub, + struct dcn_hubbub_wm *wm); + + void (*get_dchub_ref_freq)(struct hubbub *hubbub, + unsigned int dccg_ref_freq_inKhz, + unsigned int *dchub_ref_freq_inKhz); + + bool (*program_watermarks)( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower); + + bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub); + void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow); + + bool (*verify_allow_pstate_change_high)(struct hubbub *hubbub); + + void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub); + + void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub); + + void (*hubbub_read_state)(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state); + + void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow); + + void (*init_watermarks)(struct hubbub *hubbub); + + void (*hubbub_read_reg_state)(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state); + + /** + * @program_det_size: + * + * DE-Tile buffers (DET) is a memory that is used to convert the tiled + * data into linear, which the rest of the display can use to generate + * the graphics output. One of the main features of this component is + * that each pipe has a configurable DET buffer which means that when a + * pipe is not enabled, the device can assign the memory to other + * enabled pipes to try to be more efficient. + * + * DET logic is handled by dchubbub. Some ASICs provide a feature named + * Configurable Return Buffer (CRB) segments which can be allocated to + * compressed or detiled buffers. + */ + void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte); + void (*wait_for_det_apply)(struct hubbub *hubbub, int hubp_inst); + void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase); + void (*init_crb)(struct hubbub *hubbub); + void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow); + void (*set_request_limit)(struct hubbub *hubbub, int memory_channel_count, int words_per_channel); + void (*dchubbub_init)(struct hubbub *hubbub); + void (*get_mall_en)(struct hubbub *hubbub, unsigned int *mall_in_use); + void (*program_det_segments)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg); + void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); + void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst); + bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower); + void (*dchvm_init)(struct hubbub *hubbub); + + struct hubbub_perfmon_funcs { + void (*reset)(struct hubbub *hubbub); + void (*start_measuring_max_memory_latency_ns)( + struct hubbub *hubbub); + uint32_t (*get_max_memory_latency_ns)(struct hubbub *hubbub, + uint32_t refclk_mhz, uint32_t *sample_count); + void (*start_measuring_average_memory_latency_ns)( + struct hubbub *hubbub); + uint32_t (*get_average_memory_latency_ns)(struct hubbub *hubbub, + uint32_t refclk_mhz, uint32_t *sample_count); + void (*start_measuring_urgent_ramp_latency_ns)( + struct hubbub *hubbub, + const struct hubbub_urgent_latency_params *params); + uint32_t (*get_urgent_ramp_latency_ns)(struct hubbub *hubbub, + uint32_t refclk_mhz); + void (*start_measuring_unbounded_bandwidth_mbps)( + struct hubbub *hubbub); + uint32_t (*get_unbounded_bandwidth_mbps)(struct hubbub *hubbub, + uint32_t refclk_mhz, uint32_t *duration_ns); + void (*start_measuring_average_bandwidth_mbps)( + struct hubbub *hubbub); + uint32_t (*get_average_bandwidth_mbps)(struct hubbub *hubbub, + uint32_t refclk_mhz, uint32_t min_duration_ns, + uint32_t *duration_ns); + } perfmon; + + struct hubbub_qos_funcs { + void (*force_display_nominal_profile)(struct hubbub *hubbub); + void (*force_display_urgent_profile)(struct hubbub *hubbub); + void (*reset_display_qos_profile)(struct hubbub *hubbub); + } qos; +}; + +struct hubbub { + const struct hubbub_funcs *funcs; + struct dc_context *ctx; + bool riommu_active; +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h new file mode 100644 index 000000000000..de3113ecbc77 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h @@ -0,0 +1,96 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_DMCU_H__ +#define __DC_DMCU_H__ + +#include "dm_services_types.h" + +/* If HW itself ever powered down it will be 0. + * fwDmcuInit will write to 1. + * Driver will only call MCP init if current state is 1, + * and the MCP command will transition this to 2. + */ +enum dmcu_state { + DMCU_UNLOADED = 0, + DMCU_LOADED_UNINITIALIZED = 1, + DMCU_RUNNING = 2, +}; + +struct dmcu_version { + unsigned int interface_version; + unsigned int abm_version; + unsigned int psr_version; + unsigned int build_version; +}; + +struct dmcu { + struct dc_context *ctx; + const struct dmcu_funcs *funcs; + + enum dmcu_state dmcu_state; + struct dmcu_version dmcu_version; + unsigned int cached_wait_loop_number; + uint32_t psp_version; + bool auto_load_dmcu; +}; + +struct dmcu_funcs { + bool (*dmcu_init)(struct dmcu *dmcu); + bool (*load_iram)(struct dmcu *dmcu, + unsigned int start_offset, + const char *src, + unsigned int bytes); + void (*set_psr_enable)(struct dmcu *dmcu, bool enable, bool wait); + bool (*setup_psr)(struct dmcu *dmcu, + struct dc_link *link, + struct psr_context *psr_context); + void (*get_psr_state)(struct dmcu *dmcu, enum dc_psr_state *dc_psr_state); + void (*set_psr_wait_loop)(struct dmcu *dmcu, + unsigned int wait_loop_number); + void (*get_psr_wait_loop)(struct dmcu *dmcu, + unsigned int *psr_wait_loop_number); + bool (*is_dmcu_initialized)(struct dmcu *dmcu); + bool (*lock_phy)(struct dmcu *dmcu); + bool (*unlock_phy)(struct dmcu *dmcu); + bool (*send_edid_cea)(struct dmcu *dmcu, + int offset, + int total_length, + uint8_t *data, + int length); + bool (*recv_amd_vsdb)(struct dmcu *dmcu, + int *version, + int *min_frame_rate, + int *max_frame_rate); + bool (*recv_edid_cea_ack)(struct dmcu *dmcu, int *offset); +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + void (*forward_crc_window)(struct dmcu *dmcu, + struct rect *rect, + struct otg_phy_mux *mux_mapping); + void (*stop_crc_win_update)(struct dmcu *dmcu, + struct otg_phy_mux *mux_mapping); +#endif +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h new file mode 100644 index 000000000000..d88b57d4f512 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -0,0 +1,374 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + + +#ifndef __DAL_DPP_H__ +#define __DAL_DPP_H__ + +/** + * DOC: overview + * + * The DPP (Display Pipe and Plane) block is the unified display data + * processing engine in DCN for processing graphic or video data on per DPP + * rectangle base. This rectangle can be a part of SLS (Single Large Surface), + * or a layer to be blended with other DPP, or a rectangle associated with a + * display tile. + * + * It provides various functions including: + * - graphic color keyer + * - graphic cursor compositing + * - graphic or video image source to destination scaling + * - image sharping + * - video format conversion from 4:2:0 or 4:2:2 to 4:4:4 + * - Color Space Conversion + * - Host LUT gamma adjustment + * - Color Gamut Remap + * - brightness and contrast adjustment. + * + * DPP pipe consists of Converter and Cursor (CNVC), Scaler (DSCL), Color + * Management (CM), Output Buffer (OBUF) and Digital Bypass (DPB) module + * connected in a video/graphics pipeline. + */ + +#include "transform.h" +#include "cursor_reg_cache.h" + +union defer_reg_writes { + struct { + bool disable_blnd_lut:1; + bool disable_3dlut:1; + bool disable_shaper:1; + bool disable_gamcor:1; + bool disable_dscl:1; + } bits; + uint32_t raw; +}; +struct dpp { + const struct dpp_funcs *funcs; + struct dc_context *ctx; + /** + * @inst: + * + * inst stands for "instance," and it is an id number that references a + * specific DPP. + */ + int inst; + struct dpp_caps *caps; + struct pwl_params regamma_params; + struct pwl_params degamma_params; + struct dpp_cursor_attributes cur_attr; + union defer_reg_writes deferred_reg_writes; + + struct pwl_params shaper_params; + bool cm_bypass_mode; + bool cursor_offload; + + struct cursor_position_cache_dpp pos; + struct cursor_attribute_cache_dpp att; +}; + +struct dpp_input_csc_matrix { + enum dc_color_space color_space; + uint16_t regval[12]; +}; + +static const struct dpp_input_csc_matrix __maybe_unused dpp_input_csc_matrix[] = { + { COLOR_SPACE_SRGB, + { 0x2000, 0, 0, 0, + 0, 0x2000, 0, 0, + 0, 0, 0x2000, 0 } }, + { COLOR_SPACE_SRGB_LIMITED, + { 0x2000, 0, 0, 0, + 0, 0x2000, 0, 0, + 0, 0, 0x2000, 0 } }, + { COLOR_SPACE_YCBCR601, + { 0x2cdd, 0x2000, 0, 0xe991, + 0xe926, 0x2000, 0xf4fd, 0x10ef, + 0, 0x2000, 0x38b4, 0xe3a6 } }, + { COLOR_SPACE_YCBCR601_LIMITED, + { 0x3353, 0x2568, 0, 0xe400, + 0xe5dc, 0x2568, 0xf367, 0x1108, + 0, 0x2568, 0x40de, 0xdd3a } }, + { COLOR_SPACE_YCBCR709, + { 0x3265, 0x2000, 0, 0xe6ce, + 0xf105, 0x2000, 0xfa01, 0xa7d, + 0, 0x2000, 0x3b61, 0xe24f } }, + { COLOR_SPACE_YCBCR709_LIMITED, + { 0x39a6, 0x2568, 0, 0xe0d6, + 0xeedd, 0x2568, 0xf925, 0x9a8, + 0, 0x2568, 0x43ee, 0xdbb2 } }, + { COLOR_SPACE_2020_YCBCR_FULL, + { 0x2F30, 0x2000, 0, 0xE869, + 0xEDB7, 0x2000, 0xFABC, 0xBC6, + 0, 0x2000, 0x3C34, 0xE1E6 } }, + { COLOR_SPACE_2020_YCBCR_LIMITED, + { 0x35B9, 0x2543, 0, 0xE2B2, + 0xEB2F, 0x2543, 0xFA01, 0x0B1F, + 0, 0x2543, 0x4489, 0xDB42 } }, + { COLOR_SPACE_2020_RGB_LIMITEDRANGE, + { 0x35E0, 0x255F, 0, 0xE2B3, + 0xEB20, 0x255F, 0xF9FD, 0xB1E, + 0, 0x255F, 0x44BD, 0xDB43 } } +}; + +struct dpp_grph_csc_adjustment { + struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE]; + enum graphics_gamut_adjust_type gamut_adjust_type; +}; + +struct cnv_color_keyer_params { + int color_keyer_en; + int color_keyer_mode; + int color_keyer_alpha_low; + int color_keyer_alpha_high; + int color_keyer_red_low; + int color_keyer_red_high; + int color_keyer_green_low; + int color_keyer_green_high; + int color_keyer_blue_low; + int color_keyer_blue_high; +}; + +/** + * struct cnv_alpha_2bit_lut - Set the 8bit alpha values based on the 2 bit alpha + */ +struct cnv_alpha_2bit_lut { + /** + * @lut0: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0. Default: 0b00000000 + */ + int lut0; + + /** + * @lut1: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1. Default: 0b01010101 + */ + int lut1; + + /** + * @lut2: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2. Default: 0b10101010 + */ + int lut2; + + /** + * @lut3: ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3. Default: 0b11111111 + */ + int lut3; +}; + +struct dcn_dpp_state { + uint32_t is_enabled; + uint32_t igam_lut_mode; + uint32_t igam_input_format; + uint32_t dgam_lut_mode; + uint32_t rgam_lut_mode; + // gamut_remap data for dcn10_get_cm_states() + uint32_t gamut_remap_mode; + uint32_t gamut_remap_c11_c12; + uint32_t gamut_remap_c13_c14; + uint32_t gamut_remap_c21_c22; + uint32_t gamut_remap_c23_c24; + uint32_t gamut_remap_c31_c32; + uint32_t gamut_remap_c33_c34; + // gamut_remap data for dcn*_log_color_state() + struct dpp_grph_csc_adjustment gamut_remap; + uint32_t shaper_lut_mode; + uint32_t lut3d_mode; + uint32_t lut3d_bit_depth; + uint32_t lut3d_size; + uint32_t blnd_lut_mode; + uint32_t pre_dgam_mode; + uint32_t pre_dgam_select; + uint32_t gamcor_mode; +}; + +struct dcn_dpp_reg_state { + uint32_t recout_start; + uint32_t recout_size; + uint32_t scl_horz_filter_scale_ratio; + uint32_t scl_vert_filter_scale_ratio; + uint32_t scl_mode; + uint32_t cm_control; + uint32_t dpp_control; + uint32_t dscl_control; + uint32_t obuf_control; + uint32_t mpc_size; +}; + +struct CM_bias_params { + uint32_t cm_bias_cr_r; + uint32_t cm_bias_y_g; + uint32_t cm_bias_cb_b; + uint32_t cm_bias_format; +}; + +struct dpp_funcs { + bool (*dpp_program_gamcor_lut)( + struct dpp *dpp_base, const struct pwl_params *params); + + void (*dpp_set_pre_degam)(struct dpp *dpp_base, + enum dc_transfer_func_predefined tr); + + void (*dpp_program_cm_dealpha)(struct dpp *dpp_base, + uint32_t enable, uint32_t additive_blending); + + void (*dpp_program_cm_bias)( + struct dpp *dpp_base, + struct CM_bias_params *bias_params); + + void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s); + + void (*dpp_read_reg_state)(struct dpp *dpp, struct dcn_dpp_reg_state *dpp_reg_state); + + void (*dpp_reset)(struct dpp *dpp); + + void (*dpp_set_scaler)(struct dpp *dpp, + const struct scaler_data *scl_data); + + void (*dpp_set_pixel_storage_depth)( + struct dpp *dpp, + enum lb_pixel_depth depth, + const struct bit_depth_reduction_params *bit_depth_params); + + bool (*dpp_get_optimal_number_of_taps)( + struct dpp *dpp, + struct scaler_data *scl_data, + const struct scaling_taps *in_taps); + + void (*dpp_set_gamut_remap)( + struct dpp *dpp, + const struct dpp_grph_csc_adjustment *adjust); + + void (*dpp_set_csc_default)( + struct dpp *dpp, + enum dc_color_space colorspace); + + void (*dpp_set_csc_adjustment)( + struct dpp *dpp, + const uint16_t *regval); + + void (*dpp_power_on_regamma_lut)( + struct dpp *dpp, + bool power_on); + + void (*dpp_program_regamma_lut)( + struct dpp *dpp, + const struct pwl_result_data *rgb, + uint32_t num); + + void (*dpp_configure_regamma_lut)( + struct dpp *dpp, + bool is_ram_a); + + void (*dpp_program_regamma_lutb_settings)( + struct dpp *dpp, + const struct pwl_params *params); + + void (*dpp_program_regamma_luta_settings)( + struct dpp *dpp, + const struct pwl_params *params); + + void (*dpp_program_regamma_pwl)( + struct dpp *dpp, + const struct pwl_params *params, + enum opp_regamma mode); + + void (*dpp_program_bias_and_scale)( + struct dpp *dpp, + struct dc_bias_and_scale *params); + + void (*dpp_set_degamma)( + struct dpp *dpp_base, + enum ipp_degamma_mode mode); + + void (*dpp_program_input_lut)( + struct dpp *dpp_base, + const struct dc_gamma *gamma); + + void (*dpp_program_degamma_pwl)(struct dpp *dpp_base, + const struct pwl_params *params); + + void (*dpp_setup)( + struct dpp *dpp_base, + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space, + struct cnv_alpha_2bit_lut *alpha_2bit_lut); + + void (*dpp_full_bypass)(struct dpp *dpp_base); + + void (*set_cursor_attributes)( + struct dpp *dpp_base, + struct dc_cursor_attributes *cursor_attributes); + + void (*set_cursor_position)( + struct dpp *dpp_base, + const struct dc_cursor_position *pos, + const struct dc_cursor_mi_param *param, + uint32_t width, + uint32_t height + ); + + void (*dpp_set_hdr_multiplier)( + struct dpp *dpp_base, + uint32_t multiplier); + + void (*set_optional_cursor_attributes)( + struct dpp *dpp_base, + struct dpp_cursor_attributes *attr); + + void (*dpp_dppclk_control)( + struct dpp *dpp_base, + bool dppclk_div, + bool enable); + + void (*dpp_deferred_update)( + struct dpp *dpp); + bool (*dpp_program_blnd_lut)( + struct dpp *dpp, + const struct pwl_params *params); + bool (*dpp_program_shaper_lut)( + struct dpp *dpp, + const struct pwl_params *params); + bool (*dpp_program_3dlut)( + struct dpp *dpp, + const struct tetrahedral_params *params); + void (*dpp_cnv_set_alpha_keyer)( + struct dpp *dpp_base, + struct cnv_color_keyer_params *color_keyer); + + void (*dpp_get_gamut_remap)(struct dpp *dpp_base, + struct dpp_grph_csc_adjustment *adjust); + void (*set_cursor_matrix)( + struct dpp *dpp_base, + enum dc_color_space color_space, + struct dc_csc_transform cursor_csc_color_matrix); + + void (*dpp_force_disable_cursor)(struct dpp *dpp_base); + +}; + + + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h new file mode 100644 index 000000000000..063efc8128a7 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h @@ -0,0 +1,240 @@ +/* Copyright 2012-17 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_DWBC_H__ +#define __DC_DWBC_H__ + +#include "dal_types.h" +#include "dc_hw_types.h" + +#define DWB_SW_V2 1 +#define DWB_MCIF_BUF_COUNT 4 + +/* forward declaration of mcif_wb struct */ +struct mcif_wb; + + +enum dwb_sw_version { + dwb_ver_1_0 = 1, + dwb_ver_2_0 = 2, +}; + +enum dwb_source { + dwb_src_scl = 0, /* for DCE7x/9x, DCN won't support. */ + dwb_src_blnd, /* for DCE7x/9x */ + dwb_src_fmt, /* for DCE7x/9x */ + dwb_src_otg0 = 0x100, /* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */ + dwb_src_otg1, /* for DCN1.x/DCN2.x */ + dwb_src_otg2, /* for DCN1.x/DCN2.x */ + dwb_src_otg3, /* for DCN1.x/DCN2.x */ +}; + +/* DCN1.x, DCN2.x support 2 pipes */ +enum dwb_pipe { + dwb_pipe0 = 0, + dwb_pipe1, + dwb_pipe_max_num, +}; + +enum dwb_frame_capture_enable { + DWB_FRAME_CAPTURE_DISABLE = 0, + DWB_FRAME_CAPTURE_ENABLE = 1, +}; + +enum wbscl_coef_filter_type_sel { + WBSCL_COEF_LUMA_VERT_FILTER = 0, + WBSCL_COEF_CHROMA_VERT_FILTER = 1, + WBSCL_COEF_LUMA_HORZ_FILTER = 2, + WBSCL_COEF_CHROMA_HORZ_FILTER = 3 +}; + + +enum dwb_boundary_mode { + DWBSCL_BOUNDARY_MODE_EDGE = 0, + DWBSCL_BOUNDARY_MODE_BLACK = 1 +}; + +enum dwb_output_csc_mode { + DWB_OUTPUT_CSC_DISABLE = 0, + DWB_OUTPUT_CSC_COEF_A = 1, + DWB_OUTPUT_CSC_COEF_B = 2 +}; + +enum dwb_ogam_lut_mode { + DWB_OGAM_MODE_BYPASS, + DWB_OGAM_RAMA_LUT, + DWB_OGAM_RAMB_LUT +}; + +enum dwb_color_volume { + DWB_SRGB_BT709 = 0, //SDR + DWB_PQ = 1, //HDR + DWB_HLG = 2, //HDR +}; + +enum dwb_color_space { + DWB_SRGB = 0, //SDR + DWB_BT709 = 1, //SDR + DWB_BT2020 = 2, //HDR +}; + +struct dwb_efc_hdr_metadata { + /*display chromaticities and white point in units of 0.00001 */ + unsigned int chromaticity_green_x; + unsigned int chromaticity_green_y; + unsigned int chromaticity_blue_x; + unsigned int chromaticity_blue_y; + unsigned int chromaticity_red_x; + unsigned int chromaticity_red_y; + unsigned int chromaticity_white_point_x; + unsigned int chromaticity_white_point_y; + + /*in units of candelas per square meter */ + unsigned int min_luminance; + unsigned int max_luminance; + + /*in units of nits */ + unsigned int maximum_content_light_level; + unsigned int maximum_frame_average_light_level; +}; + +struct dwb_efc_display_settings { + unsigned int inputColorVolume; + unsigned int inputColorSpace; + unsigned int inputBitDepthMinus8; + struct dwb_efc_hdr_metadata hdr_metadata; + unsigned int dwbOutputBlack; // 0 - Normal, 1 - Output Black +}; + +struct dwb_warmup_params { + bool warmup_en; /* false: normal mode, true: enable pattern generator */ + bool warmup_mode; /* false: 420, true: 444 */ + bool warmup_depth; /* false: 8bit, true: 10bit */ + int warmup_data; /* Data to be sent by pattern generator (same for each pixel component) */ + int warmup_width; /* Pattern width (pixels) */ + int warmup_height; /* Pattern height (lines) */ +}; + +struct dwb_caps { + enum dce_version hw_version; /* DCN engine version. */ + enum dwb_sw_version sw_version; /* DWB sw implementation version. */ + unsigned int reserved[6]; /* Reserved for future use, MUST BE 0. */ + unsigned int adapter_id; + unsigned int num_pipes; /* number of DWB pipes */ + struct { + unsigned int support_dwb :1; + unsigned int support_ogam :1; + unsigned int support_wbscl :1; + unsigned int support_ocsc :1; + unsigned int support_stereo :1; + unsigned int support_4k_120p :1; + } caps; + unsigned int reserved2[10]; /* Reserved for future use, MUST BE 0. */ +}; + +struct dwbc { + const struct dwbc_funcs *funcs; + struct dc_context *ctx; + int inst; + struct mcif_wb *mcif; + bool status; + int inputSrcSelect; + bool dwb_output_black; + enum dc_transfer_func_predefined tf; + enum dc_color_space output_color_space; + bool dwb_is_efc_transition; + bool dwb_is_drc; + int wb_src_plane_inst;/*hubp, mpcc, inst*/ + uint32_t mask_id; + int otg_inst; + bool mvc_cfg; + struct dc_dwb_params params; +}; + +struct dwbc_funcs { + bool (*get_caps)( + struct dwbc *dwbc, + struct dwb_caps *caps); + + bool (*enable)( + struct dwbc *dwbc, + struct dc_dwb_params *params); + + bool (*disable)(struct dwbc *dwbc); + + bool (*update)( + struct dwbc *dwbc, + struct dc_dwb_params *params); + + bool (*is_enabled)( + struct dwbc *dwbc); + + void (*set_fc_enable)( + struct dwbc *dwbc, + enum dwb_frame_capture_enable enable); + + void (*dwb_set_scaler)( + struct dwbc *dwbc, + struct dc_dwb_params *params); + + void (*set_stereo)( + struct dwbc *dwbc, + struct dwb_stereo_params *stereo_params); + + void (*set_new_content)( + struct dwbc *dwbc, + bool is_new_content); + + + void (*set_warmup)( + struct dwbc *dwbc, + struct dwb_warmup_params *warmup_params); + + bool (*dwb_get_mcifbuf_line)( + struct dwbc *dwbc, unsigned int *buf_idx, + unsigned int *cur_line, + unsigned int *over_run); +#if defined(CONFIG_DRM_AMD_DC_FP) + void (*dwb_program_output_csc)( + struct dwbc *dwbc, + enum dc_color_space color_space, + enum dwb_output_csc_mode mode); + + bool (*dwb_ogam_set_output_transfer_func)( + struct dwbc *dwbc, + const struct dc_transfer_func *in_transfer_func_dwb_ogam); +#endif + //TODO: merge with output_transfer_func? + bool (*dwb_ogam_set_input_transfer_func)( + struct dwbc *dwbc, + const struct dc_transfer_func *in_transfer_func_dwb_ogam); + + void (*get_drr_time_stamp)( + struct dwbc *dwbc, uint32_t *time_stamp); + + bool (*get_dwb_status)( + struct dwbc *dwbc); +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h b/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h new file mode 100644 index 000000000000..5253dc8b15f8 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h @@ -0,0 +1,96 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_GPIO_H__ +#define __DAL_GPIO_H__ + +#include "gpio_types.h" + + +union gpio_hw_container { + struct hw_ddc *ddc; + struct hw_generic *generic; + struct hw_hpd *hpd; +}; + +struct gpio { + struct gpio_service *service; + struct hw_gpio_pin *pin; + enum gpio_id id; + uint32_t en; + + union gpio_hw_container hw_container; + enum gpio_mode mode; + + /* when GPIO comes from VBIOS, it has defined output state */ + enum gpio_pin_output_state output_state; +}; + +#if 0 +struct gpio_funcs { + + struct hw_gpio_pin *(*create_ddc_data)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_ddc_clock)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_generic)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_hpd)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_gpio_pad)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_sync)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_gsl)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + + /* HW translation */ + bool (*offset_to_id)( + uint32_t offset, + uint32_t mask, + enum gpio_id *id, + uint32_t *en); + bool (*id_to_offset)( + enum gpio_id id, + uint32_t en, + struct gpio_pin_info *info); +}; +#endif + +#endif /* __DAL_GPIO__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h new file mode 100644 index 000000000000..a79019365af8 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -0,0 +1,316 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_HUBP_H__ +#define __DAL_HUBP_H__ + +/** + * DOC: overview + * + * Display Controller Hub (DCHUB) is the gateway between the Scalable Data Port + * (SDP) and DCN. This component has multiple features, such as memory + * arbitration, rotation, and cursor manipulation. + * + * There is one HUBP allocated per pipe, which fetches data and converts + * different pixel formats (i.e. ARGB8888, NV12, etc) into linear, interleaved + * and fixed-depth streams of pixel data. + */ + +#include "mem_input.h" +#include "cursor_reg_cache.h" + +#include "dml2_0/dml21/inc/dml_top_dchub_registers.h" +#include "dml2_0/dml21/inc/dml_top_types.h" + +#define OPP_ID_INVALID 0xf +#define MAX_TTU 0xffffff + +enum cursor_pitch { + CURSOR_PITCH_64_PIXELS = 0, + CURSOR_PITCH_128_PIXELS, + CURSOR_PITCH_256_PIXELS +}; + +enum cursor_lines_per_chunk { + CURSOR_LINE_PER_CHUNK_1 = 0, /* new for DCN2 */ + CURSOR_LINE_PER_CHUNK_2 = 1, + CURSOR_LINE_PER_CHUNK_4, + CURSOR_LINE_PER_CHUNK_8, + CURSOR_LINE_PER_CHUNK_16 +}; + +enum hubp_ind_block_size { + hubp_ind_block_unconstrained = 0, + hubp_ind_block_64b, + hubp_ind_block_128b, + hubp_ind_block_64b_no_128bcl, +}; + +enum hubp_3dlut_fl_mode { + hubp_3dlut_fl_mode_disable = 0, + hubp_3dlut_fl_mode_native_1 = 1, + hubp_3dlut_fl_mode_native_2 = 2, + hubp_3dlut_fl_mode_transform = 3 +}; + +enum hubp_3dlut_fl_format { + hubp_3dlut_fl_format_unorm_12msb_bitslice = 0, + hubp_3dlut_fl_format_unorm_12lsb_bitslice = 1, + hubp_3dlut_fl_format_float_fp1_5_10 = 2 +}; + +enum hubp_3dlut_fl_addressing_mode { + hubp_3dlut_fl_addressing_mode_sw_linear = 0, + hubp_3dlut_fl_addressing_mode_simple_linear = 1 +}; + +enum hubp_3dlut_fl_width { + hubp_3dlut_fl_width_17 = 17, + hubp_3dlut_fl_width_33 = 33, + hubp_3dlut_fl_width_transformed = 4916, //mpc default +}; + +enum hubp_3dlut_fl_crossbar_bit_slice { + hubp_3dlut_fl_crossbar_bit_slice_0_15 = 0, + hubp_3dlut_fl_crossbar_bit_slice_16_31 = 1, + hubp_3dlut_fl_crossbar_bit_slice_32_47 = 2, + hubp_3dlut_fl_crossbar_bit_slice_48_63 = 3 +}; + +struct hubp_fl_3dlut_config { + bool enabled; + enum hubp_3dlut_fl_width width; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_format format; + uint16_t bias; + uint16_t scale; + struct dc_plane_address address; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum dc_cm2_gpu_mem_layout layout; + uint8_t protection_bits; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r; +}; + +struct hubp { + const struct hubp_funcs *funcs; + struct dc_context *ctx; + struct dc_plane_address request_address; + int inst; + + /* run time states */ + int opp_id; + int mpcc_id; + struct dc_cursor_attributes curs_attr; + struct dc_cursor_position curs_pos; + bool cursor_offload; + bool power_gated; + + struct cursor_position_cache_hubp pos; + struct cursor_attribute_cache_hubp att; + struct cursor_rect cur_rect; + bool use_mall_for_cursor; +}; + +struct surface_flip_registers { + uint32_t DCSURF_SURFACE_CONTROL; + uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; + uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; + uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; + uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; + uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; + uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; + uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; + uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; + uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; + uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; + uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; + uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; + bool tmz_surface; + bool immediate; + uint8_t vmid; + bool grph_stereo; +}; + +struct hubp_funcs { + void (*hubp_setup)( + struct hubp *hubp, + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, + struct _vcs_dpi_display_ttu_regs_st *ttu_regs, + struct _vcs_dpi_display_rq_regs_st *rq_regs, + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); + + void (*hubp_setup2)( + struct hubp *hubp, + struct dml2_dchub_per_pipe_register_set *pipe_regs, + union dml2_global_sync_programming *pipe_global_sync, + struct dc_crtc_timing *timing); + + void (*hubp_setup_interdependent)( + struct hubp *hubp, + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, + struct _vcs_dpi_display_ttu_regs_st *ttu_regs); + + void (*hubp_setup_interdependent2)( + struct hubp *hubp, + struct dml2_dchub_per_pipe_register_set *pipe_regs); + + void (*dcc_control)(struct hubp *hubp, bool enable, + enum hubp_ind_block_size blk_size); + + void (*hubp_reset)(struct hubp *hubp); + + void (*mem_program_viewport)( + struct hubp *hubp, + const struct rect *viewport, + const struct rect *viewport_c); + + bool (*hubp_program_surface_flip_and_addr)( + struct hubp *hubp, + const struct dc_plane_address *address, + bool flip_immediate); + + void (*hubp_program_pte_vm)( + struct hubp *hubp, + enum surface_pixel_format format, + struct dc_tiling_info *tiling_info, + enum dc_rotation_angle rotation); + + void (*hubp_set_vm_system_aperture_settings)( + struct hubp *hubp, + struct vm_system_aperture_param *apt); + + void (*hubp_set_vm_context0_settings)( + struct hubp *hubp, + const struct vm_context0_param *vm0); + + void (*hubp_program_surface_config)( + struct hubp *hubp, + enum surface_pixel_format format, + struct dc_tiling_info *tiling_info, + struct plane_size *plane_size, + enum dc_rotation_angle rotation, + struct dc_plane_dcc_param *dcc, + bool horizontal_mirror, + unsigned int compa_level); + + bool (*hubp_is_flip_pending)(struct hubp *hubp); + + void (*set_blank)(struct hubp *hubp, bool blank); + void (*set_blank_regs)(struct hubp *hubp, bool blank); + void (*phantom_hubp_post_enable)(struct hubp *hubp); + void (*set_hubp_blank_en)(struct hubp *hubp, bool blank); + + void (*set_cursor_attributes)( + struct hubp *hubp, + const struct dc_cursor_attributes *attr); + + void (*set_cursor_position)( + struct hubp *hubp, + const struct dc_cursor_position *pos, + const struct dc_cursor_mi_param *param); + + void (*hubp_disconnect)(struct hubp *hubp); + + void (*hubp_clk_cntl)(struct hubp *hubp, bool enable); + void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst); + void (*hubp_read_state)(struct hubp *hubp); + void (*hubp_read_reg_state)(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state); + void (*hubp_clear_underflow)(struct hubp *hubp); + void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp); + unsigned int (*hubp_get_underflow_status)(struct hubp *hubp); + void (*hubp_init)(struct hubp *hubp); + + void (*dmdata_set_attributes)( + struct hubp *hubp, + const struct dc_dmdata_attributes *attr); + + void (*dmdata_load)( + struct hubp *hubp, + uint32_t dmdata_sw_size, + const uint32_t *dmdata_sw_data); + bool (*dmdata_status_done)(struct hubp *hubp); + void (*hubp_enable_tripleBuffer)( + struct hubp *hubp, + bool enable); + + bool (*hubp_is_triplebuffer_enabled)( + struct hubp *hubp); + + void (*hubp_set_flip_control_surface_gsl)( + struct hubp *hubp, + bool enable); + + void (*validate_dml_output)( + struct hubp *hubp, + struct dc_context *ctx, + struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, + struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, + struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr); + void (*set_unbounded_requesting)( + struct hubp *hubp, + bool enable); + bool (*hubp_in_blank)(struct hubp *hubp); + void (*hubp_soft_reset)(struct hubp *hubp, bool reset); + + void (*hubp_set_flip_int)(struct hubp *hubp); + + void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow); + void (*hubp_update_force_cursor_pstate_disallow)(struct hubp *hubp, bool allow); + void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool c_cursor); + void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable); + void (*hubp_surface_update_lock)(struct hubp *hubp, + bool lock); + + void (*program_extended_blank)(struct hubp *hubp, + unsigned int min_dst_y_next_start_optimized); + + void (*hubp_wait_pipe_read_start)(struct hubp *hubp); + void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs); + void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale); + void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp, + enum hubp_3dlut_fl_mode mode); + void (*hubp_program_3dlut_fl_format)(struct hubp *hubp, + enum hubp_3dlut_fl_format format); + void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp, + const struct dc_plane_address address); + void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group); + void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable); + void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode); + void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width); + void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits); + void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); + int (*hubp_get_3dlut_fl_done)(struct hubp *hubp); + void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg); + void (*hubp_clear_tiling)(struct hubp *hubp); + uint32_t (*hubp_get_current_read_line)(struct hubp *hubp); + uint32_t (*hubp_get_det_config_error)(struct hubp *hubp); +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h new file mode 100644 index 000000000000..a61d12ec61bc --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -0,0 +1,419 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_HW_SHARED_H__ +#define __DAL_HW_SHARED_H__ + +#include "os_types.h" +#include "fixed31_32.h" +#include "dc_hw_types.h" + +/****************************************************************************** + * Data types shared between different Virtual HW blocks + ******************************************************************************/ + +#define MAX_AUDIOS 7 + +/** + * @MAX_PIPES: + * + * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number + * to be used inside loops and for determining array sizes. + */ +#define MAX_PIPES 6 +#define MAX_PHANTOM_PIPES (MAX_PIPES / 2) + +#define MAX_DPIA 6 +#define MAX_CONNECTOR 6 +#define MAX_VIRTUAL_LINKS 4 + +#define MAX_LINKS (MAX_DPIA + MAX_CONNECTOR + MAX_VIRTUAL_LINKS) + +/** + * define MAX_DIG_LINK_ENCODERS - maximum number of digital encoders + * + * Digital encoders are ENGINE_ID_DIGA...G, there are at most 7, + * although not every GPU may have that many. + */ +#define MAX_DIG_LINK_ENCODERS 7 + +/** + * define MAX_DAC_LINK_ENCODERS - maximum number of analog link encoders + * + * Analog encoders are ENGINE_ID_DACA/B, there are at most 2, + * although not every GPU may have that many. Modern GPUs typically + * don't have analog encoders. + */ +#define MAX_DAC_LINK_ENCODERS 2 + +/** + * define MAX_LINK_ENCODERS - maximum number link encoders in total + * + * This includes both analog and digital encoders. + */ +#define MAX_LINK_ENCODERS (MAX_DIG_LINK_ENCODERS + MAX_DAC_LINK_ENCODERS) + +#define MAX_DWB_PIPES 1 +#define MAX_HPO_DP2_ENCODERS 4 +#define MAX_HPO_DP2_LINK_ENCODERS 4 + +/* Pipe topology snapshot structures */ +#define MAX_TOPOLOGY_SNAPSHOTS 4 + +struct pipe_topology_line { + bool is_phantom_pipe; + int plane_idx; + int slice_idx; + int stream_idx; + int dpp_inst; + int opp_inst; + int tg_inst; +}; + +struct pipe_topology_snapshot { + struct pipe_topology_line pipe_log_lines[MAX_PIPES]; + int line_count; + uint64_t timestamp_us; + int stream_count; + int phantom_stream_count; +}; + +struct pipe_topology_history { + struct pipe_topology_snapshot snapshots[MAX_TOPOLOGY_SNAPSHOTS]; + int current_snapshot_index; +}; + +struct gamma_curve { + uint32_t offset; + uint32_t segments_num; +}; + +struct curve_points { + struct fixed31_32 x; + struct fixed31_32 y; + struct fixed31_32 offset; + struct fixed31_32 slope; + + uint32_t custom_float_x; + uint32_t custom_float_y; + uint32_t custom_float_offset; + uint32_t custom_float_slope; +}; + +struct curve_points3 { + struct curve_points red; + struct curve_points green; + struct curve_points blue; +}; + +struct pwl_result_data { + struct fixed31_32 red; + struct fixed31_32 green; + struct fixed31_32 blue; + + struct fixed31_32 delta_red; + struct fixed31_32 delta_green; + struct fixed31_32 delta_blue; + + uint32_t red_reg; + uint32_t green_reg; + uint32_t blue_reg; + + uint32_t delta_red_reg; + uint32_t delta_green_reg; + uint32_t delta_blue_reg; +}; + +struct dc_rgb { + uint32_t red; + uint32_t green; + uint32_t blue; +}; + +struct tetrahedral_17x17x17 { + struct dc_rgb lut0[1229]; + struct dc_rgb lut1[1228]; + struct dc_rgb lut2[1228]; + struct dc_rgb lut3[1228]; +}; +struct tetrahedral_9x9x9 { + struct dc_rgb lut0[183]; + struct dc_rgb lut1[182]; + struct dc_rgb lut2[182]; + struct dc_rgb lut3[182]; +}; + +struct tetrahedral_params { + union { + struct tetrahedral_17x17x17 tetrahedral_17; + struct tetrahedral_9x9x9 tetrahedral_9; + }; + bool use_tetrahedral_9; + bool use_12bits; + +}; + +/* arr_curve_points - regamma regions/segments specification + * arr_points - beginning and end point specified separately (only one on DCE) + * corner_points - beginning and end point for all 3 colors (DCN) + * rgb_resulted - final curve + */ +struct pwl_params { + struct gamma_curve arr_curve_points[34]; + union { + struct curve_points arr_points[2]; + struct curve_points3 corner_points[2]; + }; + struct pwl_result_data rgb_resulted[256 + 3]; + uint32_t hw_points_num; +}; + +/* move to dpp + * while we are moving functionality out of opp to dpp to align + * HW programming to HW IP, we define these struct in hw_shared + * so we can still compile while refactoring + */ + +enum lb_pixel_depth { + /* do not change the values because it is used as bit vector */ + LB_PIXEL_DEPTH_18BPP = 1, + LB_PIXEL_DEPTH_24BPP = 2, + LB_PIXEL_DEPTH_30BPP = 4, + LB_PIXEL_DEPTH_36BPP = 8 +}; + +enum graphics_csc_adjust_type { + GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, + GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ + GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ +}; + +enum ipp_degamma_mode { + IPP_DEGAMMA_MODE_BYPASS, + IPP_DEGAMMA_MODE_HW_sRGB, + IPP_DEGAMMA_MODE_HW_xvYCC, + IPP_DEGAMMA_MODE_USER_PWL +}; + +enum gamcor_mode { + GAMCOR_MODE_BYPASS, + GAMCOR_MODE_RESERVED_1, + GAMCOR_MODE_USER_PWL, + GAMCOR_MODE_RESERVED_3 +}; + +enum ipp_output_format { + IPP_OUTPUT_FORMAT_12_BIT_FIX, + IPP_OUTPUT_FORMAT_16_BIT_BYPASS, + IPP_OUTPUT_FORMAT_FLOAT +}; + +enum expansion_mode { + EXPANSION_MODE_DYNAMIC, + EXPANSION_MODE_ZERO +}; + +struct default_adjustment { + enum lb_pixel_depth lb_color_depth; + enum dc_color_space out_color_space; + enum dc_color_space in_color_space; + enum dc_color_depth color_depth; + enum pixel_format surface_pixel_format; + enum graphics_csc_adjust_type csc_adjust_type; + bool force_hw_default; +}; + + +struct out_csc_color_matrix { + enum dc_color_space color_space; + uint16_t regval[12]; +}; + +enum gamut_remap_select { + GAMUT_REMAP_BYPASS = 0, + GAMUT_REMAP_COEFF, + GAMUT_REMAP_COMA_COEFF, + GAMUT_REMAP_COMB_COEFF +}; + +enum opp_regamma { + OPP_REGAMMA_BYPASS = 0, + OPP_REGAMMA_SRGB, + OPP_REGAMMA_XVYCC, + OPP_REGAMMA_USER +}; + +enum optc_dsc_mode { + OPTC_DSC_DISABLED = 0, + OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */ + OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */ +}; + +struct dc_bias_and_scale { + uint32_t scale_red; + uint32_t bias_red; + uint32_t scale_green; + uint32_t bias_green; + uint32_t scale_blue; + uint32_t bias_blue; + bool bias_and_scale_valid; +}; + +enum test_pattern_dyn_range { + TEST_PATTERN_DYN_RANGE_VESA = 0, + TEST_PATTERN_DYN_RANGE_CEA +}; + +enum test_pattern_mode { + TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, + TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, + TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, + TEST_PATTERN_MODE_VERTICALBARS, + TEST_PATTERN_MODE_HORIZONTALBARS, + TEST_PATTERN_MODE_SINGLERAMP_RGB, + TEST_PATTERN_MODE_DUALRAMP_RGB, + TEST_PATTERN_MODE_XR_BIAS_RGB +}; + +enum test_pattern_color_format { + TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, + TEST_PATTERN_COLOR_FORMAT_BPC_8, + TEST_PATTERN_COLOR_FORMAT_BPC_10, + TEST_PATTERN_COLOR_FORMAT_BPC_12 +}; + +enum controller_dp_test_pattern { + CONTROLLER_DP_TEST_PATTERN_D102 = 0, + CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, + CONTROLLER_DP_TEST_PATTERN_PRBS7, + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, + CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, + CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, + CONTROLLER_DP_TEST_PATTERN_COLORRAMP, + CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, + CONTROLLER_DP_TEST_PATTERN_RESERVED_8, + CONTROLLER_DP_TEST_PATTERN_RESERVED_9, + CONTROLLER_DP_TEST_PATTERN_RESERVED_A, + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA, + CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR +}; + +enum controller_dp_color_space { + CONTROLLER_DP_COLOR_SPACE_RGB, + CONTROLLER_DP_COLOR_SPACE_YCBCR601, + CONTROLLER_DP_COLOR_SPACE_YCBCR709, + CONTROLLER_DP_COLOR_SPACE_UDEFINED +}; + +enum dc_lut_mode { + LUT_BYPASS, + LUT_RAM_A, + LUT_RAM_B +}; + +/** + * speakersToChannels + * + * @brief + * translate speakers to channels + * + * FL - Front Left + * FR - Front Right + * RL - Rear Left + * RR - Rear Right + * RC - Rear Center + * FC - Front Center + * FLC - Front Left Center + * FRC - Front Right Center + * RLC - Rear Left Center + * RRC - Rear Right Center + * LFE - Low Freq Effect + * + * FC + * FLC FRC + * FL FR + * + * LFE + * () + * + * + * RL RR + * RLC RRC + * RC + * + * ch 8 7 6 5 4 3 2 1 + * 0b00000011 - - - - - - FR FL + * 0b00000111 - - - - - LFE FR FL + * 0b00001011 - - - - FC - FR FL + * 0b00001111 - - - - FC LFE FR FL + * 0b00010011 - - - RC - - FR FL + * 0b00010111 - - - RC - LFE FR FL + * 0b00011011 - - - RC FC - FR FL + * 0b00011111 - - - RC FC LFE FR FL + * 0b00110011 - - RR RL - - FR FL + * 0b00110111 - - RR RL - LFE FR FL + * 0b00111011 - - RR RL FC - FR FL + * 0b00111111 - - RR RL FC LFE FR FL + * 0b01110011 - RC RR RL - - FR FL + * 0b01110111 - RC RR RL - LFE FR FL + * 0b01111011 - RC RR RL FC - FR FL + * 0b01111111 - RC RR RL FC LFE FR FL + * 0b11110011 RRC RLC RR RL - - FR FL + * 0b11110111 RRC RLC RR RL - LFE FR FL + * 0b11111011 RRC RLC RR RL FC - FR FL + * 0b11111111 RRC RLC RR RL FC LFE FR FL + * 0b11000011 FRC FLC - - - - FR FL + * 0b11000111 FRC FLC - - - LFE FR FL + * 0b11001011 FRC FLC - - FC - FR FL + * 0b11001111 FRC FLC - - FC LFE FR FL + * 0b11010011 FRC FLC - RC - - FR FL + * 0b11010111 FRC FLC - RC - LFE FR FL + * 0b11011011 FRC FLC - RC FC - FR FL + * 0b11011111 FRC FLC - RC FC LFE FR FL + * 0b11110011 FRC FLC RR RL - - FR FL + * 0b11110111 FRC FLC RR RL - LFE FR FL + * 0b11111011 FRC FLC RR RL FC - FR FL + * 0b11111111 FRC FLC RR RL FC LFE FR FL + * + * @param + * speakers - speaker information as it comes from CEA audio block + */ +/* translate speakers to channels */ + +union audio_cea_channels { + uint8_t all; + struct audio_cea_channels_bits { + uint32_t FL:1; + uint32_t FR:1; + uint32_t LFE:1; + uint32_t FC:1; + uint32_t RL_RC:1; + uint32_t RR:1; + uint32_t RC_RLC_FLC:1; + uint32_t RRC_FRC:1; + } channels; +}; + +#endif /* __DAL_HW_SHARED_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h new file mode 100644 index 000000000000..b2fa4c4cd920 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -0,0 +1,114 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_IPP_H__ +#define __DAL_IPP_H__ + +#include "hw_shared.h" +#include "dc_hw_types.h" + +#define MAXTRIX_COEFFICIENTS_NUMBER 12 +#define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4) +#define MAX_OVL_MATRIX_COUNT 12 + +/* IPP RELATED */ +struct input_pixel_processor { + struct dc_context *ctx; + unsigned int inst; + const struct ipp_funcs *funcs; +}; + +enum ipp_prescale_mode { + IPP_PRESCALE_MODE_BYPASS, + IPP_PRESCALE_MODE_FIXED_SIGNED, + IPP_PRESCALE_MODE_FLOAT_SIGNED, + IPP_PRESCALE_MODE_FIXED_UNSIGNED, + IPP_PRESCALE_MODE_FLOAT_UNSIGNED +}; + +struct ipp_prescale_params { + enum ipp_prescale_mode mode; + uint16_t bias; + uint16_t scale; +}; + + + +enum ovl_color_space { + OVL_COLOR_SPACE_UNKNOWN = 0, + OVL_COLOR_SPACE_RGB, + OVL_COLOR_SPACE_YUV601, + OVL_COLOR_SPACE_YUV709 +}; + + +struct ipp_funcs { + + /*** cursor ***/ + void (*ipp_cursor_set_position)( + struct input_pixel_processor *ipp, + const struct dc_cursor_position *position, + const struct dc_cursor_mi_param *param); + + void (*ipp_cursor_set_attributes)( + struct input_pixel_processor *ipp, + const struct dc_cursor_attributes *attributes); + + /*** setup input pixel processing ***/ + + /* put the entire pixel processor to bypass */ + void (*ipp_full_bypass)( + struct input_pixel_processor *ipp); + + /* setup ipp to expand/convert input to pixel processor internal format */ + void (*ipp_setup)( + struct input_pixel_processor *ipp, + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space); + + /* DCE function to setup IPP. TODO: see if we can consolidate to setup */ + void (*ipp_program_prescale)( + struct input_pixel_processor *ipp, + struct ipp_prescale_params *params); + + void (*ipp_program_input_lut)( + struct input_pixel_processor *ipp, + const struct dc_gamma *gamma); + + /*** DEGAMMA RELATED ***/ + void (*ipp_set_degamma)( + struct input_pixel_processor *ipp, + enum ipp_degamma_mode mode); + + void (*ipp_program_degamma_pwl)( + struct input_pixel_processor *ipp, + const struct pwl_params *params); + + void (*ipp_destroy)(struct input_pixel_processor **ipp); +}; + +#endif /* __DAL_IPP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h new file mode 100644 index 000000000000..df512920a9fa --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -0,0 +1,288 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +/* + * link_encoder.h + * + * Created on: Oct 6, 2015 + * Author: yonsun + */ + +#ifndef LINK_ENCODER_H_ +#define LINK_ENCODER_H_ + +#include "grph_object_defs.h" +#include "signal_types.h" +#include "dc_types.h" + +struct dc_context; +struct encoder_set_dp_phy_pattern_param; +struct link_mst_stream_allocation_table; +struct dc_link_settings; +struct link_training_settings; +struct pipe_ctx; + +struct encoder_init_data { + enum channel_id channel; + struct graphics_object_id connector; + enum hpd_source_id hpd_source; + /* TODO: in DAL2, here was pointer to EventManagerInterface */ + struct graphics_object_id encoder; + enum engine_id analog_engine; + struct dc_context *ctx; + enum transmitter transmitter; +}; + +struct encoder_feature_support { + union { + struct { + uint32_t IS_HBR2_CAPABLE:1; + uint32_t IS_HBR3_CAPABLE:1; + uint32_t IS_TPS3_CAPABLE:1; + uint32_t IS_TPS4_CAPABLE:1; + uint32_t HDMI_6GB_EN:1; + uint32_t IS_DP2_CAPABLE:1; + uint32_t IS_UHBR10_CAPABLE:1; + uint32_t IS_UHBR13_5_CAPABLE:1; + uint32_t IS_UHBR20_CAPABLE:1; + uint32_t DP_IS_USB_C:1; + } bits; + uint32_t raw; + } flags; + + enum dc_color_depth max_hdmi_deep_color; + unsigned int max_hdmi_pixel_clock; + bool hdmi_ycbcr420_supported; + bool dp_ycbcr420_supported; + bool fec_supported; +}; + +struct link_encoder { + const struct link_encoder_funcs *funcs; + int32_t aux_channel_offset; + struct dc_context *ctx; + struct graphics_object_id id; + struct graphics_object_id connector; + uint32_t output_signals; + enum engine_id preferred_engine; + enum engine_id analog_engine; + struct encoder_feature_support features; + enum transmitter transmitter; + enum hpd_source_id hpd_source; + bool usbc_combo_phy; +}; + +struct link_enc_state { + + uint32_t dphy_fec_en; + uint32_t dphy_fec_ready_shadow; + uint32_t dphy_fec_active_status; + uint32_t dp_link_training_complete; + +}; + +enum encoder_type_select { + ENCODER_TYPE_DIG = 0, + ENCODER_TYPE_HDMI_FRL = 1, + ENCODER_TYPE_DP_128B132B = 2 +}; + +struct link_encoder_funcs { + void (*read_state)( + struct link_encoder *enc, struct link_enc_state *s); + bool (*validate_output_with_stream)( + struct link_encoder *enc, const struct dc_stream_state *stream); + void (*hw_init)(struct link_encoder *enc); + void (*setup)(struct link_encoder *enc, + enum signal_type signal); + void (*enable_tmds_output)(struct link_encoder *enc, + enum clock_source_id clock_source, + enum dc_color_depth color_depth, + enum signal_type signal, + uint32_t pixel_clock); + void (*enable_dp_output)(struct link_encoder *enc, + const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + void (*enable_dp_mst_output)(struct link_encoder *enc, + const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + void (*enable_lvds_output)(struct link_encoder *enc, + enum clock_source_id clock_source, + uint32_t pixel_clock); + void (*disable_output)(struct link_encoder *link_enc, + enum signal_type signal); + void (*dp_set_lane_settings)(struct link_encoder *enc, + const struct dc_link_settings *link_settings, + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); + void (*dp_set_phy_pattern)(struct link_encoder *enc, + const struct encoder_set_dp_phy_pattern_param *para); + void (*update_mst_stream_allocation_table)( + struct link_encoder *enc, + const struct link_mst_stream_allocation_table *table); + void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc, + bool exit_link_training_required); + void (*psr_program_secondary_packet)(struct link_encoder *enc, + unsigned int sdp_transmit_line_num_deadline); + void (*connect_dig_be_to_fe)(struct link_encoder *enc, + enum engine_id engine, + bool connect); + void (*enable_hpd)(struct link_encoder *enc); + void (*disable_hpd)(struct link_encoder *enc); + bool (*is_dig_enabled)(struct link_encoder *enc); + unsigned int (*get_dig_frontend)(struct link_encoder *enc); + void (*destroy)(struct link_encoder **enc); + + void (*fec_set_enable)(struct link_encoder *enc, + bool enable); + + void (*fec_set_ready)(struct link_encoder *enc, + bool ready); + + bool (*fec_is_active)(struct link_encoder *enc); + bool (*is_in_alt_mode) (struct link_encoder *enc); + + void (*get_max_link_cap)(struct link_encoder *enc, + struct dc_link_settings *link_settings); + + enum signal_type (*get_dig_mode)( + struct link_encoder *enc); + + void (*set_dio_phy_mux)( + struct link_encoder *enc, + enum encoder_type_select sel, + uint32_t hpo_inst); + void (*enable_dpia_output)(struct link_encoder *enc, + const struct dc_link_settings *link_settings, + uint8_t dpia_id, + uint8_t digmode, + uint8_t fec_rdy); + void (*disable_dpia_output)(struct link_encoder *link_enc, + uint8_t dpia_id, + uint8_t digmode); +}; + +/* + * Used to track assignments of links (display endpoints) to link encoders. + * + * Entry in link_enc_assignments table in struct resource_context. + * Entries only marked valid once encoder assigned to a link and invalidated once unassigned. + * Uses engine ID as identifier since PHY ID not relevant for USB4 DPIA endpoint. + */ +struct link_enc_assignment { + bool valid; + struct display_endpoint_id ep_id; + enum engine_id eng_id; + struct dc_stream_state *stream; +}; + +enum link_enc_cfg_mode { + LINK_ENC_CFG_STEADY, /* Normal operation - use current_state. */ + LINK_ENC_CFG_TRANSIENT /* During commit state - use state to be committed. */ +}; + +enum dp2_link_mode { + DP2_LINK_TRAINING_TPS1, + DP2_LINK_TRAINING_TPS2, + DP2_LINK_ACTIVE, + DP2_TEST_PATTERN +}; + +enum dp2_phy_tp_select { + DP_DPHY_TP_SELECT_TPS1, + DP_DPHY_TP_SELECT_TPS2, + DP_DPHY_TP_SELECT_PRBS, + DP_DPHY_TP_SELECT_CUSTOM, + DP_DPHY_TP_SELECT_SQUARE +}; + +enum dp2_phy_tp_prbs { + DP_DPHY_TP_PRBS7, + DP_DPHY_TP_PRBS9, + DP_DPHY_TP_PRBS11, + DP_DPHY_TP_PRBS15, + DP_DPHY_TP_PRBS23, + DP_DPHY_TP_PRBS31 +}; + +struct hpo_dp_link_enc_state { + uint32_t link_enc_enabled; + uint32_t link_mode; + uint32_t lane_count; + uint32_t slot_count[4]; + uint32_t stream_src[4]; + uint32_t vc_rate_x[4]; + uint32_t vc_rate_y[4]; +}; + +struct hpo_dp_link_encoder { + const struct hpo_dp_link_encoder_funcs *funcs; + struct dc_context *ctx; + int inst; + enum engine_id preferred_engine; + enum transmitter transmitter; + enum hpd_source_id hpd_source; +}; + +struct hpo_dp_link_encoder_funcs { + + void (*enable_link_phy)(struct hpo_dp_link_encoder *enc, + const struct dc_link_settings *link_settings, + enum transmitter transmitter, + enum hpd_source_id hpd_source); + + void (*disable_link_phy)(struct hpo_dp_link_encoder *link_enc, + enum signal_type signal); + + void (*link_enable)( + struct hpo_dp_link_encoder *enc, + enum dc_lane_count num_lanes); + + void (*link_disable)( + struct hpo_dp_link_encoder *enc); + + void (*set_link_test_pattern)( + struct hpo_dp_link_encoder *enc, + struct encoder_set_dp_phy_pattern_param *tp_params); + + void (*update_stream_allocation_table)( + struct hpo_dp_link_encoder *enc, + const struct link_mst_stream_allocation_table *table); + + void (*set_throttled_vcp_size)( + struct hpo_dp_link_encoder *enc, + uint32_t stream_encoder_inst, + struct fixed31_32 avg_time_slots_per_mtp); + + bool (*is_in_alt_mode) ( + struct hpo_dp_link_encoder *enc); + + void (*read_state)( + struct hpo_dp_link_encoder *enc, + struct hpo_dp_link_enc_state *state); + + void (*set_ffe)( + struct hpo_dp_link_encoder *enc, + const struct dc_link_settings *link_settings, + uint8_t ffe_preset); +}; + +#endif /* LINK_ENCODER_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h new file mode 100644 index 000000000000..15cb782f129b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h @@ -0,0 +1,109 @@ +/* Copyright 2012-17 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_MCIF_WB_H__ +#define __DC_MCIF_WB_H__ + +#include "dc_hw_types.h" + + +enum mmhubbub_wbif_mode { + PACKED_444 = 0, + PACKED_444_FP16 = 1, + PLANAR_420_8BPC = 2, + PLANAR_420_10BPC = 3 +}; + +struct mcif_arb_params { + + unsigned int time_per_pixel; + unsigned int cli_watermark[4]; + unsigned int pstate_watermark[4]; + unsigned int arbitration_slice; + unsigned int slice_lines; + unsigned int max_scaled_time; + unsigned int dram_speed_change_duration; +}; + +struct mcif_irq_params { + unsigned int sw_int_en; + unsigned int sw_slice_int_en; + unsigned int sw_overrun_int_en; + unsigned int vce_int_en; + unsigned int vce_slice_int_en; +}; + + +/* / - mcif_wb_frame_dump_info is the info of the dumping WB data */ +struct mcif_wb_frame_dump_info { + unsigned int size; + unsigned int width; + unsigned int height; + unsigned int luma_pitch; + unsigned int chroma_pitch; + enum dwb_scaler_mode format; +}; + +struct mcif_wb { + const struct mcif_wb_funcs *funcs; + struct dc_context *ctx; + int inst; +}; + +struct mcif_wb_funcs { + + void (*warmup_mcif)( + struct mcif_wb *mcif_wb, + struct mcif_warmup_params *params); + void (*enable_mcif)(struct mcif_wb *mcif_wb); + + void (*disable_mcif)(struct mcif_wb *mcif_wb); + + void (*config_mcif_buf)( + struct mcif_wb *mcif_wb, + struct mcif_buf_params *params, + unsigned int dest_height); + + void (*config_mcif_arb)( + struct mcif_wb *mcif_wb, + struct mcif_arb_params *params); + + void (*config_mcif_irq)( + struct mcif_wb *mcif_wb, + struct mcif_irq_params *params); + + void (*dump_frame)( + struct mcif_wb *mcif_wb, + struct mcif_buf_params *mcif_params, + enum dwb_scaler_mode out_format, + unsigned int dest_width, + unsigned int dest_height, + struct mcif_wb_frame_dump_info *dump_info, + unsigned char *luma_buffer, + unsigned char *chroma_buffer, + unsigned char *dest_luma_buffer, + unsigned char *dest_chroma_buffer); +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h new file mode 100644 index 000000000000..d468bc85566a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -0,0 +1,194 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef __DAL_MEM_INPUT_H__ +#define __DAL_MEM_INPUT_H__ + +#include "dc.h" +#include "include/grph_object_id.h" + +#include "dml/display_mode_structs.h" +#include "dml2_0/dml21/inc/dml_top_dchub_registers.h" + +struct dchub_init_data; +struct cstate_pstate_watermarks_st { + uint32_t cstate_exit_ns; + uint32_t cstate_exit_z8_ns; + uint32_t cstate_enter_plus_exit_z8_ns; + uint32_t cstate_enter_plus_exit_ns; + uint32_t pstate_change_ns; + uint32_t fclk_pstate_change_ns; +}; + +struct dcn_watermarks { + uint32_t pte_meta_urgent_ns; + uint32_t urgent_ns; + uint32_t frac_urg_bw_nom; + uint32_t frac_urg_bw_flip; + uint32_t urgent_latency_ns; + struct cstate_pstate_watermarks_st cstate_pstate; + uint32_t usr_retraining_ns; +}; + +union dcn_watermark_set { + struct { + struct dcn_watermarks a; + struct dcn_watermarks b; + struct dcn_watermarks c; + struct dcn_watermarks d; + }; // legacy + struct { + struct dml2_dchub_watermark_regs a; + struct dml2_dchub_watermark_regs b; + struct dml2_dchub_watermark_regs c; + struct dml2_dchub_watermark_regs d; + } dcn4x; //dcn4+ +}; + +struct dce_watermarks { + int a_mark; + int b_mark; + int c_mark; + int d_mark; +}; + +struct stutter_modes { + bool enhanced; + bool quad_dmif_buffer; + bool watermark_nb_pstate; +}; + +struct mem_input { + const struct mem_input_funcs *funcs; + struct dc_context *ctx; + struct dc_plane_address request_address; + struct dc_plane_address current_address; + int inst; + struct stutter_modes stutter_mode; +}; + +struct vm_system_aperture_param { + PHYSICAL_ADDRESS_LOC sys_default; + PHYSICAL_ADDRESS_LOC sys_low; + PHYSICAL_ADDRESS_LOC sys_high; +}; + +struct vm_context0_param { + PHYSICAL_ADDRESS_LOC pte_base; + PHYSICAL_ADDRESS_LOC pte_start; + PHYSICAL_ADDRESS_LOC pte_end; + PHYSICAL_ADDRESS_LOC fault_default; +}; + +struct mem_input_funcs { + void (*mem_input_setup)( + struct mem_input *mem_input, + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, + struct _vcs_dpi_display_ttu_regs_st *ttu_regs, + struct _vcs_dpi_display_rq_regs_st *rq_regs, + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); + + void (*dcc_control)(struct mem_input *mem_input, bool enable, + bool independent_64b_blks); + void (*mem_program_viewport)( + struct mem_input *mem_input, + const struct rect *viewport, + const struct rect *viewport_c); + + void (*mem_input_program_display_marks)( + struct mem_input *mem_input, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks stutter_enter, + struct dce_watermarks urgent, + uint32_t total_dest_line_time_ns); + + void (*mem_input_program_chroma_display_marks)( + struct mem_input *mem_input, + struct dce_watermarks nbp, + struct dce_watermarks stutter, + struct dce_watermarks urgent, + uint32_t total_dest_line_time_ns); + + void (*allocate_mem_input)( + struct mem_input *mem_input, + uint32_t h_total,/* for current target */ + uint32_t v_total,/* for current target */ + uint32_t pix_clk_khz,/* for current target */ + uint32_t total_streams_num); + + void (*free_mem_input)( + struct mem_input *mem_input, + uint32_t paths_num); + + bool (*mem_input_program_surface_flip_and_addr)( + struct mem_input *mem_input, + const struct dc_plane_address *address, + bool flip_immediate); + + void (*mem_input_program_pte_vm)( + struct mem_input *mem_input, + enum surface_pixel_format format, + struct dc_tiling_info *tiling_info, + enum dc_rotation_angle rotation); + + void (*mem_input_set_vm_system_aperture_settings)( + struct mem_input *mem_input, + struct vm_system_aperture_param *apt); + + void (*mem_input_set_vm_context0_settings)( + struct mem_input *mem_input, + const struct vm_context0_param *vm0); + + void (*mem_input_program_surface_config)( + struct mem_input *mem_input, + enum surface_pixel_format format, + struct dc_tiling_info *tiling_info, + struct plane_size *plane_size, + enum dc_rotation_angle rotation, + struct dc_plane_dcc_param *dcc, + bool horizontal_mirror); + + bool (*mem_input_is_flip_pending)(struct mem_input *mem_input); + + void (*mem_input_update_dchub)(struct mem_input *mem_input, + struct dchub_init_data *dh_data); + + void (*set_blank)(struct mem_input *mi, bool blank); + void (*set_hubp_blank_en)(struct mem_input *mi, bool blank); + + void (*set_cursor_attributes)( + struct mem_input *mem_input, + const struct dc_cursor_attributes *attr); + + void (*set_cursor_position)( + struct mem_input *mem_input, + const struct dc_cursor_position *pos, + const struct dc_cursor_mi_param *param); + + void (*mem_input_clear_tiling)( + struct mem_input *mem_input); +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h new file mode 100644 index 000000000000..a8d1abe20f62 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -0,0 +1,1141 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +/** + * DOC: overview + * + * Multiple Pipe/Plane Combiner (MPC) is a component in the hardware pipeline + * that performs blending of multiple planes, using global and per-pixel alpha. + * It also performs post-blending color correction operations according to the + * hardware capabilities, such as color transformation matrix and gamma 1D and + * 3D LUT. + * + * MPC receives output from all DPP pipes and combines them to multiple outputs + * supporting "M MPC inputs -> N MPC outputs" flexible composition + * architecture. It features: + * + * - Programmable blending structure to allow software controlled blending and + * cascading; + * - Programmable window location of each DPP in active region of display; + * - Combining multiple DPP pipes in one active region when a single DPP pipe + * cannot process very large surface; + * - Combining multiple DPP from different SLS with blending; + * - Stereo formats from single DPP in top-bottom or side-by-side modes; + * - Stereo formats from 2 DPPs; + * - Alpha blending of multiple layers from different DPP pipes; + * - Programmable background color; + */ + +#ifndef __DC_MPCC_H__ +#define __DC_MPCC_H__ + +#include "dc_hw_types.h" +#include "hw_shared.h" +#include "transform.h" + +#define MAX_MPCC 6 +#define MAX_OPP 6 + +#define MAX_DWB 2 + +enum mpc_output_csc_mode { + MPC_OUTPUT_CSC_DISABLE = 0, + MPC_OUTPUT_CSC_COEF_A, + MPC_OUTPUT_CSC_COEF_B +}; + + +enum mpcc_blend_mode { + MPCC_BLEND_MODE_BYPASS, + MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH, + MPCC_BLEND_MODE_TOP_LAYER_ONLY, + MPCC_BLEND_MODE_TOP_BOT_BLENDING +}; + +/** + * enum mpcc_alpha_blend_mode - define the alpha blend mode regarding pixel + * alpha and plane alpha values + */ +enum mpcc_alpha_blend_mode { + /** + * @MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA: per pixel alpha using DPP + * alpha value + */ + MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA, + /** + * @MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN: per + * pixel alpha using DPP alpha value multiplied by a global gain (plane + * alpha) + */ + MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN, + /** + * @MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA: global alpha value, ignores + * pixel alpha and consider only plane alpha + */ + MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA +}; + +enum mpcc_movable_cm_location { + MPCC_MOVABLE_CM_LOCATION_BEFORE, + MPCC_MOVABLE_CM_LOCATION_AFTER, +}; + +enum MCM_LUT_XABLE { + MCM_LUT_DISABLE, + MCM_LUT_DISABLED = MCM_LUT_DISABLE, + MCM_LUT_ENABLE, + MCM_LUT_ENABLED = MCM_LUT_ENABLE, +}; + +enum MCM_LUT_ID { + MCM_LUT_3DLUT, + MCM_LUT_1DLUT, + MCM_LUT_SHAPER +}; + +struct mpc_fl_3dlut_config { + bool enabled; + uint16_t width; + bool select_lut_bank_a; + uint16_t bit_depth; + int hubp_index; + uint16_t bias; + uint16_t scale; +}; + +union mcm_lut_params { + const struct pwl_params *pwl; + const struct tetrahedral_params *lut3d; +}; + +/** + * struct mpcc_blnd_cfg - MPCC blending configuration + */ +struct mpcc_blnd_cfg { + /** + * @black_color: background color. + */ + struct tg_color black_color; + + /** + * @alpha_mode: alpha blend mode (MPCC_ALPHA_BLND_MODE). + */ + enum mpcc_alpha_blend_mode alpha_mode; + + /** + * @pre_multiplied_alpha: + * Whether pixel color values were pre-multiplied by the alpha channel + * (MPCC_ALPHA_MULTIPLIED_MODE). + */ + bool pre_multiplied_alpha; + + /** + * @global_gain: Used when blend mode considers both pixel alpha and plane. + */ + int global_gain; + + /** + * @global_alpha: Plane alpha value. + */ + int global_alpha; + + /** + * @overlap_only: Whether overlapping of different planes is allowed. + */ + bool overlap_only; + + /* MPCC top/bottom gain settings */ + + /** + * @bottom_gain_mode: Blend mode for bottom gain setting. + */ + int bottom_gain_mode; + + /** + * @background_color_bpc: Background color for bpc. + */ + int background_color_bpc; + + /** + * @top_gain: Top gain setting. + */ + int top_gain; + + /** + * @bottom_inside_gain: Blend mode for bottom inside. + */ + int bottom_inside_gain; + + /** + * @bottom_outside_gain: Blend mode for bottom outside. + */ + int bottom_outside_gain; +}; + +struct mpc_grph_gamut_adjustment { + struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE]; + enum graphics_gamut_adjust_type gamut_adjust_type; + enum mpcc_gamut_remap_id mpcc_gamut_remap_block_id; +}; + +struct mpc_rmcm_regs { + uint32_t rmcm_3dlut_mem_pwr_state; + uint32_t rmcm_3dlut_mem_pwr_force; + uint32_t rmcm_3dlut_mem_pwr_dis; + uint32_t rmcm_3dlut_mem_pwr_mode; + uint32_t rmcm_3dlut_size; + uint32_t rmcm_3dlut_mode; + uint32_t rmcm_3dlut_mode_cur; + uint32_t rmcm_3dlut_read_sel; + uint32_t rmcm_3dlut_30bit_en; + uint32_t rmcm_3dlut_wr_en_mask; + uint32_t rmcm_3dlut_ram_sel; + uint32_t rmcm_3dlut_out_norm_factor; + uint32_t rmcm_3dlut_fl_sel; + uint32_t rmcm_3dlut_out_offset_r; + uint32_t rmcm_3dlut_out_scale_r; + uint32_t rmcm_3dlut_fl_done; + uint32_t rmcm_3dlut_fl_soft_underflow; + uint32_t rmcm_3dlut_fl_hard_underflow; + uint32_t rmcm_cntl; + uint32_t rmcm_shaper_mem_pwr_state; + uint32_t rmcm_shaper_mem_pwr_force; + uint32_t rmcm_shaper_mem_pwr_dis; + uint32_t rmcm_shaper_mem_pwr_mode; + uint32_t rmcm_shaper_lut_mode; + uint32_t rmcm_shaper_mode_cur; + uint32_t rmcm_shaper_lut_write_en_mask; + uint32_t rmcm_shaper_lut_write_sel; + uint32_t rmcm_shaper_offset_b; + uint32_t rmcm_shaper_scale_b; + uint32_t rmcm_shaper_rama_exp_region_start_b; + uint32_t rmcm_shaper_rama_exp_region_start_seg_b; + uint32_t rmcm_shaper_rama_exp_region_end_b; + uint32_t rmcm_shaper_rama_exp_region_end_base_b; +}; + +struct mpcc_sm_cfg { + bool enable; + /* 0-single plane,2-row subsampling,4-column subsampling,6-checkboard subsampling */ + int sm_mode; + /* 0- disable frame alternate, 1- enable frame alternate */ + bool frame_alt; + /* 0- disable field alternate, 1- enable field alternate */ + bool field_alt; + /* 0-no force,2-force frame polarity from top,3-force frame polarity from bottom */ + int force_next_frame_porlarity; + /* 0-no force,2-force field polarity from top,3-force field polarity from bottom */ + int force_next_field_polarity; +}; + +struct mpc_denorm_clamp { + int clamp_max_r_cr; + int clamp_min_r_cr; + int clamp_max_g_y; + int clamp_min_g_y; + int clamp_max_b_cb; + int clamp_min_b_cb; +}; + +struct mpc_dwb_flow_control { + int flow_ctrl_mode; + int flow_ctrl_cnt0; + int flow_ctrl_cnt1; +}; + +/** + * struct mpcc - MPCC connection and blending configuration for a single MPCC instance. + * + * This struct is used as a node in an MPC tree. + */ +struct mpcc { + /** + * @mpcc_id: MPCC physical instance. + */ + int mpcc_id; + + /** + * @dpp_id: DPP input to this MPCC + */ + int dpp_id; + + /** + * @mpcc_bot: Pointer to bottom layer MPCC. NULL when not connected. + */ + struct mpcc *mpcc_bot; + + /** + * @blnd_cfg: The blending configuration for this MPCC. + */ + struct mpcc_blnd_cfg blnd_cfg; + + /** + * @sm_cfg: stereo mix setting for this MPCC + */ + struct mpcc_sm_cfg sm_cfg; + + /** + * @shared_bottom: + * + * If MPCC output to both OPP and DWB endpoints, true. Otherwise, false. + */ + bool shared_bottom; +}; + +/** + * struct mpc_tree - MPC tree represents all MPCC connections for a pipe. + * + * + */ +struct mpc_tree { + /** + * @opp_id: The OPP instance that owns this MPC tree. + */ + int opp_id; + + /** + * @opp_list: the top MPCC layer of the MPC tree that outputs to OPP endpoint + */ + struct mpcc *opp_list; +}; + +struct mpc { + const struct mpc_funcs *funcs; + struct dc_context *ctx; + + struct mpcc mpcc_array[MAX_MPCC]; + struct pwl_params blender_params; + bool cm_bypass_mode; +}; + +struct mpcc_state { + uint32_t opp_id; + uint32_t dpp_id; + uint32_t bot_mpcc_id; + uint32_t mode; + uint32_t alpha_mode; + uint32_t pre_multiplied_alpha; + uint32_t overlap_only; + uint32_t idle; + uint32_t busy; + uint32_t shaper_lut_mode; + uint32_t lut3d_mode; + uint32_t lut3d_bit_depth; + uint32_t lut3d_size; + uint32_t rgam_mode; + uint32_t rgam_lut; + struct mpc_grph_gamut_adjustment gamut_remap; + struct mpc_rmcm_regs rmcm_regs; +}; + +struct dcn_mpc_reg_state { + uint32_t mpcc_bot_sel; + uint32_t mpcc_control; + uint32_t mpcc_status; + uint32_t mpcc_top_sel; + uint32_t mpcc_opp_id; + uint32_t mpcc_ogam_control; +}; + +/** + * struct mpc_funcs - funcs + */ +struct mpc_funcs { + /** + * @read_mpcc_state: + * + * Read register content from given MPCC physical instance. + * + * Parameters: + * + * - [in/out] mpc - MPC context + * - [in] mpcc_instance - MPC context instance + * - [in] mpcc_state - MPC context state + * + * Return: + * + * void + */ + void (*read_mpcc_state)( + struct mpc *mpc, + int mpcc_inst, + struct mpcc_state *s); + /** + * @mpc_read_reg_state: + * + * Read MPC register state for debugging underflow purposes. + * + * Parameters: + * + * - [in] mpc - MPC context + * - [out] reg_state - MPC register state structure + * + * Return: + * + * void + */ + void (*mpc_read_reg_state)( + struct mpc *mpc, + int mpcc_inst, + struct dcn_mpc_reg_state *mpc_reg_state); + + /** + * @insert_plane: + * + * Insert DPP into MPC tree based on specified blending position. + * Only used for planes that are part of blending chain for OPP output + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * - [in/out] tree - MPC tree structure that plane will be added to. + * - [in] blnd_cfg - MPCC blending configuration for the new blending layer. + * - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. + * stereo mix must disable for the very bottom layer of the tree config. + * - [in] insert_above_mpcc - Insert new plane above this MPCC. + * If NULL, insert as bottom plane. + * - [in] dpp_id - DPP instance for the plane to be added. + * - [in] mpcc_id - The MPCC physical instance to use for blending. + * + * Return: + * + * struct mpcc* - MPCC that was added. + */ + struct mpcc* (*insert_plane)( + struct mpc *mpc, + struct mpc_tree *tree, + struct mpcc_blnd_cfg *blnd_cfg, + struct mpcc_sm_cfg *sm_cfg, + struct mpcc *insert_above_mpcc, + int dpp_id, + int mpcc_id); + + /** + * @remove_mpcc: + * + * Remove a specified MPCC from the MPC tree. + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * - [in/out] tree - MPC tree structure that plane will be removed from. + * - [in/out] mpcc - MPCC to be removed from tree. + * + * Return: + * + * void + */ + void (*remove_mpcc)( + struct mpc *mpc, + struct mpc_tree *tree, + struct mpcc *mpcc); + + /** + * @mpc_init: + * + * Reset the MPCC HW status by disconnecting all muxes. + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * + * Return: + * + * void + */ + void (*mpc_init)(struct mpc *mpc); + + /** + * @mpc_init_single_inst: + * + * Initialize given MPCC physical instance. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id - The MPCC physical instance to be initialized. + */ + void (*mpc_init_single_inst)( + struct mpc *mpc, + unsigned int mpcc_id); + + /** + * @update_blending: + * + * Update the blending configuration for a specified MPCC. + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * - [in] blnd_cfg - MPCC blending configuration. + * - [in] mpcc_id - The MPCC physical instance. + * + * Return: + * + * void + */ + void (*update_blending)( + struct mpc *mpc, + struct mpcc_blnd_cfg *blnd_cfg, + int mpcc_id); + + /** + * @cursor_lock: + * + * Lock cursor updates for the specified OPP. OPP defines the set of + * MPCC that are locked together for cursor. + * + * Parameters: + * + * - [in] mpc - MPC context. + * - [in] opp_id - The OPP to lock cursor updates on + * - [in] lock - lock/unlock the OPP + * + * Return: + * + * void + */ + void (*cursor_lock)( + struct mpc *mpc, + int opp_id, + bool lock); + + /** + * @insert_plane_to_secondary: + * + * Add DPP into secondary MPC tree based on specified blending + * position. Only used for planes that are part of blending chain for + * DWB output + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * - [in/out] tree - MPC tree structure that plane will be added to. + * - [in] blnd_cfg - MPCC blending configuration for the new blending layer. + * - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. + * stereo mix must disable for the very bottom layer of the tree config. + * - [in] insert_above_mpcc - Insert new plane above this MPCC. If + * NULL, insert as bottom plane. + * - [in] dpp_id - DPP instance for the plane to be added. + * - [in] mpcc_id - The MPCC physical instance to use for blending. + * + * Return: + * + * struct mpcc* - MPCC that was added. + */ + struct mpcc* (*insert_plane_to_secondary)( + struct mpc *mpc, + struct mpc_tree *tree, + struct mpcc_blnd_cfg *blnd_cfg, + struct mpcc_sm_cfg *sm_cfg, + struct mpcc *insert_above_mpcc, + int dpp_id, + int mpcc_id); + + /** + * @remove_mpcc_from_secondary: + * + * Remove a specified DPP from the 'secondary' MPC tree. + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * - [in/out] tree - MPC tree structure that plane will be removed from. + * - [in] mpcc - MPCC to be removed from tree. + * + * Return: + * + * void + */ + void (*remove_mpcc_from_secondary)( + struct mpc *mpc, + struct mpc_tree *tree, + struct mpcc *mpcc); + + /** + * @get_mpcc_for_dpp_from_secondary: + * + * Find, if it exists, a MPCC from a given 'secondary' MPC tree that + * is associated with specified plane. + * + * Parameters: + * - [in/out] tree - MPC tree structure to search for plane. + * - [in] dpp_id - DPP to be searched. + * + * Return: + * + * struct mpcc* - pointer to plane or NULL if no plane found. + */ + struct mpcc* (*get_mpcc_for_dpp_from_secondary)( + struct mpc_tree *tree, + int dpp_id); + + /** + * @get_mpcc_for_dpp: + * + * Find, if it exists, a MPCC from a given MPC tree that + * is associated with specified plane. + * + * Parameters: + * - [in/out] tree - MPC tree structure to search for plane. + * - [in] dpp_id - DPP to be searched. + * + * Return: + * + * struct mpcc* - pointer to plane or NULL if no plane found. + */ + struct mpcc* (*get_mpcc_for_dpp)( + struct mpc_tree *tree, + int dpp_id); + + /** + * @wait_for_idle: + * + * Wait for a MPCC in MPC context to enter idle state. + * + * Parameters: + * - [in/out] mpc - MPC Context. + * - [in] id - MPCC to wait for idle state. + * + * Return: + * + * void + */ + void (*wait_for_idle)(struct mpc *mpc, int id); + + /** + * @assert_mpcc_idle_before_connect: + * + * Assert if MPCC in MPC context is in idle state. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] id - MPCC to assert idle state. + * + * Return: + * + * void + */ + void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); + + /** + * @init_mpcc_list_from_hw: + * + * Iterate through the MPCC array from a given MPC context struct + * and configure each MPCC according to its registers' values. + * + * Parameters: + * - [in/out] mpc - MPC context to initialize MPCC array. + * - [in/out] tree - MPC tree structure containing MPCC contexts to initialize. + * + * Return: + * + * void + */ + void (*init_mpcc_list_from_hw)( + struct mpc *mpc, + struct mpc_tree *tree); + + /** + * @set_denorm: + * + * Set corresponding OPP DENORM_CONTROL register value to specific denorm_mode + * based on given color depth. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] opp_id - Corresponding OPP to update register. + * - [in] output_depth - Arbitrary color depth to set denorm_mode. + * + * Return: + * + * void + */ + void (*set_denorm)(struct mpc *mpc, + int opp_id, + enum dc_color_depth output_depth); + + /** + * @set_denorm_clamp: + * + * Set denorm clamp values on corresponding OPP DENORM CONTROL register. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] opp_id - Corresponding OPP to update register. + * - [in] denorm_clamp - Arbitrary denorm clamp to be set. + * + * Return: + * + * void + */ + void (*set_denorm_clamp)( + struct mpc *mpc, + int opp_id, + struct mpc_denorm_clamp denorm_clamp); + + /** + * @set_output_csc: + * + * Set the Output Color Space Conversion matrix + * with given values and mode. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] opp_id - Corresponding OPP to update register. + * - [in] regval - Values to set in CSC matrix. + * - [in] ocsc_mode - Mode to set CSC. + * + * Return: + * + * void + */ + void (*set_output_csc)(struct mpc *mpc, + int opp_id, + const uint16_t *regval, + enum mpc_output_csc_mode ocsc_mode); + + /** + * @set_ocsc_default: + * + * Set the Output Color Space Conversion matrix + * to default values according to color space. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] opp_id - Corresponding OPP to update register. + * - [in] color_space - OCSC color space. + * - [in] ocsc_mode - Mode to set CSC. + * + * Return: + * + * void + * + */ + void (*set_ocsc_default)(struct mpc *mpc, + int opp_id, + enum dc_color_space color_space, + enum mpc_output_csc_mode ocsc_mode); + + /** + * @set_output_gamma: + * + * Set Output Gamma with given curve parameters. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id - Corresponding MPC to update registers. + * - [in] params - Parameters. + * + * Return: + * + * void + * + */ + void (*set_output_gamma)( + struct mpc *mpc, + int mpcc_id, + const struct pwl_params *params); + /** + * @power_on_mpc_mem_pwr: + * + * Power on/off memory LUT for given MPCC. + * Powering on enables LUT to be updated. + * Powering off allows entering low power mode. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id - MPCC to power on. + * - [in] power_on + * + * Return: + * + * void + */ + void (*power_on_mpc_mem_pwr)( + struct mpc *mpc, + int mpcc_id, + bool power_on); + /** + * @set_dwb_mux: + * + * Set corresponding Display Writeback mux + * MPC register field to given MPCC id. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] dwb_id - DWB to be set. + * - [in] mpcc_id - MPCC id to be stored in DWB mux register. + * + * Return: + * + * void + */ + void (*set_dwb_mux)( + struct mpc *mpc, + int dwb_id, + int mpcc_id); + + /** + * @disable_dwb_mux: + * + * Reset corresponding Display Writeback mux + * MPC register field. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] dwb_id - DWB to be set. + * + * Return: + * + * void + */ + void (*disable_dwb_mux)( + struct mpc *mpc, + int dwb_id); + + /** + * @is_dwb_idle: + * + * Check DWB status on MPC_DWB0_MUX_STATUS register field. + * Return if it is null. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] dwb_id - DWB to be checked. + * + * Return: + * + * bool - wheter DWB is idle or not + */ + bool (*is_dwb_idle)( + struct mpc *mpc, + int dwb_id); + + /** + * @set_out_rate_control: + * + * Set display output rate control. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] opp_id - OPP to be set. + * - [in] enable + * - [in] rate_2x_mode + * - [in] flow_control + * + * Return: + * + * void + */ + void (*set_out_rate_control)( + struct mpc *mpc, + int opp_id, + bool enable, + bool rate_2x_mode, + struct mpc_dwb_flow_control *flow_control); + + /** + * @set_gamut_remap: + * + * Set post-blending CTM for given MPCC. + * + * Parameters: + * - [in] mpc - MPC context. + * - [in] mpcc_id - MPCC to set gamut map. + * - [in] adjust + * + * Return: + * + * void + */ + void (*set_gamut_remap)( + struct mpc *mpc, + int mpcc_id, + const struct mpc_grph_gamut_adjustment *adjust); + + /** + * @program_1dlut: + * + * Set 1 dimensional Lookup Table. + * + * Parameters: + * - [in/out] mpc - MPC context + * - [in] params - curve parameters for the LUT configuration + * - [in] rmu_idx + * + * bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). + */ + bool (*program_1dlut)( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t rmu_idx); + + /** + * @program_shaper: + * + * Set shaper. + * + * Parameters: + * - [in/out] mpc - MPC context + * - [in] params - curve parameters to be set + * - [in] rmu_idx + * + * Return: + * + * bool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disabled). + */ + bool (*program_shaper)( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t rmu_idx); + + /** + * @acquire_rmu: + * + * Set given MPCC to be multiplexed to given RMU unit. + * + * Parameters: + * - [in/out] mpc - MPC context + * - [in] mpcc_id - MPCC + * - [in] rmu_idx - Given RMU unit to set MPCC to be multiplexed to. + * + * Return: + * + * unit32_t - rmu_idx if operation was successful, -1 else. + */ + uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx); + + /** + * @program_3dlut: + * + * Set 3 dimensional Lookup Table. + * + * Parameters: + * - [in/out] mpc - MPC context + * - [in] params - tetrahedral parameters for the LUT configuration + * - [in] rmu_idx + * + * bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). + */ + bool (*program_3dlut)( + struct mpc *mpc, + const struct tetrahedral_params *params, + int rmu_idx); + + /** + * @release_rmu: + * + * For a given MPCC, release the RMU unit it muliplexes to. + * + * Parameters: + * - [in/out] mpc - MPC context + * - [in] mpcc_id - MPCC + * + * Return: + * + * int - a valid rmu_idx representing released RMU unit or -1 if there was no RMU unit to release. + */ + int (*release_rmu)(struct mpc *mpc, int mpcc_id); + + /** + * @get_mpc_out_mux: + * + * Return MPC out mux. + * + * Parameters: + * - [in] mpc - MPC context. + * - [in] opp_id - OPP + * + * Return: + * + * unsigned int - Out Mux + */ + unsigned int (*get_mpc_out_mux)( + struct mpc *mpc, + int opp_id); + + /** + * @set_bg_color: + * + * Find corresponding bottommost MPCC and + * set its bg color. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] bg_color - background color to be set. + * - [in] mpcc_id + * + * Return: + * + * void + */ + void (*set_bg_color)(struct mpc *mpc, + struct tg_color *bg_color, + int mpcc_id); + + /** + * @set_mpc_mem_lp_mode: + * + * Set mpc_mem_lp_mode. + * + * Parameters: + * - [in/out] mpc - MPC context. + * + * Return: + * + * void + */ + + void (*set_mpc_mem_lp_mode)(struct mpc *mpc); + /** + * @set_movable_cm_location: + * + * Set Movable CM Location. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] location + * - [in] mpcc_id + * + * Return: + * + * void + */ + + void (*set_movable_cm_location)(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); + /** + * @update_3dlut_fast_load_select: + * + * Update 3D LUT fast load select. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id + * - [in] hubp_idx + * + * Return: + * + * void + */ + + void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); + + /** + * @populate_lut: + * + * Populate LUT with given tetrahedral parameters. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] id + * - [in] params + * - [in] lut_bank_a + * - [in] mpcc_id + * + * Return: + * + * void + */ + void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id); + + /** + * @program_lut_read_write_control: + * + * Program LUT RW control. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] id + * - [in] lut_bank_a + * - [in] mpcc_id + * + * Return: + * + * void + */ + void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id); + + /** + * @program_lut_mode: + * + * Program LUT mode. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] id + * - [in] xable + * - [in] lut_bank_a + * - [in] mpcc_id + * + * Return: + * + * void + */ + void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable, + bool lut_bank_a, int mpcc_id); + + /** + * @mcm: + * + * MPC MCM new HW sequential programming functions + */ + struct { + void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id); + void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); + void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); + bool (*is_config_supported)(uint32_t width); + void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, + bool lut_bank_a, bool enabled, int mpcc_id); + + void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id); + } mcm; + + /** + * @rmcm: + * + * MPC RMCM new HW sequential programming functions + */ + struct { + void (*fl_3dlut_configure)(struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, int mpcc_id); + void (*enable_3dlut_fl)(struct mpc *mpc, bool enable, int mpcc_id); + void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); + void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, + bool lut_bank_a, bool enabled, int mpcc_id); + void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_XABLE xable, + bool lut_bank_a, int mpcc_id); + void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id); + void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); + void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); + bool (*is_config_supported)(uint32_t width); + + void (*power_on_shaper_3dlut)(struct mpc *mpc, uint32_t mpcc_id, bool power_on); + void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id); + } rmcm; +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h new file mode 100644 index 000000000000..e1428a83ecbc --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -0,0 +1,386 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +/** + * DOC: overview + * + * The Output Plane Processor (OPP) block groups have functions that format + * pixel streams such that they are suitable for display at the display device. + * The key functions contained in the OPP are: + * + * - Adaptive Backlight Modulation (ABM) + * - Formatter (FMT) which provide pixel-by-pixel operations for format the + * incoming pixel stream. + * - Output Buffer that provide pixel replication, and overlapping. + * - Interface between MPC and OPTC. + * - Clock and reset generation. + * - CRC generation. + */ + +#ifndef __DAL_OPP_H__ +#define __DAL_OPP_H__ + +#include "hw_shared.h" +#include "dc_hw_types.h" +#include "transform.h" +#include "mpc.h" + +struct fixed31_32; + +/* TODO: Need cleanup */ +enum clamping_range { + CLAMPING_FULL_RANGE = 0, /* No Clamping */ + CLAMPING_LIMITED_RANGE_8BPC, /* 8 bpc: Clamping 1 to FE */ + CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4 to 3FB */ + CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */ + /* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */ + CLAMPING_LIMITED_RANGE_PROGRAMMABLE +}; + +struct clamping_and_pixel_encoding_params { + enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */ + enum clamping_range clamping_level; /* Clamping identifier */ + enum dc_color_depth c_depth; /* Deep color use. */ +}; + +struct bit_depth_reduction_params { + struct { + /* truncate/round */ + /* trunc/round enabled*/ + uint32_t TRUNCATE_ENABLED:1; + /* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/ + uint32_t TRUNCATE_DEPTH:2; + /* truncate or round*/ + uint32_t TRUNCATE_MODE:1; + + /* spatial dither */ + /* Spatial Bit Depth Reduction enabled*/ + uint32_t SPATIAL_DITHER_ENABLED:1; + /* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/ + uint32_t SPATIAL_DITHER_DEPTH:2; + /* 0-3 to select patterns*/ + uint32_t SPATIAL_DITHER_MODE:2; + /* Enable RGB random dithering*/ + uint32_t RGB_RANDOM:1; + /* Enable Frame random dithering*/ + uint32_t FRAME_RANDOM:1; + /* Enable HighPass random dithering*/ + uint32_t HIGHPASS_RANDOM:1; + + /* temporal dither*/ + /* frame modulation enabled*/ + uint32_t FRAME_MODULATION_ENABLED:1; + /* same as for trunc/spatial*/ + uint32_t FRAME_MODULATION_DEPTH:2; + /* 2/4 gray levels*/ + uint32_t TEMPORAL_LEVEL:1; + uint32_t FRC25:2; + uint32_t FRC50:2; + uint32_t FRC75:2; + } flags; + + uint32_t r_seed_value; + uint32_t b_seed_value; + uint32_t g_seed_value; + enum dc_pixel_encoding pixel_encoding; +}; + +enum wide_gamut_regamma_mode { + /* 0x0 - BITS2:0 Bypass */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS, + /* 0x1 - Fixed curve sRGB 2.4 */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24, + /* 0x2 - Fixed curve xvYCC 2.22 */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_XYYCC22, + /* 0x3 - Programmable control A */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A, + /* 0x4 - Programmable control B */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_B, + /* 0x0 - BITS6:4 Bypass */ + WIDE_GAMUT_REGAMMA_MODE_OVL_BYPASS, + /* 0x1 - Fixed curve sRGB 2.4 */ + WIDE_GAMUT_REGAMMA_MODE_OVL_SRGB24, + /* 0x2 - Fixed curve xvYCC 2.22 */ + WIDE_GAMUT_REGAMMA_MODE_OVL_XYYCC22, + /* 0x3 - Programmable control A */ + WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_A, + /* 0x4 - Programmable control B */ + WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_B +}; + +struct gamma_pixel { + struct fixed31_32 r; + struct fixed31_32 g; + struct fixed31_32 b; +}; + +enum channel_name { + CHANNEL_NAME_RED, + CHANNEL_NAME_GREEN, + CHANNEL_NAME_BLUE +}; + +struct custom_float_format { + uint32_t mantissa_bits; + uint32_t exponenta_bits; + bool sign; +}; + +struct custom_float_value { + uint32_t mantissa; + uint32_t exponenta; + uint32_t value; + bool negative; +}; + +struct hw_x_point { + uint32_t custom_float_x; + struct fixed31_32 x; + struct fixed31_32 regamma_y_red; + struct fixed31_32 regamma_y_green; + struct fixed31_32 regamma_y_blue; + +}; + +struct pwl_float_data_ex { + struct fixed31_32 r; + struct fixed31_32 g; + struct fixed31_32 b; + struct fixed31_32 delta_r; + struct fixed31_32 delta_g; + struct fixed31_32 delta_b; +}; + +enum hw_point_position { + /* hw point sits between left and right sw points */ + HW_POINT_POSITION_MIDDLE, + /* hw point lays left from left (smaller) sw point */ + HW_POINT_POSITION_LEFT, + /* hw point lays stays from right (bigger) sw point */ + HW_POINT_POSITION_RIGHT +}; + +struct gamma_point { + int32_t left_index; + int32_t right_index; + enum hw_point_position pos; + struct fixed31_32 coeff; +}; + +struct pixel_gamma_point { + struct gamma_point r; + struct gamma_point g; + struct gamma_point b; +}; + +struct gamma_coefficients { + struct fixed31_32 a0[3]; + struct fixed31_32 a1[3]; + struct fixed31_32 a2[3]; + struct fixed31_32 a3[3]; + struct fixed31_32 user_gamma[3]; + struct fixed31_32 user_contrast; + struct fixed31_32 user_brightness; +}; + +/** + * struct pwl_float_data - Fixed point RGB color + */ +struct pwl_float_data { + /** + * @r: Component Red. + */ + struct fixed31_32 r; + + /** + * @g: Component Green. + */ + + struct fixed31_32 g; + + /** + * @b: Component Blue. + */ + struct fixed31_32 b; +}; + +struct mpc_tree_cfg { + int num_pipes; + int dpp[MAX_PIPES]; + int mpcc[MAX_PIPES]; +}; + +struct output_pixel_processor { + struct dc_context *ctx; + uint32_t inst; + struct pwl_params regamma_params; + struct mpc_tree mpc_tree_params; + bool mpcc_disconnect_pending[MAX_PIPES]; + const struct opp_funcs *funcs; + uint32_t dyn_expansion; +}; + +enum fmt_stereo_action { + FMT_STEREO_ACTION_ENABLE = 0, + FMT_STEREO_ACTION_DISABLE, + FMT_STEREO_ACTION_UPDATE_POLARITY +}; + +struct opp_grph_csc_adjustment { + //enum grph_color_adjust_option color_adjust_option; + enum dc_color_space c_space; + enum dc_color_depth color_depth; /* clean up to uint32_t */ + enum graphics_csc_adjust_type csc_adjust_type; + int32_t adjust_divider; + int32_t grph_cont; + int32_t grph_sat; + int32_t grph_bright; + int32_t grph_hue; +}; + +/* Underlay related types */ + +struct hw_adjustment_range { + int32_t hw_default; + int32_t min; + int32_t max; + int32_t step; + uint32_t divider; /* (actually HW range is min/divider; divider !=0) */ +}; + +enum ovl_csc_adjust_item { + OVERLAY_BRIGHTNESS = 0, + OVERLAY_GAMMA, + OVERLAY_CONTRAST, + OVERLAY_SATURATION, + OVERLAY_HUE, + OVERLAY_ALPHA, + OVERLAY_ALPHA_PER_PIX, + OVERLAY_COLOR_TEMPERATURE +}; + +enum oppbuf_display_segmentation { + OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0, + OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1, + OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2, + OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3, + OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4 +}; + +struct oppbuf_params { + uint32_t active_width; + enum oppbuf_display_segmentation mso_segmentation; + uint32_t mso_overlap_pixel_num; + uint32_t pixel_repetition; + uint32_t num_segment_padded_pixels; +}; + +struct dcn_opp_reg_state { + uint32_t dpg_control; + uint32_t fmt_control; + uint32_t oppbuf_control; + uint32_t opp_pipe_control; + uint32_t opp_pipe_crc_control; + uint32_t opp_abm_control; + uint32_t dscrm_dsc_forward_config; +}; + +struct opp_funcs { + + + /* FORMATTER RELATED */ + + void (*opp_program_fmt)( + struct output_pixel_processor *opp, + struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping); + + void (*opp_set_dyn_expansion)( + struct output_pixel_processor *opp, + enum dc_color_space color_sp, + enum dc_color_depth color_dpth, + enum signal_type signal); + + void (*opp_program_bit_depth_reduction)( + struct output_pixel_processor *opp, + const struct bit_depth_reduction_params *params); + + /* underlay related */ + void (*opp_get_underlay_adjustment_range)( + struct output_pixel_processor *opp, + enum ovl_csc_adjust_item overlay_adjust_item, + struct hw_adjustment_range *range); + + void (*opp_destroy)(struct output_pixel_processor **opp); + + void (*opp_program_stereo)( + struct output_pixel_processor *opp, + bool enable, + const struct dc_crtc_timing *timing); + + void (*opp_pipe_clock_control)( + struct output_pixel_processor *opp, + bool enable); + + void (*opp_set_disp_pattern_generator)( + struct output_pixel_processor *opp, + enum controller_dp_test_pattern test_pattern, + enum controller_dp_color_space color_space, + enum dc_color_depth color_depth, + const struct tg_color *solid_color, + int width, + int height, + int offset); + + void (*opp_program_dpg_dimensions)( + struct output_pixel_processor *opp, + int width, + int height); + + bool (*dpg_is_blanked)( + struct output_pixel_processor *opp); + + bool (*dpg_is_pending)(struct output_pixel_processor *opp); + + + void (*opp_dpg_set_blank_color)( + struct output_pixel_processor *opp, + const struct tg_color *color); + + void (*opp_program_left_edge_extra_pixel)( + struct output_pixel_processor *opp, + enum dc_pixel_encoding pixel_encoding, + bool is_primary); + + uint32_t (*opp_get_left_edge_extra_pixel_count)( + struct output_pixel_processor *opp, + enum dc_pixel_encoding pixel_encoding, + bool is_primary); + + void (*opp_read_reg_state)( + struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state); +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h new file mode 100644 index 000000000000..0d5a8358a778 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +/** + * DOC: overview + * + * Output Pipe Timing Combiner (OPTC) includes two major functional blocks: + * Output Data Mapper (ODM) and Output Timing Generator (OTG). + * + * - ODM: It is Output Data Mapping block. It can combine input data from + * multiple OPP data pipes into one single data stream or split data from one + * OPP data pipe into multiple data streams or just bypass OPP data to DIO. + * - OTG: It is Output Timing Generator. It generates display timing signals to + * drive the display output. + */ + +#ifndef __DC_OPTC_H__ +#define __DC_OPTC_H__ + +#include "timing_generator.h" + +struct optc { + struct timing_generator base; + + const struct dcn_optc_registers *tg_regs; + const struct dcn_optc_shift *tg_shift; + const struct dcn_optc_mask *tg_mask; + + int opp_count; + + uint32_t max_h_total; + uint32_t max_v_total; + + uint32_t min_h_blank; + + uint32_t min_h_sync_width; + uint32_t min_v_sync_width; + uint32_t min_v_blank; + uint32_t min_v_blank_interlace; + + int vstartup_start; + int vupdate_offset; + int vupdate_width; + int vready_offset; + int pstate_keepout; + struct dc_crtc_timing orginal_patched_timing; + enum signal_type signal; + uint32_t max_frame_count; +}; + +void optc1_read_otg_state(struct timing_generator *optc, struct dcn_otg_state *s); + +bool optc1_get_hw_timing(struct timing_generator *tg, struct dc_crtc_timing *hw_crtc_timing); + +bool optc1_validate_timing(struct timing_generator *optc, + const struct dc_crtc_timing *timing); + +void optc1_program_timing(struct timing_generator *optc, + const struct dc_crtc_timing *dc_crtc_timing, + int vready_offset, + int vstartup_start, + int vupdate_offset, + int vupdate_width, + int pstate_keepout, + const enum signal_type signal, + bool use_vbios); + +void optc1_setup_vertical_interrupt0(struct timing_generator *optc, + uint32_t start_line, + uint32_t end_line); + +void optc1_setup_vertical_interrupt1(struct timing_generator *optc, + uint32_t start_line); + +void optc1_setup_vertical_interrupt2(struct timing_generator *optc, + uint32_t start_line); + +void optc1_program_global_sync(struct timing_generator *optc, + int vready_offset, + int vstartup_start, + int vupdate_offset, + int vupdate_width, + int pstate_keepout); + +bool optc1_disable_crtc(struct timing_generator *optc); + +bool optc1_is_counter_moving(struct timing_generator *optc); + +void optc1_get_position(struct timing_generator *optc, + struct crtc_position *position); + +uint32_t optc1_get_vblank_counter(struct timing_generator *optc); + +void optc1_get_crtc_scanoutpos(struct timing_generator *optc, + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); + +void optc1_set_early_control(struct timing_generator *optc, + uint32_t early_cntl); + +void optc1_wait_for_state(struct timing_generator *optc, + enum crtc_state state); + +void optc1_set_blank(struct timing_generator *optc, + bool enable_blanking); + +bool optc1_is_blanked(struct timing_generator *optc); + +void optc1_program_blank_color(struct timing_generator *optc, + const struct tg_color *black_color); + +bool optc1_did_triggered_reset_occur(struct timing_generator *optc); + +void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst); + +void optc1_disable_reset_trigger(struct timing_generator *optc); + +void optc1_lock(struct timing_generator *optc); + +void optc1_unlock(struct timing_generator *optc); + +void optc1_enable_optc_clock(struct timing_generator *optc, bool enable); + +void optc1_set_drr(struct timing_generator *optc, + const struct drr_params *params); + +void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); + +void optc1_set_static_screen_control(struct timing_generator *optc, + uint32_t event_triggers, + uint32_t num_frames); + +void optc1_program_stereo(struct timing_generator *optc, + const struct dc_crtc_timing *timing, + struct crtc_stereo_flags *flags); + +bool optc1_is_stereo_left_eye(struct timing_generator *optc); + +void optc1_clear_optc_underflow(struct timing_generator *optc); + +void optc1_tg_init(struct timing_generator *optc); + +bool optc1_is_tg_enabled(struct timing_generator *optc); + +bool optc1_is_optc_underflow_occurred(struct timing_generator *optc); + +void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable); + +void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable); + +bool optc1_get_otg_active_size(struct timing_generator *optc, + uint32_t *otg_active_width, + uint32_t *otg_active_height); + +void optc1_enable_crtc_reset(struct timing_generator *optc, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp); + +bool optc1_configure_crc(struct timing_generator *optc, const struct crc_params *params); + +bool optc1_get_crc(struct timing_generator *optc, uint8_t idx, + uint32_t *r_cr, + uint32_t *g_y, + uint32_t *b_cb); + +void optc1_set_vtg_params(struct timing_generator *optc, + const struct dc_crtc_timing *dc_crtc_timing, + bool program_fp2); + +bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h b/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h new file mode 100644 index 000000000000..e97d964a1791 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h @@ -0,0 +1,72 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +/* + * panel_cntl.h + * + * Created on: Oct 6, 2015 + * Author: yonsun + */ + +#ifndef DC_PANEL_CNTL_H_ +#define DC_PANEL_CNTL_H_ + +#include "dc_types.h" + +#define MAX_BACKLIGHT_LEVEL 0xFFFF + +struct panel_cntl_backlight_registers { + unsigned int BL_PWM_CNTL; + unsigned int BL_PWM_CNTL2; + unsigned int BL_PWM_PERIOD_CNTL; + unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV; + unsigned int PANEL_PWRSEQ_REF_DIV2; + unsigned int USER_LEVEL; +}; + +struct panel_cntl_funcs { + void (*destroy)(struct panel_cntl **panel_cntl); + uint32_t (*hw_init)(struct panel_cntl *panel_cntl); + bool (*is_panel_backlight_on)(struct panel_cntl *panel_cntl); + bool (*is_panel_powered_on)(struct panel_cntl *panel_cntl); + void (*store_backlight_level)(struct panel_cntl *panel_cntl); + void (*driver_set_backlight)(struct panel_cntl *panel_cntl, + uint32_t backlight_pwm_u16_16); + uint32_t (*get_current_backlight)(struct panel_cntl *panel_cntl); +}; + +struct panel_cntl_init_data { + struct dc_context *ctx; + uint32_t inst; + uint32_t eng_id; +}; + +struct panel_cntl { + const struct panel_cntl_funcs *funcs; + struct dc_context *ctx; + uint32_t inst; + uint32_t pwrseq_inst; + /* registers setting needs to be saved and restored at InitBacklight */ + struct panel_cntl_backlight_registers stored_backlight_registers; +}; + +#endif /* DC_PANEL_CNTL_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h b/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h new file mode 100644 index 000000000000..227e3f8d7e5f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h @@ -0,0 +1,55 @@ +/* Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_PG_CNTL_H__ +#define __DC_PG_CNTL_H__ + +#include "dc.h" +#include "dc_types.h" +#include "hw_shared.h" + +struct pg_cntl { + struct dc_context *ctx; + const struct pg_cntl_funcs *funcs; + bool pg_pipe_res_enable[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; + bool pg_res_enable[PG_HW_RESOURCES_NUM_ELEMENT]; +}; + +struct pg_cntl_funcs { + void (*dsc_pg_control)(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on); + void (*hubp_dpp_pg_control)(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on); + void (*hpo_pg_control)(struct pg_cntl *pg_cntl, bool power_on); + void (*io_clk_pg_control)(struct pg_cntl *pg_cntl, bool power_on); + void (*plane_otg_pg_control)(struct pg_cntl *pg_cntl, bool power_on); + void (*mpcc_pg_control)(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on); + void (*opp_pg_control)(struct pg_cntl *pg_cntl, unsigned int opp_inst, bool power_on); + void (*optc_pg_control)(struct pg_cntl *pg_cntl, unsigned int optc_inst, bool power_on); + void (*dwb_pg_control)(struct pg_cntl *pg_cntl, bool power_on); + void (*mem_pg_control)(struct pg_cntl *pg_cntl, bool power_on); + void (*dio_pg_control)(struct pg_cntl *pg_cntl, bool power_on); + void (*init_pg_status)(struct pg_cntl *pg_cntl); + void (*print_pg_status)(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log); +}; + +#endif //__DC_PG_CNTL_H__ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h new file mode 100644 index 000000000000..27f950ae45ee --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -0,0 +1,365 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +/* + * stream_encoder.h + * + */ + +#ifndef STREAM_ENCODER_H_ +#define STREAM_ENCODER_H_ + +#include "audio_types.h" +#include "hw_shared.h" + +struct dc_bios; +struct dc_context; +struct dc_crtc_timing; + +enum dp_pixel_encoding_type { + DP_PIXEL_ENCODING_TYPE_RGB444 = 0x00000000, + DP_PIXEL_ENCODING_TYPE_YCBCR422 = 0x00000001, + DP_PIXEL_ENCODING_TYPE_YCBCR444 = 0x00000002, + DP_PIXEL_ENCODING_TYPE_RGB_WIDE_GAMUT = 0x00000003, + DP_PIXEL_ENCODING_TYPE_Y_ONLY = 0x00000004, + DP_PIXEL_ENCODING_TYPE_YCBCR420 = 0x00000005 +}; + +enum dp_component_depth { + DP_COMPONENT_PIXEL_DEPTH_6BPC = 0x00000000, + DP_COMPONENT_PIXEL_DEPTH_8BPC = 0x00000001, + DP_COMPONENT_PIXEL_DEPTH_10BPC = 0x00000002, + DP_COMPONENT_PIXEL_DEPTH_12BPC = 0x00000003, + DP_COMPONENT_PIXEL_DEPTH_16BPC = 0x00000004 +}; + +struct audio_clock_info { + /* pixel clock frequency*/ + uint32_t pixel_clock_in_10khz; + /* N - 32KHz audio */ + uint32_t n_32khz; + /* CTS - 32KHz audio*/ + uint32_t cts_32khz; + uint32_t n_44khz; + uint32_t cts_44khz; + uint32_t n_48khz; + uint32_t cts_48khz; +}; + +enum dynamic_metadata_mode { + dmdata_dp, + dmdata_hdmi, + dmdata_dolby_vision +}; + +struct enc_sdp_line_num { + /* Adaptive Sync SDP */ + bool adaptive_sync_line_num_valid; + uint32_t adaptive_sync_line_num; +}; + +struct encoder_info_frame { + /* auxiliary video information */ + struct dc_info_packet avi; + struct dc_info_packet gamut; + struct dc_info_packet vendor; + struct dc_info_packet hfvsif; + struct dc_info_packet vtem; + /* source product description */ + struct dc_info_packet spd; + /* video stream configuration */ + struct dc_info_packet vsc; + /* HDR Static MetaData */ + struct dc_info_packet hdrsmd; + /* Adaptive Sync SDP*/ + struct dc_info_packet adaptive_sync; + struct enc_sdp_line_num sdp_line_num; +}; + +struct encoder_unblank_param { + struct dc_link_settings link_settings; + struct dc_crtc_timing timing; + int opp_cnt; + uint32_t pix_per_cycle; +}; + +struct encoder_set_dp_phy_pattern_param { + enum dp_test_pattern dp_phy_pattern; + const uint8_t *custom_pattern; + uint32_t custom_pattern_size; + enum dp_panel_mode dp_panel_mode; +}; + +struct stream_encoder { + const struct stream_encoder_funcs *funcs; + struct dc_context *ctx; + struct dc_bios *bp; + enum engine_id id; + uint32_t stream_enc_inst; + struct vpg *vpg; + struct afmt *afmt; + struct apg *apg; +}; + +struct enc_state { + uint32_t dsc_mode; // DISABLED 0; 1 or 2 indicate enabled state. + uint32_t dsc_slice_width; + uint32_t sec_gsp_pps_line_num; + uint32_t vbid6_line_reference; + uint32_t vbid6_line_num; + uint32_t sec_gsp_pps_enable; + uint32_t sec_stream_enable; +}; + +struct stream_encoder_funcs { + void (*dp_set_stream_attribute)( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + enum dc_color_space output_color_space, + bool use_vsc_sdp_for_colorimetry, + uint32_t enable_sdp_splitting); + + void (*hdmi_set_stream_attribute)( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + int actual_pix_clk_khz, + bool enable_audio); + + void (*dvi_set_stream_attribute)( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + bool is_dual_link); + + void (*lvds_set_stream_attribute)( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing); + + void (*set_throttled_vcp_size)( + struct stream_encoder *enc, + struct fixed31_32 avg_time_slots_per_mtp); + + void (*update_hdmi_info_packets)( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame); + + void (*stop_hdmi_info_packets)( + struct stream_encoder *enc); + + void (*update_dp_info_packets_sdp_line_num)( + struct stream_encoder *enc, + struct encoder_info_frame *info_frame); + + void (*update_dp_info_packets)( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame); + + void (*send_immediate_sdp_message)( + struct stream_encoder *enc, + const uint8_t *custom_sdp_message, + unsigned int sdp_message_size); + + void (*stop_dp_info_packets)( + struct stream_encoder *enc); + + void (*dp_blank)( + struct dc_link *link, + struct stream_encoder *enc); + + void (*dp_unblank)( + struct dc_link *link, + struct stream_encoder *enc, + const struct encoder_unblank_param *param); + + void (*audio_mute_control)( + struct stream_encoder *enc, bool mute); + + void (*dp_audio_setup)( + struct stream_encoder *enc, + unsigned int az_inst, + struct audio_info *info); + + void (*dp_audio_enable) ( + struct stream_encoder *enc); + + void (*dp_audio_disable) ( + struct stream_encoder *enc); + + void (*hdmi_audio_setup)( + struct stream_encoder *enc, + unsigned int az_inst, + struct audio_info *info, + struct audio_crtc_info *audio_crtc_info); + + void (*hdmi_audio_disable) ( + struct stream_encoder *enc); + + void (*setup_stereo_sync) ( + struct stream_encoder *enc, + int tg_inst, + bool enable); + + void (*set_avmute)( + struct stream_encoder *enc, bool enable); + + void (*dig_connect_to_otg)( + struct stream_encoder *enc, + int tg_inst); + + void (*enable_stream)( + struct stream_encoder *enc, + enum signal_type signal, + bool enable); + + void (*hdmi_reset_stream_attribute)( + struct stream_encoder *enc); + + unsigned int (*dig_source_otg)( + struct stream_encoder *enc); + + bool (*dp_get_pixel_format)( + struct stream_encoder *enc, + enum dc_pixel_encoding *encoding, + enum dc_color_depth *depth); + + void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s); + + void (*dp_set_dsc_config)( + struct stream_encoder *enc, + enum optc_dsc_mode dsc_mode, + uint32_t dsc_bytes_per_pixel, + uint32_t dsc_slice_width); + + void (*dp_set_dsc_pps_info_packet)(struct stream_encoder *enc, + bool enable, + uint8_t *dsc_packed_pps, + bool immediate_update); + + void (*set_dynamic_metadata)(struct stream_encoder *enc, + bool enable, + uint32_t hubp_requestor_id, + enum dynamic_metadata_mode dmdata_mode); + + /** + * @dp_set_odm_combine: Sets up DP stream encoder for ODM. + */ + void (*dp_set_odm_combine)( + struct stream_encoder *enc, + bool odm_combine); + + uint32_t (*get_fifo_cal_average_level)( + struct stream_encoder *enc); + + void (*set_input_mode)( + struct stream_encoder *enc, unsigned int pix_per_container); + void (*enable_fifo)(struct stream_encoder *enc); + void (*disable_fifo)(struct stream_encoder *enc); + bool (*is_fifo_enabled)(struct stream_encoder *enc); + void (*map_stream_to_link)(struct stream_encoder *enc, uint32_t stream_enc_inst, uint32_t link_enc_inst); + uint32_t (*get_pixels_per_cycle)(struct stream_encoder *enc); +}; + +struct hpo_dp_stream_encoder_state { + uint32_t stream_enc_enabled; + uint32_t vid_stream_enabled; + uint32_t otg_inst; + uint32_t pixel_encoding; + uint32_t component_depth; + uint32_t compressed_format; + uint32_t sdp_enabled; + uint32_t mapped_to_link_enc; +}; + +struct hpo_dp_stream_encoder { + const struct hpo_dp_stream_encoder_funcs *funcs; + struct dc_context *ctx; + struct dc_bios *bp; + uint32_t inst; + enum engine_id id; + struct vpg *vpg; + struct apg *apg; +}; + +struct hpo_dp_stream_encoder_funcs { + void (*enable_stream)( + struct hpo_dp_stream_encoder *enc); + + void (*dp_unblank)( + struct hpo_dp_stream_encoder *enc, + uint32_t stream_source); + + void (*dp_blank)( + struct hpo_dp_stream_encoder *enc); + + void (*disable)( + struct hpo_dp_stream_encoder *enc); + + void (*set_stream_attribute)( + struct hpo_dp_stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + enum dc_color_space output_color_space, + bool use_vsc_sdp_for_colorimetry, + bool compressed_format, + bool double_buffer_en); + + void (*update_dp_info_packets_sdp_line_num)( + struct hpo_dp_stream_encoder *enc, + struct encoder_info_frame *info_frame); + + void (*update_dp_info_packets)( + struct hpo_dp_stream_encoder *enc, + const struct encoder_info_frame *info_frame); + + void (*stop_dp_info_packets)( + struct hpo_dp_stream_encoder *enc); + + void (*dp_set_dsc_pps_info_packet)( + struct hpo_dp_stream_encoder *enc, + bool enable, + uint8_t *dsc_packed_pps, + bool immediate_update); + + void (*map_stream_to_link)( + struct hpo_dp_stream_encoder *enc, + uint32_t stream_enc_inst, + uint32_t link_enc_inst); + + void (*dp_audio_setup)( + struct hpo_dp_stream_encoder *enc, + unsigned int az_inst, + struct audio_info *info); + + void (*dp_audio_enable)( + struct hpo_dp_stream_encoder *enc); + + void (*dp_audio_disable)( + struct hpo_dp_stream_encoder *enc); + + void (*read_state)( + struct hpo_dp_stream_encoder *enc, + struct hpo_dp_stream_encoder_state *state); + + void (*set_hblank_min_symbol_width)( + struct hpo_dp_stream_encoder *enc, + uint16_t width); +}; + +#endif /* STREAM_ENCODER_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h new file mode 100644 index 000000000000..da7bf59c4b9d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -0,0 +1,516 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_TIMING_GENERATOR_TYPES_H__ +#define __DAL_TIMING_GENERATOR_TYPES_H__ + +#include "hw_shared.h" + +struct dc_bios; + +/* Contains CRTC vertical/horizontal pixel counters */ +struct crtc_position { + int32_t vertical_count; + int32_t horizontal_count; + int32_t nominal_vcount; +}; + +struct dcp_gsl_params { + int gsl_group; + int gsl_master; +}; + +struct gsl_params { + int gsl0_en; + int gsl1_en; + int gsl2_en; + int gsl_master_en; + int gsl_master_mode; + int master_update_lock_gsl_en; + int gsl_window_start_x; + int gsl_window_end_x; + int gsl_window_start_y; + int gsl_window_end_y; +}; + +/* define the structure of Dynamic Refresh Mode */ +struct drr_params { + uint32_t vertical_total_min; + uint32_t vertical_total_max; + uint32_t vertical_total_mid; + uint32_t vertical_total_mid_frame_num; + bool immediate_flip; +}; + +struct long_vtotal_params { + uint32_t vertical_total_min; + uint32_t vertical_total_max; + uint32_t vertical_blank_start; +}; + +#define LEFT_EYE_3D_PRIMARY_SURFACE 1 +#define RIGHT_EYE_3D_PRIMARY_SURFACE 0 + +enum crtc_state { + CRTC_STATE_VBLANK = 0, + CRTC_STATE_VACTIVE +}; + +struct vupdate_keepout_params { + int start_offset; + int end_offset; + int enable; +}; + +struct crtc_stereo_flags { + uint8_t PROGRAM_STEREO : 1; + uint8_t PROGRAM_POLARITY : 1; + uint8_t RIGHT_EYE_POLARITY : 1; + uint8_t FRAME_PACKED : 1; + uint8_t DISABLE_STEREO_DP_SYNC : 1; +}; + +enum crc_selection { + /* Order must match values expected by hardware */ + UNION_WINDOW_A_B = 0, + UNION_WINDOW_A_NOT_B, + UNION_WINDOW_NOT_A_B, + UNION_WINDOW_NOT_A_NOT_B, + INTERSECT_WINDOW_A_B, + INTERSECT_WINDOW_A_NOT_B, + INTERSECT_WINDOW_NOT_A_B, + INTERSECT_WINDOW_NOT_A_NOT_B, +}; + +enum otg_out_mux_dest { + OUT_MUX_DIO = 0, + OUT_MUX_HPO_DP = 2, +}; + +enum h_timing_div_mode { + H_TIMING_NO_DIV, + H_TIMING_DIV_BY2, + H_TIMING_RESERVED, + H_TIMING_DIV_BY4, +}; + +enum timing_synchronization_type { + NOT_SYNCHRONIZABLE, + TIMING_SYNCHRONIZABLE, + VBLANK_SYNCHRONIZABLE +}; + +struct crc_params { + /* Regions used to calculate CRC*/ + uint16_t windowa_x_start; + uint16_t windowa_x_end; + uint16_t windowa_y_start; + uint16_t windowa_y_end; + + uint16_t windowb_x_start; + uint16_t windowb_x_end; + uint16_t windowb_y_start; + uint16_t windowb_y_end; + + enum crc_selection selection; + + uint8_t dsc_mode; + uint8_t odm_mode; + + bool continuous_mode; + bool enable; + + uint8_t crc_eng_inst; + bool reset; +}; + +struct dcn_otg_state { + uint32_t v_blank_start; + uint32_t v_blank_end; + uint32_t v_sync_a_pol; + uint32_t v_total; + uint32_t v_total_max; + uint32_t v_total_min; + uint32_t v_total_min_sel; + uint32_t v_total_max_sel; + uint32_t v_sync_a_start; + uint32_t v_sync_a_end; + uint32_t h_blank_start; + uint32_t h_blank_end; + uint32_t h_sync_a_start; + uint32_t h_sync_a_end; + uint32_t h_sync_a_pol; + uint32_t h_total; + uint32_t underflow_occurred_status; + uint32_t otg_enabled; + uint32_t blank_enabled; + uint32_t vertical_interrupt1_en; + uint32_t vertical_interrupt1_line; + uint32_t vertical_interrupt2_en; + uint32_t vertical_interrupt2_line; + uint32_t vertical_interrupt2_dest; + uint32_t otg_master_update_lock; + uint32_t otg_double_buffer_control; +}; + +struct dcn_optc_reg_state { + uint32_t optc_bytes_per_pixel; + uint32_t optc_data_format_control; + uint32_t optc_data_source_select; + uint32_t optc_input_clock_control; + uint32_t optc_input_global_control; + uint32_t optc_input_spare_register; + uint32_t optc_memory_config; + uint32_t optc_rsmu_underflow; + uint32_t optc_underflow_threshold; + uint32_t optc_width_control; + + uint32_t otg_3d_structure_control; + uint32_t otg_clock_control; + uint32_t otg_control; + uint32_t otg_count_control; + uint32_t otg_count_reset; + uint32_t otg_crc_cntl; + uint32_t otg_crc_sig_blue_control_mask; + uint32_t otg_crc_sig_red_green_mask; + uint32_t otg_crc0_data_b; + uint32_t otg_crc0_data_rg; + uint32_t otg_crc0_windowa_x_control; + uint32_t otg_crc0_windowa_x_control_readback; + uint32_t otg_crc0_windowa_y_control; + uint32_t otg_crc0_windowa_y_control_readback; + uint32_t otg_crc0_windowb_x_control; + uint32_t otg_crc0_windowb_x_control_readback; + uint32_t otg_crc0_windowb_y_control; + uint32_t otg_crc0_windowb_y_control_readback; + uint32_t otg_crc1_data_b; + uint32_t otg_crc1_data_rg; + uint32_t otg_crc1_windowa_x_control; + uint32_t otg_crc1_windowa_x_control_readback; + uint32_t otg_crc1_windowa_y_control; + uint32_t otg_crc1_windowa_y_control_readback; + uint32_t otg_crc1_windowb_x_control; + uint32_t otg_crc1_windowb_x_control_readback; + uint32_t otg_crc1_windowb_y_control; + uint32_t otg_crc1_windowb_y_control_readback; + uint32_t otg_crc2_data_b; + uint32_t otg_crc2_data_rg; + uint32_t otg_crc3_data_b; + uint32_t otg_crc3_data_rg; + uint32_t otg_dlpc_control; + uint32_t otg_double_buffer_control; + uint32_t otg_drr_control2; + uint32_t otg_drr_control; + uint32_t otg_drr_timing_int_status; + uint32_t otg_drr_trigger_window; + uint32_t otg_drr_v_total_change; + uint32_t otg_drr_v_total_reach_range; + uint32_t otg_dsc_start_position; + uint32_t otg_force_count_now_cntl; + uint32_t otg_global_control0; + uint32_t otg_global_control1; + uint32_t otg_global_control2; + uint32_t otg_global_control3; + uint32_t otg_global_control4; + uint32_t otg_global_sync_status; + uint32_t otg_gsl_control; + uint32_t otg_gsl_vsync_gap; + uint32_t otg_gsl_window_x; + uint32_t otg_gsl_window_y; + uint32_t otg_h_blank_start_end; + uint32_t otg_h_sync_a; + uint32_t otg_h_sync_a_cntl; + uint32_t otg_h_timing_cntl; + uint32_t otg_h_total; + uint32_t otg_interlace_control; + uint32_t otg_interlace_status; + uint32_t otg_interrupt_control; + uint32_t otg_long_vblank_status; + uint32_t otg_m_const_dto0; + uint32_t otg_m_const_dto1; + uint32_t otg_manual_force_vsync_next_line; + uint32_t otg_master_en; + uint32_t otg_master_update_lock; + uint32_t otg_master_update_mode; + uint32_t otg_nom_vert_position; + uint32_t otg_pipe_update_status; + uint32_t otg_pixel_data_readback0; + uint32_t otg_pixel_data_readback1; + uint32_t otg_request_control; + uint32_t otg_snapshot_control; + uint32_t otg_snapshot_frame; + uint32_t otg_snapshot_position; + uint32_t otg_snapshot_status; + uint32_t otg_spare_register; + uint32_t otg_static_screen_control; + uint32_t otg_status; + uint32_t otg_status_frame_count; + uint32_t otg_status_hv_count; + uint32_t otg_status_position; + uint32_t otg_status_vf_count; + uint32_t otg_stereo_control; + uint32_t otg_stereo_force_next_eye; + uint32_t otg_stereo_status; + uint32_t otg_trig_manual_control; + uint32_t otg_triga_cntl; + uint32_t otg_triga_manual_trig; + uint32_t otg_trigb_cntl; + uint32_t otg_trigb_manual_trig; + uint32_t otg_update_lock; + uint32_t otg_v_blank_start_end; + uint32_t otg_v_count_stop_control; + uint32_t otg_v_count_stop_control2; + uint32_t otg_v_sync_a; + uint32_t otg_v_sync_a_cntl; + uint32_t otg_v_total; + uint32_t otg_v_total_control; + uint32_t otg_v_total_int_status; + uint32_t otg_v_total_max; + uint32_t otg_v_total_mid; + uint32_t otg_v_total_min; + uint32_t otg_vert_sync_control; + uint32_t otg_vertical_interrupt0_control; + uint32_t otg_vertical_interrupt0_position; + uint32_t otg_vertical_interrupt1_control; + uint32_t otg_vertical_interrupt1_position; + uint32_t otg_vertical_interrupt2_control; + uint32_t otg_vertical_interrupt2_position; + uint32_t otg_vready_param; + uint32_t otg_vstartup_param; + uint32_t otg_vsync_nom_int_status; + uint32_t otg_vupdate_keepout; + uint32_t otg_vupdate_param; +}; + +/** + * struct timing_generator - Entry point to Output Timing Generator feature. + */ +struct timing_generator { + /** + * @funcs: Timing generator control functions + */ + const struct timing_generator_funcs *funcs; + struct dc_bios *bp; + struct dc_context *ctx; + int inst; +}; + +struct dc_crtc_timing; + +struct drr_params; + +/** + * struct timing_generator_funcs - Control timing generator on a given device. + */ +struct timing_generator_funcs { + bool (*validate_timing)(struct timing_generator *tg, + const struct dc_crtc_timing *timing); + void (*program_timing)(struct timing_generator *tg, + const struct dc_crtc_timing *timing, + int vready_offset, + int vstartup_start, + int vupdate_offset, + int vupdate_width, + int pstate_keepout, + const enum signal_type signal, + bool use_vbios + ); + void (*setup_vertical_interrupt0)( + struct timing_generator *optc, + uint32_t start_line, + uint32_t end_line); + void (*setup_vertical_interrupt1)( + struct timing_generator *optc, + uint32_t start_line); + void (*setup_vertical_interrupt2)( + struct timing_generator *optc, + uint32_t start_line); + + bool (*enable_crtc)(struct timing_generator *tg); + bool (*disable_crtc)(struct timing_generator *tg); + void (*phantom_crtc_post_enable)(struct timing_generator *tg); + void (*disable_phantom_crtc)(struct timing_generator *tg); + bool (*immediate_disable_crtc)(struct timing_generator *tg); + bool (*is_counter_moving)(struct timing_generator *tg); + void (*get_position)(struct timing_generator *tg, + struct crtc_position *position); + + uint32_t (*get_frame_count)(struct timing_generator *tg); + void (*get_scanoutpos)( + struct timing_generator *tg, + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); + bool (*get_otg_active_size)(struct timing_generator *optc, + uint32_t *otg_active_width, + uint32_t *otg_active_height); + bool (*is_matching_timing)(struct timing_generator *tg, + const struct dc_crtc_timing *otg_timing); + void (*set_early_control)(struct timing_generator *tg, + uint32_t early_cntl); + void (*wait_for_state)(struct timing_generator *tg, + enum crtc_state state); + void (*set_blank)(struct timing_generator *tg, + bool enable_blanking); + bool (*is_blanked)(struct timing_generator *tg); + void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color); + void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color); + void (*set_colors)(struct timing_generator *tg, + const struct tg_color *blank_color, + const struct tg_color *overscan_color); + + void (*disable_vga)(struct timing_generator *tg); + bool (*did_triggered_reset_occur)(struct timing_generator *tg); + void (*setup_global_swap_lock)(struct timing_generator *tg, + const struct dcp_gsl_params *gsl_params); + void (*unlock)(struct timing_generator *tg); + void (*lock)(struct timing_generator *tg); + void (*lock_doublebuffer_disable)(struct timing_generator *tg); + void (*lock_doublebuffer_enable)(struct timing_generator *tg); + void(*triplebuffer_unlock)(struct timing_generator *tg); + void(*triplebuffer_lock)(struct timing_generator *tg); + void (*enable_reset_trigger)(struct timing_generator *tg, + int source_tg_inst); + void (*enable_crtc_reset)(struct timing_generator *tg, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp); + void (*disable_reset_trigger)(struct timing_generator *tg); + void (*tear_down_global_swap_lock)(struct timing_generator *tg); + void (*enable_advanced_request)(struct timing_generator *tg, + bool enable, const struct dc_crtc_timing *timing); + void (*set_drr)(struct timing_generator *tg, const struct drr_params *params); + void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max); + void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate); + void (*set_static_screen_control)(struct timing_generator *tg, + uint32_t event_triggers, + uint32_t num_frames); + void (*set_test_pattern)( + struct timing_generator *tg, + enum controller_dp_test_pattern test_pattern, + enum dc_color_depth color_depth); + + bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width); + + void (*program_global_sync)(struct timing_generator *tg, + int vready_offset, + int vstartup_start, + int vupdate_offset, + int vupdate_width, + int pstate_keepout); + void (*enable_optc_clock)(struct timing_generator *tg, bool enable); + void (*program_stereo)(struct timing_generator *tg, + const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); + bool (*is_stereo_left_eye)(struct timing_generator *tg); + + void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable); + + void (*tg_init)(struct timing_generator *tg); + bool (*is_tg_enabled)(struct timing_generator *tg); + bool (*is_optc_underflow_occurred)(struct timing_generator *tg); + void (*clear_optc_underflow)(struct timing_generator *tg); + + void (*set_dwb_source)(struct timing_generator *optc, + uint32_t dwb_pipe_inst); + + void (*get_optc_source)(struct timing_generator *optc, + uint32_t *num_of_input_segments, + uint32_t *seg0_src_sel, + uint32_t *seg1_src_sel); + bool (*is_two_pixels_per_container)(const struct dc_crtc_timing *timing); + + /** + * Configure CRCs for the given timing generator. Return false if TG is + * not on. + */ + bool (*configure_crc)(struct timing_generator *tg, + const struct crc_params *params); + + /** + * @get_crc: Get CRCs for the given timing generator. Return false if + * CRCs are not enabled (via configure_crc). + */ + bool (*get_crc)(struct timing_generator *tg, uint8_t idx, + uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); + + void (*program_manual_trigger)(struct timing_generator *optc); + void (*setup_manual_trigger)(struct timing_generator *optc); + bool (*get_hw_timing)(struct timing_generator *optc, + struct dc_crtc_timing *hw_crtc_timing); + + void (*set_vtg_params)(struct timing_generator *optc, + const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); + + void (*set_dsc_config)(struct timing_generator *optc, + enum optc_dsc_mode dsc_mode, + uint32_t dsc_bytes_per_pixel, + uint32_t dsc_slice_width); + void (*get_dsc_status)(struct timing_generator *optc, + uint32_t *dsc_mode); + void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); + + /** + * @set_odm_combine: Set up the ODM block to read from the correct + * OPP(s) and turn on/off ODM memory. + */ + void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, + int segment_width, int last_segment_width); + void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments); + void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode); + void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); + void (*set_gsl_source_select)(struct timing_generator *optc, + int group_idx, + uint32_t gsl_ready_signal); + void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest); + void (*set_drr_trigger_window)(struct timing_generator *optc, + uint32_t window_start, uint32_t window_end); + void (*set_vtotal_change_limit)(struct timing_generator *optc, + uint32_t limit); + void (*align_vblanks)(struct timing_generator *master_optc, + struct timing_generator *slave_optc, + uint32_t master_pixel_clock_100Hz, + uint32_t slave_pixel_clock_100Hz, + uint8_t master_clock_divider, + uint8_t slave_clock_divider); + bool (*validate_vmin_vmax)(struct timing_generator *optc, + int vmin, int vmax); + bool (*validate_vtotal_change_limit)(struct timing_generator *optc, + uint32_t vtotal_change_limit); + + void (*init_odm)(struct timing_generator *tg); + void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg); + void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params); + void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg); + void (*wait_otg_disable)(struct timing_generator *optc); + bool (*get_optc_double_buffer_pending)(struct timing_generator *tg); + bool (*get_otg_double_buffer_pending)(struct timing_generator *tg); + bool (*get_pipe_update_pending)(struct timing_generator *tg); + void (*set_vupdate_keepout)(struct timing_generator *tg, bool enable); + bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked); + void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s); + void (*optc_read_reg_state)(struct timing_generator *tg, struct dcn_optc_reg_state *optc_reg_state); +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h new file mode 100644 index 000000000000..5a1d9b708a9d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -0,0 +1,293 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_TRANSFORM_H__ +#define __DAL_TRANSFORM_H__ + +#include "hw_shared.h" +#include "dc_hw_types.h" +#include "fixed31_32.h" +#include "sspl/dc_spl_types.h" + +#define CSC_TEMPERATURE_MATRIX_SIZE 12 + +struct bit_depth_reduction_params; + +struct transform { + const struct transform_funcs *funcs; + struct dc_context *ctx; + int inst; + struct dpp_caps *caps; + struct pwl_params regamma_params; +}; + +/* Colorimetry */ +enum colorimetry { + COLORIMETRY_NO_DATA = 0, + COLORIMETRY_ITU601 = 1, + COLORIMETRY_ITU709 = 2, + COLORIMETRY_EXTENDED = 3 +}; + +enum colorimetry_ext { + COLORIMETRYEX_XVYCC601 = 0, + COLORIMETRYEX_XVYCC709 = 1, + COLORIMETRYEX_SYCC601 = 2, + COLORIMETRYEX_ADOBEYCC601 = 3, + COLORIMETRYEX_ADOBERGB = 4, + COLORIMETRYEX_BT2020YCC = 5, + COLORIMETRYEX_BT2020RGBYCBCR = 6, + COLORIMETRYEX_RESERVED = 7 +}; + +enum active_format_info { + ACTIVE_FORMAT_NO_DATA = 0, + ACTIVE_FORMAT_VALID = 1 +}; + +/* Active format aspect ratio */ +enum active_format_aspect_ratio { + ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE = 8, + ACTIVE_FORMAT_ASPECT_RATIO_4_3 = 9, + ACTIVE_FORMAT_ASPECT_RATIO_16_9 = 0XA, + ACTIVE_FORMAT_ASPECT_RATIO_14_9 = 0XB +}; + +enum bar_info { + BAR_INFO_NOT_VALID = 0, + BAR_INFO_VERTICAL_VALID = 1, + BAR_INFO_HORIZONTAL_VALID = 2, + BAR_INFO_BOTH_VALID = 3 +}; + +enum picture_scaling { + PICTURE_SCALING_UNIFORM = 0, + PICTURE_SCALING_HORIZONTAL = 1, + PICTURE_SCALING_VERTICAL = 2, + PICTURE_SCALING_BOTH = 3 +}; + +/* RGB quantization range */ +enum rgb_quantization_range { + RGB_QUANTIZATION_DEFAULT_RANGE = 0, + RGB_QUANTIZATION_LIMITED_RANGE = 1, + RGB_QUANTIZATION_FULL_RANGE = 2, + RGB_QUANTIZATION_RESERVED = 3 +}; + +/* YYC quantization range */ +enum yyc_quantization_range { + YYC_QUANTIZATION_LIMITED_RANGE = 0, + YYC_QUANTIZATION_FULL_RANGE = 1, + YYC_QUANTIZATION_RESERVED2 = 2, + YYC_QUANTIZATION_RESERVED3 = 3 +}; + +enum graphics_gamut_adjust_type { + GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS = 0, + GRAPHICS_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ + GRAPHICS_GAMUT_ADJUST_TYPE_SW /* use adjustments */ +}; + +struct xfm_grph_csc_adjustment { + struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE]; + enum graphics_gamut_adjust_type gamut_adjust_type; +}; + +struct overscan_info { + int left; + int right; + int top; + int bottom; +}; + +struct scaling_ratios { + struct fixed31_32 horz; + struct fixed31_32 vert; + struct fixed31_32 horz_c; + struct fixed31_32 vert_c; +}; + +struct sharpness_adj { + int horz; + int vert; +}; + +struct line_buffer_params { + bool alpha_en; + bool pixel_expan_mode; + bool interleave_en; + int dynamic_pixel_depth; + enum lb_pixel_depth depth; +}; + +struct scl_inits { + struct fixed31_32 h; + struct fixed31_32 h_c; + struct fixed31_32 v; + struct fixed31_32 v_c; +}; + +struct scaler_data { + int h_active; + int v_active; + struct scaling_taps taps; + struct rect viewport; + struct rect viewport_c; + struct rect recout; + struct scaling_ratios ratios; + struct scl_inits inits; + struct sharpness_adj sharpness; + enum pixel_format format; + struct line_buffer_params lb_params; + // Below struct holds the scaler values to program hw registers + struct dscl_prog_data dscl_prog_data; +}; + +struct transform_funcs { + void (*transform_reset)(struct transform *xfm); + + void (*transform_set_scaler)(struct transform *xfm, + const struct scaler_data *scl_data); + + void (*transform_set_pixel_storage_depth)( + struct transform *xfm, + enum lb_pixel_depth depth, + const struct bit_depth_reduction_params *bit_depth_params); + + bool (*transform_get_optimal_number_of_taps)( + struct transform *xfm, + struct scaler_data *scl_data, + const struct scaling_taps *in_taps); + + void (*transform_set_gamut_remap)( + struct transform *xfm, + const struct xfm_grph_csc_adjustment *adjust); + + void (*opp_set_csc_default)( + struct transform *xfm, + const struct default_adjustment *default_adjust); + + void (*opp_set_csc_adjustment)( + struct transform *xfm, + const struct out_csc_color_matrix *tbl_entry); + + void (*opp_power_on_regamma_lut)( + struct transform *xfm, + bool power_on); + + void (*opp_program_regamma_lut)( + struct transform *xfm, + const struct pwl_result_data *rgb, + uint32_t num); + + void (*opp_configure_regamma_lut)( + struct transform *xfm, + bool is_ram_a); + + void (*opp_program_regamma_lutb_settings)( + struct transform *xfm, + const struct pwl_params *params); + + void (*opp_program_regamma_luta_settings)( + struct transform *xfm, + const struct pwl_params *params); + + void (*opp_program_regamma_pwl)( + struct transform *xfm, const struct pwl_params *params); + + void (*opp_set_regamma_mode)( + struct transform *xfm_base, + enum opp_regamma mode); + + void (*ipp_set_degamma)( + struct transform *xfm_base, + enum ipp_degamma_mode mode); + + void (*ipp_program_input_lut)( + struct transform *xfm_base, + const struct dc_gamma *gamma); + + void (*ipp_program_degamma_pwl)(struct transform *xfm_base, + const struct pwl_params *params); + + void (*ipp_setup)( + struct transform *xfm_base, + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space); + + void (*ipp_full_bypass)(struct transform *xfm_base); + + void (*set_cursor_attributes)( + struct transform *xfm_base, + const struct dc_cursor_attributes *attr); +}; + +const uint16_t *get_filter_2tap_16p(void); +const uint16_t *get_filter_2tap_64p(void); +const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio); +const uint16_t *get_filter_3tap_64p(struct fixed31_32 ratio); +const uint16_t *get_filter_4tap_16p(struct fixed31_32 ratio); +const uint16_t *get_filter_4tap_64p(struct fixed31_32 ratio); +const uint16_t *get_filter_5tap_64p(struct fixed31_32 ratio); +const uint16_t *get_filter_6tap_64p(struct fixed31_32 ratio); +const uint16_t *get_filter_7tap_64p(struct fixed31_32 ratio); +const uint16_t *get_filter_8tap_64p(struct fixed31_32 ratio); + + +/* Defines the pixel processing capability of the DSCL */ +enum dscl_data_processing_format { + DSCL_DATA_PRCESSING_FIXED_FORMAT, /* The DSCL processes pixel data in fixed format */ + DSCL_DATA_PRCESSING_FLOAT_FORMAT, /* The DSCL processes pixel data in float format */ +}; + +/* + * The DPP capabilities structure contains enumerations to specify the + * HW processing features and an associated function pointers to + * provide the function interface that can be overloaded for implementations + * based on different capabilities + */ +struct dpp_caps { + /* DSCL processing pixel data in fixed or float format */ + enum dscl_data_processing_format dscl_data_proc_format; + + /* max LB partitions */ + unsigned int max_lb_partitions; + + /* Calculates the number of partitions in the line buffer. + * The implementation of this function is overloaded for + * different versions of DSCL LB. + */ + void (*dscl_calc_lb_num_partitions)( + const struct scaler_data *scl_data, + enum lb_memory_config lb_config, + int *num_part_y, + int *num_part_c); +}; + + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h b/drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h new file mode 100644 index 000000000000..76de0e4284e0 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h @@ -0,0 +1,50 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef DAL_DC_INC_HW_VMID_H_ +#define DAL_DC_INC_HW_VMID_H_ + +#include "core_types.h" +#include "dchubbub.h" + +struct dcn_vmid_registers { + uint32_t CNTL; + uint32_t PAGE_TABLE_BASE_ADDR_HI32; + uint32_t PAGE_TABLE_BASE_ADDR_LO32; + uint32_t PAGE_TABLE_START_ADDR_HI32; + uint32_t PAGE_TABLE_START_ADDR_LO32; + uint32_t PAGE_TABLE_END_ADDR_HI32; + uint32_t PAGE_TABLE_END_ADDR_LO32; +}; + +struct dcn_vmid_page_table_config { + uint64_t page_table_start_addr; + uint64_t page_table_end_addr; + enum dcn_hubbub_page_table_depth depth; + enum dcn_hubbub_page_table_block_size block_size; + uint64_t page_table_base_addr; +}; + +#endif /* DAL_DC_INC_HW_VMID_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/vpg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/vpg.h new file mode 100644 index 000000000000..51da368f5c3e --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/vpg.h @@ -0,0 +1,53 @@ +/* + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + */ + +#ifndef __DC_VPG_H__ +#define __DC_VPG_H__ + +struct dc_context; +struct dc_info_packet; + +struct vpg; + +struct vpg_funcs { + void (*update_generic_info_packet)( + struct vpg *vpg, + uint32_t packet_index, + const struct dc_info_packet *info_packet, + bool immediate_update); + + void (*vpg_poweron)( + struct vpg *vpg); + + void (*vpg_powerdown)( + struct vpg *vpg); +}; + +struct vpg { + const struct vpg_funcs *funcs; + struct dc_context *ctx; + int inst; +}; + +#endif /* DC_INC_VPG_H_ */
\ No newline at end of file |