diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h index a734abaa91a5..5e15ac14b63c 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h @@ -26,6 +26,8 @@ #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 #define mmSQ_DEBUG_STS_GLOBAL2 0x10B0 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 +#define mmSQ_DEBUG 0x10B1 +#define mmSQ_DEBUG_BASE_IDX 0 // addressBlock: gc_sdma0_sdma0dec // base address: 0x4980 @@ -4853,10 +4855,18 @@ #define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 #define mmSPI_GDBG_WAVE_CNTL 0x1f71 #define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_CONFIG 0x1f72 +#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 #define mmSPI_GDBG_TRAP_MASK 0x1f73 #define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0 #define mmSPI_GDBG_WAVE_CNTL2 0x1f74 #define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0 +#define mmSPI_GDBG_WAVE_CNTL3 0x1f75 +#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_DATA0 0x1f78 +#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_DATA1 0x1f79 +#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0 #define mmSPI_COMPUTE_QUEUE_RESET 0x1f7b #define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 #define mmSPI_RESOURCE_RESERVE_CU_0 0x1f7c |