diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/smu')
16 files changed, 39788 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h new file mode 100644 index 000000000000..f67560b82fe9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h @@ -0,0 +1,741 @@ +/* + * SMU_7_0_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_0_0_D_H +#define SMU_7_0_0_D_H + +#define mmGCK_SMC_IND_INDEX 0x80 +#define mmGCK0_GCK_SMC_IND_INDEX 0x80 +#define mmGCK1_GCK_SMC_IND_INDEX 0x82 +#define mmGCK2_GCK_SMC_IND_INDEX 0x84 +#define mmGCK3_GCK_SMC_IND_INDEX 0x86 +#define mmGCK_SMC_IND_DATA 0x81 +#define mmGCK0_GCK_SMC_IND_DATA 0x81 +#define mmGCK1_GCK_SMC_IND_DATA 0x83 +#define mmGCK2_GCK_SMC_IND_DATA 0x85 +#define mmGCK3_GCK_SMC_IND_DATA 0x87 +#define ixCG_DCLK_CNTL 0xc050009c +#define ixCG_DCLK_STATUS 0xc05000a0 +#define ixCG_VCLK_CNTL 0xc05000a4 +#define ixCG_VCLK_STATUS 0xc05000a8 +#define ixCG_ECLK_CNTL 0xc05000ac +#define ixCG_ECLK_STATUS 0xc05000b0 +#define ixCG_ACLK_CNTL 0xc05000dc +#define ixGCK_DFS_BYPASS_CNTL 0xc0500118 +#define ixCG_SPLL_FUNC_CNTL 0xc0500140 +#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 +#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 +#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c +#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 +#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 +#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 +#define ixSPLL_CNTL_MODE 0xc0500160 +#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 +#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +#define ixMPLL_BYPASSCLK_SEL 0xc050019c +#define ixCG_CLKPIN_CNTL 0xc05001a0 +#define ixCG_CLKPIN_CNTL_2 0xc05001a4 +#define ixTHM_CLK_CNTL 0xc05001a8 +#define ixMISC_CLK_CTRL 0xc05001ac +#define ixGCK_PLL_TEST_CNTL 0xc05001c0 +#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 +#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 +#define mmSMC_IND_INDEX 0x80 +#define mmSMC0_SMC_IND_INDEX 0x80 +#define mmSMC1_SMC_IND_INDEX 0x82 +#define mmSMC2_SMC_IND_INDEX 0x84 +#define mmSMC3_SMC_IND_INDEX 0x86 +#define mmSMC_IND_DATA 0x81 +#define mmSMC0_SMC_IND_DATA 0x81 +#define mmSMC1_SMC_IND_DATA 0x83 +#define mmSMC2_SMC_IND_DATA 0x85 +#define mmSMC3_SMC_IND_DATA 0x87 +#define mmSMC_IND_INDEX_0 0x80 +#define mmSMC_IND_DATA_0 0x81 +#define mmSMC_IND_INDEX_1 0x82 +#define mmSMC_IND_DATA_1 0x83 +#define mmSMC_IND_INDEX_2 0x84 +#define mmSMC_IND_DATA_2 0x85 +#define mmSMC_IND_INDEX_3 0x86 +#define mmSMC_IND_DATA_3 0x87 +#define mmSMC_IND_INDEX_4 0x88 +#define mmSMC_IND_DATA_4 0x89 +#define mmSMC_IND_INDEX_5 0x8a +#define mmSMC_IND_DATA_5 0x8b +#define mmSMC_IND_INDEX_6 0x8c +#define mmSMC_IND_DATA_6 0x8d +#define mmSMC_IND_INDEX_7 0x8e +#define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_ACCESS_CNTL 0x90 +#define mmSMC_MESSAGE_0 0x94 +#define mmSMC_RESP_0 0x95 +#define mmSMC_MESSAGE_1 0x96 +#define mmSMC_RESP_1 0x97 +#define mmSMC_MESSAGE_2 0x98 +#define mmSMC_RESP_2 0x99 +#define mmSMC_MESSAGE_3 0x9a +#define mmSMC_RESP_3 0x9b +#define mmSMC_MESSAGE_4 0x9c +#define mmSMC_RESP_4 0x9d +#define mmSMC_MESSAGE_5 0x9e +#define mmSMC_RESP_5 0x9f +#define mmSMC_MESSAGE_6 0xa0 +#define mmSMC_RESP_6 0xa1 +#define mmSMC_MESSAGE_7 0xa2 +#define mmSMC_RESP_7 0xa3 +#define mmSMC_MSG_ARG_0 0xa4 +#define mmSMC_MSG_ARG_1 0xa5 +#define mmSMC_MSG_ARG_2 0xa6 +#define mmSMC_MSG_ARG_3 0xa7 +#define mmSMC_MSG_ARG_4 0xa8 +#define mmSMC_MSG_ARG_5 0xa9 +#define mmSMC_MSG_ARG_6 0xaa +#define mmSMC_MSG_ARG_7 0xab +#define mmSMC_MESSAGE_8 0xb5 +#define mmSMC_RESP_8 0xb6 +#define mmSMC_MESSAGE_9 0xb7 +#define mmSMC_RESP_9 0xb8 +#define mmSMC_MESSAGE_10 0xb9 +#define mmSMC_RESP_10 0xba +#define mmSMC_MESSAGE_11 0xbb +#define mmSMC_RESP_11 0xbc +#define mmSMC_MSG_ARG_8 0xbd +#define mmSMC_MSG_ARG_9 0xbe +#define mmSMC_MSG_ARG_10 0xbf +#define mmSMC_MSG_ARG_11 0x91 +#define ixSMC_SYSCON_RESET_CNTL 0x80000000 +#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 +#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 +#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c +#define ixSMC_SYSCON_MISC_CNTL 0x80000010 +#define ixSMC_SYSCON_MSG_ARG_0 0x80000068 +#define ixSMC_PC_C 0x80000370 +#define ixSMC_SCRATCH9 0x80000424 +#define mmCG_FPS_CNT 0x1a4 +#define mmSMU_SMC_IND_INDEX 0x80 +#define mmSMU0_SMU_SMC_IND_INDEX 0x80 +#define mmSMU1_SMU_SMC_IND_INDEX 0x82 +#define mmSMU2_SMU_SMC_IND_INDEX 0x84 +#define mmSMU3_SMU_SMC_IND_INDEX 0x86 +#define mmSMU_SMC_IND_DATA 0x81 +#define mmSMU0_SMU_SMC_IND_DATA 0x81 +#define mmSMU1_SMU_SMC_IND_DATA 0x83 +#define mmSMU2_SMU_SMC_IND_DATA 0x85 +#define mmSMU3_SMU_SMC_IND_DATA 0x87 +#define ixRCU_UC_EVENTS 0xc0000004 +#define ixRCU_MISC_CTRL 0xc0000010 +#define ixCC_RCU_FUSES 0xc00c0000 +#define ixCC_SMU_MISC_FUSES 0xc00c0004 +#define ixCC_SCLK_VID_FUSES 0xc00c0008 +#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c +#define ixCC_GIO_IOC_FUSES 0xc00c0010 +#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c +#define ixCC_TST_ID_STRAPS 0xc00c0020 +#define ixCC_FCTRL_FUSES 0xc00c0024 +#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 +#define ixSMU_STATUS 0xe0003088 +#define ixSMU_FIRMWARE 0xe00030a4 +#define ixSMU_INPUT_DATA 0xe00030b8 +#define ixSMU_EFUSE_0 0xc0100000 +#define ixDPM_TABLE_1 0x3f000 +#define ixDPM_TABLE_2 0x3f004 +#define ixDPM_TABLE_3 0x3f008 +#define ixDPM_TABLE_4 0x3f00c +#define ixDPM_TABLE_5 0x3f010 +#define ixDPM_TABLE_6 0x3f014 +#define ixDPM_TABLE_7 0x3f018 +#define ixDPM_TABLE_8 0x3f01c +#define ixDPM_TABLE_9 0x3f020 +#define ixDPM_TABLE_10 0x3f024 +#define ixDPM_TABLE_11 0x3f028 +#define ixDPM_TABLE_12 0x3f02c +#define ixDPM_TABLE_13 0x3f030 +#define ixDPM_TABLE_14 0x3f034 +#define ixDPM_TABLE_15 0x3f038 +#define ixDPM_TABLE_16 0x3f03c +#define ixDPM_TABLE_17 0x3f040 +#define ixDPM_TABLE_18 0x3f044 +#define ixDPM_TABLE_19 0x3f048 +#define ixDPM_TABLE_20 0x3f04c +#define ixDPM_TABLE_21 0x3f050 +#define ixDPM_TABLE_22 0x3f054 +#define ixDPM_TABLE_23 0x3f058 +#define ixDPM_TABLE_24 0x3f05c +#define ixDPM_TABLE_25 0x3f060 +#define ixDPM_TABLE_26 0x3f064 +#define ixDPM_TABLE_27 0x3f068 +#define ixDPM_TABLE_28 0x3f06c +#define ixDPM_TABLE_29 0x3f070 +#define ixDPM_TABLE_30 0x3f074 +#define ixDPM_TABLE_31 0x3f078 +#define ixDPM_TABLE_32 0x3f07c +#define ixDPM_TABLE_33 0x3f080 +#define ixDPM_TABLE_34 0x3f084 +#define ixDPM_TABLE_35 0x3f088 +#define ixDPM_TABLE_36 0x3f08c +#define ixDPM_TABLE_37 0x3f090 +#define ixDPM_TABLE_38 0x3f094 +#define ixDPM_TABLE_39 0x3f098 +#define ixDPM_TABLE_40 0x3f09c +#define ixDPM_TABLE_41 0x3f0a0 +#define ixDPM_TABLE_42 0x3f0a4 +#define ixDPM_TABLE_43 0x3f0a8 +#define ixDPM_TABLE_44 0x3f0ac +#define ixDPM_TABLE_45 0x3f0b0 +#define ixDPM_TABLE_46 0x3f0b4 +#define ixDPM_TABLE_47 0x3f0b8 +#define ixDPM_TABLE_48 0x3f0bc +#define ixDPM_TABLE_49 0x3f0c0 +#define ixDPM_TABLE_50 0x3f0c4 +#define ixDPM_TABLE_51 0x3f0c8 +#define ixDPM_TABLE_52 0x3f0cc +#define ixDPM_TABLE_53 0x3f0d0 +#define ixDPM_TABLE_54 0x3f0d4 +#define ixDPM_TABLE_55 0x3f0d8 +#define ixDPM_TABLE_56 0x3f0dc +#define ixDPM_TABLE_57 0x3f0e0 +#define ixDPM_TABLE_58 0x3f0e4 +#define ixDPM_TABLE_59 0x3f0e8 +#define ixDPM_TABLE_60 0x3f0ec +#define ixDPM_TABLE_61 0x3f0f0 +#define ixDPM_TABLE_62 0x3f0f4 +#define ixDPM_TABLE_63 0x3f0f8 +#define ixDPM_TABLE_64 0x3f0fc +#define ixDPM_TABLE_65 0x3f100 +#define ixDPM_TABLE_66 0x3f104 +#define ixDPM_TABLE_67 0x3f108 +#define ixDPM_TABLE_68 0x3f10c +#define ixDPM_TABLE_69 0x3f110 +#define ixDPM_TABLE_70 0x3f114 +#define ixDPM_TABLE_71 0x3f118 +#define ixDPM_TABLE_72 0x3f11c +#define ixDPM_TABLE_73 0x3f120 +#define ixDPM_TABLE_74 0x3f124 +#define ixDPM_TABLE_75 0x3f128 +#define ixDPM_TABLE_76 0x3f12c +#define ixDPM_TABLE_77 0x3f130 +#define ixDPM_TABLE_78 0x3f134 +#define ixDPM_TABLE_79 0x3f138 +#define ixDPM_TABLE_80 0x3f13c +#define ixDPM_TABLE_81 0x3f140 +#define ixDPM_TABLE_82 0x3f144 +#define ixDPM_TABLE_83 0x3f148 +#define ixDPM_TABLE_84 0x3f14c +#define ixDPM_TABLE_85 0x3f150 +#define ixDPM_TABLE_86 0x3f154 +#define ixDPM_TABLE_87 0x3f158 +#define ixDPM_TABLE_88 0x3f15c +#define ixDPM_TABLE_89 0x3f160 +#define ixDPM_TABLE_90 0x3f164 +#define ixDPM_TABLE_91 0x3f168 +#define ixDPM_TABLE_92 0x3f16c +#define ixDPM_TABLE_93 0x3f170 +#define ixDPM_TABLE_94 0x3f174 +#define ixDPM_TABLE_95 0x3f178 +#define ixDPM_TABLE_96 0x3f17c +#define ixDPM_TABLE_97 0x3f180 +#define ixDPM_TABLE_98 0x3f184 +#define ixDPM_TABLE_99 0x3f188 +#define ixDPM_TABLE_100 0x3f18c +#define ixDPM_TABLE_101 0x3f190 +#define ixDPM_TABLE_102 0x3f194 +#define ixDPM_TABLE_103 0x3f198 +#define ixDPM_TABLE_104 0x3f19c +#define ixDPM_TABLE_105 0x3f1a0 +#define ixDPM_TABLE_106 0x3f1a4 +#define ixDPM_TABLE_107 0x3f1a8 +#define ixDPM_TABLE_108 0x3f1ac +#define ixDPM_TABLE_109 0x3f1b0 +#define ixDPM_TABLE_110 0x3f1b4 +#define ixDPM_TABLE_111 0x3f1b8 +#define ixDPM_TABLE_112 0x3f1bc +#define ixDPM_TABLE_113 0x3f1c0 +#define ixDPM_TABLE_114 0x3f1c4 +#define ixDPM_TABLE_115 0x3f1c8 +#define ixDPM_TABLE_116 0x3f1cc +#define ixDPM_TABLE_117 0x3f1d0 +#define ixDPM_TABLE_118 0x3f1d4 +#define ixDPM_TABLE_119 0x3f1d8 +#define ixDPM_TABLE_120 0x3f1dc +#define ixDPM_TABLE_121 0x3f1e0 +#define ixDPM_TABLE_122 0x3f1e4 +#define ixDPM_TABLE_123 0x3f1e8 +#define ixDPM_TABLE_124 0x3f1ec +#define ixDPM_TABLE_125 0x3f1f0 +#define ixDPM_TABLE_126 0x3f1f4 +#define ixDPM_TABLE_127 0x3f1f8 +#define ixDPM_TABLE_128 0x3f1fc +#define ixDPM_TABLE_129 0x3f200 +#define ixDPM_TABLE_130 0x3f204 +#define ixDPM_TABLE_131 0x3f208 +#define ixDPM_TABLE_132 0x3f20c +#define ixDPM_TABLE_133 0x3f210 +#define ixDPM_TABLE_134 0x3f214 +#define ixDPM_TABLE_135 0x3f218 +#define ixDPM_TABLE_136 0x3f21c +#define ixDPM_TABLE_137 0x3f220 +#define ixDPM_TABLE_138 0x3f224 +#define ixDPM_TABLE_139 0x3f228 +#define ixDPM_TABLE_140 0x3f22c +#define ixDPM_TABLE_141 0x3f230 +#define ixDPM_TABLE_142 0x3f234 +#define ixDPM_TABLE_143 0x3f238 +#define ixDPM_TABLE_144 0x3f23c +#define ixDPM_TABLE_145 0x3f240 +#define ixDPM_TABLE_146 0x3f244 +#define ixDPM_TABLE_147 0x3f248 +#define ixDPM_TABLE_148 0x3f24c +#define ixDPM_TABLE_149 0x3f250 +#define ixDPM_TABLE_150 0x3f254 +#define ixDPM_TABLE_151 0x3f258 +#define ixDPM_TABLE_152 0x3f25c +#define ixDPM_TABLE_153 0x3f260 +#define ixDPM_TABLE_154 0x3f264 +#define ixDPM_TABLE_155 0x3f268 +#define ixDPM_TABLE_156 0x3f26c +#define ixDPM_TABLE_157 0x3f270 +#define ixDPM_TABLE_158 0x3f274 +#define ixDPM_TABLE_159 0x3f278 +#define ixDPM_TABLE_160 0x3f27c +#define ixDPM_TABLE_161 0x3f280 +#define ixDPM_TABLE_162 0x3f284 +#define ixDPM_TABLE_163 0x3f288 +#define ixDPM_TABLE_164 0x3f28c +#define ixDPM_TABLE_165 0x3f290 +#define ixDPM_TABLE_166 0x3f294 +#define ixDPM_TABLE_167 0x3f298 +#define ixDPM_TABLE_168 0x3f29c +#define ixDPM_TABLE_169 0x3f2a0 +#define ixDPM_TABLE_170 0x3f2a4 +#define ixDPM_TABLE_171 0x3f2a8 +#define ixDPM_TABLE_172 0x3f2ac +#define ixDPM_TABLE_173 0x3f2b0 +#define ixDPM_TABLE_174 0x3f2b4 +#define ixDPM_TABLE_175 0x3f2b8 +#define ixDPM_TABLE_176 0x3f2bc +#define ixDPM_TABLE_177 0x3f2c0 +#define ixDPM_TABLE_178 0x3f2c4 +#define ixDPM_TABLE_179 0x3f2c8 +#define ixDPM_TABLE_180 0x3f2cc +#define ixDPM_TABLE_181 0x3f2d0 +#define ixDPM_TABLE_182 0x3f2d4 +#define ixDPM_TABLE_183 0x3f2d8 +#define ixDPM_TABLE_184 0x3f2dc +#define ixDPM_TABLE_185 0x3f2e0 +#define ixDPM_TABLE_186 0x3f2e4 +#define ixDPM_TABLE_187 0x3f2e8 +#define ixDPM_TABLE_188 0x3f2ec +#define ixDPM_TABLE_189 0x3f2f0 +#define ixDPM_TABLE_190 0x3f2f4 +#define ixDPM_TABLE_191 0x3f2f8 +#define ixSOFT_REGISTERS_TABLE_1 0x3f900 +#define ixSOFT_REGISTERS_TABLE_2 0x3f904 +#define ixSOFT_REGISTERS_TABLE_3 0x3f908 +#define ixSOFT_REGISTERS_TABLE_4 0x3f90c +#define ixSOFT_REGISTERS_TABLE_5 0x3f910 +#define ixSOFT_REGISTERS_TABLE_6 0x3f914 +#define ixSOFT_REGISTERS_TABLE_7 0x3f918 +#define ixSOFT_REGISTERS_TABLE_8 0x3f91c +#define ixSOFT_REGISTERS_TABLE_9 0x3f920 +#define ixSOFT_REGISTERS_TABLE_10 0x3f924 +#define ixSOFT_REGISTERS_TABLE_11 0x3f928 +#define ixSOFT_REGISTERS_TABLE_12 0x3f92c +#define ixSOFT_REGISTERS_TABLE_13 0x3f930 +#define ixSOFT_REGISTERS_TABLE_14 0x3f934 +#define ixSOFT_REGISTERS_TABLE_15 0x3f938 +#define ixSOFT_REGISTERS_TABLE_16 0x3f93c +#define ixSOFT_REGISTERS_TABLE_17 0x3f940 +#define ixSOFT_REGISTERS_TABLE_18 0x3f944 +#define ixSOFT_REGISTERS_TABLE_19 0x3f948 +#define ixSOFT_REGISTERS_TABLE_20 0x3f94c +#define ixSOFT_REGISTERS_TABLE_21 0x3f950 +#define ixSMU_LCLK_DPM_STATE_0_CNTL_0 0x3fd00 +#define ixSMU_LCLK_DPM_STATE_1_CNTL_0 0x3fd14 +#define ixSMU_LCLK_DPM_STATE_2_CNTL_0 0x3fd28 +#define ixSMU_LCLK_DPM_STATE_3_CNTL_0 0x3fd3c +#define ixSMU_LCLK_DPM_STATE_4_CNTL_0 0x3fd50 +#define ixSMU_LCLK_DPM_STATE_5_CNTL_0 0x3fd64 +#define ixSMU_LCLK_DPM_STATE_6_CNTL_0 0x3fd78 +#define ixSMU_LCLK_DPM_STATE_7_CNTL_0 0x3fd8c +#define ixSMU_LCLK_DPM_STATE_0_CNTL_1 0x3fd04 +#define ixSMU_LCLK_DPM_STATE_1_CNTL_1 0x3fd18 +#define ixSMU_LCLK_DPM_STATE_2_CNTL_1 0x3fd2c +#define ixSMU_LCLK_DPM_STATE_3_CNTL_1 0x3fd40 +#define ixSMU_LCLK_DPM_STATE_4_CNTL_1 0x3fd54 +#define ixSMU_LCLK_DPM_STATE_5_CNTL_1 0x3fd68 +#define ixSMU_LCLK_DPM_STATE_6_CNTL_1 0x3fd7c +#define ixSMU_LCLK_DPM_STATE_7_CNTL_1 0x3fd90 +#define ixSMU_LCLK_DPM_STATE_0_CNTL_2 0x3fd08 +#define ixSMU_LCLK_DPM_STATE_1_CNTL_2 0x3fd1c +#define ixSMU_LCLK_DPM_STATE_2_CNTL_2 0x3fd30 +#define ixSMU_LCLK_DPM_STATE_3_CNTL_2 0x3fd44 +#define ixSMU_LCLK_DPM_STATE_4_CNTL_2 0x3fd58 +#define ixSMU_LCLK_DPM_STATE_5_CNTL_2 0x3fd6c +#define ixSMU_LCLK_DPM_STATE_6_CNTL_2 0x3fd80 +#define ixSMU_LCLK_DPM_STATE_7_CNTL_2 0x3fd94 +#define ixSMU_LCLK_DPM_STATE_0_CNTL_3 0x3fd0c +#define ixSMU_LCLK_DPM_STATE_1_CNTL_3 0x3fd20 +#define ixSMU_LCLK_DPM_STATE_2_CNTL_3 0x3fd34 +#define ixSMU_LCLK_DPM_STATE_3_CNTL_3 0x3fd48 +#define ixSMU_LCLK_DPM_STATE_4_CNTL_3 0x3fd5c +#define ixSMU_LCLK_DPM_STATE_5_CNTL_3 0x3fd70 +#define ixSMU_LCLK_DPM_STATE_6_CNTL_3 0x3fd84 +#define ixSMU_LCLK_DPM_STATE_7_CNTL_3 0x3fd98 +#define ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD 0x3fd10 +#define ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD 0x3fd24 +#define ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD 0x3fd38 +#define ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD 0x3fd4c +#define ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD 0x3fd60 +#define ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD 0x3fd74 +#define ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD 0x3fd88 +#define ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD 0x3fd9c +#define ixGIO_PID_CONTROLLER_CNTL_0 0x3fda0 +#define ixGIO_PID_CONTROLLER_CNTL_1 0x3fda4 +#define ixGIO_PID_CONTROLLER_CNTL_2 0x3fda8 +#define ixGIO_PID_CONTROLLER_CNTL_3 0x3fdac +#define ixGIO_PID_CONTROLLER_CNTL_4 0x3fdb0 +#define ixGIO_PID_CONTROLLER_CNTL_5 0x3fdb4 +#define ixGIO_PID_CONTROLLER_CNTL_6 0x3fdb8 +#define ixGIO_PID_CONTROLLER_CNTL_7 0x3fdbc +#define ixGIO_PID_CONTROLLER_CNTL_8 0x3fdc0 +#define ixSMU_LCLK_DPM_LEVEL_COUNT 0x3fdc4 +#define ixSMU_LCLK_DPM_CNTL 0x3fdc8 +#define ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE 0x3fdcc +#define ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL 0x3fdd0 +#define ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS 0x3fdd4 +#define ixPM_FUSES_1 0x3fa80 +#define ixPM_FUSES_2 0x3fa84 +#define ixPM_FUSES_3 0x3fa88 +#define ixPM_FUSES_4 0x3fa8c +#define ixPM_FUSES_5 0x3fa90 +#define ixPM_FUSES_6 0x3fa94 +#define ixPM_FUSES_7 0x3fa98 +#define ixPM_FUSES_8 0x3fa9c +#define ixPM_FUSES_9 0x3faa0 +#define ixPM_FUSES_10 0x3faa4 +#define ixPM_FUSES_11 0x3faa8 +#define ixPM_FUSES_12 0x3faac +#define ixPM_FUSES_13 0x3fab0 +#define ixPM_FUSES_14 0x3fab4 +#define ixPM_FUSES_15 0x3fab8 +#define ixPM_FUSES_16 0x3fabc +#define ixPM_FUSES_17 0x3fac0 +#define ixPM_FUSES_18 0x3fac4 +#define ixPM_FUSES_19 0x3fac8 +#define ixPM_FUSES_20 0x3facc +#define ixPM_FUSES_21 0x3fad0 +#define ixPM_FUSES_22 0x3fad4 +#define ixPM_FUSES_23 0x3fad8 +#define ixPM_FUSES_24 0x3fadc +#define ixPM_FUSES_25 0x3fae0 +#define ixPM_FUSES_26 0x3fae4 +#define ixPM_FUSES_27 0x3fae8 +#define ixPM_FUSES_28 0x3faec +#define ixPM_FUSES_29 0x3faf0 +#define ixPM_FUSES_30 0x3faf4 +#define ixPM_FUSES_31 0x3faf8 +#define ixPM_FUSES_32 0x3fafc +#define ixPM_FUSES_33 0x3fb00 +#define ixPM_FUSES_34 0x3fb04 +#define ixPM_FUSES_35 0x3fb08 +#define ixPM_FUSES_36 0x3fb0c +#define ixPM_FUSES_37 0x3fb10 +#define ixPM_FUSES_38 0x3fb14 +#define ixPM_FUSES_39 0x3fb18 +#define ixPM_FUSES_40 0x3fb1c +#define ixPM_FUSES_41 0x3fb20 +#define ixPM_FUSES_42 0x3fb24 +#define ixPM_FUSES_43 0x3fb28 +#define ixPM_FUSES_44 0x3fb2c +#define ixPM_FUSES_45 0x3fb30 +#define ixPM_FUSES_46 0x3fb34 +#define ixPM_FUSES_47 0x3fb38 +#define ixPM_FUSES_48 0x3fb3c +#define ixPM_FUSES_49 0x3fb40 +#define ixPM_FUSES_50 0x3fb44 +#define ixPM_FUSES_51 0x3fb48 +#define ixPM_FUSES_52 0x3fb4c +#define ixPM_FUSES_53 0x3fb50 +#define ixPM_FUSES_54 0x3fb54 +#define ixPM_FUSES_55 0x3fb58 +#define ixPM_FUSES_56 0x3fb5c +#define ixPM_FUSES_57 0x3fb60 +#define ixPM_FUSES_58 0x3fb64 +#define ixPM_FUSES_59 0x3fb68 +#define ixPM_FUSES_60 0x3fb6c +#define ixPM_FUSES_61 0x3fb70 +#define ixPM_FUSES_62 0x3fb74 +#define ixPM_FUSES_63 0x3fb78 +#define ixPM_FUSES_64 0x3fb7c +#define ixPM_FUSES_65 0x3fb80 +#define ixFIRMWARE_FLAGS 0x3f800 +#define ixTEMPERATURE_READ_ADDR 0x3f808 +#define ixCURRENT_GNB_TEMP 0x3f810 +#define ixCURRENT_GLOBAL_TEMP 0x3f814 +#define ixFEATURE_STATUS 0x3f818 +#define ixPCIE_PLL_RECONF 0x3f81c +#define ixPM_INTERVAL_CNTL_0 0x3f820 +#define ixPM_INTERVAL_CNTL_1 0x3f824 +#define ixPM_INTERVAL_CNTL_2 0x3f82c +#define ixVPC_INTERVAL_CNTL 0x3f830 +#define ixDISP_PHY_TDP_LIMIT 0x3f834 +#define ixFCH_PWR_CREDIT 0x3f838 +#define ixPKGPWR_MV_AVG 0x3f83c +#define ixPACKAGE_POWER 0x3f840 +#define ixPKG_PWR_CNTL 0x3f844 +#define ixPKG_PWR_STATUS 0x3f848 +#define ixDISP_PHY_CONFIG 0x3f84c +#define ixGPU_TDP_LIMIT 0x3f850 +#define ixEXT_API_IN_DATA_0_0 0x3f858 +#define ixEXT_API_IN_DATA_0_1 0x3f85c +#define ixEXT_API_IN_DATA_0_2 0x3f860 +#define ixEXT_API_IN_DATA_0_3 0x3f864 +#define ixEXT_API_OUT_DATA_0_0 0x3f868 +#define ixEXT_API_OUT_DATA_0_1 0x3f86c +#define ixEXT_API_OUT_DATA_0_2 0x3f870 +#define ixEXT_API_OUT_DATA_0_3 0x3f874 +#define ixBAPM_PARAMETERS 0x3f984 +#define ixBAPM_PARAMETERS_2 0x3f988 +#define ixBAPM_PARAMETERS_3 0x3f98c +#define ixBAPM_PARAMETERS_4 0x3f990 +#define ixSMU_SVI_TELEMETRY 0x3f994 +#define ixBAPM_STATUS 0x3f998 +#define ixSMU_HTC_STATUS 0x3f99c +#define ixSMU_VPC_STATUS 0x3f9a0 +#define ixENTITY_TEMPERATURES_1 0x3f9a4 +#define ixENTITY_TEMPERATURES_2 0x3f9a8 +#define ixENTITY_TEMPERATURES_3 0x3f9ac +#define ixCU_POWER 0x3f9b0 +#define ixGPU_POWER 0x3f9b4 +#define ixNTE_POWER 0x3f9b8 +#define ixTDC_STATUS 0x3f9d0 +#define ixTDC_MV_AVERAGE 0x3f9d4 +#define ixPM_CONFIG 0x3f9d8 +#define ixTE0_TEMPERATURE_READ_ADDR 0x3f9dc +#define ixTE1_TEMPERATURE_READ_ADDR 0x3f9e0 +#define ixTE2_TEMPERATURE_READ_ADDR 0x3f9e4 +#define ixNB_DPM_CONFIG_1 0x3f9e8 +#define ixNB_DPM_CONFIG_2 0x3f9ec +#define ixNB_DPM_CONFIG_3 0x3f9f0 +#define ixSMU_IDD_OVERRIDE 0x3f9fc +#define ixAVS_CONFIG 0x3fa00 +#define ixTDC_VRM_LIMIT 0x3fa04 +#define ixCU0_PSM_CONFIG 0x3fa08 +#define ixCU1_PSM_CONFIG 0x3fa0c +#define ixSPMI_CONFIG 0x3fa10 +#define ixSPMI_SMC_CHAIN_ADDR 0x3fa14 +#define ixSPMI_STATUS 0x3fa30 +#define ixAVSNB_CONFIG 0x3fa34 +#define ixHTC_CONFIG 0x3fa38 +#define ixAVS_CU0_TEMPERATURE_SENSOR 0x3fa3c +#define ixAVS_CU1_TEMPERATURE_SENSOR 0x3fa40 +#define ixAVS_GNB_TEMPERATURE_SENSOR 0x3fa44 +#define ixAVS_UNB_TEMPERATURE_SENSOR 0x3fa48 +#define ixSMU_MONITOR_PORT80_MMIO_ADDR 0x3fa4c +#define ixSMU_MONITOR_PORT80_MEMBASE_HI 0x3fa50 +#define ixSMU_MONITOR_PORT80_MEMBASE_LO 0x3fa54 +#define ixSMU_MONITOR_PORT80_MEMSETUP 0x3fa58 +#define ixSMU_MONITOR_PORT80_CTRL 0x3fa5c +#define ixSMU_TCEN_ALIVE 0x3fa60 +#define ixPDM_STATUS 0x3fa64 +#define ixPDM_CNTL_1 0x3fa68 +#define ixPDM_CNTL_2 0x3fa6c +#define ixPDM_CNTL_3 0x3fa70 +#define ixSMU_PM_STATUS_0 0x3fe00 +#define ixSMU_PM_STATUS_1 0x3fe04 +#define ixSMU_PM_STATUS_2 0x3fe08 +#define ixSMU_PM_STATUS_3 0x3fe0c +#define ixSMU_PM_STATUS_4 0x3fe10 +#define ixSMU_PM_STATUS_5 0x3fe14 +#define ixSMU_PM_STATUS_6 0x3fe18 +#define ixSMU_PM_STATUS_7 0x3fe1c +#define ixSMU_PM_STATUS_8 0x3fe20 +#define ixSMU_PM_STATUS_9 0x3fe24 +#define ixSMU_PM_STATUS_10 0x3fe28 +#define ixSMU_PM_STATUS_11 0x3fe2c +#define ixSMU_PM_STATUS_12 0x3fe30 +#define ixSMU_PM_STATUS_13 0x3fe34 +#define ixSMU_PM_STATUS_14 0x3fe38 +#define ixSMU_PM_STATUS_15 0x3fe3c +#define ixSMU_PM_STATUS_16 0x3fe40 +#define ixSMU_PM_STATUS_17 0x3fe44 +#define ixSMU_PM_STATUS_18 0x3fe48 +#define ixSMU_PM_STATUS_19 0x3fe4c +#define ixSMU_PM_STATUS_20 0x3fe50 +#define ixSMU_PM_STATUS_21 0x3fe54 +#define ixSMU_PM_STATUS_22 0x3fe58 +#define ixSMU_PM_STATUS_23 0x3fe5c +#define ixSMU_PM_STATUS_24 0x3fe60 +#define ixSMU_PM_STATUS_25 0x3fe64 +#define ixSMU_PM_STATUS_26 0x3fe68 +#define ixSMU_PM_STATUS_27 0x3fe6c +#define ixSMU_PM_STATUS_28 0x3fe70 +#define ixSMU_PM_STATUS_29 0x3fe74 +#define ixSMU_PM_STATUS_30 0x3fe78 +#define ixSMU_PM_STATUS_31 0x3fe7c +#define ixSMU_PM_STATUS_32 0x3fe80 +#define ixSMU_PM_STATUS_33 0x3fe84 +#define ixSMU_PM_STATUS_34 0x3fe88 +#define ixSMU_PM_STATUS_35 0x3fe8c +#define ixSMU_PM_STATUS_36 0x3fe90 +#define ixSMU_PM_STATUS_37 0x3fe94 +#define ixSMU_PM_STATUS_38 0x3fe98 +#define ixSMU_PM_STATUS_39 0x3fe9c +#define ixSMU_PM_STATUS_40 0x3fea0 +#define ixSMU_PM_STATUS_41 0x3fea4 +#define ixSMU_PM_STATUS_42 0x3fea8 +#define ixSMU_PM_STATUS_43 0x3feac +#define ixSMU_PM_STATUS_44 0x3feb0 +#define ixSMU_PM_STATUS_45 0x3feb4 +#define ixSMU_PM_STATUS_46 0x3feb8 +#define ixSMU_PM_STATUS_47 0x3febc +#define ixSMU_PM_STATUS_48 0x3fec0 +#define ixSMU_PM_STATUS_49 0x3fec4 +#define ixSMU_PM_STATUS_50 0x3fec8 +#define ixSMU_PM_STATUS_51 0x3fecc +#define ixSMU_PM_STATUS_52 0x3fed0 +#define ixSMU_PM_STATUS_53 0x3fed4 +#define ixSMU_PM_STATUS_54 0x3fed8 +#define ixSMU_PM_STATUS_55 0x3fedc +#define ixSMU_PM_STATUS_56 0x3fee0 +#define ixSMU_PM_STATUS_57 0x3fee4 +#define ixSMU_PM_STATUS_58 0x3fee8 +#define ixSMU_PM_STATUS_59 0x3feec +#define ixSMU_PM_STATUS_60 0x3fef0 +#define ixSMU_PM_STATUS_61 0x3fef4 +#define ixSMU_PM_STATUS_62 0x3fef8 +#define ixSMU_PM_STATUS_63 0x3fefc +#define ixSMU_PM_STATUS_64 0x3ff00 +#define ixSMU_PM_STATUS_65 0x3ff04 +#define ixSMU_PM_STATUS_66 0x3ff08 +#define ixSMU_PM_STATUS_67 0x3ff0c +#define ixSMU_PM_STATUS_68 0x3ff10 +#define ixSMU_PM_STATUS_69 0x3ff14 +#define ixSMU_PM_STATUS_70 0x3ff18 +#define ixSMU_PM_STATUS_71 0x3ff1c +#define ixSMU_PM_STATUS_72 0x3ff20 +#define ixSMU_PM_STATUS_73 0x3ff24 +#define ixSMU_PM_STATUS_74 0x3ff28 +#define ixSMU_PM_STATUS_75 0x3ff2c +#define ixSMU_PM_STATUS_76 0x3ff30 +#define ixSMU_PM_STATUS_77 0x3ff34 +#define ixSMU_PM_STATUS_78 0x3ff38 +#define ixSMU_PM_STATUS_79 0x3ff3c +#define ixSMU_PM_STATUS_80 0x3ff40 +#define ixSMU_PM_STATUS_81 0x3ff44 +#define ixSMU_PM_STATUS_82 0x3ff48 +#define ixSMU_PM_STATUS_83 0x3ff4c +#define ixSMU_PM_STATUS_84 0x3ff50 +#define ixSMU_PM_STATUS_85 0x3ff54 +#define ixSMU_PM_STATUS_86 0x3ff58 +#define ixSMU_PM_STATUS_87 0x3ff5c +#define ixSMU_PM_STATUS_88 0x3ff60 +#define ixSMU_PM_STATUS_89 0x3ff64 +#define ixSMU_PM_STATUS_90 0x3ff68 +#define ixSMU_PM_STATUS_91 0x3ff6c +#define ixSMU_PM_STATUS_92 0x3ff70 +#define ixSMU_PM_STATUS_93 0x3ff74 +#define ixSMU_PM_STATUS_94 0x3ff78 +#define ixSMU_PM_STATUS_95 0x3ff7c +#define ixSMU_PM_STATUS_96 0x3ff80 +#define ixSMU_PM_STATUS_97 0x3ff84 +#define ixSMU_PM_STATUS_98 0x3ff88 +#define ixSMU_PM_STATUS_99 0x3ff8c +#define ixSMU_PM_STATUS_100 0x3ff90 +#define ixSMU_PM_STATUS_101 0x3ff94 +#define ixSMU_PM_STATUS_102 0x3ff98 +#define ixSMU_PM_STATUS_103 0x3ff9c +#define ixSMU_PM_STATUS_104 0x3ffa0 +#define ixSMU_PM_STATUS_105 0x3ffa4 +#define ixSMU_PM_STATUS_106 0x3ffa8 +#define ixSMU_PM_STATUS_107 0x3ffac +#define ixSMU_PM_STATUS_108 0x3ffb0 +#define ixSMU_PM_STATUS_109 0x3ffb4 +#define ixSMU_PM_STATUS_110 0x3ffb8 +#define ixSMU_PM_STATUS_111 0x3ffbc +#define ixSMU_PM_STATUS_112 0x3ffc0 +#define ixSMU_PM_STATUS_113 0x3ffc4 +#define ixSMU_PM_STATUS_114 0x3ffc8 +#define ixSMU_PM_STATUS_115 0x3ffcc +#define ixSMU_PM_STATUS_116 0x3ffd0 +#define ixSMU_PM_STATUS_117 0x3ffd4 +#define ixSMU_PM_STATUS_118 0x3ffd8 +#define ixSMU_PM_STATUS_119 0x3ffdc +#define ixSMU_PM_STATUS_120 0x3ffe0 +#define ixSMU_PM_STATUS_121 0x3ffe4 +#define ixSMU_PM_STATUS_122 0x3ffe8 +#define ixSMU_PM_STATUS_123 0x3ffec +#define ixSMU_PM_STATUS_124 0x3fff0 +#define ixSMU_PM_STATUS_125 0x3fff4 +#define ixSMU_PM_STATUS_126 0x3fff8 +#define ixSMU_PM_STATUS_127 0x3fffc +#define ixCG_THERMAL_INT_ENA 0xc2100024 +#define ixCG_THERMAL_INT_CTRL 0xc2100028 +#define ixCG_THERMAL_INT_STATUS 0xc210002c +#define ixGENERAL_PWRMGT 0xc0200000 +#define ixCNB_PWRMGT_CNTL 0xc0200004 +#define ixSCLK_PWRMGT_CNTL 0xc0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 +#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 +#define ixPLL_TEST_CNTL 0xc020003c +#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 +#define ixCG_DISPLAY_GAP_CNTL 0xc0200060 +#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 +#define ixCG_ACPI_CNTL 0xc0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 +#define ixSMU_VOLTAGE_STATUS 0xc0200094 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 +#define ixCG_ULV_PARAMETER 0xc020015c +#define ixSCLK_MIN_DIV 0xc0200308 +#define ixLCAC_SX0_CNTL 0xc0400d00 +#define ixLCAC_SX0_OVR_SEL 0xc0400d04 +#define ixLCAC_SX0_OVR_VAL 0xc0400d08 +#define ixLCAC_MC0_CNTL 0xc0400d30 +#define ixLCAC_MC0_OVR_SEL 0xc0400d34 +#define ixLCAC_MC0_OVR_VAL 0xc0400d38 +#define ixLCAC_MC1_CNTL 0xc0400d3c +#define ixLCAC_MC1_OVR_SEL 0xc0400d40 +#define ixLCAC_MC1_OVR_VAL 0xc0400d44 +#define ixLCAC_MC2_CNTL 0xc0400d48 +#define ixLCAC_MC2_OVR_SEL 0xc0400d4c +#define ixLCAC_MC2_OVR_VAL 0xc0400d50 +#define ixLCAC_MC3_CNTL 0xc0400d54 +#define ixLCAC_MC3_OVR_SEL 0xc0400d58 +#define ixLCAC_MC3_OVR_VAL 0xc0400d5c +#define ixLCAC_CPL_CNTL 0xc0400d80 +#define ixLCAC_CPL_OVR_SEL 0xc0400d84 +#define ixLCAC_CPL_OVR_VAL 0xc0400d88 + +#endif /* SMU_7_0_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h new file mode 100644 index 000000000000..54e0e4c3f1bc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h @@ -0,0 +1,3842 @@ +/* + * SMU_7_0_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_0_0_SH_MASK_H +#define SMU_7_0_0_SH_MASK_H + +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f +#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 +#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f +#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 +#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f +#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 +#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f +#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON_MASK 0x2000 +#define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON__SHIFT 0xd +#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ_MASK 0x3c000 +#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ__SHIFT 0xe +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x1fc0000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x12 +#define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS_MASK 0xe000000 +#define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fc00 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0xa +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN_MASK 0x400 +#define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN__SHIFT 0xa +#define CG_SPLL_FUNC_CNTL_5__PLLBYPASS_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_5__PLLBYPASS__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d +#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 +#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 +#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 +#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 +#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 +#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 +#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff +#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 +#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 +#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 +#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 +#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa +#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 +#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_0__SMC_RESP_MASK 0xffff +#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_1__SMC_RESP_MASK 0xffff +#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_2__SMC_RESP_MASK 0xffff +#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_3__SMC_RESP_MASK 0xffff +#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_4__SMC_RESP_MASK 0xffff +#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_5__SMC_RESP_MASK 0xffff +#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_6__SMC_RESP_MASK 0xffff +#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_7__SMC_RESP_MASK 0xffff +#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_8__SMC_RESP_MASK 0xffff +#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_9__SMC_RESP_MASK 0xffff +#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_10__SMC_RESP_MASK 0xffff +#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_11__SMC_RESP_MASK 0xffff +#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 +#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 +#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 +#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 +#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 +#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffff +#define SMC_PC_C__smc_pc_c__SHIFT 0x0 +#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff +#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 +#define CG_FPS_CNT__FPS_CNT_MASK 0xff +#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 +#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 +#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 +#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 +#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 +#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 +#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa +#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 +#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 +#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 +#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 +#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 +#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 +#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 +#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 +#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 +#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 +#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 +#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 +#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 +#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 +#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 +#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 +#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 +#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 +#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 +#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 +#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 +#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 +#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 +#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa +#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000 +#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000 +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000 +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11 +#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000 +#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14 +#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000 +#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17 +#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000 +#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18 +#define CC_RCU_FUSES__RCU_SPARE_MASK 0x7e000000 +#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19 +#define CC_RCU_FUSES__PSP_ENABLE_MASK 0x80000000 +#define CC_RCU_FUSES__PSP_ENABLE__SHIFT 0x1f +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 +#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc +#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 +#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 +#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 +#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 +#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c +#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 +#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d +#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff +#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 +#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 +#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 +#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 +#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 +#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 +#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 +#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3fffe +#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 +#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a +#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 +#define SMU_STATUS__SMU_DONE_MASK 0x1 +#define SMU_STATUS__SMU_DONE__SHIFT 0x0 +#define SMU_STATUS__SMU_PASS_MASK 0x2 +#define SMU_STATUS__SMU_PASS__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 +#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 +#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 +#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 +#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 +#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 +#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 +#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 +#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 +#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff +#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 +#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 +#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f +#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff +#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 +#define DPM_TABLE_1__SystemFlags_MASK 0xffffffff +#define DPM_TABLE_1__SystemFlags__SHIFT 0x0 +#define DPM_TABLE_2__GraphicsPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_2__GraphicsPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_5__GraphicsPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_5__GraphicsPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_6__GraphicsPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_6__GraphicsPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_7__GraphicsPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_7__GraphicsPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_8__GraphicsPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_8__GraphicsPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_9__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_9__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_10__GraphicsPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_10__GraphicsPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_11__GioPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_11__GioPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_12__GioPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_12__GioPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_13__GioPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_13__GioPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_14__GioPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_14__GioPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_15__GioPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_15__GioPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_16__GioPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_16__GioPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_17__GioPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_17__GioPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_18__GioPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_18__GioPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_19__GioPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_19__GioPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_20__VceLevelCount_MASK 0xff +#define DPM_TABLE_20__VceLevelCount__SHIFT 0x0 +#define DPM_TABLE_20__UvdLevelCount_MASK 0xff00 +#define DPM_TABLE_20__UvdLevelCount__SHIFT 0x8 +#define DPM_TABLE_20__GIOLevelCount_MASK 0xff0000 +#define DPM_TABLE_20__GIOLevelCount__SHIFT 0x10 +#define DPM_TABLE_20__GraphicsDpmLevelCount_MASK 0xff000000 +#define DPM_TABLE_20__GraphicsDpmLevelCount__SHIFT 0x18 +#define DPM_TABLE_21__FpsHighThreshold_MASK 0xffff +#define DPM_TABLE_21__FpsHighThreshold__SHIFT 0x0 +#define DPM_TABLE_21__SamuLevelCount_MASK 0xff0000 +#define DPM_TABLE_21__SamuLevelCount__SHIFT 0x10 +#define DPM_TABLE_21__AcpLevelCount_MASK 0xff000000 +#define DPM_TABLE_21__AcpLevelCount__SHIFT 0x18 +#define DPM_TABLE_22__GraphicsLevel_0_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_22__GraphicsLevel_0_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_23__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_23__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_24__GraphicsLevel_0_ActivityLevel_MASK 0xffff +#define DPM_TABLE_24__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_24__GraphicsLevel_0_VidOffset_MASK 0xff0000 +#define DPM_TABLE_24__GraphicsLevel_0_VidOffset__SHIFT 0x10 +#define DPM_TABLE_24__GraphicsLevel_0_Vid_MASK 0xff000000 +#define DPM_TABLE_24__GraphicsLevel_0_Vid__SHIFT 0x18 +#define DPM_TABLE_25__GraphicsLevel_0_SclkDid_MASK 0xff +#define DPM_TABLE_25__GraphicsLevel_0_SclkDid__SHIFT 0x0 +#define DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_25__GraphicsLevel_0_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_25__GraphicsLevel_0_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_25__GraphicsLevel_0_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_25__GraphicsLevel_0_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_26__GraphicsLevel_0_UpHyst_MASK 0xff +#define DPM_TABLE_26__GraphicsLevel_0_UpHyst__SHIFT 0x0 +#define DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_27__GraphicsLevel_0_DownHyst_MASK 0xff000000 +#define DPM_TABLE_27__GraphicsLevel_0_DownHyst__SHIFT 0x18 +#define DPM_TABLE_28__GraphicsLevel_0_reserved_MASK 0xffffffff +#define DPM_TABLE_28__GraphicsLevel_0_reserved__SHIFT 0x0 +#define DPM_TABLE_29__GraphicsLevel_1_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_29__GraphicsLevel_1_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_30__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_30__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_31__GraphicsLevel_1_ActivityLevel_MASK 0xffff +#define DPM_TABLE_31__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_31__GraphicsLevel_1_VidOffset_MASK 0xff0000 +#define DPM_TABLE_31__GraphicsLevel_1_VidOffset__SHIFT 0x10 +#define DPM_TABLE_31__GraphicsLevel_1_Vid_MASK 0xff000000 +#define DPM_TABLE_31__GraphicsLevel_1_Vid__SHIFT 0x18 +#define DPM_TABLE_32__GraphicsLevel_1_SclkDid_MASK 0xff +#define DPM_TABLE_32__GraphicsLevel_1_SclkDid__SHIFT 0x0 +#define DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_32__GraphicsLevel_1_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_32__GraphicsLevel_1_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_32__GraphicsLevel_1_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_32__GraphicsLevel_1_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_33__GraphicsLevel_1_UpHyst_MASK 0xff +#define DPM_TABLE_33__GraphicsLevel_1_UpHyst__SHIFT 0x0 +#define DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_34__GraphicsLevel_1_DownHyst_MASK 0xff000000 +#define DPM_TABLE_34__GraphicsLevel_1_DownHyst__SHIFT 0x18 +#define DPM_TABLE_35__GraphicsLevel_1_reserved_MASK 0xffffffff +#define DPM_TABLE_35__GraphicsLevel_1_reserved__SHIFT 0x0 +#define DPM_TABLE_36__GraphicsLevel_2_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_36__GraphicsLevel_2_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_37__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_37__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_38__GraphicsLevel_2_ActivityLevel_MASK 0xffff +#define DPM_TABLE_38__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_38__GraphicsLevel_2_VidOffset_MASK 0xff0000 +#define DPM_TABLE_38__GraphicsLevel_2_VidOffset__SHIFT 0x10 +#define DPM_TABLE_38__GraphicsLevel_2_Vid_MASK 0xff000000 +#define DPM_TABLE_38__GraphicsLevel_2_Vid__SHIFT 0x18 +#define DPM_TABLE_39__GraphicsLevel_2_SclkDid_MASK 0xff +#define DPM_TABLE_39__GraphicsLevel_2_SclkDid__SHIFT 0x0 +#define DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_39__GraphicsLevel_2_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_39__GraphicsLevel_2_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_39__GraphicsLevel_2_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_39__GraphicsLevel_2_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_40__GraphicsLevel_2_UpHyst_MASK 0xff +#define DPM_TABLE_40__GraphicsLevel_2_UpHyst__SHIFT 0x0 +#define DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_41__GraphicsLevel_2_DownHyst_MASK 0xff000000 +#define DPM_TABLE_41__GraphicsLevel_2_DownHyst__SHIFT 0x18 +#define DPM_TABLE_42__GraphicsLevel_2_reserved_MASK 0xffffffff +#define DPM_TABLE_42__GraphicsLevel_2_reserved__SHIFT 0x0 +#define DPM_TABLE_43__GraphicsLevel_3_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_43__GraphicsLevel_3_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_44__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_44__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_45__GraphicsLevel_3_ActivityLevel_MASK 0xffff +#define DPM_TABLE_45__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_45__GraphicsLevel_3_VidOffset_MASK 0xff0000 +#define DPM_TABLE_45__GraphicsLevel_3_VidOffset__SHIFT 0x10 +#define DPM_TABLE_45__GraphicsLevel_3_Vid_MASK 0xff000000 +#define DPM_TABLE_45__GraphicsLevel_3_Vid__SHIFT 0x18 +#define DPM_TABLE_46__GraphicsLevel_3_SclkDid_MASK 0xff +#define DPM_TABLE_46__GraphicsLevel_3_SclkDid__SHIFT 0x0 +#define DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_46__GraphicsLevel_3_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_46__GraphicsLevel_3_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_46__GraphicsLevel_3_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_46__GraphicsLevel_3_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_47__GraphicsLevel_3_UpHyst_MASK 0xff +#define DPM_TABLE_47__GraphicsLevel_3_UpHyst__SHIFT 0x0 +#define DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_48__GraphicsLevel_3_DownHyst_MASK 0xff000000 +#define DPM_TABLE_48__GraphicsLevel_3_DownHyst__SHIFT 0x18 +#define DPM_TABLE_49__GraphicsLevel_3_reserved_MASK 0xffffffff +#define DPM_TABLE_49__GraphicsLevel_3_reserved__SHIFT 0x0 +#define DPM_TABLE_50__GraphicsLevel_4_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_50__GraphicsLevel_4_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_51__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_51__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_52__GraphicsLevel_4_ActivityLevel_MASK 0xffff +#define DPM_TABLE_52__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_52__GraphicsLevel_4_VidOffset_MASK 0xff0000 +#define DPM_TABLE_52__GraphicsLevel_4_VidOffset__SHIFT 0x10 +#define DPM_TABLE_52__GraphicsLevel_4_Vid_MASK 0xff000000 +#define DPM_TABLE_52__GraphicsLevel_4_Vid__SHIFT 0x18 +#define DPM_TABLE_53__GraphicsLevel_4_SclkDid_MASK 0xff +#define DPM_TABLE_53__GraphicsLevel_4_SclkDid__SHIFT 0x0 +#define DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_53__GraphicsLevel_4_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_53__GraphicsLevel_4_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_53__GraphicsLevel_4_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_53__GraphicsLevel_4_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_54__GraphicsLevel_4_UpHyst_MASK 0xff +#define DPM_TABLE_54__GraphicsLevel_4_UpHyst__SHIFT 0x0 +#define DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_55__GraphicsLevel_4_DownHyst_MASK 0xff000000 +#define DPM_TABLE_55__GraphicsLevel_4_DownHyst__SHIFT 0x18 +#define DPM_TABLE_56__GraphicsLevel_4_reserved_MASK 0xffffffff +#define DPM_TABLE_56__GraphicsLevel_4_reserved__SHIFT 0x0 +#define DPM_TABLE_57__GraphicsLevel_5_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_57__GraphicsLevel_5_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_58__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_58__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_59__GraphicsLevel_5_ActivityLevel_MASK 0xffff +#define DPM_TABLE_59__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_59__GraphicsLevel_5_VidOffset_MASK 0xff0000 +#define DPM_TABLE_59__GraphicsLevel_5_VidOffset__SHIFT 0x10 +#define DPM_TABLE_59__GraphicsLevel_5_Vid_MASK 0xff000000 +#define DPM_TABLE_59__GraphicsLevel_5_Vid__SHIFT 0x18 +#define DPM_TABLE_60__GraphicsLevel_5_SclkDid_MASK 0xff +#define DPM_TABLE_60__GraphicsLevel_5_SclkDid__SHIFT 0x0 +#define DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_60__GraphicsLevel_5_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_60__GraphicsLevel_5_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_60__GraphicsLevel_5_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_60__GraphicsLevel_5_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_61__GraphicsLevel_5_UpHyst_MASK 0xff +#define DPM_TABLE_61__GraphicsLevel_5_UpHyst__SHIFT 0x0 +#define DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_62__GraphicsLevel_5_DownHyst_MASK 0xff000000 +#define DPM_TABLE_62__GraphicsLevel_5_DownHyst__SHIFT 0x18 +#define DPM_TABLE_63__GraphicsLevel_5_reserved_MASK 0xffffffff +#define DPM_TABLE_63__GraphicsLevel_5_reserved__SHIFT 0x0 +#define DPM_TABLE_64__GraphicsLevel_6_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_64__GraphicsLevel_6_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_65__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_65__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_66__GraphicsLevel_6_ActivityLevel_MASK 0xffff +#define DPM_TABLE_66__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_66__GraphicsLevel_6_VidOffset_MASK 0xff0000 +#define DPM_TABLE_66__GraphicsLevel_6_VidOffset__SHIFT 0x10 +#define DPM_TABLE_66__GraphicsLevel_6_Vid_MASK 0xff000000 +#define DPM_TABLE_66__GraphicsLevel_6_Vid__SHIFT 0x18 +#define DPM_TABLE_67__GraphicsLevel_6_SclkDid_MASK 0xff +#define DPM_TABLE_67__GraphicsLevel_6_SclkDid__SHIFT 0x0 +#define DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_67__GraphicsLevel_6_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_67__GraphicsLevel_6_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_67__GraphicsLevel_6_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_67__GraphicsLevel_6_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_68__GraphicsLevel_6_UpHyst_MASK 0xff +#define DPM_TABLE_68__GraphicsLevel_6_UpHyst__SHIFT 0x0 +#define DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_69__GraphicsLevel_6_DownHyst_MASK 0xff000000 +#define DPM_TABLE_69__GraphicsLevel_6_DownHyst__SHIFT 0x18 +#define DPM_TABLE_70__GraphicsLevel_6_reserved_MASK 0xffffffff +#define DPM_TABLE_70__GraphicsLevel_6_reserved__SHIFT 0x0 +#define DPM_TABLE_71__GraphicsLevel_7_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_71__GraphicsLevel_7_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_72__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_72__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_73__GraphicsLevel_7_ActivityLevel_MASK 0xffff +#define DPM_TABLE_73__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_73__GraphicsLevel_7_VidOffset_MASK 0xff0000 +#define DPM_TABLE_73__GraphicsLevel_7_VidOffset__SHIFT 0x10 +#define DPM_TABLE_73__GraphicsLevel_7_Vid_MASK 0xff000000 +#define DPM_TABLE_73__GraphicsLevel_7_Vid__SHIFT 0x18 +#define DPM_TABLE_74__GraphicsLevel_7_SclkDid_MASK 0xff +#define DPM_TABLE_74__GraphicsLevel_7_SclkDid__SHIFT 0x0 +#define DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_74__GraphicsLevel_7_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_74__GraphicsLevel_7_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_74__GraphicsLevel_7_PowerThrottle_MASK 0xff000000 +#define DPM_TABLE_74__GraphicsLevel_7_PowerThrottle__SHIFT 0x18 +#define DPM_TABLE_75__GraphicsLevel_7_UpHyst_MASK 0xff +#define DPM_TABLE_75__GraphicsLevel_7_UpHyst__SHIFT 0x0 +#define DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity_MASK 0xff0000 +#define DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity__SHIFT 0x10 +#define DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark_MASK 0xff000000 +#define DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark__SHIFT 0x18 +#define DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst_MASK 0xff0000 +#define DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x10 +#define DPM_TABLE_76__GraphicsLevel_7_DownHyst_MASK 0xff000000 +#define DPM_TABLE_76__GraphicsLevel_7_DownHyst__SHIFT 0x18 +#define DPM_TABLE_77__GraphicsLevel_7_reserved_MASK 0xffffffff +#define DPM_TABLE_77__GraphicsLevel_7_reserved__SHIFT 0x0 +#define DPM_TABLE_78__ACPILevel_Flags_MASK 0xffffffff +#define DPM_TABLE_78__ACPILevel_Flags__SHIFT 0x0 +#define DPM_TABLE_79__ACPILevel_MinVddNb_MASK 0xffffffff +#define DPM_TABLE_79__ACPILevel_MinVddNb__SHIFT 0x0 +#define DPM_TABLE_80__ACPILevel_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_80__ACPILevel_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_81__ACPILevel_DisplayWatermark_MASK 0xff +#define DPM_TABLE_81__ACPILevel_DisplayWatermark__SHIFT 0x0 +#define DPM_TABLE_81__ACPILevel_ForceNbPs1_MASK 0xff00 +#define DPM_TABLE_81__ACPILevel_ForceNbPs1__SHIFT 0x8 +#define DPM_TABLE_81__ACPILevel_GnbSlow_MASK 0xff0000 +#define DPM_TABLE_81__ACPILevel_GnbSlow__SHIFT 0x10 +#define DPM_TABLE_81__ACPILevel_SclkDid_MASK 0xff000000 +#define DPM_TABLE_81__ACPILevel_SclkDid__SHIFT 0x18 +#define DPM_TABLE_82__ACPILevel_padding_2_MASK 0xff +#define DPM_TABLE_82__ACPILevel_padding_2__SHIFT 0x0 +#define DPM_TABLE_82__ACPILevel_padding_1_MASK 0xff00 +#define DPM_TABLE_82__ACPILevel_padding_1__SHIFT 0x8 +#define DPM_TABLE_82__ACPILevel_padding_0_MASK 0xff0000 +#define DPM_TABLE_82__ACPILevel_padding_0__SHIFT 0x10 +#define DPM_TABLE_82__ACPILevel_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_82__ACPILevel_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_83__UvdLevel_0_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_83__UvdLevel_0_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_84__UvdLevel_0_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_84__UvdLevel_0_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_85__UvdLevel_0_DclkDivider_MASK 0xff +#define DPM_TABLE_85__UvdLevel_0_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_85__UvdLevel_0_VclkDivider_MASK 0xff00 +#define DPM_TABLE_85__UvdLevel_0_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_85__UvdLevel_0_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_85__UvdLevel_0_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_86__UvdLevel_0_padding_1_MASK 0xff +#define DPM_TABLE_86__UvdLevel_0_padding_1__SHIFT 0x0 +#define DPM_TABLE_86__UvdLevel_0_padding_0_MASK 0xff00 +#define DPM_TABLE_86__UvdLevel_0_padding_0__SHIFT 0x8 +#define DPM_TABLE_86__UvdLevel_0_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_86__UvdLevel_0_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_86__UvdLevel_0_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_86__UvdLevel_0_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_87__UvdLevel_1_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_87__UvdLevel_1_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_88__UvdLevel_1_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_88__UvdLevel_1_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_89__UvdLevel_1_DclkDivider_MASK 0xff +#define DPM_TABLE_89__UvdLevel_1_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_89__UvdLevel_1_VclkDivider_MASK 0xff00 +#define DPM_TABLE_89__UvdLevel_1_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_89__UvdLevel_1_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_89__UvdLevel_1_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_90__UvdLevel_1_padding_1_MASK 0xff +#define DPM_TABLE_90__UvdLevel_1_padding_1__SHIFT 0x0 +#define DPM_TABLE_90__UvdLevel_1_padding_0_MASK 0xff00 +#define DPM_TABLE_90__UvdLevel_1_padding_0__SHIFT 0x8 +#define DPM_TABLE_90__UvdLevel_1_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_90__UvdLevel_1_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_90__UvdLevel_1_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_90__UvdLevel_1_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_91__UvdLevel_2_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_91__UvdLevel_2_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_92__UvdLevel_2_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_92__UvdLevel_2_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_93__UvdLevel_2_DclkDivider_MASK 0xff +#define DPM_TABLE_93__UvdLevel_2_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_93__UvdLevel_2_VclkDivider_MASK 0xff00 +#define DPM_TABLE_93__UvdLevel_2_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_93__UvdLevel_2_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_93__UvdLevel_2_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_94__UvdLevel_2_padding_1_MASK 0xff +#define DPM_TABLE_94__UvdLevel_2_padding_1__SHIFT 0x0 +#define DPM_TABLE_94__UvdLevel_2_padding_0_MASK 0xff00 +#define DPM_TABLE_94__UvdLevel_2_padding_0__SHIFT 0x8 +#define DPM_TABLE_94__UvdLevel_2_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_94__UvdLevel_2_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_94__UvdLevel_2_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_94__UvdLevel_2_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_95__UvdLevel_3_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_95__UvdLevel_3_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_96__UvdLevel_3_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_96__UvdLevel_3_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_97__UvdLevel_3_DclkDivider_MASK 0xff +#define DPM_TABLE_97__UvdLevel_3_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_97__UvdLevel_3_VclkDivider_MASK 0xff00 +#define DPM_TABLE_97__UvdLevel_3_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_97__UvdLevel_3_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_97__UvdLevel_3_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_98__UvdLevel_3_padding_1_MASK 0xff +#define DPM_TABLE_98__UvdLevel_3_padding_1__SHIFT 0x0 +#define DPM_TABLE_98__UvdLevel_3_padding_0_MASK 0xff00 +#define DPM_TABLE_98__UvdLevel_3_padding_0__SHIFT 0x8 +#define DPM_TABLE_98__UvdLevel_3_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_98__UvdLevel_3_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_98__UvdLevel_3_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_98__UvdLevel_3_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_99__UvdLevel_4_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_99__UvdLevel_4_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_100__UvdLevel_4_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_100__UvdLevel_4_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_101__UvdLevel_4_DclkDivider_MASK 0xff +#define DPM_TABLE_101__UvdLevel_4_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_101__UvdLevel_4_VclkDivider_MASK 0xff00 +#define DPM_TABLE_101__UvdLevel_4_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_101__UvdLevel_4_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_101__UvdLevel_4_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_102__UvdLevel_4_padding_1_MASK 0xff +#define DPM_TABLE_102__UvdLevel_4_padding_1__SHIFT 0x0 +#define DPM_TABLE_102__UvdLevel_4_padding_0_MASK 0xff00 +#define DPM_TABLE_102__UvdLevel_4_padding_0__SHIFT 0x8 +#define DPM_TABLE_102__UvdLevel_4_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_102__UvdLevel_4_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_102__UvdLevel_4_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_102__UvdLevel_4_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_103__UvdLevel_5_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_103__UvdLevel_5_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_104__UvdLevel_5_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_104__UvdLevel_5_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_105__UvdLevel_5_DclkDivider_MASK 0xff +#define DPM_TABLE_105__UvdLevel_5_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_105__UvdLevel_5_VclkDivider_MASK 0xff00 +#define DPM_TABLE_105__UvdLevel_5_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_105__UvdLevel_5_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_105__UvdLevel_5_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_106__UvdLevel_5_padding_1_MASK 0xff +#define DPM_TABLE_106__UvdLevel_5_padding_1__SHIFT 0x0 +#define DPM_TABLE_106__UvdLevel_5_padding_0_MASK 0xff00 +#define DPM_TABLE_106__UvdLevel_5_padding_0__SHIFT 0x8 +#define DPM_TABLE_106__UvdLevel_5_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_106__UvdLevel_5_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_106__UvdLevel_5_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_106__UvdLevel_5_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_107__UvdLevel_6_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_107__UvdLevel_6_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_108__UvdLevel_6_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_108__UvdLevel_6_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_109__UvdLevel_6_DclkDivider_MASK 0xff +#define DPM_TABLE_109__UvdLevel_6_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_109__UvdLevel_6_VclkDivider_MASK 0xff00 +#define DPM_TABLE_109__UvdLevel_6_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_109__UvdLevel_6_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_109__UvdLevel_6_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_110__UvdLevel_6_padding_1_MASK 0xff +#define DPM_TABLE_110__UvdLevel_6_padding_1__SHIFT 0x0 +#define DPM_TABLE_110__UvdLevel_6_padding_0_MASK 0xff00 +#define DPM_TABLE_110__UvdLevel_6_padding_0__SHIFT 0x8 +#define DPM_TABLE_110__UvdLevel_6_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_110__UvdLevel_6_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_110__UvdLevel_6_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_110__UvdLevel_6_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_111__UvdLevel_7_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_111__UvdLevel_7_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_112__UvdLevel_7_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_112__UvdLevel_7_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_113__UvdLevel_7_DclkDivider_MASK 0xff +#define DPM_TABLE_113__UvdLevel_7_DclkDivider__SHIFT 0x0 +#define DPM_TABLE_113__UvdLevel_7_VclkDivider_MASK 0xff00 +#define DPM_TABLE_113__UvdLevel_7_VclkDivider__SHIFT 0x8 +#define DPM_TABLE_113__UvdLevel_7_MinVddNb_MASK 0xffff0000 +#define DPM_TABLE_113__UvdLevel_7_MinVddNb__SHIFT 0x10 +#define DPM_TABLE_114__UvdLevel_7_padding_1_MASK 0xff +#define DPM_TABLE_114__UvdLevel_7_padding_1__SHIFT 0x0 +#define DPM_TABLE_114__UvdLevel_7_padding_0_MASK 0xff00 +#define DPM_TABLE_114__UvdLevel_7_padding_0__SHIFT 0x8 +#define DPM_TABLE_114__UvdLevel_7_DClkBypassCntl_MASK 0xff0000 +#define DPM_TABLE_114__UvdLevel_7_DClkBypassCntl__SHIFT 0x10 +#define DPM_TABLE_114__UvdLevel_7_VClkBypassCntl_MASK 0xff000000 +#define DPM_TABLE_114__UvdLevel_7_VClkBypassCntl__SHIFT 0x18 +#define DPM_TABLE_115__VceLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_115__VceLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_116__VceLevel_0_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_116__VceLevel_0_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_116__VceLevel_0_Divider_MASK 0xff00 +#define DPM_TABLE_116__VceLevel_0_Divider__SHIFT 0x8 +#define DPM_TABLE_116__VceLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_116__VceLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_117__VceLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_117__VceLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_118__VceLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_118__VceLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_119__VceLevel_1_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_119__VceLevel_1_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_119__VceLevel_1_Divider_MASK 0xff00 +#define DPM_TABLE_119__VceLevel_1_Divider__SHIFT 0x8 +#define DPM_TABLE_119__VceLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_119__VceLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_120__VceLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_120__VceLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_121__VceLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_121__VceLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_122__VceLevel_2_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_122__VceLevel_2_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_122__VceLevel_2_Divider_MASK 0xff00 +#define DPM_TABLE_122__VceLevel_2_Divider__SHIFT 0x8 +#define DPM_TABLE_122__VceLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_122__VceLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_123__VceLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_123__VceLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_124__VceLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_124__VceLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_125__VceLevel_3_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_125__VceLevel_3_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_125__VceLevel_3_Divider_MASK 0xff00 +#define DPM_TABLE_125__VceLevel_3_Divider__SHIFT 0x8 +#define DPM_TABLE_125__VceLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_125__VceLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_126__VceLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_126__VceLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_127__VceLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_127__VceLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_128__VceLevel_4_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_128__VceLevel_4_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_128__VceLevel_4_Divider_MASK 0xff00 +#define DPM_TABLE_128__VceLevel_4_Divider__SHIFT 0x8 +#define DPM_TABLE_128__VceLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_128__VceLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_129__VceLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_129__VceLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_130__VceLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_130__VceLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_131__VceLevel_5_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_131__VceLevel_5_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_131__VceLevel_5_Divider_MASK 0xff00 +#define DPM_TABLE_131__VceLevel_5_Divider__SHIFT 0x8 +#define DPM_TABLE_131__VceLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_131__VceLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_132__VceLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_132__VceLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_133__VceLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_133__VceLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_134__VceLevel_6_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_134__VceLevel_6_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_134__VceLevel_6_Divider_MASK 0xff00 +#define DPM_TABLE_134__VceLevel_6_Divider__SHIFT 0x8 +#define DPM_TABLE_134__VceLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_134__VceLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_135__VceLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_135__VceLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_136__VceLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_136__VceLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_137__VceLevel_7_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_137__VceLevel_7_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_137__VceLevel_7_Divider_MASK 0xff00 +#define DPM_TABLE_137__VceLevel_7_Divider__SHIFT 0x8 +#define DPM_TABLE_137__VceLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_137__VceLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_138__VceLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_138__VceLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_139__AcpLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_139__AcpLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_140__AcpLevel_0_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_140__AcpLevel_0_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_140__AcpLevel_0_Divider_MASK 0xff00 +#define DPM_TABLE_140__AcpLevel_0_Divider__SHIFT 0x8 +#define DPM_TABLE_140__AcpLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_140__AcpLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_141__AcpLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_141__AcpLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_142__AcpLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_142__AcpLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_143__AcpLevel_1_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_143__AcpLevel_1_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_143__AcpLevel_1_Divider_MASK 0xff00 +#define DPM_TABLE_143__AcpLevel_1_Divider__SHIFT 0x8 +#define DPM_TABLE_143__AcpLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_143__AcpLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_144__AcpLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_144__AcpLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_145__AcpLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_145__AcpLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_146__AcpLevel_2_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_146__AcpLevel_2_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_146__AcpLevel_2_Divider_MASK 0xff00 +#define DPM_TABLE_146__AcpLevel_2_Divider__SHIFT 0x8 +#define DPM_TABLE_146__AcpLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_146__AcpLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_147__AcpLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_147__AcpLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_148__AcpLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_148__AcpLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_149__AcpLevel_3_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_149__AcpLevel_3_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_149__AcpLevel_3_Divider_MASK 0xff00 +#define DPM_TABLE_149__AcpLevel_3_Divider__SHIFT 0x8 +#define DPM_TABLE_149__AcpLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_149__AcpLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_150__AcpLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_150__AcpLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_151__AcpLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_151__AcpLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_152__AcpLevel_4_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_152__AcpLevel_4_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_152__AcpLevel_4_Divider_MASK 0xff00 +#define DPM_TABLE_152__AcpLevel_4_Divider__SHIFT 0x8 +#define DPM_TABLE_152__AcpLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_152__AcpLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_153__AcpLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_153__AcpLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_154__AcpLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_154__AcpLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_155__AcpLevel_5_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_155__AcpLevel_5_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_155__AcpLevel_5_Divider_MASK 0xff00 +#define DPM_TABLE_155__AcpLevel_5_Divider__SHIFT 0x8 +#define DPM_TABLE_155__AcpLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_155__AcpLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_156__AcpLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_156__AcpLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_157__AcpLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_157__AcpLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_158__AcpLevel_6_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_158__AcpLevel_6_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_158__AcpLevel_6_Divider_MASK 0xff00 +#define DPM_TABLE_158__AcpLevel_6_Divider__SHIFT 0x8 +#define DPM_TABLE_158__AcpLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_158__AcpLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_159__AcpLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_159__AcpLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_160__AcpLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_160__AcpLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_161__AcpLevel_7_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_161__AcpLevel_7_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_161__AcpLevel_7_Divider_MASK 0xff00 +#define DPM_TABLE_161__AcpLevel_7_Divider__SHIFT 0x8 +#define DPM_TABLE_161__AcpLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_161__AcpLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_162__AcpLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_162__AcpLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_163__SamuLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_163__SamuLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_164__SamuLevel_0_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_164__SamuLevel_0_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_164__SamuLevel_0_Divider_MASK 0xff00 +#define DPM_TABLE_164__SamuLevel_0_Divider__SHIFT 0x8 +#define DPM_TABLE_164__SamuLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_164__SamuLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_165__SamuLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_165__SamuLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_166__SamuLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_166__SamuLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_167__SamuLevel_1_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_167__SamuLevel_1_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_167__SamuLevel_1_Divider_MASK 0xff00 +#define DPM_TABLE_167__SamuLevel_1_Divider__SHIFT 0x8 +#define DPM_TABLE_167__SamuLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_167__SamuLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_168__SamuLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_168__SamuLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_169__SamuLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_169__SamuLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_170__SamuLevel_2_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_170__SamuLevel_2_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_170__SamuLevel_2_Divider_MASK 0xff00 +#define DPM_TABLE_170__SamuLevel_2_Divider__SHIFT 0x8 +#define DPM_TABLE_170__SamuLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_170__SamuLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_171__SamuLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_171__SamuLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_172__SamuLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_172__SamuLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_173__SamuLevel_3_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_173__SamuLevel_3_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_173__SamuLevel_3_Divider_MASK 0xff00 +#define DPM_TABLE_173__SamuLevel_3_Divider__SHIFT 0x8 +#define DPM_TABLE_173__SamuLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_173__SamuLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_174__SamuLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_174__SamuLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_175__SamuLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_175__SamuLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_176__SamuLevel_4_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_176__SamuLevel_4_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_176__SamuLevel_4_Divider_MASK 0xff00 +#define DPM_TABLE_176__SamuLevel_4_Divider__SHIFT 0x8 +#define DPM_TABLE_176__SamuLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_176__SamuLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_177__SamuLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_177__SamuLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_178__SamuLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_178__SamuLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_179__SamuLevel_5_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_179__SamuLevel_5_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_179__SamuLevel_5_Divider_MASK 0xff00 +#define DPM_TABLE_179__SamuLevel_5_Divider__SHIFT 0x8 +#define DPM_TABLE_179__SamuLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_179__SamuLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_180__SamuLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_180__SamuLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_181__SamuLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_181__SamuLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_182__SamuLevel_6_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_182__SamuLevel_6_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_182__SamuLevel_6_Divider_MASK 0xff00 +#define DPM_TABLE_182__SamuLevel_6_Divider__SHIFT 0x8 +#define DPM_TABLE_182__SamuLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_182__SamuLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_183__SamuLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_183__SamuLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_184__SamuLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_184__SamuLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_185__SamuLevel_7_ClkBypassCntl_MASK 0xff +#define DPM_TABLE_185__SamuLevel_7_ClkBypassCntl__SHIFT 0x0 +#define DPM_TABLE_185__SamuLevel_7_Divider_MASK 0xff00 +#define DPM_TABLE_185__SamuLevel_7_Divider__SHIFT 0x8 +#define DPM_TABLE_185__SamuLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_185__SamuLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_186__SamuLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_186__SamuLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_187__SamuBootLevel_MASK 0xff +#define DPM_TABLE_187__SamuBootLevel__SHIFT 0x0 +#define DPM_TABLE_187__AcpBootLevel_MASK 0xff00 +#define DPM_TABLE_187__AcpBootLevel__SHIFT 0x8 +#define DPM_TABLE_187__VceBootLevel_MASK 0xff0000 +#define DPM_TABLE_187__VceBootLevel__SHIFT 0x10 +#define DPM_TABLE_187__UvdBootLevel_MASK 0xff000000 +#define DPM_TABLE_187__UvdBootLevel__SHIFT 0x18 +#define DPM_TABLE_188__SAMUInterval_MASK 0xff +#define DPM_TABLE_188__SAMUInterval__SHIFT 0x0 +#define DPM_TABLE_188__ACPInterval_MASK 0xff00 +#define DPM_TABLE_188__ACPInterval__SHIFT 0x8 +#define DPM_TABLE_188__VCEInterval_MASK 0xff0000 +#define DPM_TABLE_188__VCEInterval__SHIFT 0x10 +#define DPM_TABLE_188__UVDInterval_MASK 0xff000000 +#define DPM_TABLE_188__UVDInterval__SHIFT 0x18 +#define DPM_TABLE_189__GraphicsVoltageChangeEnable_MASK 0xff +#define DPM_TABLE_189__GraphicsVoltageChangeEnable__SHIFT 0x0 +#define DPM_TABLE_189__GraphicsThermThrottleEnable_MASK 0xff00 +#define DPM_TABLE_189__GraphicsThermThrottleEnable__SHIFT 0x8 +#define DPM_TABLE_189__GraphicsInterval_MASK 0xff0000 +#define DPM_TABLE_189__GraphicsInterval__SHIFT 0x10 +#define DPM_TABLE_189__GraphicsBootLevel_MASK 0xff000000 +#define DPM_TABLE_189__GraphicsBootLevel__SHIFT 0x18 +#define DPM_TABLE_190__FpsLowThreshold_MASK 0xffff +#define DPM_TABLE_190__FpsLowThreshold__SHIFT 0x0 +#define DPM_TABLE_190__GraphicsClkSlowDivider_MASK 0xff0000 +#define DPM_TABLE_190__GraphicsClkSlowDivider__SHIFT 0x10 +#define DPM_TABLE_190__GraphicsClkSlowEnable_MASK 0xff000000 +#define DPM_TABLE_190__GraphicsClkSlowEnable__SHIFT 0x18 +#define DPM_TABLE_191__DisplayCac_MASK 0xffffffff +#define DPM_TABLE_191__DisplayCac__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_4__HandshakeDisables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_4__HandshakeDisables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy4Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_5__DisplayPhy4Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy3Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy3Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy2Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy2Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy1Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_5__DisplayPhy1Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy8Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_6__DisplayPhy8Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy7Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy7Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy6Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy6Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy5Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_6__DisplayPhy5Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_7__AverageGraphicsActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_7__AverageGraphicsActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_8__AverageMemoryActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_8__AverageMemoryActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_9__AverageGioActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_9__AverageGioActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__PCIeDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_10__PCIeDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__LClkDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_10__LClkDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_10__MClkDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_10__MClkDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_10__SClkDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_10__SClkDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_11__VCEDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_11__VCEDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_11__ACPDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_11__ACPDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_11__SAMUDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_11__SAMUDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_11__UVDDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_11__UVDDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_12__Reserved_0_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_12__Reserved_0__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_13__Reserved_1_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_13__Reserved_1__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__Reserved_2_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_14__Reserved_2__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_15__Reserved_3_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_15__Reserved_3__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_16__Reserved_4_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_16__Reserved_4__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_17__Reserved_5_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_17__Reserved_5__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_18__Reserved_6_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_18__Reserved_6__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__Reserved_7_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_19__Reserved_7__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_20__Reserved_8_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_20__Reserved_8__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_21__Reserved_9_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_21__Reserved_9__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_0_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_0_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_1_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_1_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_2_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_2_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_3_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_3_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_4_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_4_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_5_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_5_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_6_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_6_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff +#define SMU_LCLK_DPM_STATE_7_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__VID_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__VID__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__CLK_DIVIDER_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__CLK_DIVIDER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__STATE_VALID_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_7_CNTL_0__STATE_VALID__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_0_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_0_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_1_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_1_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_2_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_2_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_3_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_3_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_4_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_4_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_5_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_5_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_6_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_6_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_7_CNTL_1__MIN_VDDNB_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_7_CNTL_1__MIN_VDDNB__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_0_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_0_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_1_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_1_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_2_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_2_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_3_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_3_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_4_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_4_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_5_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_5_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_6_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_6_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_DOWN_MASK 0xff +#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_UP_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_UP__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_7_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000 +#define SMU_LCLK_DPM_STATE_7_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_0_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_0_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_1_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_1_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_2_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_2_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_3_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_3_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_4_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_4_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_5_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_5_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_6_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_6_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_7_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff +#define SMU_LCLK_DPM_STATE_7_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000 +#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18 +#define GIO_PID_CONTROLLER_CNTL_0__K_I_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_0__K_I__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_6__MAX_STATE_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_6__MAX_STATE__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION__SHIFT 0x0 +#define GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT_MASK 0xffffffff +#define GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT__SHIFT 0x0 +#define SMU_LCLK_DPM_LEVEL_COUNT__LCLK_DPM_LEVEL_COUNT_MASK 0xffffffff +#define SMU_LCLK_DPM_LEVEL_COUNT__LCLK_DPM_LEVEL_COUNT__SHIFT 0x0 +#define SMU_LCLK_DPM_CNTL__RESERVED_MASK 0xff +#define SMU_LCLK_DPM_CNTL__RESERVED__SHIFT 0x0 +#define SMU_LCLK_DPM_CNTL__LCLK_DPM_BOOT_STATE_MASK 0xff00 +#define SMU_LCLK_DPM_CNTL__LCLK_DPM_BOOT_STATE__SHIFT 0x8 +#define SMU_LCLK_DPM_CNTL__VOLTAGE_CHG_EN_MASK 0xff0000 +#define SMU_LCLK_DPM_CNTL__VOLTAGE_CHG_EN__SHIFT 0x10 +#define SMU_LCLK_DPM_CNTL__LCLK_DPM_EN_MASK 0xff000000 +#define SMU_LCLK_DPM_CNTL__LCLK_DPM_EN__SHIFT 0x18 +#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__CURRENT_STATE_MASK 0xff +#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__CURRENT_STATE__SHIFT 0x0 +#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__TARGET_STATE_MASK 0xff00 +#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__TARGET_STATE__SHIFT 0x8 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_THERMAL_THROTTLING_EN_MASK 0xff +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_THERMAL_THROTTLING_EN__SHIFT 0x0 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TEMPERATURE_SEL_MASK 0xff00 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TEMPERATURE_SEL__SHIFT 0x8 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_TT_MODE_MASK 0xff0000 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_TT_MODE__SHIFT 0x10 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TT_HTC_ACTIVE_MASK 0xff000000 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TT_HTC_ACTIVE__SHIFT 0x18 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__LOW_THRESHOLD_MASK 0xffff +#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__LOW_THRESHOLD__SHIFT 0x0 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__HIGH_THRESHOLD_MASK 0xffff0000 +#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__HIGH_THRESHOLD__SHIFT 0x10 +#define PM_FUSES_1__BapmPstateVid_3_MASK 0xff +#define PM_FUSES_1__BapmPstateVid_3__SHIFT 0x0 +#define PM_FUSES_1__BapmPstateVid_2_MASK 0xff00 +#define PM_FUSES_1__BapmPstateVid_2__SHIFT 0x8 +#define PM_FUSES_1__BapmPstateVid_1_MASK 0xff0000 +#define PM_FUSES_1__BapmPstateVid_1__SHIFT 0x10 +#define PM_FUSES_1__BapmPstateVid_0_MASK 0xff000000 +#define PM_FUSES_1__BapmPstateVid_0__SHIFT 0x18 +#define PM_FUSES_2__BapmPstateVid_7_MASK 0xff +#define PM_FUSES_2__BapmPstateVid_7__SHIFT 0x0 +#define PM_FUSES_2__BapmPstateVid_6_MASK 0xff00 +#define PM_FUSES_2__BapmPstateVid_6__SHIFT 0x8 +#define PM_FUSES_2__BapmPstateVid_5_MASK 0xff0000 +#define PM_FUSES_2__BapmPstateVid_5__SHIFT 0x10 +#define PM_FUSES_2__BapmPstateVid_4_MASK 0xff000000 +#define PM_FUSES_2__BapmPstateVid_4__SHIFT 0x18 +#define PM_FUSES_3__BapmVddNbVidHiSidd_3_MASK 0xff +#define PM_FUSES_3__BapmVddNbVidHiSidd_3__SHIFT 0x0 +#define PM_FUSES_3__BapmVddNbVidHiSidd_2_MASK 0xff00 +#define PM_FUSES_3__BapmVddNbVidHiSidd_2__SHIFT 0x8 +#define PM_FUSES_3__BapmVddNbVidHiSidd_1_MASK 0xff0000 +#define PM_FUSES_3__BapmVddNbVidHiSidd_1__SHIFT 0x10 +#define PM_FUSES_3__BapmVddNbVidHiSidd_0_MASK 0xff000000 +#define PM_FUSES_3__BapmVddNbVidHiSidd_0__SHIFT 0x18 +#define PM_FUSES_4__BapmVddNbVidLoSidd_2_MASK 0xff +#define PM_FUSES_4__BapmVddNbVidLoSidd_2__SHIFT 0x0 +#define PM_FUSES_4__BapmVddNbVidLoSidd_1_MASK 0xff00 +#define PM_FUSES_4__BapmVddNbVidLoSidd_1__SHIFT 0x8 +#define PM_FUSES_4__BapmVddNbVidLoSidd_0_MASK 0xff0000 +#define PM_FUSES_4__BapmVddNbVidLoSidd_0__SHIFT 0x10 +#define PM_FUSES_4__BapmVddNbVidHiSidd_4_MASK 0xff000000 +#define PM_FUSES_4__BapmVddNbVidHiSidd_4__SHIFT 0x18 +#define PM_FUSES_5__CpuIdModel_MASK 0xff +#define PM_FUSES_5__CpuIdModel__SHIFT 0x0 +#define PM_FUSES_5__SviLoadLineEn_MASK 0xff00 +#define PM_FUSES_5__SviLoadLineEn__SHIFT 0x8 +#define PM_FUSES_5__BapmVddNbVidLoSidd_4_MASK 0xff0000 +#define PM_FUSES_5__BapmVddNbVidLoSidd_4__SHIFT 0x10 +#define PM_FUSES_5__BapmVddNbVidLoSidd_3_MASK 0xff000000 +#define PM_FUSES_5__BapmVddNbVidLoSidd_3__SHIFT 0x18 +#define PM_FUSES_6__SviLoadLineTrimVddNb_MASK 0xff +#define PM_FUSES_6__SviLoadLineTrimVddNb__SHIFT 0x0 +#define PM_FUSES_6__SviLoadLineTrimVdd_MASK 0xff00 +#define PM_FUSES_6__SviLoadLineTrimVdd__SHIFT 0x8 +#define PM_FUSES_6__SviLoadLineVddNb_MASK 0xff0000 +#define PM_FUSES_6__SviLoadLineVddNb__SHIFT 0x10 +#define PM_FUSES_6__SviLoadLineVdd_MASK 0xff000000 +#define PM_FUSES_6__SviLoadLineVdd__SHIFT 0x18 +#define PM_FUSES_7__BAPMTI_TjOffset_0_MASK 0xffff +#define PM_FUSES_7__BAPMTI_TjOffset_0__SHIFT 0x0 +#define PM_FUSES_7__SviLoadLineOffsetVddNb_MASK 0xff0000 +#define PM_FUSES_7__SviLoadLineOffsetVddNb__SHIFT 0x10 +#define PM_FUSES_7__SviLoadLineOffsetVdd_MASK 0xff000000 +#define PM_FUSES_7__SviLoadLineOffsetVdd__SHIFT 0x18 +#define PM_FUSES_8__BAPMTI_TjOffset_2_MASK 0xffff +#define PM_FUSES_8__BAPMTI_TjOffset_2__SHIFT 0x0 +#define PM_FUSES_8__BAPMTI_TjOffset_1_MASK 0xffff0000 +#define PM_FUSES_8__BAPMTI_TjOffset_1__SHIFT 0x10 +#define PM_FUSES_9__BAPMTI_TjHyst_1_MASK 0xffff +#define PM_FUSES_9__BAPMTI_TjHyst_1__SHIFT 0x0 +#define PM_FUSES_9__BAPMTI_TjHyst_0_MASK 0xffff0000 +#define PM_FUSES_9__BAPMTI_TjHyst_0__SHIFT 0x10 +#define PM_FUSES_10__BAPMTI_TjMax_1_MASK 0xff +#define PM_FUSES_10__BAPMTI_TjMax_1__SHIFT 0x0 +#define PM_FUSES_10__BAPMTI_TjMax_0_MASK 0xff00 +#define PM_FUSES_10__BAPMTI_TjMax_0__SHIFT 0x8 +#define PM_FUSES_10__BAPMTI_GpuTjHyst_MASK 0xffff0000 +#define PM_FUSES_10__BAPMTI_GpuTjHyst__SHIFT 0x10 +#define PM_FUSES_11__LhtcTmpLmt_MASK 0xff +#define PM_FUSES_11__LhtcTmpLmt__SHIFT 0x0 +#define PM_FUSES_11__LhtcPstateLimit_MASK 0xff00 +#define PM_FUSES_11__LhtcPstateLimit__SHIFT 0x8 +#define PM_FUSES_11__LhtcHystLmt_MASK 0xff0000 +#define PM_FUSES_11__LhtcHystLmt__SHIFT 0x10 +#define PM_FUSES_11__BAPMTI_GpuTjMax_MASK 0xff000000 +#define PM_FUSES_11__BAPMTI_GpuTjMax__SHIFT 0x18 +#define PM_FUSES_12__MaxPwrCpu_1_MASK 0xff +#define PM_FUSES_12__MaxPwrCpu_1__SHIFT 0x0 +#define PM_FUSES_12__MaxPwrCpu_0_MASK 0xff00 +#define PM_FUSES_12__MaxPwrCpu_0__SHIFT 0x8 +#define PM_FUSES_12__NomPwrCpu_1_MASK 0xff0000 +#define PM_FUSES_12__NomPwrCpu_1__SHIFT 0x10 +#define PM_FUSES_12__NomPwrCpu_0_MASK 0xff000000 +#define PM_FUSES_12__NomPwrCpu_0__SHIFT 0x18 +#define PM_FUSES_13__NomPwrGpu_MASK 0xffff +#define PM_FUSES_13__NomPwrGpu__SHIFT 0x0 +#define PM_FUSES_13__MidPwrCpu_1_MASK 0xff0000 +#define PM_FUSES_13__MidPwrCpu_1__SHIFT 0x10 +#define PM_FUSES_13__MidPwrCpu_0_MASK 0xff000000 +#define PM_FUSES_13__MidPwrCpu_0__SHIFT 0x18 +#define PM_FUSES_14__MinPwrGpu_MASK 0xffff +#define PM_FUSES_14__MinPwrGpu__SHIFT 0x0 +#define PM_FUSES_14__MaxPwrGpu_MASK 0xffff0000 +#define PM_FUSES_14__MaxPwrGpu__SHIFT 0x10 +#define PM_FUSES_15__PCIe3PhyOffset_MASK 0xff +#define PM_FUSES_15__PCIe3PhyOffset__SHIFT 0x0 +#define PM_FUSES_15__PCIe2PhyOffset_MASK 0xff00 +#define PM_FUSES_15__PCIe2PhyOffset__SHIFT 0x8 +#define PM_FUSES_15__PCIe1PhyOffset_MASK 0xff0000 +#define PM_FUSES_15__PCIe1PhyOffset__SHIFT 0x10 +#define PM_FUSES_15__MidPwrTempHyst_MASK 0xff000000 +#define PM_FUSES_15__MidPwrTempHyst__SHIFT 0x18 +#define PM_FUSES_16__TDC_VDD_PkgLimit_MASK 0xffff +#define PM_FUSES_16__TDC_VDD_PkgLimit__SHIFT 0x0 +#define PM_FUSES_16__DCE2PhyOffset_MASK 0xff0000 +#define PM_FUSES_16__DCE2PhyOffset__SHIFT 0x10 +#define PM_FUSES_16__DCE1PhyOffset_MASK 0xff000000 +#define PM_FUSES_16__DCE1PhyOffset__SHIFT 0x18 +#define PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc_MASK 0xff +#define PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc__SHIFT 0x0 +#define PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc_MASK 0xff00 +#define PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc__SHIFT 0x8 +#define PM_FUSES_17__TDC_VDDNB_PkgLimit_MASK 0xffff0000 +#define PM_FUSES_17__TDC_VDDNB_PkgLimit__SHIFT 0x10 +#define PM_FUSES_18__TdcWaterfallCtl_MASK 0xff +#define PM_FUSES_18__TdcWaterfallCtl__SHIFT 0x0 +#define PM_FUSES_18__TdpAgeRate_MASK 0xff00 +#define PM_FUSES_18__TdpAgeRate__SHIFT 0x8 +#define PM_FUSES_18__TdpAgeValue_MASK 0xff0000 +#define PM_FUSES_18__TdpAgeValue__SHIFT 0x10 +#define PM_FUSES_18__TDC_MAWt_MASK 0xff000000 +#define PM_FUSES_18__TDC_MAWt__SHIFT 0x18 +#define PM_FUSES_19__BapmLhtcCap_MASK 0xff +#define PM_FUSES_19__BapmLhtcCap__SHIFT 0x0 +#define PM_FUSES_19__BapmFuseOverride_MASK 0xff00 +#define PM_FUSES_19__BapmFuseOverride__SHIFT 0x8 +#define PM_FUSES_19__SmuCoolingIndex_MASK 0xff0000 +#define PM_FUSES_19__SmuCoolingIndex__SHIFT 0x10 +#define PM_FUSES_19__SmuSocIndex_MASK 0xff000000 +#define PM_FUSES_19__SmuSocIndex__SHIFT 0x18 +#define PM_FUSES_20__SamClkDid_3_MASK 0xff +#define PM_FUSES_20__SamClkDid_3__SHIFT 0x0 +#define PM_FUSES_20__SamClkDid_2_MASK 0xff00 +#define PM_FUSES_20__SamClkDid_2__SHIFT 0x8 +#define PM_FUSES_20__SamClkDid_1_MASK 0xff0000 +#define PM_FUSES_20__SamClkDid_1__SHIFT 0x10 +#define PM_FUSES_20__SamClkDid_0_MASK 0xff000000 +#define PM_FUSES_20__SamClkDid_0__SHIFT 0x18 +#define PM_FUSES_21__AmbientTempBase_MASK 0xff +#define PM_FUSES_21__AmbientTempBase__SHIFT 0x0 +#define PM_FUSES_21__LPMLTemperatureMax_MASK 0xff00 +#define PM_FUSES_21__LPMLTemperatureMax__SHIFT 0x8 +#define PM_FUSES_21__LPMLTemperatureMin_MASK 0xff0000 +#define PM_FUSES_21__LPMLTemperatureMin__SHIFT 0x10 +#define PM_FUSES_21__SamClkDid_4_MASK 0xff000000 +#define PM_FUSES_21__SamClkDid_4__SHIFT 0x18 +#define PM_FUSES_22__LPMLTemperatureScaler_3_MASK 0xff +#define PM_FUSES_22__LPMLTemperatureScaler_3__SHIFT 0x0 +#define PM_FUSES_22__LPMLTemperatureScaler_2_MASK 0xff00 +#define PM_FUSES_22__LPMLTemperatureScaler_2__SHIFT 0x8 +#define PM_FUSES_22__LPMLTemperatureScaler_1_MASK 0xff0000 +#define PM_FUSES_22__LPMLTemperatureScaler_1__SHIFT 0x10 +#define PM_FUSES_22__LPMLTemperatureScaler_0_MASK 0xff000000 +#define PM_FUSES_22__LPMLTemperatureScaler_0__SHIFT 0x18 +#define PM_FUSES_23__LPMLTemperatureScaler_7_MASK 0xff +#define PM_FUSES_23__LPMLTemperatureScaler_7__SHIFT 0x0 +#define PM_FUSES_23__LPMLTemperatureScaler_6_MASK 0xff00 +#define PM_FUSES_23__LPMLTemperatureScaler_6__SHIFT 0x8 +#define PM_FUSES_23__LPMLTemperatureScaler_5_MASK 0xff0000 +#define PM_FUSES_23__LPMLTemperatureScaler_5__SHIFT 0x10 +#define PM_FUSES_23__LPMLTemperatureScaler_4_MASK 0xff000000 +#define PM_FUSES_23__LPMLTemperatureScaler_4__SHIFT 0x18 +#define PM_FUSES_24__LPMLTemperatureScaler_11_MASK 0xff +#define PM_FUSES_24__LPMLTemperatureScaler_11__SHIFT 0x0 +#define PM_FUSES_24__LPMLTemperatureScaler_10_MASK 0xff00 +#define PM_FUSES_24__LPMLTemperatureScaler_10__SHIFT 0x8 +#define PM_FUSES_24__LPMLTemperatureScaler_9_MASK 0xff0000 +#define PM_FUSES_24__LPMLTemperatureScaler_9__SHIFT 0x10 +#define PM_FUSES_24__LPMLTemperatureScaler_8_MASK 0xff000000 +#define PM_FUSES_24__LPMLTemperatureScaler_8__SHIFT 0x18 +#define PM_FUSES_25__LPMLTemperatureScaler_15_MASK 0xff +#define PM_FUSES_25__LPMLTemperatureScaler_15__SHIFT 0x0 +#define PM_FUSES_25__LPMLTemperatureScaler_14_MASK 0xff00 +#define PM_FUSES_25__LPMLTemperatureScaler_14__SHIFT 0x8 +#define PM_FUSES_25__LPMLTemperatureScaler_13_MASK 0xff0000 +#define PM_FUSES_25__LPMLTemperatureScaler_13__SHIFT 0x10 +#define PM_FUSES_25__LPMLTemperatureScaler_12_MASK 0xff000000 +#define PM_FUSES_25__LPMLTemperatureScaler_12__SHIFT 0x18 +#define PM_FUSES_26__GnbLPML_3_MASK 0xff +#define PM_FUSES_26__GnbLPML_3__SHIFT 0x0 +#define PM_FUSES_26__GnbLPML_2_MASK 0xff00 +#define PM_FUSES_26__GnbLPML_2__SHIFT 0x8 +#define PM_FUSES_26__GnbLPML_1_MASK 0xff0000 +#define PM_FUSES_26__GnbLPML_1__SHIFT 0x10 +#define PM_FUSES_26__GnbLPML_0_MASK 0xff000000 +#define PM_FUSES_26__GnbLPML_0__SHIFT 0x18 +#define PM_FUSES_27__GnbLPML_7_MASK 0xff +#define PM_FUSES_27__GnbLPML_7__SHIFT 0x0 +#define PM_FUSES_27__GnbLPML_6_MASK 0xff00 +#define PM_FUSES_27__GnbLPML_6__SHIFT 0x8 +#define PM_FUSES_27__GnbLPML_5_MASK 0xff0000 +#define PM_FUSES_27__GnbLPML_5__SHIFT 0x10 +#define PM_FUSES_27__GnbLPML_4_MASK 0xff000000 +#define PM_FUSES_27__GnbLPML_4__SHIFT 0x18 +#define PM_FUSES_28__GnbLPML_11_MASK 0xff +#define PM_FUSES_28__GnbLPML_11__SHIFT 0x0 +#define PM_FUSES_28__GnbLPML_10_MASK 0xff00 +#define PM_FUSES_28__GnbLPML_10__SHIFT 0x8 +#define PM_FUSES_28__GnbLPML_9_MASK 0xff0000 +#define PM_FUSES_28__GnbLPML_9__SHIFT 0x10 +#define PM_FUSES_28__GnbLPML_8_MASK 0xff000000 +#define PM_FUSES_28__GnbLPML_8__SHIFT 0x18 +#define PM_FUSES_29__GnbLPML_15_MASK 0xff +#define PM_FUSES_29__GnbLPML_15__SHIFT 0x0 +#define PM_FUSES_29__GnbLPML_14_MASK 0xff00 +#define PM_FUSES_29__GnbLPML_14__SHIFT 0x8 +#define PM_FUSES_29__GnbLPML_13_MASK 0xff0000 +#define PM_FUSES_29__GnbLPML_13__SHIFT 0x10 +#define PM_FUSES_29__GnbLPML_12_MASK 0xff000000 +#define PM_FUSES_29__GnbLPML_12__SHIFT 0x18 +#define PM_FUSES_30__NbVid_3_MASK 0xff +#define PM_FUSES_30__NbVid_3__SHIFT 0x0 +#define PM_FUSES_30__NbVid_2_MASK 0xff00 +#define PM_FUSES_30__NbVid_2__SHIFT 0x8 +#define PM_FUSES_30__NbVid_1_MASK 0xff0000 +#define PM_FUSES_30__NbVid_1__SHIFT 0x10 +#define PM_FUSES_30__NbVid_0_MASK 0xff000000 +#define PM_FUSES_30__NbVid_0__SHIFT 0x18 +#define PM_FUSES_31__CpuVid_3_MASK 0xff +#define PM_FUSES_31__CpuVid_3__SHIFT 0x0 +#define PM_FUSES_31__CpuVid_2_MASK 0xff00 +#define PM_FUSES_31__CpuVid_2__SHIFT 0x8 +#define PM_FUSES_31__CpuVid_1_MASK 0xff0000 +#define PM_FUSES_31__CpuVid_1__SHIFT 0x10 +#define PM_FUSES_31__CpuVid_0_MASK 0xff000000 +#define PM_FUSES_31__CpuVid_0__SHIFT 0x18 +#define PM_FUSES_32__CpuVid_7_MASK 0xff +#define PM_FUSES_32__CpuVid_7__SHIFT 0x0 +#define PM_FUSES_32__CpuVid_6_MASK 0xff00 +#define PM_FUSES_32__CpuVid_6__SHIFT 0x8 +#define PM_FUSES_32__CpuVid_5_MASK 0xff0000 +#define PM_FUSES_32__CpuVid_5__SHIFT 0x10 +#define PM_FUSES_32__CpuVid_4_MASK 0xff000000 +#define PM_FUSES_32__CpuVid_4__SHIFT 0x18 +#define PM_FUSES_33__Tdp2Watt_MASK 0xffff +#define PM_FUSES_33__Tdp2Watt__SHIFT 0x0 +#define PM_FUSES_33__GnbLPMLMinVid_MASK 0xff0000 +#define PM_FUSES_33__GnbLPMLMinVid__SHIFT 0x10 +#define PM_FUSES_33__GnbLPMLMaxVid_MASK 0xff000000 +#define PM_FUSES_33__GnbLPMLMaxVid__SHIFT 0x18 +#define PM_FUSES_34__Lpml_3_MASK 0xff +#define PM_FUSES_34__Lpml_3__SHIFT 0x0 +#define PM_FUSES_34__Lpml_2_MASK 0xff00 +#define PM_FUSES_34__Lpml_2__SHIFT 0x8 +#define PM_FUSES_34__Lpml_1_MASK 0xff0000 +#define PM_FUSES_34__Lpml_1__SHIFT 0x10 +#define PM_FUSES_34__Lpml_0_MASK 0xff000000 +#define PM_FUSES_34__Lpml_0__SHIFT 0x18 +#define PM_FUSES_35__Lpml_7_MASK 0xff +#define PM_FUSES_35__Lpml_7__SHIFT 0x0 +#define PM_FUSES_35__Lpml_6_MASK 0xff00 +#define PM_FUSES_35__Lpml_6__SHIFT 0x8 +#define PM_FUSES_35__Lpml_5_MASK 0xff0000 +#define PM_FUSES_35__Lpml_5__SHIFT 0x10 +#define PM_FUSES_35__Lpml_4_MASK 0xff000000 +#define PM_FUSES_35__Lpml_4__SHIFT 0x18 +#define PM_FUSES_36__Lpmv_3_MASK 0xff +#define PM_FUSES_36__Lpmv_3__SHIFT 0x0 +#define PM_FUSES_36__Lpmv_2_MASK 0xff00 +#define PM_FUSES_36__Lpmv_2__SHIFT 0x8 +#define PM_FUSES_36__Lpmv_1_MASK 0xff0000 +#define PM_FUSES_36__Lpmv_1__SHIFT 0x10 +#define PM_FUSES_36__Lpmv_0_MASK 0xff000000 +#define PM_FUSES_36__Lpmv_0__SHIFT 0x18 +#define PM_FUSES_37__Lpmv_7_MASK 0xff +#define PM_FUSES_37__Lpmv_7__SHIFT 0x0 +#define PM_FUSES_37__Lpmv_6_MASK 0xff00 +#define PM_FUSES_37__Lpmv_6__SHIFT 0x8 +#define PM_FUSES_37__Lpmv_5_MASK 0xff0000 +#define PM_FUSES_37__Lpmv_5__SHIFT 0x10 +#define PM_FUSES_37__Lpmv_4_MASK 0xff000000 +#define PM_FUSES_37__Lpmv_4__SHIFT 0x18 +#define PM_FUSES_38__EClkDid_3_MASK 0xff +#define PM_FUSES_38__EClkDid_3__SHIFT 0x0 +#define PM_FUSES_38__EClkDid_2_MASK 0xff00 +#define PM_FUSES_38__EClkDid_2__SHIFT 0x8 +#define PM_FUSES_38__EClkDid_1_MASK 0xff0000 +#define PM_FUSES_38__EClkDid_1__SHIFT 0x10 +#define PM_FUSES_38__EClkDid_0_MASK 0xff000000 +#define PM_FUSES_38__EClkDid_0__SHIFT 0x18 +#define PM_FUSES_39__CoreDis_MASK 0xff +#define PM_FUSES_39__CoreDis__SHIFT 0x0 +#define PM_FUSES_39__C6CstatePower_MASK 0xff00 +#define PM_FUSES_39__C6CstatePower__SHIFT 0x8 +#define PM_FUSES_39__BoostLock_MASK 0xff0000 +#define PM_FUSES_39__BoostLock__SHIFT 0x10 +#define PM_FUSES_39__EClkDid_4_MASK 0xff000000 +#define PM_FUSES_39__EClkDid_4__SHIFT 0x18 +#define PM_FUSES_40__BapmVddNbBaseLeakageLoSidd_MASK 0xffff +#define PM_FUSES_40__BapmVddNbBaseLeakageLoSidd__SHIFT 0x0 +#define PM_FUSES_40__BapmVddNbBaseLeakageHiSidd_MASK 0xffff0000 +#define PM_FUSES_40__BapmVddNbBaseLeakageHiSidd__SHIFT 0x10 +#define PM_FUSES_41__VddNbVid_3_MASK 0xff +#define PM_FUSES_41__VddNbVid_3__SHIFT 0x0 +#define PM_FUSES_41__VddNbVid_2_MASK 0xff00 +#define PM_FUSES_41__VddNbVid_2__SHIFT 0x8 +#define PM_FUSES_41__VddNbVid_1_MASK 0xff0000 +#define PM_FUSES_41__VddNbVid_1__SHIFT 0x10 +#define PM_FUSES_41__VddNbVid_0_MASK 0xff000000 +#define PM_FUSES_41__VddNbVid_0__SHIFT 0x18 +#define PM_FUSES_42__VddNbVidOffset_2_MASK 0xff +#define PM_FUSES_42__VddNbVidOffset_2__SHIFT 0x0 +#define PM_FUSES_42__VddNbVidOffset_1_MASK 0xff00 +#define PM_FUSES_42__VddNbVidOffset_1__SHIFT 0x8 +#define PM_FUSES_42__VddNbVidOffset_0_MASK 0xff0000 +#define PM_FUSES_42__VddNbVidOffset_0__SHIFT 0x10 +#define PM_FUSES_42__VddNbVid_4_MASK 0xff000000 +#define PM_FUSES_42__VddNbVid_4__SHIFT 0x18 +#define PM_FUSES_43__BapmDisable_MASK 0xff +#define PM_FUSES_43__BapmDisable__SHIFT 0x0 +#define PM_FUSES_43__CoreTdpLimit0_MASK 0xff00 +#define PM_FUSES_43__CoreTdpLimit0__SHIFT 0x8 +#define PM_FUSES_43__VddNbVidOffset_4_MASK 0xff0000 +#define PM_FUSES_43__VddNbVidOffset_4__SHIFT 0x10 +#define PM_FUSES_43__VddNbVidOffset_3_MASK 0xff000000 +#define PM_FUSES_43__VddNbVidOffset_3__SHIFT 0x18 +#define PM_FUSES_44__LpmlL2_3_MASK 0xff +#define PM_FUSES_44__LpmlL2_3__SHIFT 0x0 +#define PM_FUSES_44__LpmlL2_2_MASK 0xff00 +#define PM_FUSES_44__LpmlL2_2__SHIFT 0x8 +#define PM_FUSES_44__LpmlL2_1_MASK 0xff0000 +#define PM_FUSES_44__LpmlL2_1__SHIFT 0x10 +#define PM_FUSES_44__LpmlL2_0_MASK 0xff000000 +#define PM_FUSES_44__LpmlL2_0__SHIFT 0x18 +#define PM_FUSES_45__LpmlL2_7_MASK 0xff +#define PM_FUSES_45__LpmlL2_7__SHIFT 0x0 +#define PM_FUSES_45__LpmlL2_6_MASK 0xff00 +#define PM_FUSES_45__LpmlL2_6__SHIFT 0x8 +#define PM_FUSES_45__LpmlL2_5_MASK 0xff0000 +#define PM_FUSES_45__LpmlL2_5__SHIFT 0x10 +#define PM_FUSES_45__LpmlL2_4_MASK 0xff000000 +#define PM_FUSES_45__LpmlL2_4__SHIFT 0x18 +#define PM_FUSES_46__CoolPdmTc_MASK 0xff +#define PM_FUSES_46__CoolPdmTc__SHIFT 0x0 +#define PM_FUSES_46__BaseCpcTdpLimit2_MASK 0xff00 +#define PM_FUSES_46__BaseCpcTdpLimit2__SHIFT 0x8 +#define PM_FUSES_46__BaseCpcTdpLimit1_MASK 0xff0000 +#define PM_FUSES_46__BaseCpcTdpLimit1__SHIFT 0x10 +#define PM_FUSES_46__BaseCpcTdpLimit_MASK 0xff000000 +#define PM_FUSES_46__BaseCpcTdpLimit__SHIFT 0x18 +#define PM_FUSES_47__CoolPdmThr2_MASK 0xff +#define PM_FUSES_47__CoolPdmThr2__SHIFT 0x0 +#define PM_FUSES_47__CoolPdmThr1_MASK 0xff00 +#define PM_FUSES_47__CoolPdmThr1__SHIFT 0x8 +#define PM_FUSES_47__GpuPdmTc_MASK 0xff0000 +#define PM_FUSES_47__GpuPdmTc__SHIFT 0x10 +#define PM_FUSES_47__HeatPdmTc_MASK 0xff000000 +#define PM_FUSES_47__HeatPdmTc__SHIFT 0x18 +#define PM_FUSES_48__PkgPwr_MAWt_MASK 0xff +#define PM_FUSES_48__PkgPwr_MAWt__SHIFT 0x0 +#define PM_FUSES_48__GpuActThr_MASK 0xff00 +#define PM_FUSES_48__GpuActThr__SHIFT 0x8 +#define PM_FUSES_48__HeatPdmThr2_MASK 0xff0000 +#define PM_FUSES_48__HeatPdmThr2__SHIFT 0x10 +#define PM_FUSES_48__HeatPdmThr1_MASK 0xff000000 +#define PM_FUSES_48__HeatPdmThr1__SHIFT 0x18 +#define PM_FUSES_49__SocketTdp_MASK 0xffff +#define PM_FUSES_49__SocketTdp__SHIFT 0x0 +#define PM_FUSES_49__GpuPdmMult_MASK 0xffff0000 +#define PM_FUSES_49__GpuPdmMult__SHIFT 0x10 +#define PM_FUSES_50__Reserved2_MASK 0xffff +#define PM_FUSES_50__Reserved2__SHIFT 0x0 +#define PM_FUSES_50__Reserved1_MASK 0xff0000 +#define PM_FUSES_50__Reserved1__SHIFT 0x10 +#define PM_FUSES_50__NumBoostStates_MASK 0xff000000 +#define PM_FUSES_50__NumBoostStates__SHIFT 0x18 +#define PM_FUSES_51__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_51__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_52__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_52__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_53__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_53__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_54__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_54__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_55__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_55__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_56__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_56__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_57__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_57__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_58__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_58__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_59__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_59__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_60__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_60__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_61__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_61__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_62__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_62__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_63__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_63__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_64__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_64__FUSE_DATA__SHIFT 0x0 +#define PM_FUSES_65__FUSE_DATA_MASK 0xffffffff +#define PM_FUSES_65__FUSE_DATA__SHIFT 0x0 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe +#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 +#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 +#define TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f +#define TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0 +#define TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0 +#define TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6 +#define TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00 +#define TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa +#define CURRENT_GNB_TEMP__TEMP_MASK 0x7ff +#define CURRENT_GNB_TEMP__TEMP__SHIFT 0x0 +#define CURRENT_GLOBAL_TEMP__TEMP_MASK 0x7ff +#define CURRENT_GLOBAL_TEMP__TEMP__SHIFT 0x0 +#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 +#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 +#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 +#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 +#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 +#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 +#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 +#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 +#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 +#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 +#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20 +#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5 +#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40 +#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6 +#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 +#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 +#define FEATURE_STATUS__BAPM_ON_MASK 0x100 +#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 +#define FEATURE_STATUS__LPMX_ON_MASK 0x200 +#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 +#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 +#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa +#define FEATURE_STATUS__LHTC_ON_MASK 0x800 +#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb +#define FEATURE_STATUS__VPC_ON_MASK 0x1000 +#define FEATURE_STATUS__VPC_ON__SHIFT 0xc +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd +#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 +#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe +#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 +#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf +#define FEATURE_STATUS__AVS_ON_MASK 0x10000 +#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 +#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 +#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 +#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 +#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 +#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 +#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 +#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 +#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 +#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 +#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 +#define FEATURE_STATUS__CLK_MON_ON_MASK 0x400000 +#define FEATURE_STATUS__CLK_MON_ON__SHIFT 0x16 +#define FEATURE_STATUS__RESERVED_MASK 0xff800000 +#define FEATURE_STATUS__RESERVED__SHIFT 0x17 +#define PCIE_PLL_RECONF__RECONF_WAIT_MASK 0xff +#define PCIE_PLL_RECONF__RECONF_WAIT__SHIFT 0x0 +#define PCIE_PLL_RECONF__RECONF_WRAPPER_MASK 0xff00 +#define PCIE_PLL_RECONF__RECONF_WRAPPER__SHIFT 0x8 +#define PCIE_PLL_RECONF__SB_RELOCATE_EN_MASK 0xff0000 +#define PCIE_PLL_RECONF__SB_RELOCATE_EN__SHIFT 0x10 +#define PCIE_PLL_RECONF__SB_NEW_PORT_MASK 0xff000000 +#define PCIE_PLL_RECONF__SB_NEW_PORT__SHIFT 0x18 +#define PM_INTERVAL_CNTL_0__LCLK_DPM_MASK 0xff +#define PM_INTERVAL_CNTL_0__LCLK_DPM__SHIFT 0x0 +#define PM_INTERVAL_CNTL_0__THERMAL_CNTL_MASK 0xff00 +#define PM_INTERVAL_CNTL_0__THERMAL_CNTL__SHIFT 0x8 +#define PM_INTERVAL_CNTL_0__VOLTAGE_CNTL_MASK 0xff0000 +#define PM_INTERVAL_CNTL_0__VOLTAGE_CNTL__SHIFT 0x10 +#define PM_INTERVAL_CNTL_0__LOADLINE_MASK 0xff000000 +#define PM_INTERVAL_CNTL_0__LOADLINE__SHIFT 0x18 +#define PM_INTERVAL_CNTL_1__NB_DPM_MASK 0xff +#define PM_INTERVAL_CNTL_1__NB_DPM__SHIFT 0x0 +#define PM_INTERVAL_CNTL_1__AVS_PERIOD_MASK 0xff00 +#define PM_INTERVAL_CNTL_1__AVS_PERIOD__SHIFT 0x8 +#define PM_INTERVAL_CNTL_1__PKGPWR_PERIOD_MASK 0xff0000 +#define PM_INTERVAL_CNTL_1__PKGPWR_PERIOD__SHIFT 0x10 +#define PM_INTERVAL_CNTL_1__TDP_CNTL_MASK 0xff000000 +#define PM_INTERVAL_CNTL_1__TDP_CNTL__SHIFT 0x18 +#define PM_INTERVAL_CNTL_2__BAPM_PERIOD_MASK 0xff +#define PM_INTERVAL_CNTL_2__BAPM_PERIOD__SHIFT 0x0 +#define PM_INTERVAL_CNTL_2__HTC_PERIOD_MASK 0xff00 +#define PM_INTERVAL_CNTL_2__HTC_PERIOD__SHIFT 0x8 +#define PM_INTERVAL_CNTL_2__TDC_PERIOD_MASK 0xff0000 +#define PM_INTERVAL_CNTL_2__TDC_PERIOD__SHIFT 0x10 +#define PM_INTERVAL_CNTL_2__LPMX_PERIOD_MASK 0xff000000 +#define PM_INTERVAL_CNTL_2__LPMX_PERIOD__SHIFT 0x18 +#define VPC_INTERVAL_CNTL__VPC_PERIOD_MASK 0xffffffff +#define VPC_INTERVAL_CNTL__VPC_PERIOD__SHIFT 0x0 +#define DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit_MASK 0xffffffff +#define DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit__SHIFT 0x0 +#define FCH_PWR_CREDIT__FchPwrCredit_MASK 0xffffffff +#define FCH_PWR_CREDIT__FchPwrCredit__SHIFT 0x0 +#define PKGPWR_MV_AVG__Avg_Pkg_Pwr_MASK 0xffffffff +#define PKGPWR_MV_AVG__Avg_Pkg_Pwr__SHIFT 0x0 +#define PACKAGE_POWER__Pkg_power_MASK 0xffffffff +#define PACKAGE_POWER__Pkg_power__SHIFT 0x0 +#define PKG_PWR_CNTL__CpcGpuPerfPri_MASK 0x1 +#define PKG_PWR_CNTL__CpcGpuPerfPri__SHIFT 0x0 +#define PKG_PWR_CNTL__PkgPwrLimit_MASK 0x1fffe +#define PKG_PWR_CNTL__PkgPwrLimit__SHIFT 0x1 +#define PKG_PWR_CNTL__FchPwrCreditScale_MASK 0x7e0000 +#define PKG_PWR_CNTL__FchPwrCreditScale__SHIFT 0x11 +#define PKG_PWR_CNTL__PkgHystCoeff_MASK 0x1f800000 +#define PKG_PWR_CNTL__PkgHystCoeff__SHIFT 0x17 +#define PKG_PWR_CNTL__RESERVED_MASK 0xe0000000 +#define PKG_PWR_CNTL__RESERVED__SHIFT 0x1d +#define PKG_PWR_STATUS__GnbMinLimitSetFlag_MASK 0x1 +#define PKG_PWR_STATUS__GnbMinLimitSetFlag__SHIFT 0x0 +#define PKG_PWR_STATUS__PstateLimitSetFlag_MASK 0x2 +#define PKG_PWR_STATUS__PstateLimitSetFlag__SHIFT 0x1 +#define PKG_PWR_STATUS__PkgPwrLimit_base_MASK 0x3fffc +#define PKG_PWR_STATUS__PkgPwrLimit_base__SHIFT 0x2 +#define PKG_PWR_STATUS__RESERVED_MASK 0xfc0000 +#define PKG_PWR_STATUS__RESERVED__SHIFT 0x12 +#define PKG_PWR_STATUS__PkgPwr_MAWt_MASK 0xff000000 +#define PKG_PWR_STATUS__PkgPwr_MAWt__SHIFT 0x18 +#define DISP_PHY_CONFIG__Corner_MASK 0xff +#define DISP_PHY_CONFIG__Corner__SHIFT 0x0 +#define DISP_PHY_CONFIG__DispPHYConfig_MASK 0xff00 +#define DISP_PHY_CONFIG__DispPHYConfig__SHIFT 0x8 +#define GPU_TDP_LIMIT__Gpu_Tdp_Limit_MASK 0xffff +#define GPU_TDP_LIMIT__Gpu_Tdp_Limit__SHIFT 0x0 +#define GPU_TDP_LIMIT__Reserved_MASK 0xffff0000 +#define GPU_TDP_LIMIT__Reserved__SHIFT 0x10 +#define EXT_API_IN_DATA_0_0__byte0_MASK 0xff +#define EXT_API_IN_DATA_0_0__byte0__SHIFT 0x0 +#define EXT_API_IN_DATA_0_0__byte1_MASK 0xff00 +#define EXT_API_IN_DATA_0_0__byte1__SHIFT 0x8 +#define EXT_API_IN_DATA_0_0__byte2_MASK 0xff0000 +#define EXT_API_IN_DATA_0_0__byte2__SHIFT 0x10 +#define EXT_API_IN_DATA_0_0__byte3_MASK 0xff000000 +#define EXT_API_IN_DATA_0_0__byte3__SHIFT 0x18 +#define EXT_API_IN_DATA_0_1__byte0_MASK 0xff +#define EXT_API_IN_DATA_0_1__byte0__SHIFT 0x0 +#define EXT_API_IN_DATA_0_1__byte1_MASK 0xff00 +#define EXT_API_IN_DATA_0_1__byte1__SHIFT 0x8 +#define EXT_API_IN_DATA_0_1__byte2_MASK 0xff0000 +#define EXT_API_IN_DATA_0_1__byte2__SHIFT 0x10 +#define EXT_API_IN_DATA_0_1__byte3_MASK 0xff000000 +#define EXT_API_IN_DATA_0_1__byte3__SHIFT 0x18 +#define EXT_API_IN_DATA_0_2__byte0_MASK 0xff +#define EXT_API_IN_DATA_0_2__byte0__SHIFT 0x0 +#define EXT_API_IN_DATA_0_2__byte1_MASK 0xff00 +#define EXT_API_IN_DATA_0_2__byte1__SHIFT 0x8 +#define EXT_API_IN_DATA_0_2__byte2_MASK 0xff0000 +#define EXT_API_IN_DATA_0_2__byte2__SHIFT 0x10 +#define EXT_API_IN_DATA_0_2__byte3_MASK 0xff000000 +#define EXT_API_IN_DATA_0_2__byte3__SHIFT 0x18 +#define EXT_API_IN_DATA_0_3__byte0_MASK 0xff +#define EXT_API_IN_DATA_0_3__byte0__SHIFT 0x0 +#define EXT_API_IN_DATA_0_3__byte1_MASK 0xff00 +#define EXT_API_IN_DATA_0_3__byte1__SHIFT 0x8 +#define EXT_API_IN_DATA_0_3__byte2_MASK 0xff0000 +#define EXT_API_IN_DATA_0_3__byte2__SHIFT 0x10 +#define EXT_API_IN_DATA_0_3__byte3_MASK 0xff000000 +#define EXT_API_IN_DATA_0_3__byte3__SHIFT 0x18 +#define EXT_API_OUT_DATA_0_0__byte0_MASK 0xff +#define EXT_API_OUT_DATA_0_0__byte0__SHIFT 0x0 +#define EXT_API_OUT_DATA_0_0__byte1_MASK 0xff00 +#define EXT_API_OUT_DATA_0_0__byte1__SHIFT 0x8 +#define EXT_API_OUT_DATA_0_0__byte2_MASK 0xff0000 +#define EXT_API_OUT_DATA_0_0__byte2__SHIFT 0x10 +#define EXT_API_OUT_DATA_0_0__byte3_MASK 0xff000000 +#define EXT_API_OUT_DATA_0_0__byte3__SHIFT 0x18 +#define EXT_API_OUT_DATA_0_1__byte0_MASK 0xff +#define EXT_API_OUT_DATA_0_1__byte0__SHIFT 0x0 +#define EXT_API_OUT_DATA_0_1__byte1_MASK 0xff00 +#define EXT_API_OUT_DATA_0_1__byte1__SHIFT 0x8 +#define EXT_API_OUT_DATA_0_1__byte2_MASK 0xff0000 +#define EXT_API_OUT_DATA_0_1__byte2__SHIFT 0x10 +#define EXT_API_OUT_DATA_0_1__byte3_MASK 0xff000000 +#define EXT_API_OUT_DATA_0_1__byte3__SHIFT 0x18 +#define EXT_API_OUT_DATA_0_2__byte0_MASK 0xff +#define EXT_API_OUT_DATA_0_2__byte0__SHIFT 0x0 +#define EXT_API_OUT_DATA_0_2__byte1_MASK 0xff00 +#define EXT_API_OUT_DATA_0_2__byte1__SHIFT 0x8 +#define EXT_API_OUT_DATA_0_2__byte2_MASK 0xff0000 +#define EXT_API_OUT_DATA_0_2__byte2__SHIFT 0x10 +#define EXT_API_OUT_DATA_0_2__byte3_MASK 0xff000000 +#define EXT_API_OUT_DATA_0_2__byte3__SHIFT 0x18 +#define EXT_API_OUT_DATA_0_3__byte0_MASK 0xff +#define EXT_API_OUT_DATA_0_3__byte0__SHIFT 0x0 +#define EXT_API_OUT_DATA_0_3__byte1_MASK 0xff00 +#define EXT_API_OUT_DATA_0_3__byte1__SHIFT 0x8 +#define EXT_API_OUT_DATA_0_3__byte2_MASK 0xff0000 +#define EXT_API_OUT_DATA_0_3__byte2__SHIFT 0x10 +#define EXT_API_OUT_DATA_0_3__byte3_MASK 0xff000000 +#define EXT_API_OUT_DATA_0_3__byte3__SHIFT 0x18 +#define BAPM_PARAMETERS__MaxPwrCpu_1_MASK 0xff +#define BAPM_PARAMETERS__MaxPwrCpu_1__SHIFT 0x0 +#define BAPM_PARAMETERS__NomPwrCpu_1_MASK 0xff00 +#define BAPM_PARAMETERS__NomPwrCpu_1__SHIFT 0x8 +#define BAPM_PARAMETERS__MaxPwrCpu_0_MASK 0xff0000 +#define BAPM_PARAMETERS__MaxPwrCpu_0__SHIFT 0x10 +#define BAPM_PARAMETERS__NomPwrCpu_0_MASK 0xff000000 +#define BAPM_PARAMETERS__NomPwrCpu_0__SHIFT 0x18 +#define BAPM_PARAMETERS_2__MaxPwrGpu_MASK 0xffff +#define BAPM_PARAMETERS_2__MaxPwrGpu__SHIFT 0x0 +#define BAPM_PARAMETERS_2__NomPwrGpu_MASK 0xffff0000 +#define BAPM_PARAMETERS_2__NomPwrGpu__SHIFT 0x10 +#define BAPM_PARAMETERS_3__TjOffset_MASK 0xff +#define BAPM_PARAMETERS_3__TjOffset__SHIFT 0x0 +#define BAPM_PARAMETERS_3__EnergyCntNorm_MASK 0x3ff00 +#define BAPM_PARAMETERS_3__EnergyCntNorm__SHIFT 0x8 +#define BAPM_PARAMETERS_3__Reserved_MASK 0xfffc0000 +#define BAPM_PARAMETERS_3__Reserved__SHIFT 0x12 +#define BAPM_PARAMETERS_4__MinPwrGpu_MASK 0xffff +#define BAPM_PARAMETERS_4__MinPwrGpu__SHIFT 0x0 +#define BAPM_PARAMETERS_4__MidPwrCpu_1_MASK 0xff0000 +#define BAPM_PARAMETERS_4__MidPwrCpu_1__SHIFT 0x10 +#define BAPM_PARAMETERS_4__MidPwrCpu_0_MASK 0xff000000 +#define BAPM_PARAMETERS_4__MidPwrCpu_0__SHIFT 0x18 +#define SMU_SVI_TELEMETRY__Iddspike_OCP_MASK 0xffff +#define SMU_SVI_TELEMETRY__Iddspike_OCP__SHIFT 0x0 +#define SMU_SVI_TELEMETRY__IddNbspike_OCP_MASK 0xffff0000 +#define SMU_SVI_TELEMETRY__IddNbspike_OCP__SHIFT 0x10 +#define BAPM_STATUS__THROTTLE_MASK 0xff +#define BAPM_STATUS__THROTTLE__SHIFT 0x0 +#define BAPM_STATUS__THROTTLE_LAST_MASK 0xff00 +#define BAPM_STATUS__THROTTLE_LAST__SHIFT 0x8 +#define BAPM_STATUS__COUNT_CORE1_MASK 0xff0000 +#define BAPM_STATUS__COUNT_CORE1__SHIFT 0x10 +#define BAPM_STATUS__COUNT_CORE0_MASK 0xff000000 +#define BAPM_STATUS__COUNT_CORE0__SHIFT 0x18 +#define SMU_HTC_STATUS__HTC_ACTIVE_MASK 0x1 +#define SMU_HTC_STATUS__HTC_ACTIVE__SHIFT 0x0 +#define SMU_HTC_STATUS__Reserved_MASK 0xfffffffe +#define SMU_HTC_STATUS__Reserved__SHIFT 0x1 +#define SMU_VPC_STATUS__AllCpuIdleLast_MASK 0x1 +#define SMU_VPC_STATUS__AllCpuIdleLast__SHIFT 0x0 +#define SMU_VPC_STATUS__Reserved_MASK 0xfffffffe +#define SMU_VPC_STATUS__Reserved__SHIFT 0x1 +#define ENTITY_TEMPERATURES_1__CORE0_MASK 0xffffffff +#define ENTITY_TEMPERATURES_1__CORE0__SHIFT 0x0 +#define ENTITY_TEMPERATURES_2__CORE1_MASK 0xffffffff +#define ENTITY_TEMPERATURES_2__CORE1__SHIFT 0x0 +#define ENTITY_TEMPERATURES_3__GPU_MASK 0xffffffff +#define ENTITY_TEMPERATURES_3__GPU__SHIFT 0x0 +#define CU_POWER__CU0_POWER_MASK 0xffff +#define CU_POWER__CU0_POWER__SHIFT 0x0 +#define CU_POWER__CU1_POWER_MASK 0xffff0000 +#define CU_POWER__CU1_POWER__SHIFT 0x10 +#define GPU_POWER__IGPU_POWER_MASK 0xffff +#define GPU_POWER__IGPU_POWER__SHIFT 0x0 +#define GPU_POWER__DGPU_POWER_MASK 0xffff0000 +#define GPU_POWER__DGPU_POWER__SHIFT 0x10 +#define NTE_POWER__NTE0_POWER_MASK 0xffff +#define NTE_POWER__NTE0_POWER__SHIFT 0x0 +#define NTE_POWER__NTE1_POWER_MASK 0xffff0000 +#define NTE_POWER__NTE1_POWER__SHIFT 0x10 +#define TDC_STATUS__VDD_Boost_MASK 0xff +#define TDC_STATUS__VDD_Boost__SHIFT 0x0 +#define TDC_STATUS__VDD_Throttle_MASK 0xff00 +#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 +#define TDC_STATUS__VDDNB_Boost_MASK 0xff0000 +#define TDC_STATUS__VDDNB_Boost__SHIFT 0x10 +#define TDC_STATUS__VDDNB_Throttle_MASK 0xff000000 +#define TDC_STATUS__VDDNB_Throttle__SHIFT 0x18 +#define TDC_MV_AVERAGE__IDD_MASK 0xffff +#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 +#define TDC_MV_AVERAGE__IDDNB_MASK 0xffff0000 +#define TDC_MV_AVERAGE__IDDNB__SHIFT 0x10 +#define PM_CONFIG__Enable_VPC_Accumulators_MASK 0x1 +#define PM_CONFIG__Enable_VPC_Accumulators__SHIFT 0x0 +#define PM_CONFIG__Enable_BAPM_MASK 0x2 +#define PM_CONFIG__Enable_BAPM__SHIFT 0x1 +#define PM_CONFIG__Enable_TDC_Limit_MASK 0x4 +#define PM_CONFIG__Enable_TDC_Limit__SHIFT 0x2 +#define PM_CONFIG__Enable_LPMx_MASK 0x8 +#define PM_CONFIG__Enable_LPMx__SHIFT 0x3 +#define PM_CONFIG__Enable_HTC_Limit_MASK 0x10 +#define PM_CONFIG__Enable_HTC_Limit__SHIFT 0x4 +#define PM_CONFIG__Enable_NBDPM_MASK 0x20 +#define PM_CONFIG__Enable_NBDPM__SHIFT 0x5 +#define PM_CONFIG__Enable_LoadLine_MASK 0x40 +#define PM_CONFIG__Enable_LoadLine__SHIFT 0x6 +#define PM_CONFIG__Reserved_MASK 0xff80 +#define PM_CONFIG__Reserved__SHIFT 0x7 +#define PM_CONFIG__Override_VPC_Current_MASK 0x10000 +#define PM_CONFIG__Override_VPC_Current__SHIFT 0x10 +#define PM_CONFIG__Reserved1_MASK 0x60000 +#define PM_CONFIG__Reserved1__SHIFT 0x11 +#define PM_CONFIG__Override_Calc_Temp_MASK 0x80000 +#define PM_CONFIG__Override_Calc_Temp__SHIFT 0x13 +#define PM_CONFIG__Enable_Hybrid_Boost_MASK 0x100000 +#define PM_CONFIG__Enable_Hybrid_Boost__SHIFT 0x14 +#define PM_CONFIG__Reserved2_MASK 0xe00000 +#define PM_CONFIG__Reserved2__SHIFT 0x15 +#define PM_CONFIG__PSTATE_AllCpusIdle_MASK 0x7000000 +#define PM_CONFIG__PSTATE_AllCpusIdle__SHIFT 0x18 +#define PM_CONFIG__NBPSTATE_AllCpusIdle_MASK 0x8000000 +#define PM_CONFIG__NBPSTATE_AllCpusIdle__SHIFT 0x1b +#define PM_CONFIG__Reserved3_MASK 0x10000000 +#define PM_CONFIG__Reserved3__SHIFT 0x1c +#define PM_CONFIG__SVI_Mode_MASK 0x20000000 +#define PM_CONFIG__SVI_Mode__SHIFT 0x1d +#define PM_CONFIG__Enable_PDM_MASK 0x40000000 +#define PM_CONFIG__Enable_PDM__SHIFT 0x1e +#define PM_CONFIG__Enable_PKG_PWR_LIMIT_MASK 0x80000000 +#define PM_CONFIG__Enable_PKG_PWR_LIMIT__SHIFT 0x1f +#define TE0_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f +#define TE0_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0 +#define TE0_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0 +#define TE0_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6 +#define TE0_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00 +#define TE0_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa +#define TE1_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f +#define TE1_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0 +#define TE1_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0 +#define TE1_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6 +#define TE1_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00 +#define TE1_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa +#define TE2_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f +#define TE2_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0 +#define TE2_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0 +#define TE2_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6 +#define TE2_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00 +#define TE2_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa +#define NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK 0xff +#define NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT 0x0 +#define NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK 0xff00 +#define NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT 0x8 +#define NB_DPM_CONFIG_1__DpmXNbPsLo_MASK 0xff0000 +#define NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT 0x10 +#define NB_DPM_CONFIG_1__DpmXNbPsHi_MASK 0xff000000 +#define NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT 0x18 +#define NB_DPM_CONFIG_2__Hysteresis_MASK 0xff +#define NB_DPM_CONFIG_2__Hysteresis__SHIFT 0x0 +#define NB_DPM_CONFIG_2__SkipPG_MASK 0xff00 +#define NB_DPM_CONFIG_2__SkipPG__SHIFT 0x8 +#define NB_DPM_CONFIG_2__SkipDPM0_MASK 0xff0000 +#define NB_DPM_CONFIG_2__SkipDPM0__SHIFT 0x10 +#define NB_DPM_CONFIG_2__EnablePSI1_MASK 0xff000000 +#define NB_DPM_CONFIG_2__EnablePSI1__SHIFT 0x18 +#define NB_DPM_CONFIG_3__RESERVED_MASK 0xffffff +#define NB_DPM_CONFIG_3__RESERVED__SHIFT 0x0 +#define NB_DPM_CONFIG_3__EnableDpmPstatePoll_MASK 0xff000000 +#define NB_DPM_CONFIG_3__EnableDpmPstatePoll__SHIFT 0x18 +#define SMU_IDD_OVERRIDE__IDD_MASK 0xffff +#define SMU_IDD_OVERRIDE__IDD__SHIFT 0x0 +#define SMU_IDD_OVERRIDE__IDDNB_MASK 0xffff0000 +#define SMU_IDD_OVERRIDE__IDDNB__SHIFT 0x10 +#define AVS_CONFIG__AvsEnabledForPstates_MASK 0xff +#define AVS_CONFIG__AvsEnabledForPstates__SHIFT 0x0 +#define AVS_CONFIG__AvsOverrideEnabled_MASK 0x100 +#define AVS_CONFIG__AvsOverrideEnabled__SHIFT 0x8 +#define AVS_CONFIG__AvsPsmTempCompensation_MASK 0x200 +#define AVS_CONFIG__AvsPsmTempCompensation__SHIFT 0x9 +#define AVS_CONFIG__RESERVED1_MASK 0xfc00 +#define AVS_CONFIG__RESERVED1__SHIFT 0xa +#define AVS_CONFIG__AvsOverrideOffset_MASK 0xff0000 +#define AVS_CONFIG__AvsOverrideOffset__SHIFT 0x10 +#define AVS_CONFIG__RESERVED_MASK 0xff000000 +#define AVS_CONFIG__RESERVED__SHIFT 0x18 +#define TDC_VRM_LIMIT__IDD_MASK 0xffff +#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 +#define TDC_VRM_LIMIT__IDDNB_MASK 0xffff0000 +#define TDC_VRM_LIMIT__IDDNB__SHIFT 0x10 +#define CU0_PSM_CONFIG__Psm4_MASK 0xff +#define CU0_PSM_CONFIG__Psm4__SHIFT 0x0 +#define CU0_PSM_CONFIG__Psm3_MASK 0xff00 +#define CU0_PSM_CONFIG__Psm3__SHIFT 0x8 +#define CU0_PSM_CONFIG__Psm2_MASK 0xff0000 +#define CU0_PSM_CONFIG__Psm2__SHIFT 0x10 +#define CU0_PSM_CONFIG__Psm1_MASK 0xff000000 +#define CU0_PSM_CONFIG__Psm1__SHIFT 0x18 +#define CU1_PSM_CONFIG__Psm4_MASK 0xff +#define CU1_PSM_CONFIG__Psm4__SHIFT 0x0 +#define CU1_PSM_CONFIG__Psm3_MASK 0xff00 +#define CU1_PSM_CONFIG__Psm3__SHIFT 0x8 +#define CU1_PSM_CONFIG__Psm2_MASK 0xff0000 +#define CU1_PSM_CONFIG__Psm2__SHIFT 0x10 +#define CU1_PSM_CONFIG__Psm1_MASK 0xff000000 +#define CU1_PSM_CONFIG__Psm1__SHIFT 0x18 +#define SPMI_CONFIG__SpmiTestCode_MASK 0xff +#define SPMI_CONFIG__SpmiTestCode__SHIFT 0x0 +#define SPMI_CONFIG__SpmiTestData_MASK 0xff00 +#define SPMI_CONFIG__SpmiTestData__SHIFT 0x8 +#define SPMI_CONFIG__RESERVED_MASK 0xffff0000 +#define SPMI_CONFIG__RESERVED__SHIFT 0x10 +#define SPMI_SMC_CHAIN_ADDR__Addr_MASK 0xffffffff +#define SPMI_SMC_CHAIN_ADDR__Addr__SHIFT 0x0 +#define SPMI_STATUS__OpDone_MASK 0xff +#define SPMI_STATUS__OpDone__SHIFT 0x0 +#define SPMI_STATUS__OpFailed_MASK 0xff00 +#define SPMI_STATUS__OpFailed__SHIFT 0x8 +#define AVSNB_CONFIG__AvsEnabledForPstates_MASK 0xf +#define AVSNB_CONFIG__AvsEnabledForPstates__SHIFT 0x0 +#define AVSNB_CONFIG__RESERVED0_MASK 0xf0 +#define AVSNB_CONFIG__RESERVED0__SHIFT 0x4 +#define AVSNB_CONFIG__AvsOverrideEnabled_MASK 0x100 +#define AVSNB_CONFIG__AvsOverrideEnabled__SHIFT 0x8 +#define AVSNB_CONFIG__AvsPsmTempCompensation_MASK 0x200 +#define AVSNB_CONFIG__AvsPsmTempCompensation__SHIFT 0x9 +#define AVSNB_CONFIG__RESERVED1_MASK 0xfc00 +#define AVSNB_CONFIG__RESERVED1__SHIFT 0xa +#define AVSNB_CONFIG__AvsOverrideOffset_MASK 0xff0000 +#define AVSNB_CONFIG__AvsOverrideOffset__SHIFT 0x10 +#define AVSNB_CONFIG__RESERVED_MASK 0xff000000 +#define AVSNB_CONFIG__RESERVED__SHIFT 0x18 +#define HTC_CONFIG__CSR_ADDR_MASK 0x3f +#define HTC_CONFIG__CSR_ADDR__SHIFT 0x0 +#define HTC_CONFIG__TCEN_ID_MASK 0x3c0 +#define HTC_CONFIG__TCEN_ID__SHIFT 0x6 +#define HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT_MASK 0xff0000 +#define HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT__SHIFT 0x10 +#define HTC_CONFIG__Reserved_MASK 0xff000000 +#define HTC_CONFIG__Reserved__SHIFT 0x18 +#define AVS_CU0_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f +#define AVS_CU0_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0 +#define AVS_CU0_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0 +#define AVS_CU0_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6 +#define AVS_CU0_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00 +#define AVS_CU0_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa +#define AVS_CU1_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f +#define AVS_CU1_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0 +#define AVS_CU1_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0 +#define AVS_CU1_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6 +#define AVS_CU1_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00 +#define AVS_CU1_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa +#define AVS_GNB_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f +#define AVS_GNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0 +#define AVS_GNB_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0 +#define AVS_GNB_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6 +#define AVS_GNB_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00 +#define AVS_GNB_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa +#define AVS_UNB_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f +#define AVS_UNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0 +#define AVS_UNB_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0 +#define AVS_UNB_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6 +#define AVS_UNB_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00 +#define AVS_UNB_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa +#define SMU_MONITOR_PORT80_MMIO_ADDR__MMIO_ADDRESS_MASK 0xffffffff +#define SMU_MONITOR_PORT80_MMIO_ADDR__MMIO_ADDRESS__SHIFT 0x0 +#define SMU_MONITOR_PORT80_MEMBASE_HI__MEMORY_BASE_HI_MASK 0xffffffff +#define SMU_MONITOR_PORT80_MEMBASE_HI__MEMORY_BASE_HI__SHIFT 0x0 +#define SMU_MONITOR_PORT80_MEMBASE_LO__MEMORY_BASE_LO_MASK 0xffffffff +#define SMU_MONITOR_PORT80_MEMBASE_LO__MEMORY_BASE_LO__SHIFT 0x0 +#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_POSITION_MASK 0xffff +#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_POSITION__SHIFT 0x0 +#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_BUFFER_SIZE_MASK 0xffff0000 +#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_BUFFER_SIZE__SHIFT 0x10 +#define SMU_MONITOR_PORT80_CTRL__ENABLE_DRAM_SHADOW_MASK 0x1 +#define SMU_MONITOR_PORT80_CTRL__ENABLE_DRAM_SHADOW__SHIFT 0x0 +#define SMU_MONITOR_PORT80_CTRL__ENABLE_CSR_SHADOW_MASK 0x2 +#define SMU_MONITOR_PORT80_CTRL__ENABLE_CSR_SHADOW__SHIFT 0x1 +#define SMU_MONITOR_PORT80_CTRL__RESERVED_MASK 0xfffc +#define SMU_MONITOR_PORT80_CTRL__RESERVED__SHIFT 0x2 +#define SMU_MONITOR_PORT80_CTRL__POLLING_INTERVAL_MASK 0xffff0000 +#define SMU_MONITOR_PORT80_CTRL__POLLING_INTERVAL__SHIFT 0x10 +#define SMU_TCEN_ALIVE__CORE_TCEN_ID_MASK 0xff +#define SMU_TCEN_ALIVE__CORE_TCEN_ID__SHIFT 0x0 +#define SMU_TCEN_ALIVE__GNB_TCEN_ID_MASK 0xff00 +#define SMU_TCEN_ALIVE__GNB_TCEN_ID__SHIFT 0x8 +#define SMU_TCEN_ALIVE__RESERVED_MASK 0xffff0000 +#define SMU_TCEN_ALIVE__RESERVED__SHIFT 0x10 +#define PDM_STATUS__PDM_ENABLED_MASK 0x1 +#define PDM_STATUS__PDM_ENABLED__SHIFT 0x0 +#define PDM_STATUS__NewCpcTdpLimit_MASK 0x1fffe +#define PDM_STATUS__NewCpcTdpLimit__SHIFT 0x1 +#define PDM_STATUS__NoofConnectedCores_MASK 0x1e0000 +#define PDM_STATUS__NoofConnectedCores__SHIFT 0x11 +#define PDM_STATUS__Reserved_MASK 0xffe00000 +#define PDM_STATUS__Reserved__SHIFT 0x15 +#define PDM_CNTL_1__BaseCoreTdpLimit0_MASK 0xff +#define PDM_CNTL_1__BaseCoreTdpLimit0__SHIFT 0x0 +#define PDM_CNTL_1__BaseCoreTdpLimit1_MASK 0xff00 +#define PDM_CNTL_1__BaseCoreTdpLimit1__SHIFT 0x8 +#define PDM_CNTL_1__BaseCoreTdpLimit2_MASK 0xff0000 +#define PDM_CNTL_1__BaseCoreTdpLimit2__SHIFT 0x10 +#define PDM_CNTL_1__GpuPdmMult_MASK 0xff000000 +#define PDM_CNTL_1__GpuPdmMult__SHIFT 0x18 +#define PDM_CNTL_2__HeatPdmTc_MASK 0xff +#define PDM_CNTL_2__HeatPdmTc__SHIFT 0x0 +#define PDM_CNTL_2__CoolPdmTc_MASK 0xff00 +#define PDM_CNTL_2__CoolPdmTc__SHIFT 0x8 +#define PDM_CNTL_2__GpuPdmTc_MASK 0xff0000 +#define PDM_CNTL_2__GpuPdmTc__SHIFT 0x10 +#define PDM_CNTL_2__GpuActThr_MASK 0xff000000 +#define PDM_CNTL_2__GpuActThr__SHIFT 0x18 +#define PDM_CNTL_3__HeatPdmThr1_MASK 0xff +#define PDM_CNTL_3__HeatPdmThr1__SHIFT 0x0 +#define PDM_CNTL_3__HeatPdmThr2_MASK 0xff00 +#define PDM_CNTL_3__HeatPdmThr2__SHIFT 0x8 +#define PDM_CNTL_3__CoolPdmThr1_MASK 0xff0000 +#define PDM_CNTL_3__CoolPdmThr1__SHIFT 0x10 +#define PDM_CNTL_3__CoolPdmThr2_MASK 0xff000000 +#define PDM_CNTL_3__CoolPdmThr2__SHIFT 0x18 +#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_52__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40 +#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17 +#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000 +#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf +#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 +#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 +#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 +#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 +#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 +#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf +#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 +#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS_MASK 0x1 +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS__SHIFT 0x0 +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK 0x1fe +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT 0x1 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1 +#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0 +#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe +#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0 +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 + +#endif /* SMU_7_0_0_SH_MASK_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h new file mode 100644 index 000000000000..f9fd2ea4625b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h @@ -0,0 +1,1314 @@ +/* + * SMU_7_0_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_0_1_D_H +#define SMU_7_0_1_D_H + +#define mmGCK_SMC_IND_INDEX 0x80 +#define mmGCK0_GCK_SMC_IND_INDEX 0x80 +#define mmGCK1_GCK_SMC_IND_INDEX 0x82 +#define mmGCK2_GCK_SMC_IND_INDEX 0x84 +#define mmGCK3_GCK_SMC_IND_INDEX 0x86 +#define mmGCK_SMC_IND_DATA 0x81 +#define mmGCK0_GCK_SMC_IND_DATA 0x81 +#define mmGCK1_GCK_SMC_IND_DATA 0x83 +#define mmGCK2_GCK_SMC_IND_DATA 0x85 +#define mmGCK3_GCK_SMC_IND_DATA 0x87 +#define ixCG_DCLK_CNTL 0xc050009c +#define ixCG_DCLK_STATUS 0xc05000a0 +#define ixCG_VCLK_CNTL 0xc05000a4 +#define ixCG_VCLK_STATUS 0xc05000a8 +#define ixCG_ECLK_CNTL 0xc05000ac +#define ixCG_ECLK_STATUS 0xc05000b0 +#define ixCG_ACLK_CNTL 0xc05000dc +#define ixGCK_DFS_BYPASS_CNTL 0xc0500118 +#define ixCG_SPLL_FUNC_CNTL 0xc0500140 +#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 +#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 +#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c +#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 +#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 +#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 +#define ixSPLL_CNTL_MODE 0xc0500160 +#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 +#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +#define ixMPLL_BYPASSCLK_SEL 0xc050019c +#define ixCG_CLKPIN_CNTL 0xc05001a0 +#define ixCG_CLKPIN_CNTL_2 0xc05001a4 +#define ixCG_CLKPIN_CNTL_DC 0xc0500204 +#define ixTHM_CLK_CNTL 0xc05001a8 +#define ixMISC_CLK_CTRL 0xc05001ac +#define ixGCK_PLL_TEST_CNTL 0xc05001c0 +#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 +#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 +#define mmSMC_IND_INDEX 0x80 +#define mmSMC0_SMC_IND_INDEX 0x80 +#define mmSMC1_SMC_IND_INDEX 0x82 +#define mmSMC2_SMC_IND_INDEX 0x84 +#define mmSMC3_SMC_IND_INDEX 0x86 +#define mmSMC_IND_DATA 0x81 +#define mmSMC0_SMC_IND_DATA 0x81 +#define mmSMC1_SMC_IND_DATA 0x83 +#define mmSMC2_SMC_IND_DATA 0x85 +#define mmSMC3_SMC_IND_DATA 0x87 +#define mmSMC_IND_INDEX_0 0x80 +#define mmSMC_IND_DATA_0 0x81 +#define mmSMC_IND_INDEX_1 0x82 +#define mmSMC_IND_DATA_1 0x83 +#define mmSMC_IND_INDEX_2 0x84 +#define mmSMC_IND_DATA_2 0x85 +#define mmSMC_IND_INDEX_3 0x86 +#define mmSMC_IND_DATA_3 0x87 +#define mmSMC_IND_INDEX_4 0x88 +#define mmSMC_IND_DATA_4 0x89 +#define mmSMC_IND_INDEX_5 0x8a +#define mmSMC_IND_DATA_5 0x8b +#define mmSMC_IND_INDEX_6 0x8c +#define mmSMC_IND_DATA_6 0x8d +#define mmSMC_IND_INDEX_7 0x8e +#define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_ACCESS_CNTL 0x90 +#define mmSMC_MESSAGE_0 0x94 +#define mmSMC_RESP_0 0x95 +#define mmSMC_MESSAGE_1 0x96 +#define mmSMC_RESP_1 0x97 +#define mmSMC_MESSAGE_2 0x98 +#define mmSMC_RESP_2 0x99 +#define mmSMC_MESSAGE_3 0x9a +#define mmSMC_RESP_3 0x9b +#define mmSMC_MESSAGE_4 0x9c +#define mmSMC_RESP_4 0x9d +#define mmSMC_MESSAGE_5 0x9e +#define mmSMC_RESP_5 0x9f +#define mmSMC_MESSAGE_6 0xa0 +#define mmSMC_RESP_6 0xa1 +#define mmSMC_MESSAGE_7 0xa2 +#define mmSMC_RESP_7 0xa3 +#define mmSMC_MSG_ARG_0 0xa4 +#define mmSMC_MSG_ARG_1 0xa5 +#define mmSMC_MSG_ARG_2 0xa6 +#define mmSMC_MSG_ARG_3 0xa7 +#define mmSMC_MSG_ARG_4 0xa8 +#define mmSMC_MSG_ARG_5 0xa9 +#define mmSMC_MSG_ARG_6 0xaa +#define mmSMC_MSG_ARG_7 0xab +#define mmSMC_MESSAGE_8 0xb5 +#define mmSMC_RESP_8 0xb6 +#define mmSMC_MESSAGE_9 0xb7 +#define mmSMC_RESP_9 0xb8 +#define mmSMC_MESSAGE_10 0xb9 +#define mmSMC_RESP_10 0xba +#define mmSMC_MESSAGE_11 0xbb +#define mmSMC_RESP_11 0xbc +#define mmSMC_MSG_ARG_8 0xbd +#define mmSMC_MSG_ARG_9 0xbe +#define mmSMC_MSG_ARG_10 0xbf +#define mmSMC_MSG_ARG_11 0x91 +#define ixSMC_SYSCON_RESET_CNTL 0x80000000 +#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 +#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 +#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c +#define ixSMC_SYSCON_MISC_CNTL 0x80000010 +#define ixSMC_SYSCON_MSG_ARG_0 0x80000068 +#define ixSMC_PC_C 0x80000370 +#define ixSMC_SCRATCH9 0x80000424 +#define mmGPIOPAD_SW_INT_STAT 0x180 +#define mmGPIOPAD_STRENGTH 0x181 +#define mmGPIOPAD_MASK 0x182 +#define mmGPIOPAD_A 0x183 +#define mmGPIOPAD_EN 0x184 +#define mmGPIOPAD_Y 0x185 +#define mmGPIOPAD_PINSTRAPS 0x186 +#define mmGPIOPAD_INT_STAT_EN 0x187 +#define mmGPIOPAD_INT_STAT 0x188 +#define mmGPIOPAD_INT_STAT_AK 0x189 +#define mmGPIOPAD_INT_EN 0x18a +#define mmGPIOPAD_INT_TYPE 0x18b +#define mmGPIOPAD_INT_POLARITY 0x18c +#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d +#define mmGPIOPAD_RCVR_SEL 0x191 +#define mmGPIOPAD_PU_EN 0x192 +#define mmGPIOPAD_PD_EN 0x193 +#define mmCG_FPS_CNT 0x1a4 +#define mmSMU_SMC_IND_INDEX 0x80 +#define mmSMU0_SMU_SMC_IND_INDEX 0x80 +#define mmSMU1_SMU_SMC_IND_INDEX 0x82 +#define mmSMU2_SMU_SMC_IND_INDEX 0x84 +#define mmSMU3_SMU_SMC_IND_INDEX 0x86 +#define mmSMU_SMC_IND_DATA 0x81 +#define mmSMU0_SMU_SMC_IND_DATA 0x81 +#define mmSMU1_SMU_SMC_IND_DATA 0x83 +#define mmSMU2_SMU_SMC_IND_DATA 0x85 +#define mmSMU3_SMU_SMC_IND_DATA 0x87 +#define ixRCU_UC_EVENTS 0xc0000004 +#define ixRCU_MISC_CTRL 0xc0000010 +#define ixCC_RCU_FUSES 0xc00c0000 +#define ixCC_SMU_MISC_FUSES 0xc00c0004 +#define ixCC_SCLK_VID_FUSES 0xc00c0008 +#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c +#define ixCC_GIO_IOC_FUSES 0xc00c0010 +#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c +#define ixCC_TST_ID_STRAPS 0xc00c0020 +#define ixCC_FCTRL_FUSES 0xc00c0024 +#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 +#define ixSMU_STATUS 0xe0003088 +#define ixSMU_FIRMWARE 0xe00030a4 +#define ixSMU_INPUT_DATA 0xe00030b8 +#define ixSMU_EFUSE_0 0xc0100000 +#define ixDPM_TABLE_1 0x3f000 +#define ixDPM_TABLE_2 0x3f004 +#define ixDPM_TABLE_3 0x3f008 +#define ixDPM_TABLE_4 0x3f00c +#define ixDPM_TABLE_5 0x3f010 +#define ixDPM_TABLE_6 0x3f014 +#define ixDPM_TABLE_7 0x3f018 +#define ixDPM_TABLE_8 0x3f01c +#define ixDPM_TABLE_9 0x3f020 +#define ixDPM_TABLE_10 0x3f024 +#define ixDPM_TABLE_11 0x3f028 +#define ixDPM_TABLE_12 0x3f02c +#define ixDPM_TABLE_13 0x3f030 +#define ixDPM_TABLE_14 0x3f034 +#define ixDPM_TABLE_15 0x3f038 +#define ixDPM_TABLE_16 0x3f03c +#define ixDPM_TABLE_17 0x3f040 +#define ixDPM_TABLE_18 0x3f044 +#define ixDPM_TABLE_19 0x3f048 +#define ixDPM_TABLE_20 0x3f04c +#define ixDPM_TABLE_21 0x3f050 +#define ixDPM_TABLE_22 0x3f054 +#define ixDPM_TABLE_23 0x3f058 +#define ixDPM_TABLE_24 0x3f05c +#define ixDPM_TABLE_25 0x3f060 +#define ixDPM_TABLE_26 0x3f064 +#define ixDPM_TABLE_27 0x3f068 +#define ixDPM_TABLE_28 0x3f06c +#define ixDPM_TABLE_29 0x3f070 +#define ixDPM_TABLE_30 0x3f074 +#define ixDPM_TABLE_31 0x3f078 +#define ixDPM_TABLE_32 0x3f07c +#define ixDPM_TABLE_33 0x3f080 +#define ixDPM_TABLE_34 0x3f084 +#define ixDPM_TABLE_35 0x3f088 +#define ixDPM_TABLE_36 0x3f08c +#define ixDPM_TABLE_37 0x3f090 +#define ixDPM_TABLE_38 0x3f094 +#define ixDPM_TABLE_39 0x3f098 +#define ixDPM_TABLE_40 0x3f09c +#define ixDPM_TABLE_41 0x3f0a0 +#define ixDPM_TABLE_42 0x3f0a4 +#define ixDPM_TABLE_43 0x3f0a8 +#define ixDPM_TABLE_44 0x3f0ac +#define ixDPM_TABLE_45 0x3f0b0 +#define ixDPM_TABLE_46 0x3f0b4 +#define ixDPM_TABLE_47 0x3f0b8 +#define ixDPM_TABLE_48 0x3f0bc +#define ixDPM_TABLE_49 0x3f0c0 +#define ixDPM_TABLE_50 0x3f0c4 +#define ixDPM_TABLE_51 0x3f0c8 +#define ixDPM_TABLE_52 0x3f0cc +#define ixDPM_TABLE_53 0x3f0d0 +#define ixDPM_TABLE_54 0x3f0d4 +#define ixDPM_TABLE_55 0x3f0d8 +#define ixDPM_TABLE_56 0x3f0dc +#define ixDPM_TABLE_57 0x3f0e0 +#define ixDPM_TABLE_58 0x3f0e4 +#define ixDPM_TABLE_59 0x3f0e8 +#define ixDPM_TABLE_60 0x3f0ec +#define ixDPM_TABLE_61 0x3f0f0 +#define ixDPM_TABLE_62 0x3f0f4 +#define ixDPM_TABLE_63 0x3f0f8 +#define ixDPM_TABLE_64 0x3f0fc +#define ixDPM_TABLE_65 0x3f100 +#define ixDPM_TABLE_66 0x3f104 +#define ixDPM_TABLE_67 0x3f108 +#define ixDPM_TABLE_68 0x3f10c +#define ixDPM_TABLE_69 0x3f110 +#define ixDPM_TABLE_70 0x3f114 +#define ixDPM_TABLE_71 0x3f118 +#define ixDPM_TABLE_72 0x3f11c +#define ixDPM_TABLE_73 0x3f120 +#define ixDPM_TABLE_74 0x3f124 +#define ixDPM_TABLE_75 0x3f128 +#define ixDPM_TABLE_76 0x3f12c +#define ixDPM_TABLE_77 0x3f130 +#define ixDPM_TABLE_78 0x3f134 +#define ixDPM_TABLE_79 0x3f138 +#define ixDPM_TABLE_80 0x3f13c +#define ixDPM_TABLE_81 0x3f140 +#define ixDPM_TABLE_82 0x3f144 +#define ixDPM_TABLE_83 0x3f148 +#define ixDPM_TABLE_84 0x3f14c +#define ixDPM_TABLE_85 0x3f150 +#define ixDPM_TABLE_86 0x3f154 +#define ixDPM_TABLE_87 0x3f158 +#define ixDPM_TABLE_88 0x3f15c +#define ixDPM_TABLE_89 0x3f160 +#define ixDPM_TABLE_90 0x3f164 +#define ixDPM_TABLE_91 0x3f168 +#define ixDPM_TABLE_92 0x3f16c +#define ixDPM_TABLE_93 0x3f170 +#define ixDPM_TABLE_94 0x3f174 +#define ixDPM_TABLE_95 0x3f178 +#define ixDPM_TABLE_96 0x3f17c +#define ixDPM_TABLE_97 0x3f180 +#define ixDPM_TABLE_98 0x3f184 +#define ixDPM_TABLE_99 0x3f188 +#define ixDPM_TABLE_100 0x3f18c +#define ixDPM_TABLE_101 0x3f190 +#define ixDPM_TABLE_102 0x3f194 +#define ixDPM_TABLE_103 0x3f198 +#define ixDPM_TABLE_104 0x3f19c +#define ixDPM_TABLE_105 0x3f1a0 +#define ixDPM_TABLE_106 0x3f1a4 +#define ixDPM_TABLE_107 0x3f1a8 +#define ixDPM_TABLE_108 0x3f1ac +#define ixDPM_TABLE_109 0x3f1b0 +#define ixDPM_TABLE_110 0x3f1b4 +#define ixDPM_TABLE_111 0x3f1b8 +#define ixDPM_TABLE_112 0x3f1bc +#define ixDPM_TABLE_113 0x3f1c0 +#define ixDPM_TABLE_114 0x3f1c4 +#define ixDPM_TABLE_115 0x3f1c8 +#define ixDPM_TABLE_116 0x3f1cc +#define ixDPM_TABLE_117 0x3f1d0 +#define ixDPM_TABLE_118 0x3f1d4 +#define ixDPM_TABLE_119 0x3f1d8 +#define ixDPM_TABLE_120 0x3f1dc +#define ixDPM_TABLE_121 0x3f1e0 +#define ixDPM_TABLE_122 0x3f1e4 +#define ixDPM_TABLE_123 0x3f1e8 +#define ixDPM_TABLE_124 0x3f1ec +#define ixDPM_TABLE_125 0x3f1f0 +#define ixDPM_TABLE_126 0x3f1f4 +#define ixDPM_TABLE_127 0x3f1f8 +#define ixDPM_TABLE_128 0x3f1fc +#define ixDPM_TABLE_129 0x3f200 +#define ixDPM_TABLE_130 0x3f204 +#define ixDPM_TABLE_131 0x3f208 +#define ixDPM_TABLE_132 0x3f20c +#define ixDPM_TABLE_133 0x3f210 +#define ixDPM_TABLE_134 0x3f214 +#define ixDPM_TABLE_135 0x3f218 +#define ixDPM_TABLE_136 0x3f21c +#define ixDPM_TABLE_137 0x3f220 +#define ixDPM_TABLE_138 0x3f224 +#define ixDPM_TABLE_139 0x3f228 +#define ixDPM_TABLE_140 0x3f22c +#define ixDPM_TABLE_141 0x3f230 +#define ixDPM_TABLE_142 0x3f234 +#define ixDPM_TABLE_143 0x3f238 +#define ixDPM_TABLE_144 0x3f23c +#define ixDPM_TABLE_145 0x3f240 +#define ixDPM_TABLE_146 0x3f244 +#define ixDPM_TABLE_147 0x3f248 +#define ixDPM_TABLE_148 0x3f24c +#define ixDPM_TABLE_149 0x3f250 +#define ixDPM_TABLE_150 0x3f254 +#define ixDPM_TABLE_151 0x3f258 +#define ixDPM_TABLE_152 0x3f25c +#define ixDPM_TABLE_153 0x3f260 +#define ixDPM_TABLE_154 0x3f264 +#define ixDPM_TABLE_155 0x3f268 +#define ixDPM_TABLE_156 0x3f26c +#define ixDPM_TABLE_157 0x3f270 +#define ixDPM_TABLE_158 0x3f274 +#define ixDPM_TABLE_159 0x3f278 +#define ixDPM_TABLE_160 0x3f27c +#define ixDPM_TABLE_161 0x3f280 +#define ixDPM_TABLE_162 0x3f284 +#define ixDPM_TABLE_163 0x3f288 +#define ixDPM_TABLE_164 0x3f28c +#define ixDPM_TABLE_165 0x3f290 +#define ixDPM_TABLE_166 0x3f294 +#define ixDPM_TABLE_167 0x3f298 +#define ixDPM_TABLE_168 0x3f29c +#define ixDPM_TABLE_169 0x3f2a0 +#define ixDPM_TABLE_170 0x3f2a4 +#define ixDPM_TABLE_171 0x3f2a8 +#define ixDPM_TABLE_172 0x3f2ac +#define ixDPM_TABLE_173 0x3f2b0 +#define ixDPM_TABLE_174 0x3f2b4 +#define ixDPM_TABLE_175 0x3f2b8 +#define ixDPM_TABLE_176 0x3f2bc +#define ixDPM_TABLE_177 0x3f2c0 +#define ixDPM_TABLE_178 0x3f2c4 +#define ixDPM_TABLE_179 0x3f2c8 +#define ixDPM_TABLE_180 0x3f2cc +#define ixDPM_TABLE_181 0x3f2d0 +#define ixDPM_TABLE_182 0x3f2d4 +#define ixDPM_TABLE_183 0x3f2d8 +#define ixDPM_TABLE_184 0x3f2dc +#define ixDPM_TABLE_185 0x3f2e0 +#define ixDPM_TABLE_186 0x3f2e4 +#define ixDPM_TABLE_187 0x3f2e8 +#define ixDPM_TABLE_188 0x3f2ec +#define ixDPM_TABLE_189 0x3f2f0 +#define ixDPM_TABLE_190 0x3f2f4 +#define ixDPM_TABLE_191 0x3f2f8 +#define ixDPM_TABLE_192 0x3f2fc +#define ixDPM_TABLE_193 0x3f300 +#define ixDPM_TABLE_194 0x3f304 +#define ixDPM_TABLE_195 0x3f308 +#define ixDPM_TABLE_196 0x3f30c +#define ixDPM_TABLE_197 0x3f310 +#define ixDPM_TABLE_198 0x3f314 +#define ixDPM_TABLE_199 0x3f318 +#define ixDPM_TABLE_200 0x3f31c +#define ixDPM_TABLE_201 0x3f320 +#define ixDPM_TABLE_202 0x3f324 +#define ixDPM_TABLE_203 0x3f328 +#define ixDPM_TABLE_204 0x3f32c +#define ixDPM_TABLE_205 0x3f330 +#define ixDPM_TABLE_206 0x3f334 +#define ixDPM_TABLE_207 0x3f338 +#define ixDPM_TABLE_208 0x3f33c +#define ixDPM_TABLE_209 0x3f340 +#define ixDPM_TABLE_210 0x3f344 +#define ixDPM_TABLE_211 0x3f348 +#define ixDPM_TABLE_212 0x3f34c +#define ixDPM_TABLE_213 0x3f350 +#define ixDPM_TABLE_214 0x3f354 +#define ixDPM_TABLE_215 0x3f358 +#define ixDPM_TABLE_216 0x3f35c +#define ixDPM_TABLE_217 0x3f360 +#define ixDPM_TABLE_218 0x3f364 +#define ixDPM_TABLE_219 0x3f368 +#define ixDPM_TABLE_220 0x3f36c +#define ixDPM_TABLE_221 0x3f370 +#define ixDPM_TABLE_222 0x3f374 +#define ixDPM_TABLE_223 0x3f378 +#define ixDPM_TABLE_224 0x3f37c +#define ixDPM_TABLE_225 0x3f380 +#define ixDPM_TABLE_226 0x3f384 +#define ixDPM_TABLE_227 0x3f388 +#define ixDPM_TABLE_228 0x3f38c +#define ixDPM_TABLE_229 0x3f390 +#define ixDPM_TABLE_230 0x3f394 +#define ixDPM_TABLE_231 0x3f398 +#define ixDPM_TABLE_232 0x3f39c +#define ixDPM_TABLE_233 0x3f3a0 +#define ixDPM_TABLE_234 0x3f3a4 +#define ixDPM_TABLE_235 0x3f3a8 +#define ixDPM_TABLE_236 0x3f3ac +#define ixDPM_TABLE_237 0x3f3b0 +#define ixDPM_TABLE_238 0x3f3b4 +#define ixDPM_TABLE_239 0x3f3b8 +#define ixDPM_TABLE_240 0x3f3bc +#define ixDPM_TABLE_241 0x3f3c0 +#define ixDPM_TABLE_242 0x3f3c4 +#define ixDPM_TABLE_243 0x3f3c8 +#define ixDPM_TABLE_244 0x3f3cc +#define ixDPM_TABLE_245 0x3f3d0 +#define ixDPM_TABLE_246 0x3f3d4 +#define ixDPM_TABLE_247 0x3f3d8 +#define ixDPM_TABLE_248 0x3f3dc +#define ixDPM_TABLE_249 0x3f3e0 +#define ixDPM_TABLE_250 0x3f3e4 +#define ixDPM_TABLE_251 0x3f3e8 +#define ixDPM_TABLE_252 0x3f3ec +#define ixDPM_TABLE_253 0x3f3f0 +#define ixDPM_TABLE_254 0x3f3f4 +#define ixDPM_TABLE_255 0x3f3f8 +#define ixDPM_TABLE_256 0x3f3fc +#define ixDPM_TABLE_257 0x3f400 +#define ixDPM_TABLE_258 0x3f404 +#define ixDPM_TABLE_259 0x3f408 +#define ixDPM_TABLE_260 0x3f40c +#define ixDPM_TABLE_261 0x3f410 +#define ixDPM_TABLE_262 0x3f414 +#define ixDPM_TABLE_263 0x3f418 +#define ixDPM_TABLE_264 0x3f41c +#define ixDPM_TABLE_265 0x3f420 +#define ixDPM_TABLE_266 0x3f424 +#define ixDPM_TABLE_267 0x3f428 +#define ixDPM_TABLE_268 0x3f42c +#define ixDPM_TABLE_269 0x3f430 +#define ixDPM_TABLE_270 0x3f434 +#define ixDPM_TABLE_271 0x3f438 +#define ixDPM_TABLE_272 0x3f43c +#define ixDPM_TABLE_273 0x3f440 +#define ixDPM_TABLE_274 0x3f444 +#define ixDPM_TABLE_275 0x3f448 +#define ixDPM_TABLE_276 0x3f44c +#define ixDPM_TABLE_277 0x3f450 +#define ixDPM_TABLE_278 0x3f454 +#define ixDPM_TABLE_279 0x3f458 +#define ixDPM_TABLE_280 0x3f45c +#define ixDPM_TABLE_281 0x3f460 +#define ixDPM_TABLE_282 0x3f464 +#define ixDPM_TABLE_283 0x3f468 +#define ixDPM_TABLE_284 0x3f46c +#define ixDPM_TABLE_285 0x3f470 +#define ixDPM_TABLE_286 0x3f474 +#define ixDPM_TABLE_287 0x3f478 +#define ixDPM_TABLE_288 0x3f47c +#define ixDPM_TABLE_289 0x3f480 +#define ixDPM_TABLE_290 0x3f484 +#define ixDPM_TABLE_291 0x3f488 +#define ixDPM_TABLE_292 0x3f48c +#define ixDPM_TABLE_293 0x3f490 +#define ixDPM_TABLE_294 0x3f494 +#define ixDPM_TABLE_295 0x3f498 +#define ixDPM_TABLE_296 0x3f49c +#define ixDPM_TABLE_297 0x3f4a0 +#define ixDPM_TABLE_298 0x3f4a4 +#define ixDPM_TABLE_299 0x3f4a8 +#define ixDPM_TABLE_300 0x3f4ac +#define ixDPM_TABLE_301 0x3f4b0 +#define ixDPM_TABLE_302 0x3f4b4 +#define ixDPM_TABLE_303 0x3f4b8 +#define ixDPM_TABLE_304 0x3f4bc +#define ixDPM_TABLE_305 0x3f4c0 +#define ixDPM_TABLE_306 0x3f4c4 +#define ixDPM_TABLE_307 0x3f4c8 +#define ixDPM_TABLE_308 0x3f4cc +#define ixDPM_TABLE_309 0x3f4d0 +#define ixDPM_TABLE_310 0x3f4d4 +#define ixDPM_TABLE_311 0x3f4d8 +#define ixDPM_TABLE_312 0x3f4dc +#define ixDPM_TABLE_313 0x3f4e0 +#define ixDPM_TABLE_314 0x3f4e4 +#define ixDPM_TABLE_315 0x3f4e8 +#define ixDPM_TABLE_316 0x3f4ec +#define ixDPM_TABLE_317 0x3f4f0 +#define ixDPM_TABLE_318 0x3f4f4 +#define ixDPM_TABLE_319 0x3f4f8 +#define ixDPM_TABLE_320 0x3f4fc +#define ixDPM_TABLE_321 0x3f500 +#define ixDPM_TABLE_322 0x3f504 +#define ixDPM_TABLE_323 0x3f508 +#define ixDPM_TABLE_324 0x3f50c +#define ixDPM_TABLE_325 0x3f510 +#define ixDPM_TABLE_326 0x3f514 +#define ixDPM_TABLE_327 0x3f518 +#define ixDPM_TABLE_328 0x3f51c +#define ixDPM_TABLE_329 0x3f520 +#define ixDPM_TABLE_330 0x3f524 +#define ixDPM_TABLE_331 0x3f528 +#define ixDPM_TABLE_332 0x3f52c +#define ixDPM_TABLE_333 0x3f530 +#define ixDPM_TABLE_334 0x3f534 +#define ixDPM_TABLE_335 0x3f538 +#define ixDPM_TABLE_336 0x3f53c +#define ixDPM_TABLE_337 0x3f540 +#define ixDPM_TABLE_338 0x3f544 +#define ixDPM_TABLE_339 0x3f548 +#define ixDPM_TABLE_340 0x3f54c +#define ixDPM_TABLE_341 0x3f550 +#define ixDPM_TABLE_342 0x3f554 +#define ixDPM_TABLE_343 0x3f558 +#define ixDPM_TABLE_344 0x3f55c +#define ixDPM_TABLE_345 0x3f560 +#define ixDPM_TABLE_346 0x3f564 +#define ixDPM_TABLE_347 0x3f568 +#define ixDPM_TABLE_348 0x3f56c +#define ixDPM_TABLE_349 0x3f570 +#define ixDPM_TABLE_350 0x3f574 +#define ixDPM_TABLE_351 0x3f578 +#define ixDPM_TABLE_352 0x3f57c +#define ixDPM_TABLE_353 0x3f580 +#define ixDPM_TABLE_354 0x3f584 +#define ixDPM_TABLE_355 0x3f588 +#define ixDPM_TABLE_356 0x3f58c +#define ixDPM_TABLE_357 0x3f590 +#define ixDPM_TABLE_358 0x3f594 +#define ixDPM_TABLE_359 0x3f598 +#define ixDPM_TABLE_360 0x3f59c +#define ixDPM_TABLE_361 0x3f5a0 +#define ixDPM_TABLE_362 0x3f5a4 +#define ixDPM_TABLE_363 0x3f5a8 +#define ixDPM_TABLE_364 0x3f5ac +#define ixDPM_TABLE_365 0x3f5b0 +#define ixDPM_TABLE_366 0x3f5b4 +#define ixDPM_TABLE_367 0x3f5b8 +#define ixDPM_TABLE_368 0x3f5bc +#define ixDPM_TABLE_369 0x3f5c0 +#define ixDPM_TABLE_370 0x3f5c4 +#define ixDPM_TABLE_371 0x3f5c8 +#define ixDPM_TABLE_372 0x3f5cc +#define ixDPM_TABLE_373 0x3f5d0 +#define ixDPM_TABLE_374 0x3f5d4 +#define ixDPM_TABLE_375 0x3f5d8 +#define ixDPM_TABLE_376 0x3f5dc +#define ixDPM_TABLE_377 0x3f5e0 +#define ixDPM_TABLE_378 0x3f5e4 +#define ixDPM_TABLE_379 0x3f5e8 +#define ixDPM_TABLE_380 0x3f5ec +#define ixDPM_TABLE_381 0x3f5f0 +#define ixDPM_TABLE_382 0x3f5f4 +#define ixDPM_TABLE_383 0x3f5f8 +#define ixDPM_TABLE_384 0x3f5fc +#define ixDPM_TABLE_385 0x3f600 +#define ixDPM_TABLE_386 0x3f604 +#define ixDPM_TABLE_387 0x3f608 +#define ixDPM_TABLE_388 0x3f60c +#define ixDPM_TABLE_389 0x3f610 +#define ixDPM_TABLE_390 0x3f614 +#define ixDPM_TABLE_391 0x3f618 +#define ixDPM_TABLE_392 0x3f61c +#define ixDPM_TABLE_393 0x3f620 +#define ixDPM_TABLE_394 0x3f624 +#define ixDPM_TABLE_395 0x3f628 +#define ixDPM_TABLE_396 0x3f62c +#define ixDPM_TABLE_397 0x3f630 +#define ixDPM_TABLE_398 0x3f634 +#define ixDPM_TABLE_399 0x3f638 +#define ixDPM_TABLE_400 0x3f63c +#define ixDPM_TABLE_401 0x3f640 +#define ixDPM_TABLE_402 0x3f644 +#define ixDPM_TABLE_403 0x3f648 +#define ixDPM_TABLE_404 0x3f64c +#define ixDPM_TABLE_405 0x3f650 +#define ixDPM_TABLE_406 0x3f654 +#define ixDPM_TABLE_407 0x3f658 +#define ixDPM_TABLE_408 0x3f65c +#define ixDPM_TABLE_409 0x3f660 +#define ixDPM_TABLE_410 0x3f664 +#define ixDPM_TABLE_411 0x3f668 +#define ixDPM_TABLE_412 0x3f66c +#define ixDPM_TABLE_413 0x3f670 +#define ixDPM_TABLE_414 0x3f674 +#define ixDPM_TABLE_415 0x3f678 +#define ixDPM_TABLE_416 0x3f67c +#define ixDPM_TABLE_417 0x3f680 +#define ixDPM_TABLE_418 0x3f684 +#define ixDPM_TABLE_419 0x3f688 +#define ixDPM_TABLE_420 0x3f68c +#define ixDPM_TABLE_421 0x3f690 +#define ixDPM_TABLE_422 0x3f694 +#define ixDPM_TABLE_423 0x3f698 +#define ixDPM_TABLE_424 0x3f69c +#define ixDPM_TABLE_425 0x3f6a0 +#define ixDPM_TABLE_426 0x3f6a4 +#define ixDPM_TABLE_427 0x3f6a8 +#define ixDPM_TABLE_428 0x3f6ac +#define ixDPM_TABLE_429 0x3f6b0 +#define ixDPM_TABLE_430 0x3f6b4 +#define ixDPM_TABLE_431 0x3f6b8 +#define ixDPM_TABLE_432 0x3f6bc +#define ixDPM_TABLE_433 0x3f6c0 +#define ixDPM_TABLE_434 0x3f6c4 +#define ixDPM_TABLE_435 0x3f6c8 +#define ixDPM_TABLE_436 0x3f6cc +#define ixDPM_TABLE_437 0x3f6d0 +#define ixDPM_TABLE_438 0x3f6d4 +#define ixDPM_TABLE_439 0x3f6d8 +#define ixDPM_TABLE_440 0x3f6dc +#define ixDPM_TABLE_441 0x3f6e0 +#define ixDPM_TABLE_442 0x3f6e4 +#define ixDPM_TABLE_443 0x3f6e8 +#define ixDPM_TABLE_444 0x3f6ec +#define ixDPM_TABLE_445 0x3f6f0 +#define ixDPM_TABLE_446 0x3f6f4 +#define ixDPM_TABLE_447 0x3f6f8 +#define ixDPM_TABLE_448 0x3f6fc +#define ixDPM_TABLE_449 0x3f700 +#define ixDPM_TABLE_450 0x3f704 +#define ixDPM_TABLE_451 0x3f708 +#define ixDPM_TABLE_452 0x3f70c +#define ixDPM_TABLE_453 0x3f710 +#define ixDPM_TABLE_454 0x3f714 +#define ixDPM_TABLE_455 0x3f718 +#define ixDPM_TABLE_456 0x3f71c +#define ixDPM_TABLE_457 0x3f720 +#define ixDPM_TABLE_458 0x3f724 +#define ixDPM_TABLE_459 0x3f728 +#define ixDPM_TABLE_460 0x3f72c +#define ixDPM_TABLE_461 0x3f730 +#define ixDPM_TABLE_462 0x3f734 +#define ixDPM_TABLE_463 0x3f738 +#define ixDPM_TABLE_464 0x3f73c +#define ixDPM_TABLE_465 0x3f740 +#define ixDPM_TABLE_466 0x3f744 +#define ixDPM_TABLE_467 0x3f748 +#define ixDPM_TABLE_468 0x3f74c +#define ixDPM_TABLE_469 0x3f750 +#define ixDPM_TABLE_470 0x3f754 +#define ixDPM_TABLE_471 0x3f758 +#define ixDPM_TABLE_472 0x3f75c +#define ixDPM_TABLE_473 0x3f760 +#define ixDPM_TABLE_474 0x3f764 +#define ixDPM_TABLE_475 0x3f768 +#define ixDPM_TABLE_476 0x3f76c +#define ixDPM_TABLE_477 0x3f770 +#define ixDPM_TABLE_478 0x3f774 +#define ixDPM_TABLE_479 0x3f778 +#define ixDPM_TABLE_480 0x3f77c +#define ixDPM_TABLE_481 0x3f780 +#define ixDPM_TABLE_482 0x3f784 +#define ixDPM_TABLE_483 0x3f788 +#define ixDPM_TABLE_484 0x3f78c +#define ixDPM_TABLE_485 0x3f790 +#define ixDPM_TABLE_486 0x3f794 +#define ixDPM_TABLE_487 0x3f798 +#define ixDPM_TABLE_488 0x3f79c +#define ixDPM_TABLE_489 0x3f7a0 +#define ixDPM_TABLE_490 0x3f7a4 +#define ixDPM_TABLE_491 0x3f7a8 +#define ixDPM_TABLE_492 0x3f7ac +#define ixDPM_TABLE_493 0x3f7b0 +#define ixDPM_TABLE_494 0x3f7b4 +#define ixDPM_TABLE_495 0x3f7b8 +#define ixDPM_TABLE_496 0x3f7bc +#define ixDPM_TABLE_497 0x3f7c0 +#define ixDPM_TABLE_498 0x3f7c4 +#define ixDPM_TABLE_499 0x3f7c8 +#define ixDPM_TABLE_500 0x3f7cc +#define ixDPM_TABLE_501 0x3f7d0 +#define ixDPM_TABLE_502 0x3f7d4 +#define ixDPM_TABLE_503 0x3f7d8 +#define ixDPM_TABLE_504 0x3f7dc +#define ixDPM_TABLE_505 0x3f7e0 +#define ixDPM_TABLE_506 0x3f7e4 +#define ixDPM_TABLE_507 0x3f7e8 +#define ixDPM_TABLE_508 0x3f7ec +#define ixDPM_TABLE_509 0x3f7f0 +#define ixDPM_TABLE_510 0x3f7f4 +#define ixFIRMWARE_FLAGS 0x3f800 +#define ixTDC_STATUS 0x3f808 +#define ixTDC_MV_AVERAGE 0x3f80c +#define ixTDC_VRM_LIMIT 0x3f810 +#define ixFEATURE_STATUS 0x3f818 +#define ixENTITY_TEMPERATURES_1 0x3f81c +#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f900 +#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f904 +#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f908 +#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f90c +#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f910 +#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f914 +#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f918 +#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f91c +#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f920 +#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f924 +#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f928 +#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f92c +#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f930 +#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f934 +#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f938 +#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f93c +#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f940 +#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f944 +#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f948 +#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f94c +#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f950 +#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f954 +#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f958 +#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f95c +#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f960 +#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f964 +#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f968 +#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f96c +#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f970 +#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f974 +#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f978 +#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f97c +#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f980 +#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f984 +#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f988 +#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f98c +#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f990 +#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f994 +#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f998 +#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f99c +#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f9a0 +#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f9a4 +#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f9a8 +#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f9ac +#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f9b0 +#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f9b4 +#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f9b8 +#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f9bc +#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f9c0 +#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f9c4 +#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f9c8 +#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f9cc +#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f9d0 +#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f9d4 +#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f9d8 +#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f9dc +#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f9e0 +#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f9e4 +#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f9e8 +#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f9ec +#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f9f0 +#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f9f4 +#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f9f8 +#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f9fc +#define ixMCARB_DRAM_TIMING_TABLE_65 0x3fa00 +#define ixMCARB_DRAM_TIMING_TABLE_66 0x3fa04 +#define ixMCARB_DRAM_TIMING_TABLE_67 0x3fa08 +#define ixMCARB_DRAM_TIMING_TABLE_68 0x3fa0c +#define ixMCARB_DRAM_TIMING_TABLE_69 0x3fa10 +#define ixMCARB_DRAM_TIMING_TABLE_70 0x3fa14 +#define ixMCARB_DRAM_TIMING_TABLE_71 0x3fa18 +#define ixMCARB_DRAM_TIMING_TABLE_72 0x3fa1c +#define ixMCARB_DRAM_TIMING_TABLE_73 0x3fa20 +#define ixMCARB_DRAM_TIMING_TABLE_74 0x3fa24 +#define ixMCARB_DRAM_TIMING_TABLE_75 0x3fa28 +#define ixMCARB_DRAM_TIMING_TABLE_76 0x3fa2c +#define ixMCARB_DRAM_TIMING_TABLE_77 0x3fa30 +#define ixMCARB_DRAM_TIMING_TABLE_78 0x3fa34 +#define ixMCARB_DRAM_TIMING_TABLE_79 0x3fa38 +#define ixMCARB_DRAM_TIMING_TABLE_80 0x3fa3c +#define ixMCARB_DRAM_TIMING_TABLE_81 0x3fa40 +#define ixMCARB_DRAM_TIMING_TABLE_82 0x3fa44 +#define ixMCARB_DRAM_TIMING_TABLE_83 0x3fa48 +#define ixMCARB_DRAM_TIMING_TABLE_84 0x3fa4c +#define ixMCARB_DRAM_TIMING_TABLE_85 0x3fa50 +#define ixMCARB_DRAM_TIMING_TABLE_86 0x3fa54 +#define ixMCARB_DRAM_TIMING_TABLE_87 0x3fa58 +#define ixMCARB_DRAM_TIMING_TABLE_88 0x3fa5c +#define ixMCARB_DRAM_TIMING_TABLE_89 0x3fa60 +#define ixMCARB_DRAM_TIMING_TABLE_90 0x3fa64 +#define ixMCARB_DRAM_TIMING_TABLE_91 0x3fa68 +#define ixMCARB_DRAM_TIMING_TABLE_92 0x3fa6c +#define ixMCARB_DRAM_TIMING_TABLE_93 0x3fa70 +#define ixMCARB_DRAM_TIMING_TABLE_94 0x3fa74 +#define ixMCARB_DRAM_TIMING_TABLE_95 0x3fa78 +#define ixMCARB_DRAM_TIMING_TABLE_96 0x3fa7c +#define ixMCARB_DRAM_TIMING_TABLE_97 0x3fa80 +#define ixMCARB_DRAM_TIMING_TABLE_98 0x3fa84 +#define ixMCARB_DRAM_TIMING_TABLE_99 0x3fa88 +#define ixMCARB_DRAM_TIMING_TABLE_100 0x3fa8c +#define ixMCARB_DRAM_TIMING_TABLE_101 0x3fa90 +#define ixMCARB_DRAM_TIMING_TABLE_102 0x3fa94 +#define ixMCARB_DRAM_TIMING_TABLE_103 0x3fa98 +#define ixMCARB_DRAM_TIMING_TABLE_104 0x3fa9c +#define ixMCARB_DRAM_TIMING_TABLE_105 0x3faa0 +#define ixMCARB_DRAM_TIMING_TABLE_106 0x3faa4 +#define ixMCARB_DRAM_TIMING_TABLE_107 0x3faa8 +#define ixMCARB_DRAM_TIMING_TABLE_108 0x3faac +#define ixMCARB_DRAM_TIMING_TABLE_109 0x3fab0 +#define ixMCARB_DRAM_TIMING_TABLE_110 0x3fab4 +#define ixMCARB_DRAM_TIMING_TABLE_111 0x3fab8 +#define ixMCARB_DRAM_TIMING_TABLE_112 0x3fabc +#define ixMCARB_DRAM_TIMING_TABLE_113 0x3fac0 +#define ixMCARB_DRAM_TIMING_TABLE_114 0x3fac4 +#define ixMCARB_DRAM_TIMING_TABLE_115 0x3fac8 +#define ixMCARB_DRAM_TIMING_TABLE_116 0x3facc +#define ixMCARB_DRAM_TIMING_TABLE_117 0x3fad0 +#define ixMCARB_DRAM_TIMING_TABLE_118 0x3fad4 +#define ixMCARB_DRAM_TIMING_TABLE_119 0x3fad8 +#define ixMCARB_DRAM_TIMING_TABLE_120 0x3fadc +#define ixMCARB_DRAM_TIMING_TABLE_121 0x3fae0 +#define ixMCARB_DRAM_TIMING_TABLE_122 0x3fae4 +#define ixMCARB_DRAM_TIMING_TABLE_123 0x3fae8 +#define ixMCARB_DRAM_TIMING_TABLE_124 0x3faec +#define ixMCARB_DRAM_TIMING_TABLE_125 0x3faf0 +#define ixMCARB_DRAM_TIMING_TABLE_126 0x3faf4 +#define ixMCARB_DRAM_TIMING_TABLE_127 0x3faf8 +#define ixMCARB_DRAM_TIMING_TABLE_128 0x3fafc +#define ixMCARB_DRAM_TIMING_TABLE_129 0x3fb00 +#define ixMCARB_DRAM_TIMING_TABLE_130 0x3fb04 +#define ixMCARB_DRAM_TIMING_TABLE_131 0x3fb08 +#define ixMCARB_DRAM_TIMING_TABLE_132 0x3fb0c +#define ixMCARB_DRAM_TIMING_TABLE_133 0x3fb10 +#define ixMCARB_DRAM_TIMING_TABLE_134 0x3fb14 +#define ixMCARB_DRAM_TIMING_TABLE_135 0x3fb18 +#define ixMCARB_DRAM_TIMING_TABLE_136 0x3fb1c +#define ixMCARB_DRAM_TIMING_TABLE_137 0x3fb20 +#define ixMCARB_DRAM_TIMING_TABLE_138 0x3fb24 +#define ixMCARB_DRAM_TIMING_TABLE_139 0x3fb28 +#define ixMCARB_DRAM_TIMING_TABLE_140 0x3fb2c +#define ixMCARB_DRAM_TIMING_TABLE_141 0x3fb30 +#define ixMCARB_DRAM_TIMING_TABLE_142 0x3fb34 +#define ixMCARB_DRAM_TIMING_TABLE_143 0x3fb38 +#define ixMCARB_DRAM_TIMING_TABLE_144 0x3fb3c +#define ixMC_REGISTERS_TABLE_1 0x3fb40 +#define ixMC_REGISTERS_TABLE_2 0x3fb44 +#define ixMC_REGISTERS_TABLE_3 0x3fb48 +#define ixMC_REGISTERS_TABLE_4 0x3fb4c +#define ixMC_REGISTERS_TABLE_5 0x3fb50 +#define ixMC_REGISTERS_TABLE_6 0x3fb54 +#define ixMC_REGISTERS_TABLE_7 0x3fb58 +#define ixMC_REGISTERS_TABLE_8 0x3fb5c +#define ixMC_REGISTERS_TABLE_9 0x3fb60 +#define ixMC_REGISTERS_TABLE_10 0x3fb64 +#define ixMC_REGISTERS_TABLE_11 0x3fb68 +#define ixMC_REGISTERS_TABLE_12 0x3fb6c +#define ixMC_REGISTERS_TABLE_13 0x3fb70 +#define ixMC_REGISTERS_TABLE_14 0x3fb74 +#define ixMC_REGISTERS_TABLE_15 0x3fb78 +#define ixMC_REGISTERS_TABLE_16 0x3fb7c +#define ixMC_REGISTERS_TABLE_17 0x3fb80 +#define ixMC_REGISTERS_TABLE_18 0x3fb84 +#define ixMC_REGISTERS_TABLE_19 0x3fb88 +#define ixMC_REGISTERS_TABLE_20 0x3fb8c +#define ixMC_REGISTERS_TABLE_21 0x3fb90 +#define ixMC_REGISTERS_TABLE_22 0x3fb94 +#define ixMC_REGISTERS_TABLE_23 0x3fb98 +#define ixMC_REGISTERS_TABLE_24 0x3fb9c +#define ixMC_REGISTERS_TABLE_25 0x3fba0 +#define ixMC_REGISTERS_TABLE_26 0x3fba4 +#define ixMC_REGISTERS_TABLE_27 0x3fba8 +#define ixMC_REGISTERS_TABLE_28 0x3fbac +#define ixMC_REGISTERS_TABLE_29 0x3fbb0 +#define ixMC_REGISTERS_TABLE_30 0x3fbb4 +#define ixMC_REGISTERS_TABLE_31 0x3fbb8 +#define ixMC_REGISTERS_TABLE_32 0x3fbbc +#define ixMC_REGISTERS_TABLE_33 0x3fbc0 +#define ixMC_REGISTERS_TABLE_34 0x3fbc4 +#define ixMC_REGISTERS_TABLE_35 0x3fbc8 +#define ixMC_REGISTERS_TABLE_36 0x3fbcc +#define ixMC_REGISTERS_TABLE_37 0x3fbd0 +#define ixMC_REGISTERS_TABLE_38 0x3fbd4 +#define ixMC_REGISTERS_TABLE_39 0x3fbd8 +#define ixMC_REGISTERS_TABLE_40 0x3fbdc +#define ixMC_REGISTERS_TABLE_41 0x3fbe0 +#define ixMC_REGISTERS_TABLE_42 0x3fbe4 +#define ixMC_REGISTERS_TABLE_43 0x3fbe8 +#define ixMC_REGISTERS_TABLE_44 0x3fbec +#define ixMC_REGISTERS_TABLE_45 0x3fbf0 +#define ixMC_REGISTERS_TABLE_46 0x3fbf4 +#define ixMC_REGISTERS_TABLE_47 0x3fbf8 +#define ixMC_REGISTERS_TABLE_48 0x3fbfc +#define ixMC_REGISTERS_TABLE_49 0x3fc00 +#define ixMC_REGISTERS_TABLE_50 0x3fc04 +#define ixMC_REGISTERS_TABLE_51 0x3fc08 +#define ixMC_REGISTERS_TABLE_52 0x3fc0c +#define ixMC_REGISTERS_TABLE_53 0x3fc10 +#define ixMC_REGISTERS_TABLE_54 0x3fc14 +#define ixMC_REGISTERS_TABLE_55 0x3fc18 +#define ixMC_REGISTERS_TABLE_56 0x3fc1c +#define ixMC_REGISTERS_TABLE_57 0x3fc20 +#define ixMC_REGISTERS_TABLE_58 0x3fc24 +#define ixMC_REGISTERS_TABLE_59 0x3fc28 +#define ixMC_REGISTERS_TABLE_60 0x3fc2c +#define ixMC_REGISTERS_TABLE_61 0x3fc30 +#define ixMC_REGISTERS_TABLE_62 0x3fc34 +#define ixMC_REGISTERS_TABLE_63 0x3fc38 +#define ixMC_REGISTERS_TABLE_64 0x3fc3c +#define ixMC_REGISTERS_TABLE_65 0x3fc40 +#define ixMC_REGISTERS_TABLE_66 0x3fc44 +#define ixMC_REGISTERS_TABLE_67 0x3fc48 +#define ixMC_REGISTERS_TABLE_68 0x3fc4c +#define ixMC_REGISTERS_TABLE_69 0x3fc50 +#define ixMC_REGISTERS_TABLE_70 0x3fc54 +#define ixMC_REGISTERS_TABLE_71 0x3fc58 +#define ixMC_REGISTERS_TABLE_72 0x3fc5c +#define ixMC_REGISTERS_TABLE_73 0x3fc60 +#define ixMC_REGISTERS_TABLE_74 0x3fc64 +#define ixMC_REGISTERS_TABLE_75 0x3fc68 +#define ixMC_REGISTERS_TABLE_76 0x3fc6c +#define ixMC_REGISTERS_TABLE_77 0x3fc70 +#define ixMC_REGISTERS_TABLE_78 0x3fc74 +#define ixMC_REGISTERS_TABLE_79 0x3fc78 +#define ixMC_REGISTERS_TABLE_80 0x3fc7c +#define ixMC_REGISTERS_TABLE_81 0x3fc80 +#define ixMC_REGISTERS_TABLE_82 0x3fc84 +#define ixMC_REGISTERS_TABLE_83 0x3fc88 +#define ixMC_REGISTERS_TABLE_84 0x3fc8c +#define ixMC_REGISTERS_TABLE_85 0x3fc90 +#define ixMC_REGISTERS_TABLE_86 0x3fc94 +#define ixMC_REGISTERS_TABLE_87 0x3fc98 +#define ixMC_REGISTERS_TABLE_88 0x3fc9c +#define ixMC_REGISTERS_TABLE_89 0x3fca0 +#define ixMC_REGISTERS_TABLE_90 0x3fca4 +#define ixMC_REGISTERS_TABLE_91 0x3fca8 +#define ixMC_REGISTERS_TABLE_92 0x3fcac +#define ixMC_REGISTERS_TABLE_93 0x3fcb0 +#define ixMC_REGISTERS_TABLE_94 0x3fcb4 +#define ixMC_REGISTERS_TABLE_95 0x3fcb8 +#define ixMC_REGISTERS_TABLE_96 0x3fcbc +#define ixMC_REGISTERS_TABLE_97 0x3fcc0 +#define ixMC_REGISTERS_TABLE_98 0x3fcc4 +#define ixMC_REGISTERS_TABLE_99 0x3fcc8 +#define ixMC_REGISTERS_TABLE_100 0x3fccc +#define ixMC_REGISTERS_TABLE_101 0x3fcd0 +#define ixMC_REGISTERS_TABLE_102 0x3fcd4 +#define ixMC_REGISTERS_TABLE_103 0x3fcd8 +#define ixMC_REGISTERS_TABLE_104 0x3fcdc +#define ixMC_REGISTERS_TABLE_105 0x3fce0 +#define ixMC_REGISTERS_TABLE_106 0x3fce4 +#define ixMC_REGISTERS_TABLE_107 0x3fce8 +#define ixMC_REGISTERS_TABLE_108 0x3fcec +#define ixMC_REGISTERS_TABLE_109 0x3fcf0 +#define ixMC_REGISTERS_TABLE_110 0x3fcf4 +#define ixMC_REGISTERS_TABLE_111 0x3fcf8 +#define ixMC_REGISTERS_TABLE_112 0x3fcfc +#define ixMC_REGISTERS_TABLE_113 0x3fd00 +#define ixFAN_TABLE_1 0x3fd04 +#define ixFAN_TABLE_2 0x3fd08 +#define ixFAN_TABLE_3 0x3fd0c +#define ixFAN_TABLE_4 0x3fd10 +#define ixFAN_TABLE_5 0x3fd14 +#define ixFAN_TABLE_6 0x3fd18 +#define ixFAN_TABLE_7 0x3fd1c +#define ixFAN_TABLE_8 0x3fd20 +#define ixFAN_TABLE_9 0x3fd24 +#define ixSOFT_REGISTERS_TABLE_1 0x3fd28 +#define ixSOFT_REGISTERS_TABLE_2 0x3fd2c +#define ixSOFT_REGISTERS_TABLE_3 0x3fd30 +#define ixSOFT_REGISTERS_TABLE_4 0x3fd34 +#define ixSOFT_REGISTERS_TABLE_5 0x3fd38 +#define ixSOFT_REGISTERS_TABLE_6 0x3fd3c +#define ixSOFT_REGISTERS_TABLE_7 0x3fd40 +#define ixSOFT_REGISTERS_TABLE_8 0x3fd44 +#define ixSOFT_REGISTERS_TABLE_9 0x3fd48 +#define ixSOFT_REGISTERS_TABLE_10 0x3fd4c +#define ixSOFT_REGISTERS_TABLE_11 0x3fd50 +#define ixSOFT_REGISTERS_TABLE_12 0x3fd54 +#define ixSOFT_REGISTERS_TABLE_13 0x3fd58 +#define ixSOFT_REGISTERS_TABLE_14 0x3fd5c +#define ixSOFT_REGISTERS_TABLE_15 0x3fd60 +#define ixSOFT_REGISTERS_TABLE_16 0x3fd64 +#define ixSOFT_REGISTERS_TABLE_17 0x3fd68 +#define ixSOFT_REGISTERS_TABLE_18 0x3fd6c +#define ixSOFT_REGISTERS_TABLE_19 0x3fd70 +#define ixSOFT_REGISTERS_TABLE_20 0x3fd74 +#define ixSOFT_REGISTERS_TABLE_21 0x3fd78 +#define ixSOFT_REGISTERS_TABLE_22 0x3fd7c +#define ixSOFT_REGISTERS_TABLE_23 0x3fd80 +#define ixSOFT_REGISTERS_TABLE_24 0x3fd84 +#define ixSOFT_REGISTERS_TABLE_25 0x3fd88 +#define ixSOFT_REGISTERS_TABLE_26 0x3fd8c +#define ixSOFT_REGISTERS_TABLE_27 0x3fd90 +#define ixSOFT_REGISTERS_TABLE_28 0x3fd94 +#define ixSOFT_REGISTERS_TABLE_29 0x3fd98 +#define ixSOFT_REGISTERS_TABLE_30 0x3fd9c +#define ixPM_FUSES_1 0x3fda0 +#define ixPM_FUSES_2 0x3fda4 +#define ixPM_FUSES_3 0x3fda8 +#define ixPM_FUSES_4 0x3fdac +#define ixPM_FUSES_5 0x3fdb0 +#define ixPM_FUSES_6 0x3fdb4 +#define ixPM_FUSES_7 0x3fdb8 +#define ixPM_FUSES_8 0x3fdbc +#define ixPM_FUSES_9 0x3fdc0 +#define ixPM_FUSES_10 0x3fdc4 +#define ixPM_FUSES_11 0x3fdc8 +#define ixPM_FUSES_12 0x3fdcc +#define ixPM_FUSES_13 0x3fdd0 +#define ixPM_FUSES_14 0x3fdd4 +#define ixPM_FUSES_15 0x3fdd8 +#define ixPM_FUSES_16 0x3fddc +#define ixPM_FUSES_17 0x3fde0 +#define ixPM_FUSES_18 0x3fde4 +#define ixPM_FUSES_19 0x3fde8 +#define ixSMU_PM_STATUS_0 0x3fe00 +#define ixSMU_PM_STATUS_1 0x3fe04 +#define ixSMU_PM_STATUS_2 0x3fe08 +#define ixSMU_PM_STATUS_3 0x3fe0c +#define ixSMU_PM_STATUS_4 0x3fe10 +#define ixSMU_PM_STATUS_5 0x3fe14 +#define ixSMU_PM_STATUS_6 0x3fe18 +#define ixSMU_PM_STATUS_7 0x3fe1c +#define ixSMU_PM_STATUS_8 0x3fe20 +#define ixSMU_PM_STATUS_9 0x3fe24 +#define ixSMU_PM_STATUS_10 0x3fe28 +#define ixSMU_PM_STATUS_11 0x3fe2c +#define ixSMU_PM_STATUS_12 0x3fe30 +#define ixSMU_PM_STATUS_13 0x3fe34 +#define ixSMU_PM_STATUS_14 0x3fe38 +#define ixSMU_PM_STATUS_15 0x3fe3c +#define ixSMU_PM_STATUS_16 0x3fe40 +#define ixSMU_PM_STATUS_17 0x3fe44 +#define ixSMU_PM_STATUS_18 0x3fe48 +#define ixSMU_PM_STATUS_19 0x3fe4c +#define ixSMU_PM_STATUS_20 0x3fe50 +#define ixSMU_PM_STATUS_21 0x3fe54 +#define ixSMU_PM_STATUS_22 0x3fe58 +#define ixSMU_PM_STATUS_23 0x3fe5c +#define ixSMU_PM_STATUS_24 0x3fe60 +#define ixSMU_PM_STATUS_25 0x3fe64 +#define ixSMU_PM_STATUS_26 0x3fe68 +#define ixSMU_PM_STATUS_27 0x3fe6c +#define ixSMU_PM_STATUS_28 0x3fe70 +#define ixSMU_PM_STATUS_29 0x3fe74 +#define ixSMU_PM_STATUS_30 0x3fe78 +#define ixSMU_PM_STATUS_31 0x3fe7c +#define ixSMU_PM_STATUS_32 0x3fe80 +#define ixSMU_PM_STATUS_33 0x3fe84 +#define ixSMU_PM_STATUS_34 0x3fe88 +#define ixSMU_PM_STATUS_35 0x3fe8c +#define ixSMU_PM_STATUS_36 0x3fe90 +#define ixSMU_PM_STATUS_37 0x3fe94 +#define ixSMU_PM_STATUS_38 0x3fe98 +#define ixSMU_PM_STATUS_39 0x3fe9c +#define ixSMU_PM_STATUS_40 0x3fea0 +#define ixSMU_PM_STATUS_41 0x3fea4 +#define ixSMU_PM_STATUS_42 0x3fea8 +#define ixSMU_PM_STATUS_43 0x3feac +#define ixSMU_PM_STATUS_44 0x3feb0 +#define ixSMU_PM_STATUS_45 0x3feb4 +#define ixSMU_PM_STATUS_46 0x3feb8 +#define ixSMU_PM_STATUS_47 0x3febc +#define ixSMU_PM_STATUS_48 0x3fec0 +#define ixSMU_PM_STATUS_49 0x3fec4 +#define ixSMU_PM_STATUS_50 0x3fec8 +#define ixSMU_PM_STATUS_51 0x3fecc +#define ixSMU_PM_STATUS_52 0x3fed0 +#define ixSMU_PM_STATUS_53 0x3fed4 +#define ixSMU_PM_STATUS_54 0x3fed8 +#define ixSMU_PM_STATUS_55 0x3fedc +#define ixSMU_PM_STATUS_56 0x3fee0 +#define ixSMU_PM_STATUS_57 0x3fee4 +#define ixSMU_PM_STATUS_58 0x3fee8 +#define ixSMU_PM_STATUS_59 0x3feec +#define ixSMU_PM_STATUS_60 0x3fef0 +#define ixSMU_PM_STATUS_61 0x3fef4 +#define ixSMU_PM_STATUS_62 0x3fef8 +#define ixSMU_PM_STATUS_63 0x3fefc +#define ixSMU_PM_STATUS_64 0x3ff00 +#define ixSMU_PM_STATUS_65 0x3ff04 +#define ixSMU_PM_STATUS_66 0x3ff08 +#define ixSMU_PM_STATUS_67 0x3ff0c +#define ixSMU_PM_STATUS_68 0x3ff10 +#define ixSMU_PM_STATUS_69 0x3ff14 +#define ixSMU_PM_STATUS_70 0x3ff18 +#define ixSMU_PM_STATUS_71 0x3ff1c +#define ixSMU_PM_STATUS_72 0x3ff20 +#define ixSMU_PM_STATUS_73 0x3ff24 +#define ixSMU_PM_STATUS_74 0x3ff28 +#define ixSMU_PM_STATUS_75 0x3ff2c +#define ixSMU_PM_STATUS_76 0x3ff30 +#define ixSMU_PM_STATUS_77 0x3ff34 +#define ixSMU_PM_STATUS_78 0x3ff38 +#define ixSMU_PM_STATUS_79 0x3ff3c +#define ixSMU_PM_STATUS_80 0x3ff40 +#define ixSMU_PM_STATUS_81 0x3ff44 +#define ixSMU_PM_STATUS_82 0x3ff48 +#define ixSMU_PM_STATUS_83 0x3ff4c +#define ixSMU_PM_STATUS_84 0x3ff50 +#define ixSMU_PM_STATUS_85 0x3ff54 +#define ixSMU_PM_STATUS_86 0x3ff58 +#define ixSMU_PM_STATUS_87 0x3ff5c +#define ixSMU_PM_STATUS_88 0x3ff60 +#define ixSMU_PM_STATUS_89 0x3ff64 +#define ixSMU_PM_STATUS_90 0x3ff68 +#define ixSMU_PM_STATUS_91 0x3ff6c +#define ixSMU_PM_STATUS_92 0x3ff70 +#define ixSMU_PM_STATUS_93 0x3ff74 +#define ixSMU_PM_STATUS_94 0x3ff78 +#define ixSMU_PM_STATUS_95 0x3ff7c +#define ixSMU_PM_STATUS_96 0x3ff80 +#define ixSMU_PM_STATUS_97 0x3ff84 +#define ixSMU_PM_STATUS_98 0x3ff88 +#define ixSMU_PM_STATUS_99 0x3ff8c +#define ixSMU_PM_STATUS_100 0x3ff90 +#define ixSMU_PM_STATUS_101 0x3ff94 +#define ixSMU_PM_STATUS_102 0x3ff98 +#define ixSMU_PM_STATUS_103 0x3ff9c +#define ixSMU_PM_STATUS_104 0x3ffa0 +#define ixSMU_PM_STATUS_105 0x3ffa4 +#define ixSMU_PM_STATUS_106 0x3ffa8 +#define ixSMU_PM_STATUS_107 0x3ffac +#define ixSMU_PM_STATUS_108 0x3ffb0 +#define ixSMU_PM_STATUS_109 0x3ffb4 +#define ixSMU_PM_STATUS_110 0x3ffb8 +#define ixSMU_PM_STATUS_111 0x3ffbc +#define ixSMU_PM_STATUS_112 0x3ffc0 +#define ixSMU_PM_STATUS_113 0x3ffc4 +#define ixSMU_PM_STATUS_114 0x3ffc8 +#define ixSMU_PM_STATUS_115 0x3ffcc +#define ixSMU_PM_STATUS_116 0x3ffd0 +#define ixSMU_PM_STATUS_117 0x3ffd4 +#define ixSMU_PM_STATUS_118 0x3ffd8 +#define ixSMU_PM_STATUS_119 0x3ffdc +#define ixSMU_PM_STATUS_120 0x3ffe0 +#define ixSMU_PM_STATUS_121 0x3ffe4 +#define ixSMU_PM_STATUS_122 0x3ffe8 +#define ixSMU_PM_STATUS_123 0x3ffec +#define ixSMU_PM_STATUS_124 0x3fff0 +#define ixSMU_PM_STATUS_125 0x3fff4 +#define ixSMU_PM_STATUS_126 0x3fff8 +#define ixSMU_PM_STATUS_127 0x3fffc +#define ixCG_THERMAL_INT_ENA 0xc2100024 +#define ixCG_THERMAL_INT_CTRL 0xc2100028 +#define ixCG_THERMAL_INT_STATUS 0xc210002c +#define ixCG_THERMAL_CTRL 0xc0300004 +#define ixCG_THERMAL_STATUS 0xc0300008 +#define ixCG_THERMAL_INT 0xc030000c +#define ixCG_MULT_THERMAL_CTRL 0xc0300010 +#define ixCG_MULT_THERMAL_STATUS 0xc0300014 +#define ixCG_FDO_CTRL0 0xc0300064 +#define ixCG_FDO_CTRL1 0xc0300068 +#define ixCG_FDO_CTRL2 0xc030006c +#define ixCG_TACH_CTRL 0xc0300070 +#define ixCG_TACH_STATUS 0xc0300074 +#define ixCC_THM_STRAPS0 0xc0300080 +#define ixTHM_TMON0_RDIL0_DATA 0xc0300100 +#define ixTHM_TMON0_RDIL1_DATA 0xc0300104 +#define ixTHM_TMON0_RDIL2_DATA 0xc0300108 +#define ixTHM_TMON0_RDIL3_DATA 0xc030010c +#define ixTHM_TMON0_RDIL4_DATA 0xc0300110 +#define ixTHM_TMON0_RDIL5_DATA 0xc0300114 +#define ixTHM_TMON0_RDIL6_DATA 0xc0300118 +#define ixTHM_TMON0_RDIL7_DATA 0xc030011c +#define ixTHM_TMON0_RDIL8_DATA 0xc0300120 +#define ixTHM_TMON0_RDIL9_DATA 0xc0300124 +#define ixTHM_TMON0_RDIL10_DATA 0xc0300128 +#define ixTHM_TMON0_RDIL11_DATA 0xc030012c +#define ixTHM_TMON0_RDIL12_DATA 0xc0300130 +#define ixTHM_TMON0_RDIL13_DATA 0xc0300134 +#define ixTHM_TMON0_RDIL14_DATA 0xc0300138 +#define ixTHM_TMON0_RDIL15_DATA 0xc030013c +#define ixTHM_TMON0_RDIR0_DATA 0xc0300140 +#define ixTHM_TMON0_RDIR1_DATA 0xc0300144 +#define ixTHM_TMON0_RDIR2_DATA 0xc0300148 +#define ixTHM_TMON0_RDIR3_DATA 0xc030014c +#define ixTHM_TMON0_RDIR4_DATA 0xc0300150 +#define ixTHM_TMON0_RDIR5_DATA 0xc0300154 +#define ixTHM_TMON0_RDIR6_DATA 0xc0300158 +#define ixTHM_TMON0_RDIR7_DATA 0xc030015c +#define ixTHM_TMON0_RDIR8_DATA 0xc0300160 +#define ixTHM_TMON0_RDIR9_DATA 0xc0300164 +#define ixTHM_TMON0_RDIR10_DATA 0xc0300168 +#define ixTHM_TMON0_RDIR11_DATA 0xc030016c +#define ixTHM_TMON0_RDIR12_DATA 0xc0300170 +#define ixTHM_TMON0_RDIR13_DATA 0xc0300174 +#define ixTHM_TMON0_RDIR14_DATA 0xc0300178 +#define ixTHM_TMON0_RDIR15_DATA 0xc030017c +#define ixTHM_TMON0_INT_DATA 0xc0300300 +#define ixTHM_TMON0_DEBUG 0xc0300310 +#define ixGENERAL_PWRMGT 0xc0200000 +#define ixCNB_PWRMGT_CNTL 0xc0200004 +#define ixSCLK_PWRMGT_CNTL 0xc0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 +#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 +#define ixPLL_TEST_CNTL 0xc020003c +#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 +#define ixCG_DISPLAY_GAP_CNTL 0xc0200060 +#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 +#define ixCG_ACPI_CNTL 0xc0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 +#define ixCG_ULV_PARAMETER 0xc020015c +#define ixSCLK_MIN_DIV 0xc0200308 +#define ixLCAC_SX0_CNTL 0xc0400d00 +#define ixLCAC_SX0_OVR_SEL 0xc0400d04 +#define ixLCAC_SX0_OVR_VAL 0xc0400d08 +#define ixLCAC_MC0_CNTL 0xc0400d30 +#define ixLCAC_MC0_OVR_SEL 0xc0400d34 +#define ixLCAC_MC0_OVR_VAL 0xc0400d38 +#define ixLCAC_MC1_CNTL 0xc0400d3c +#define ixLCAC_MC1_OVR_SEL 0xc0400d40 +#define ixLCAC_MC1_OVR_VAL 0xc0400d44 +#define ixLCAC_MC2_CNTL 0xc0400d48 +#define ixLCAC_MC2_OVR_SEL 0xc0400d4c +#define ixLCAC_MC2_OVR_VAL 0xc0400d50 +#define ixLCAC_MC3_CNTL 0xc0400d54 +#define ixLCAC_MC3_OVR_SEL 0xc0400d58 +#define ixLCAC_MC3_OVR_VAL 0xc0400d5c +#define ixLCAC_CPL_CNTL 0xc0400d80 +#define ixLCAC_CPL_OVR_SEL 0xc0400d84 +#define ixLCAC_CPL_OVR_VAL 0xc0400d88 +#define mmROM_SMC_IND_INDEX 0x80 +#define mmROM0_ROM_SMC_IND_INDEX 0x80 +#define mmROM1_ROM_SMC_IND_INDEX 0x82 +#define mmROM2_ROM_SMC_IND_INDEX 0x84 +#define mmROM3_ROM_SMC_IND_INDEX 0x86 +#define mmROM_SMC_IND_DATA 0x81 +#define mmROM0_ROM_SMC_IND_DATA 0x81 +#define mmROM1_ROM_SMC_IND_DATA 0x83 +#define mmROM2_ROM_SMC_IND_DATA 0x85 +#define mmROM3_ROM_SMC_IND_DATA 0x87 +#define ixROM_CNTL 0xc0600000 +#define ixPAGE_MIRROR_CNTL 0xc0600004 +#define ixROM_STATUS 0xc0600008 +#define ixCGTT_ROM_CLK_CTRL0 0xc060000c +#define ixROM_INDEX 0xc0600010 +#define ixROM_DATA 0xc0600014 +#define ixROM_START 0xc0600018 +#define ixROM_SW_CNTL 0xc060001c +#define ixROM_SW_STATUS 0xc0600020 +#define ixROM_SW_COMMAND 0xc0600024 +#define ixROM_SW_DATA_1 0xc0600028 +#define ixROM_SW_DATA_2 0xc060002c +#define ixROM_SW_DATA_3 0xc0600030 +#define ixROM_SW_DATA_4 0xc0600034 +#define ixROM_SW_DATA_5 0xc0600038 +#define ixROM_SW_DATA_6 0xc060003c +#define ixROM_SW_DATA_7 0xc0600040 +#define ixROM_SW_DATA_8 0xc0600044 +#define ixROM_SW_DATA_9 0xc0600048 +#define ixROM_SW_DATA_10 0xc060004c +#define ixROM_SW_DATA_11 0xc0600050 +#define ixROM_SW_DATA_12 0xc0600054 +#define ixROM_SW_DATA_13 0xc0600058 +#define ixROM_SW_DATA_14 0xc060005c +#define ixROM_SW_DATA_15 0xc0600060 +#define ixROM_SW_DATA_16 0xc0600064 +#define ixROM_SW_DATA_17 0xc0600068 +#define ixROM_SW_DATA_18 0xc060006c +#define ixROM_SW_DATA_19 0xc0600070 +#define ixROM_SW_DATA_20 0xc0600074 +#define ixROM_SW_DATA_21 0xc0600078 +#define ixROM_SW_DATA_22 0xc060007c +#define ixROM_SW_DATA_23 0xc0600080 +#define ixROM_SW_DATA_24 0xc0600084 +#define ixROM_SW_DATA_25 0xc0600088 +#define ixROM_SW_DATA_26 0xc060008c +#define ixROM_SW_DATA_27 0xc0600090 +#define ixROM_SW_DATA_28 0xc0600094 +#define ixROM_SW_DATA_29 0xc0600098 +#define ixROM_SW_DATA_30 0xc060009c +#define ixROM_SW_DATA_31 0xc06000a0 +#define ixROM_SW_DATA_32 0xc06000a4 +#define ixROM_SW_DATA_33 0xc06000a8 +#define ixROM_SW_DATA_34 0xc06000ac +#define ixROM_SW_DATA_35 0xc06000b0 +#define ixROM_SW_DATA_36 0xc06000b4 +#define ixROM_SW_DATA_37 0xc06000b8 +#define ixROM_SW_DATA_38 0xc06000bc +#define ixROM_SW_DATA_39 0xc06000c0 +#define ixROM_SW_DATA_40 0xc06000c4 +#define ixROM_SW_DATA_41 0xc06000c8 +#define ixROM_SW_DATA_42 0xc06000cc +#define ixROM_SW_DATA_43 0xc06000d0 +#define ixROM_SW_DATA_44 0xc06000d4 +#define ixROM_SW_DATA_45 0xc06000d8 +#define ixROM_SW_DATA_46 0xc06000dc +#define ixROM_SW_DATA_47 0xc06000e0 +#define ixROM_SW_DATA_48 0xc06000e4 +#define ixROM_SW_DATA_49 0xc06000e8 +#define ixROM_SW_DATA_50 0xc06000ec +#define ixROM_SW_DATA_51 0xc06000f0 +#define ixROM_SW_DATA_52 0xc06000f4 +#define ixROM_SW_DATA_53 0xc06000f8 +#define ixROM_SW_DATA_54 0xc06000fc +#define ixROM_SW_DATA_55 0xc0600110 +#define ixROM_SW_DATA_56 0xc0600114 +#define ixROM_SW_DATA_57 0xc0600118 +#define ixROM_SW_DATA_58 0xc060011c +#define ixROM_SW_DATA_59 0xc0600120 +#define ixROM_SW_DATA_60 0xc0600124 +#define ixROM_SW_DATA_61 0xc0600128 +#define ixROM_SW_DATA_62 0xc060012c +#define ixROM_SW_DATA_63 0xc0600130 +#define ixROM_SW_DATA_64 0xc0600134 + +#endif /* SMU_7_0_1_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h new file mode 100644 index 000000000000..25882a4dea5d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h @@ -0,0 +1,5456 @@ +/* + * SMU_7_0_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_0_1_SH_MASK_H +#define SMU_7_0_1_SH_MASK_H + +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f +#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 +#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f +#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 +#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f +#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 +#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f +#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d +#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 +#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 +#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 +#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 +#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 +#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 +#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1 +#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa +#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff +#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 +#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 +#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 +#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 +#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa +#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 +#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_0__SMC_RESP_MASK 0xffff +#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_1__SMC_RESP_MASK 0xffff +#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_2__SMC_RESP_MASK 0xffff +#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_3__SMC_RESP_MASK 0xffff +#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_4__SMC_RESP_MASK 0xffff +#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_5__SMC_RESP_MASK 0xffff +#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_6__SMC_RESP_MASK 0xffff +#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_7__SMC_RESP_MASK 0xffff +#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_8__SMC_RESP_MASK 0xffff +#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_9__SMC_RESP_MASK 0xffff +#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_10__SMC_RESP_MASK 0xffff +#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_11__SMC_RESP_MASK 0xffff +#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 +#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 +#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 +#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 +#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 +#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffff +#define SMC_PC_C__smc_pc_c__SHIFT 0x0 +#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff +#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4 +#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff +#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 +#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff +#define GPIOPAD_A__GPIO_A__SHIFT 0x0 +#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff +#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0 +#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff +#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f +#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff +#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000 +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f +#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6 +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0 +#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff +#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 +#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff +#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 +#define CG_FPS_CNT__FPS_CNT_MASK 0xff +#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 +#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 +#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3 +#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 +#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 +#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 +#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa +#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 +#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 +#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 +#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 +#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 +#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 +#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 +#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 +#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 +#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 +#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 +#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 +#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 +#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 +#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 +#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 +#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 +#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 +#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 +#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 +#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 +#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 +#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 +#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa +#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000 +#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000 +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000 +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11 +#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000 +#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14 +#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000 +#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17 +#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000 +#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18 +#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfe000000 +#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 +#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc +#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 +#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 +#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 +#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 +#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c +#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 +#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d +#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff +#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 +#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 +#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 +#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 +#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 +#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 +#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 +#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e +#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 +#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a +#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 +#define SMU_STATUS__SMU_DONE_MASK 0x1 +#define SMU_STATUS__SMU_DONE__SHIFT 0x0 +#define SMU_STATUS__SMU_PASS_MASK 0x2 +#define SMU_STATUS__SMU_PASS__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 +#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 +#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 +#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 +#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 +#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 +#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 +#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 +#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 +#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff +#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 +#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 +#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f +#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff +#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 +#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff +#define DPM_TABLE_28__SystemFlags__SHIFT 0x0 +#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff +#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0 +#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff +#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0 +#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff +#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0 +#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff +#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0 +#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff +#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0 +#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff +#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0 +#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff +#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff +#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff +#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff +#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff +#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000 +#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10 +#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff +#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0 +#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00 +#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000 +#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10 +#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff +#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0 +#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00 +#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000 +#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10 +#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff +#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0 +#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00 +#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000 +#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10 +#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff +#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0 +#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00 +#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff +#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff +#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff +#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff +#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff +#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff +#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff +#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff +#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_68__UvdLevelCount_MASK 0xff +#define DPM_TABLE_68__UvdLevelCount__SHIFT 0x0 +#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00 +#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8 +#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000 +#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10 +#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000 +#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18 +#define DPM_TABLE_69__padding2_MASK 0xff +#define DPM_TABLE_69__padding2__SHIFT 0x0 +#define DPM_TABLE_69__SamuLevelCount_MASK 0xff00 +#define DPM_TABLE_69__SamuLevelCount__SHIFT 0x8 +#define DPM_TABLE_69__AcpLevelCount_MASK 0xff0000 +#define DPM_TABLE_69__AcpLevelCount__SHIFT 0x10 +#define DPM_TABLE_69__VceLevelCount_MASK 0xff000000 +#define DPM_TABLE_69__VceLevelCount__SHIFT 0x18 +#define DPM_TABLE_70__Reserved_0_MASK 0xffffffff +#define DPM_TABLE_70__Reserved_0__SHIFT 0x0 +#define DPM_TABLE_71__Reserved_1_MASK 0xffffffff +#define DPM_TABLE_71__Reserved_1__SHIFT 0x0 +#define DPM_TABLE_72__Reserved_2_MASK 0xffffffff +#define DPM_TABLE_72__Reserved_2__SHIFT 0x0 +#define DPM_TABLE_73__Reserved_3_MASK 0xffffffff +#define DPM_TABLE_73__Reserved_3__SHIFT 0x0 +#define DPM_TABLE_74__Reserved_4_MASK 0xffffffff +#define DPM_TABLE_74__Reserved_4__SHIFT 0x0 +#define DPM_TABLE_75__GraphicsLevel_0_Flags_MASK 0xffffffff +#define DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT 0x0 +#define DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK 0xffff +#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_79__GraphicsLevel_0_padding1_1_MASK 0xff0000 +#define DPM_TABLE_79__GraphicsLevel_0_padding1_1__SHIFT 0x10 +#define DPM_TABLE_79__GraphicsLevel_0_padding1_0_MASK 0xff000000 +#define DPM_TABLE_79__GraphicsLevel_0_padding1_0__SHIFT 0x18 +#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK 0xff000000 +#define DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT 0x18 +#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK 0xff +#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_89__GraphicsLevel_1_Flags_MASK 0xffffffff +#define DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT 0x0 +#define DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK 0xffff +#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_93__GraphicsLevel_1_padding1_1_MASK 0xff0000 +#define DPM_TABLE_93__GraphicsLevel_1_padding1_1__SHIFT 0x10 +#define DPM_TABLE_93__GraphicsLevel_1_padding1_0_MASK 0xff000000 +#define DPM_TABLE_93__GraphicsLevel_1_padding1_0__SHIFT 0x18 +#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK 0xff000000 +#define DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT 0x18 +#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK 0xff +#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_103__GraphicsLevel_2_Flags_MASK 0xffffffff +#define DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT 0x0 +#define DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK 0xffff +#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_107__GraphicsLevel_2_padding1_1_MASK 0xff0000 +#define DPM_TABLE_107__GraphicsLevel_2_padding1_1__SHIFT 0x10 +#define DPM_TABLE_107__GraphicsLevel_2_padding1_0_MASK 0xff000000 +#define DPM_TABLE_107__GraphicsLevel_2_padding1_0__SHIFT 0x18 +#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK 0xff000000 +#define DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT 0x18 +#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK 0xff +#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_117__GraphicsLevel_3_Flags_MASK 0xffffffff +#define DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT 0x0 +#define DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK 0xffff +#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_3_padding1_1_MASK 0xff0000 +#define DPM_TABLE_121__GraphicsLevel_3_padding1_1__SHIFT 0x10 +#define DPM_TABLE_121__GraphicsLevel_3_padding1_0_MASK 0xff000000 +#define DPM_TABLE_121__GraphicsLevel_3_padding1_0__SHIFT 0x18 +#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK 0xff000000 +#define DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT 0x18 +#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK 0xff +#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_131__GraphicsLevel_4_Flags_MASK 0xffffffff +#define DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT 0x0 +#define DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK 0xffffffff +#define DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT 0x0 +#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK 0xffff +#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_4_padding1_1_MASK 0xff0000 +#define DPM_TABLE_135__GraphicsLevel_4_padding1_1__SHIFT 0x10 +#define DPM_TABLE_135__GraphicsLevel_4_padding1_0_MASK 0xff000000 +#define DPM_TABLE_135__GraphicsLevel_4_padding1_0__SHIFT 0x18 +#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK 0xff000000 +#define DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT 0x18 +#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK 0xff +#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_145__GraphicsLevel_5_Flags_MASK 0xffffffff +#define DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT 0x0 +#define DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK 0xffffffff +#define DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT 0x0 +#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK 0xffff +#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_5_padding1_1_MASK 0xff0000 +#define DPM_TABLE_149__GraphicsLevel_5_padding1_1__SHIFT 0x10 +#define DPM_TABLE_149__GraphicsLevel_5_padding1_0_MASK 0xff000000 +#define DPM_TABLE_149__GraphicsLevel_5_padding1_0__SHIFT 0x18 +#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK 0xff000000 +#define DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT 0x18 +#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK 0xff +#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_159__GraphicsLevel_6_Flags_MASK 0xffffffff +#define DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT 0x0 +#define DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK 0xffffffff +#define DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT 0x0 +#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_padding1_1_MASK 0xff0000 +#define DPM_TABLE_163__GraphicsLevel_6_padding1_1__SHIFT 0x10 +#define DPM_TABLE_163__GraphicsLevel_6_padding1_0_MASK 0xff000000 +#define DPM_TABLE_163__GraphicsLevel_6_padding1_0__SHIFT 0x18 +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18 +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18 +#define DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_173__GraphicsLevel_7_Flags_MASK 0xffffffff +#define DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT 0x0 +#define DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK 0xffffffff +#define DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT 0x0 +#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK 0xffff +#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_177__GraphicsLevel_7_padding1_1_MASK 0xff0000 +#define DPM_TABLE_177__GraphicsLevel_7_padding1_1__SHIFT 0x10 +#define DPM_TABLE_177__GraphicsLevel_7_padding1_0_MASK 0xff000000 +#define DPM_TABLE_177__GraphicsLevel_7_padding1_0__SHIFT 0x18 +#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK 0xff000000 +#define DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT 0x18 +#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK 0xff +#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK 0xff0000 +#define DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT 0x10 +#define DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK 0xff000000 +#define DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT 0x18 +#define DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK 0xffffffff +#define DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT 0x0 +#define DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK 0xff +#define DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK 0xff00 +#define DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT 0x8 +#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK 0xff +#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_194__MemoryACPILevel_padding_MASK 0xff +#define DPM_TABLE_194__MemoryACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK 0xff0000 +#define DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT 0x10 +#define DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK 0xff000000 +#define DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT 0x18 +#define DPM_TABLE_195__MemoryACPILevel_padding1_1_MASK 0xff +#define DPM_TABLE_195__MemoryACPILevel_padding1_1__SHIFT 0x0 +#define DPM_TABLE_195__MemoryACPILevel_padding1_0_MASK 0xff00 +#define DPM_TABLE_195__MemoryACPILevel_padding1_0__SHIFT 0x8 +#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK 0xffffffff +#define DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT 0x0 +#define DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK 0xffffffff +#define DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT 0x0 +#define DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK 0xff +#define DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK 0xff00 +#define DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT 0x8 +#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK 0xff +#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_212__MemoryLevel_0_padding_MASK 0xff +#define DPM_TABLE_212__MemoryLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_213__MemoryLevel_0_padding1_1_MASK 0xff +#define DPM_TABLE_213__MemoryLevel_0_padding1_1__SHIFT 0x0 +#define DPM_TABLE_213__MemoryLevel_0_padding1_0_MASK 0xff00 +#define DPM_TABLE_213__MemoryLevel_0_padding1_0__SHIFT 0x8 +#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK 0xffffffff +#define DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT 0x0 +#define DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK 0xffffffff +#define DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT 0x0 +#define DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK 0xff +#define DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK 0xff00 +#define DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT 0x8 +#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK 0xff +#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_230__MemoryLevel_1_padding_MASK 0xff +#define DPM_TABLE_230__MemoryLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_231__MemoryLevel_1_padding1_1_MASK 0xff +#define DPM_TABLE_231__MemoryLevel_1_padding1_1__SHIFT 0x0 +#define DPM_TABLE_231__MemoryLevel_1_padding1_0_MASK 0xff00 +#define DPM_TABLE_231__MemoryLevel_1_padding1_0__SHIFT 0x8 +#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK 0xffffffff +#define DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT 0x0 +#define DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK 0xffffffff +#define DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT 0x0 +#define DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK 0xff +#define DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK 0xff00 +#define DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT 0x8 +#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK 0xff +#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_248__MemoryLevel_2_padding_MASK 0xff +#define DPM_TABLE_248__MemoryLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_249__MemoryLevel_2_padding1_1_MASK 0xff +#define DPM_TABLE_249__MemoryLevel_2_padding1_1__SHIFT 0x0 +#define DPM_TABLE_249__MemoryLevel_2_padding1_0_MASK 0xff00 +#define DPM_TABLE_249__MemoryLevel_2_padding1_0__SHIFT 0x8 +#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK 0xffffffff +#define DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT 0x0 +#define DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK 0xffffffff +#define DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT 0x0 +#define DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK 0xff +#define DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK 0xff00 +#define DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT 0x8 +#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK 0xff +#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_266__MemoryLevel_3_padding_MASK 0xff +#define DPM_TABLE_266__MemoryLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_267__MemoryLevel_3_padding1_1_MASK 0xff +#define DPM_TABLE_267__MemoryLevel_3_padding1_1__SHIFT 0x0 +#define DPM_TABLE_267__MemoryLevel_3_padding1_0_MASK 0xff00 +#define DPM_TABLE_267__MemoryLevel_3_padding1_0__SHIFT 0x8 +#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK 0xffffffff +#define DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT 0x0 +#define DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK 0xffffffff +#define DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT 0x0 +#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK 0xffffffff +#define DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT 0x0 +#define DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK 0xff +#define DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK 0xff00 +#define DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT 0x8 +#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK 0xff +#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_284__MemoryLevel_4_padding_MASK 0xff +#define DPM_TABLE_284__MemoryLevel_4_padding__SHIFT 0x0 +#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_285__MemoryLevel_4_padding1_1_MASK 0xff +#define DPM_TABLE_285__MemoryLevel_4_padding1_1__SHIFT 0x0 +#define DPM_TABLE_285__MemoryLevel_4_padding1_0_MASK 0xff00 +#define DPM_TABLE_285__MemoryLevel_4_padding1_0__SHIFT 0x8 +#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK 0xffffffff +#define DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT 0x0 +#define DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK 0xffffffff +#define DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT 0x0 +#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK 0xffffffff +#define DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT 0x0 +#define DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK 0xff +#define DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK 0xff00 +#define DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT 0x8 +#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK 0xff +#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_302__MemoryLevel_5_padding_MASK 0xff +#define DPM_TABLE_302__MemoryLevel_5_padding__SHIFT 0x0 +#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_303__MemoryLevel_5_padding1_1_MASK 0xff +#define DPM_TABLE_303__MemoryLevel_5_padding1_1__SHIFT 0x0 +#define DPM_TABLE_303__MemoryLevel_5_padding1_0_MASK 0xff00 +#define DPM_TABLE_303__MemoryLevel_5_padding1_0__SHIFT 0x8 +#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK 0xffffffff +#define DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT 0x0 +#define DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_313__LinkLevel_0_Padding_MASK 0xff +#define DPM_TABLE_313__LinkLevel_0_Padding__SHIFT 0x0 +#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_316__LinkLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_317__LinkLevel_1_Padding_MASK 0xff +#define DPM_TABLE_317__LinkLevel_1_Padding__SHIFT 0x0 +#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_320__LinkLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_321__LinkLevel_2_Padding_MASK 0xff +#define DPM_TABLE_321__LinkLevel_2_Padding__SHIFT 0x0 +#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_324__LinkLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_325__LinkLevel_3_Padding_MASK 0xff +#define DPM_TABLE_325__LinkLevel_3_Padding__SHIFT 0x0 +#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_328__LinkLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_329__LinkLevel_4_Padding_MASK 0xff +#define DPM_TABLE_329__LinkLevel_4_Padding__SHIFT 0x0 +#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_332__LinkLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_333__LinkLevel_5_Padding_MASK 0xff +#define DPM_TABLE_333__LinkLevel_5_Padding__SHIFT 0x0 +#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_336__LinkLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_337__LinkLevel_6_Padding_MASK 0xff +#define DPM_TABLE_337__LinkLevel_6_Padding__SHIFT 0x0 +#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_340__LinkLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_341__LinkLevel_7_Padding_MASK 0xff +#define DPM_TABLE_341__LinkLevel_7_Padding__SHIFT 0x0 +#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_344__LinkLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_345__ACPILevel_Flags_MASK 0xffffffff +#define DPM_TABLE_345__ACPILevel_Flags__SHIFT 0x0 +#define DPM_TABLE_346__ACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_346__ACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_348__ACPILevel_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_349__ACPILevel_padding_MASK 0xff +#define DPM_TABLE_349__ACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_349__ACPILevel_SclkDid_MASK 0xff000000 +#define DPM_TABLE_349__ACPILevel_SclkDid__SHIFT 0x18 +#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff +#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0 +#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK 0xff +#define DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_360__UvdLevel_0_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT 0x10 +#define DPM_TABLE_361__UvdLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_361__UvdLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_361__UvdLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK 0xff +#define DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_364__UvdLevel_1_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT 0x10 +#define DPM_TABLE_365__UvdLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_365__UvdLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_365__UvdLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK 0xff +#define DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_368__UvdLevel_2_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT 0x10 +#define DPM_TABLE_369__UvdLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_369__UvdLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_369__UvdLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK 0xff +#define DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_372__UvdLevel_3_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT 0x10 +#define DPM_TABLE_373__UvdLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_373__UvdLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_373__UvdLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK 0xff +#define DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_376__UvdLevel_4_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT 0x10 +#define DPM_TABLE_377__UvdLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_377__UvdLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_377__UvdLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK 0xff +#define DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_380__UvdLevel_5_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT 0x10 +#define DPM_TABLE_381__UvdLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_381__UvdLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_381__UvdLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK 0xff +#define DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_384__UvdLevel_6_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT 0x10 +#define DPM_TABLE_385__UvdLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_385__UvdLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_385__UvdLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK 0xff +#define DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_388__UvdLevel_7_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT 0x10 +#define DPM_TABLE_389__UvdLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_389__UvdLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_389__UvdLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_390__VceLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_390__VceLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_391__VceLevel_0_Divider_MASK 0xff +#define DPM_TABLE_391__VceLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_391__VceLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_391__VceLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_392__VceLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_392__VceLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_393__VceLevel_1_Divider_MASK 0xff +#define DPM_TABLE_393__VceLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_393__VceLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_393__VceLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_394__VceLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_394__VceLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_395__VceLevel_2_Divider_MASK 0xff +#define DPM_TABLE_395__VceLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_395__VceLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_395__VceLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_396__VceLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_396__VceLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_397__VceLevel_3_Divider_MASK 0xff +#define DPM_TABLE_397__VceLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_397__VceLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_397__VceLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_398__VceLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_398__VceLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_399__VceLevel_4_Divider_MASK 0xff +#define DPM_TABLE_399__VceLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_399__VceLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_399__VceLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_400__VceLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_400__VceLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_401__VceLevel_5_Divider_MASK 0xff +#define DPM_TABLE_401__VceLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_401__VceLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_401__VceLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_402__VceLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_402__VceLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_403__VceLevel_6_Divider_MASK 0xff +#define DPM_TABLE_403__VceLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_403__VceLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_403__VceLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_404__VceLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_404__VceLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_405__VceLevel_7_Divider_MASK 0xff +#define DPM_TABLE_405__VceLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_405__VceLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_405__VceLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_406__AcpLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_407__AcpLevel_0_Divider_MASK 0xff +#define DPM_TABLE_407__AcpLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_407__AcpLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_408__AcpLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_409__AcpLevel_1_Divider_MASK 0xff +#define DPM_TABLE_409__AcpLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_409__AcpLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_410__AcpLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_411__AcpLevel_2_Divider_MASK 0xff +#define DPM_TABLE_411__AcpLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_411__AcpLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_412__AcpLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_413__AcpLevel_3_Divider_MASK 0xff +#define DPM_TABLE_413__AcpLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_413__AcpLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_414__AcpLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_415__AcpLevel_4_Divider_MASK 0xff +#define DPM_TABLE_415__AcpLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_415__AcpLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_416__AcpLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_417__AcpLevel_5_Divider_MASK 0xff +#define DPM_TABLE_417__AcpLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_417__AcpLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_418__AcpLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_419__AcpLevel_6_Divider_MASK 0xff +#define DPM_TABLE_419__AcpLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_419__AcpLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_420__AcpLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_421__AcpLevel_7_Divider_MASK 0xff +#define DPM_TABLE_421__AcpLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_421__AcpLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_422__SamuLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_423__SamuLevel_0_Divider_MASK 0xff +#define DPM_TABLE_423__SamuLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_423__SamuLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_424__SamuLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_425__SamuLevel_1_Divider_MASK 0xff +#define DPM_TABLE_425__SamuLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_425__SamuLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_426__SamuLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_427__SamuLevel_2_Divider_MASK 0xff +#define DPM_TABLE_427__SamuLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_427__SamuLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_428__SamuLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_429__SamuLevel_3_Divider_MASK 0xff +#define DPM_TABLE_429__SamuLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_429__SamuLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_430__SamuLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_431__SamuLevel_4_Divider_MASK 0xff +#define DPM_TABLE_431__SamuLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_431__SamuLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_432__SamuLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_433__SamuLevel_5_Divider_MASK 0xff +#define DPM_TABLE_433__SamuLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_433__SamuLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_434__SamuLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_435__SamuLevel_6_Divider_MASK 0xff +#define DPM_TABLE_435__SamuLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_435__SamuLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_436__SamuLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_437__SamuLevel_7_Divider_MASK 0xff +#define DPM_TABLE_437__SamuLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_437__SamuLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_438__Ulv_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_440__Ulv_VddcPhase_MASK 0xff +#define DPM_TABLE_440__Ulv_VddcPhase__SHIFT 0x0 +#define DPM_TABLE_440__Ulv_VddcOffsetVid_MASK 0xff00 +#define DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT 0x8 +#define DPM_TABLE_440__Ulv_VddcOffset_MASK 0xffff0000 +#define DPM_TABLE_440__Ulv_VddcOffset__SHIFT 0x10 +#define DPM_TABLE_441__Ulv_Reserved_MASK 0xffffffff +#define DPM_TABLE_441__Ulv_Reserved__SHIFT 0x0 +#define DPM_TABLE_442__SclkStepSize_MASK 0xffffffff +#define DPM_TABLE_442__SclkStepSize__SHIFT 0x0 +#define DPM_TABLE_443__Smio_0_MASK 0xffffffff +#define DPM_TABLE_443__Smio_0__SHIFT 0x0 +#define DPM_TABLE_444__Smio_1_MASK 0xffffffff +#define DPM_TABLE_444__Smio_1__SHIFT 0x0 +#define DPM_TABLE_445__Smio_2_MASK 0xffffffff +#define DPM_TABLE_445__Smio_2__SHIFT 0x0 +#define DPM_TABLE_446__Smio_3_MASK 0xffffffff +#define DPM_TABLE_446__Smio_3__SHIFT 0x0 +#define DPM_TABLE_447__Smio_4_MASK 0xffffffff +#define DPM_TABLE_447__Smio_4__SHIFT 0x0 +#define DPM_TABLE_448__Smio_5_MASK 0xffffffff +#define DPM_TABLE_448__Smio_5__SHIFT 0x0 +#define DPM_TABLE_449__Smio_6_MASK 0xffffffff +#define DPM_TABLE_449__Smio_6__SHIFT 0x0 +#define DPM_TABLE_450__Smio_7_MASK 0xffffffff +#define DPM_TABLE_450__Smio_7__SHIFT 0x0 +#define DPM_TABLE_451__Smio_8_MASK 0xffffffff +#define DPM_TABLE_451__Smio_8__SHIFT 0x0 +#define DPM_TABLE_452__Smio_9_MASK 0xffffffff +#define DPM_TABLE_452__Smio_9__SHIFT 0x0 +#define DPM_TABLE_453__Smio_10_MASK 0xffffffff +#define DPM_TABLE_453__Smio_10__SHIFT 0x0 +#define DPM_TABLE_454__Smio_11_MASK 0xffffffff +#define DPM_TABLE_454__Smio_11__SHIFT 0x0 +#define DPM_TABLE_455__Smio_12_MASK 0xffffffff +#define DPM_TABLE_455__Smio_12__SHIFT 0x0 +#define DPM_TABLE_456__Smio_13_MASK 0xffffffff +#define DPM_TABLE_456__Smio_13__SHIFT 0x0 +#define DPM_TABLE_457__Smio_14_MASK 0xffffffff +#define DPM_TABLE_457__Smio_14__SHIFT 0x0 +#define DPM_TABLE_458__Smio_15_MASK 0xffffffff +#define DPM_TABLE_458__Smio_15__SHIFT 0x0 +#define DPM_TABLE_459__Smio_16_MASK 0xffffffff +#define DPM_TABLE_459__Smio_16__SHIFT 0x0 +#define DPM_TABLE_460__Smio_17_MASK 0xffffffff +#define DPM_TABLE_460__Smio_17__SHIFT 0x0 +#define DPM_TABLE_461__Smio_18_MASK 0xffffffff +#define DPM_TABLE_461__Smio_18__SHIFT 0x0 +#define DPM_TABLE_462__Smio_19_MASK 0xffffffff +#define DPM_TABLE_462__Smio_19__SHIFT 0x0 +#define DPM_TABLE_463__Smio_20_MASK 0xffffffff +#define DPM_TABLE_463__Smio_20__SHIFT 0x0 +#define DPM_TABLE_464__Smio_21_MASK 0xffffffff +#define DPM_TABLE_464__Smio_21__SHIFT 0x0 +#define DPM_TABLE_465__Smio_22_MASK 0xffffffff +#define DPM_TABLE_465__Smio_22__SHIFT 0x0 +#define DPM_TABLE_466__Smio_23_MASK 0xffffffff +#define DPM_TABLE_466__Smio_23__SHIFT 0x0 +#define DPM_TABLE_467__Smio_24_MASK 0xffffffff +#define DPM_TABLE_467__Smio_24__SHIFT 0x0 +#define DPM_TABLE_468__Smio_25_MASK 0xffffffff +#define DPM_TABLE_468__Smio_25__SHIFT 0x0 +#define DPM_TABLE_469__Smio_26_MASK 0xffffffff +#define DPM_TABLE_469__Smio_26__SHIFT 0x0 +#define DPM_TABLE_470__Smio_27_MASK 0xffffffff +#define DPM_TABLE_470__Smio_27__SHIFT 0x0 +#define DPM_TABLE_471__Smio_28_MASK 0xffffffff +#define DPM_TABLE_471__Smio_28__SHIFT 0x0 +#define DPM_TABLE_472__Smio_29_MASK 0xffffffff +#define DPM_TABLE_472__Smio_29__SHIFT 0x0 +#define DPM_TABLE_473__Smio_30_MASK 0xffffffff +#define DPM_TABLE_473__Smio_30__SHIFT 0x0 +#define DPM_TABLE_474__Smio_31_MASK 0xffffffff +#define DPM_TABLE_474__Smio_31__SHIFT 0x0 +#define DPM_TABLE_475__SamuBootLevel_MASK 0xff +#define DPM_TABLE_475__SamuBootLevel__SHIFT 0x0 +#define DPM_TABLE_475__AcpBootLevel_MASK 0xff00 +#define DPM_TABLE_475__AcpBootLevel__SHIFT 0x8 +#define DPM_TABLE_475__VceBootLevel_MASK 0xff0000 +#define DPM_TABLE_475__VceBootLevel__SHIFT 0x10 +#define DPM_TABLE_475__UvdBootLevel_MASK 0xff000000 +#define DPM_TABLE_475__UvdBootLevel__SHIFT 0x18 +#define DPM_TABLE_476__SAMUInterval_MASK 0xff +#define DPM_TABLE_476__SAMUInterval__SHIFT 0x0 +#define DPM_TABLE_476__ACPInterval_MASK 0xff00 +#define DPM_TABLE_476__ACPInterval__SHIFT 0x8 +#define DPM_TABLE_476__VCEInterval_MASK 0xff0000 +#define DPM_TABLE_476__VCEInterval__SHIFT 0x10 +#define DPM_TABLE_476__UVDInterval_MASK 0xff000000 +#define DPM_TABLE_476__UVDInterval__SHIFT 0x18 +#define DPM_TABLE_477__GraphicsInterval_MASK 0xff +#define DPM_TABLE_477__GraphicsInterval__SHIFT 0x0 +#define DPM_TABLE_477__GraphicsThermThrottleEnable_MASK 0xff00 +#define DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT 0x8 +#define DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK 0xff0000 +#define DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT 0x10 +#define DPM_TABLE_477__GraphicsBootLevel_MASK 0xff000000 +#define DPM_TABLE_477__GraphicsBootLevel__SHIFT 0x18 +#define DPM_TABLE_478__TemperatureLimitHigh_MASK 0xffff +#define DPM_TABLE_478__TemperatureLimitHigh__SHIFT 0x0 +#define DPM_TABLE_478__ThermalInterval_MASK 0xff0000 +#define DPM_TABLE_478__ThermalInterval__SHIFT 0x10 +#define DPM_TABLE_478__VoltageInterval_MASK 0xff000000 +#define DPM_TABLE_478__VoltageInterval__SHIFT 0x18 +#define DPM_TABLE_479__MemoryVoltageChangeEnable_MASK 0xff +#define DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT 0x0 +#define DPM_TABLE_479__MemoryBootLevel_MASK 0xff00 +#define DPM_TABLE_479__MemoryBootLevel__SHIFT 0x8 +#define DPM_TABLE_479__TemperatureLimitLow_MASK 0xffff0000 +#define DPM_TABLE_479__TemperatureLimitLow__SHIFT 0x10 +#define DPM_TABLE_480__VddcVddciDelta_MASK 0xffff +#define DPM_TABLE_480__VddcVddciDelta__SHIFT 0x0 +#define DPM_TABLE_480__MemoryThermThrottleEnable_MASK 0xff0000 +#define DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT 0x10 +#define DPM_TABLE_480__MemoryInterval_MASK 0xff000000 +#define DPM_TABLE_480__MemoryInterval__SHIFT 0x18 +#define DPM_TABLE_481__PhaseResponseTime_MASK 0xffff +#define DPM_TABLE_481__PhaseResponseTime__SHIFT 0x0 +#define DPM_TABLE_481__VoltageResponseTime_MASK 0xffff0000 +#define DPM_TABLE_481__VoltageResponseTime__SHIFT 0x10 +#define DPM_TABLE_482__DTEMode_MASK 0xff +#define DPM_TABLE_482__DTEMode__SHIFT 0x0 +#define DPM_TABLE_482__DTEInterval_MASK 0xff00 +#define DPM_TABLE_482__DTEInterval__SHIFT 0x8 +#define DPM_TABLE_482__PCIeGenInterval_MASK 0xff0000 +#define DPM_TABLE_482__PCIeGenInterval__SHIFT 0x10 +#define DPM_TABLE_482__PCIeBootLinkLevel_MASK 0xff000000 +#define DPM_TABLE_482__PCIeBootLinkLevel__SHIFT 0x18 +#define DPM_TABLE_483__ThermGpio_MASK 0xff +#define DPM_TABLE_483__ThermGpio__SHIFT 0x0 +#define DPM_TABLE_483__AcDcGpio_MASK 0xff00 +#define DPM_TABLE_483__AcDcGpio__SHIFT 0x8 +#define DPM_TABLE_483__VRHotGpio_MASK 0xff0000 +#define DPM_TABLE_483__VRHotGpio__SHIFT 0x10 +#define DPM_TABLE_483__SVI2Enable_MASK 0xff000000 +#define DPM_TABLE_483__SVI2Enable__SHIFT 0x18 +#define DPM_TABLE_484__DisplayCac_MASK 0xffffffff +#define DPM_TABLE_484__DisplayCac__SHIFT 0x0 +#define DPM_TABLE_485__NomPwr_MASK 0xffff +#define DPM_TABLE_485__NomPwr__SHIFT 0x0 +#define DPM_TABLE_485__MaxPwr_MASK 0xffff0000 +#define DPM_TABLE_485__MaxPwr__SHIFT 0x10 +#define DPM_TABLE_486__FpsLowThreshold_MASK 0xffff +#define DPM_TABLE_486__FpsLowThreshold__SHIFT 0x0 +#define DPM_TABLE_486__FpsHighThreshold_MASK 0xffff0000 +#define DPM_TABLE_486__FpsHighThreshold__SHIFT 0x10 +#define DPM_TABLE_487__BAPMTI_R_0_1_0_MASK 0xffff +#define DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT 0x0 +#define DPM_TABLE_487__BAPMTI_R_0_0_0_MASK 0xffff0000 +#define DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT 0x10 +#define DPM_TABLE_488__BAPMTI_R_1_0_0_MASK 0xffff +#define DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT 0x0 +#define DPM_TABLE_488__BAPMTI_R_0_2_0_MASK 0xffff0000 +#define DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT 0x10 +#define DPM_TABLE_489__BAPMTI_R_1_2_0_MASK 0xffff +#define DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT 0x0 +#define DPM_TABLE_489__BAPMTI_R_1_1_0_MASK 0xffff0000 +#define DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT 0x10 +#define DPM_TABLE_490__BAPMTI_R_2_1_0_MASK 0xffff +#define DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT 0x0 +#define DPM_TABLE_490__BAPMTI_R_2_0_0_MASK 0xffff0000 +#define DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT 0x10 +#define DPM_TABLE_491__BAPMTI_R_3_0_0_MASK 0xffff +#define DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT 0x0 +#define DPM_TABLE_491__BAPMTI_R_2_2_0_MASK 0xffff0000 +#define DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT 0x10 +#define DPM_TABLE_492__BAPMTI_R_3_2_0_MASK 0xffff +#define DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT 0x0 +#define DPM_TABLE_492__BAPMTI_R_3_1_0_MASK 0xffff0000 +#define DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT 0x10 +#define DPM_TABLE_493__BAPMTI_R_4_1_0_MASK 0xffff +#define DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT 0x0 +#define DPM_TABLE_493__BAPMTI_R_4_0_0_MASK 0xffff0000 +#define DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT 0x10 +#define DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK 0xffff +#define DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT 0x0 +#define DPM_TABLE_494__BAPMTI_R_4_2_0_MASK 0xffff0000 +#define DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT 0x10 +#define DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK 0xffff +#define DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT 0x0 +#define DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK 0xffff0000 +#define DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT 0x10 +#define DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK 0xffff +#define DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT 0x0 +#define DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK 0xffff0000 +#define DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT 0x10 +#define DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK 0xffff +#define DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT 0x0 +#define DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK 0xffff0000 +#define DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT 0x10 +#define DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK 0xffff +#define DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT 0x0 +#define DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK 0xffff0000 +#define DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT 0x10 +#define DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK 0xffff +#define DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT 0x0 +#define DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK 0xffff0000 +#define DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT 0x10 +#define DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK 0xffff +#define DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT 0x0 +#define DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK 0xffff0000 +#define DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT 0x10 +#define DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK 0xffff +#define DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT 0x0 +#define DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK 0xffff0000 +#define DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT 0x10 +#define DPM_TABLE_502__GpuTjHyst_MASK 0xff +#define DPM_TABLE_502__GpuTjHyst__SHIFT 0x0 +#define DPM_TABLE_502__GpuTjMax_MASK 0xff00 +#define DPM_TABLE_502__GpuTjMax__SHIFT 0x8 +#define DPM_TABLE_502__DTETjOffset_MASK 0xff0000 +#define DPM_TABLE_502__DTETjOffset__SHIFT 0x10 +#define DPM_TABLE_502__DTEAmbientTempBase_MASK 0xff000000 +#define DPM_TABLE_502__DTEAmbientTempBase__SHIFT 0x18 +#define DPM_TABLE_503__BootVddci_MASK 0xffff +#define DPM_TABLE_503__BootVddci__SHIFT 0x0 +#define DPM_TABLE_503__BootVddc_MASK 0xffff0000 +#define DPM_TABLE_503__BootVddc__SHIFT 0x10 +#define DPM_TABLE_504__padding_MASK 0xffff +#define DPM_TABLE_504__padding__SHIFT 0x0 +#define DPM_TABLE_504__BootMVdd_MASK 0xffff0000 +#define DPM_TABLE_504__BootMVdd__SHIFT 0x10 +#define DPM_TABLE_505__DRAM_LOG_ADDR_H_MASK 0xffffffff +#define DPM_TABLE_505__DRAM_LOG_ADDR_H__SHIFT 0x0 +#define DPM_TABLE_506__DRAM_LOG_ADDR_L_MASK 0xffffffff +#define DPM_TABLE_506__DRAM_LOG_ADDR_L__SHIFT 0x0 +#define DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff +#define DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0 +#define DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff +#define DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0 +#define DPM_TABLE_509__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff +#define DPM_TABLE_509__DRAM_LOG_BUFF_SIZE__SHIFT 0x0 +#define DPM_TABLE_510__BAPM_TEMP_GRADIENT_MASK 0xffffffff +#define DPM_TABLE_510__BAPM_TEMP_GRADIENT__SHIFT 0x0 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe +#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 +#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 +#define TDC_STATUS__VDD_Boost_MASK 0xff +#define TDC_STATUS__VDD_Boost__SHIFT 0x0 +#define TDC_STATUS__VDD_Throttle_MASK 0xff00 +#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 +#define TDC_STATUS__VDDC_Boost_MASK 0xff0000 +#define TDC_STATUS__VDDC_Boost__SHIFT 0x10 +#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000 +#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18 +#define TDC_MV_AVERAGE__IDD_MASK 0xffff +#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 +#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000 +#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10 +#define TDC_VRM_LIMIT__IDD_MASK 0xffff +#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 +#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000 +#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10 +#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 +#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 +#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 +#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 +#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 +#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 +#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 +#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 +#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 +#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 +#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20 +#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5 +#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40 +#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6 +#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 +#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 +#define FEATURE_STATUS__BAPM_ON_MASK 0x100 +#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 +#define FEATURE_STATUS__LPMX_ON_MASK 0x200 +#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 +#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 +#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa +#define FEATURE_STATUS__LHTC_ON_MASK 0x800 +#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb +#define FEATURE_STATUS__VPC_ON_MASK 0x1000 +#define FEATURE_STATUS__VPC_ON__SHIFT 0xc +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd +#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 +#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe +#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 +#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf +#define FEATURE_STATUS__AVS_ON_MASK 0x10000 +#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 +#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 +#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 +#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 +#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 +#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 +#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 +#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 +#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 +#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 +#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 +#define FEATURE_STATUS__RESERVED_MASK 0xffc00000 +#define FEATURE_STATUS__RESERVED__SHIFT 0x16 +#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff +#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime__SHIFT 0x18 +#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff +#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00 +#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8 +#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000 +#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000 +#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18 +#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_82__data_4_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_82__data_4_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_83__data_4_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_83__data_4_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_84__data_4_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_84__data_4_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_85__data_4_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_85__data_4_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_86__data_4_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_86__data_4_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_87__data_4_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_87__data_4_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_88__data_4_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_88__data_4_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_89__data_4_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_89__data_4_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_90__data_4_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_90__data_4_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_91__data_4_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_91__data_4_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_92__data_4_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_93__data_4_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_93__data_4_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_94__data_4_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_94__data_4_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_95__data_4_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_95__data_4_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_96__data_4_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_96__data_4_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_97__data_4_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_97__data_4_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_98__data_5_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_98__data_5_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_99__data_5_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_99__data_5_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_100__data_5_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_100__data_5_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_101__data_5_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_102__data_5_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_103__data_5_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_103__data_5_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_104__data_5_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_104__data_5_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_105__data_5_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_105__data_5_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_106__data_5_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_106__data_5_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_107__data_5_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_107__data_5_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_108__data_5_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_109__data_5_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_109__data_5_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_110__data_5_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_111__data_5_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_111__data_5_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_112__data_5_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_112__data_5_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_113__data_5_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_113__data_5_value_15__SHIFT 0x0 +#define FAN_TABLE_1__TempMin_MASK 0xffff +#define FAN_TABLE_1__TempMin__SHIFT 0x0 +#define FAN_TABLE_1__FdoMode_MASK 0xffff0000 +#define FAN_TABLE_1__FdoMode__SHIFT 0x10 +#define FAN_TABLE_2__TempMax_MASK 0xffff +#define FAN_TABLE_2__TempMax__SHIFT 0x0 +#define FAN_TABLE_2__TempMed_MASK 0xffff0000 +#define FAN_TABLE_2__TempMed__SHIFT 0x10 +#define FAN_TABLE_3__Slope2_MASK 0xffff +#define FAN_TABLE_3__Slope2__SHIFT 0x0 +#define FAN_TABLE_3__Slope1_MASK 0xffff0000 +#define FAN_TABLE_3__Slope1__SHIFT 0x10 +#define FAN_TABLE_4__HystUp_MASK 0xffff +#define FAN_TABLE_4__HystUp__SHIFT 0x0 +#define FAN_TABLE_4__FdoMin_MASK 0xffff0000 +#define FAN_TABLE_4__FdoMin__SHIFT 0x10 +#define FAN_TABLE_5__HystSlope_MASK 0xffff +#define FAN_TABLE_5__HystSlope__SHIFT 0x0 +#define FAN_TABLE_5__HystDown_MASK 0xffff0000 +#define FAN_TABLE_5__HystDown__SHIFT 0x10 +#define FAN_TABLE_6__TempCurr_MASK 0xffff +#define FAN_TABLE_6__TempCurr__SHIFT 0x0 +#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000 +#define FAN_TABLE_6__TempRespLim__SHIFT 0x10 +#define FAN_TABLE_7__PwmCurr_MASK 0xffff +#define FAN_TABLE_7__PwmCurr__SHIFT 0x0 +#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000 +#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10 +#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff +#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0 +#define FAN_TABLE_9__Padding_MASK 0xff +#define FAN_TABLE_9__Padding__SHIFT 0x0 +#define FAN_TABLE_9__TempSrc_MASK 0xff00 +#define FAN_TABLE_9__TempSrc__SHIFT 0x8 +#define FAN_TABLE_9__FdoMax_MASK 0xffff0000 +#define FAN_TABLE_9__FdoMax__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_21__Reserved_0_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_21__Reserved_0__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_22__Reserved_1_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_22__Reserved_1__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_23__Reserved_2_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_23__Reserved_2__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_24__Reserved_3_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_24__Reserved_3__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_25__Reserved_4_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_25__Reserved_4__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_26__Reserved_5_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_26__Reserved_5__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_27__Reserved_6_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_27__Reserved_6__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_28__Reserved_7_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_28__Reserved_7__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_29__Reserved_8_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_29__Reserved_8__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_30__Reserved_9_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_30__Reserved_9__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff +#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00 +#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8 +#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000 +#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10 +#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000 +#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18 +#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff +#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0 +#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00 +#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8 +#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000 +#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10 +#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000 +#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18 +#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff +#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0 +#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00 +#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8 +#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000 +#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10 +#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000 +#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18 +#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff +#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0 +#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00 +#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8 +#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000 +#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10 +#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000 +#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18 +#define PM_FUSES_5__VddCVid_3_MASK 0xff +#define PM_FUSES_5__VddCVid_3__SHIFT 0x0 +#define PM_FUSES_5__VddCVid_2_MASK 0xff00 +#define PM_FUSES_5__VddCVid_2__SHIFT 0x8 +#define PM_FUSES_5__VddCVid_1_MASK 0xff0000 +#define PM_FUSES_5__VddCVid_1__SHIFT 0x10 +#define PM_FUSES_5__VddCVid_0_MASK 0xff000000 +#define PM_FUSES_5__VddCVid_0__SHIFT 0x18 +#define PM_FUSES_6__VddCVid_7_MASK 0xff +#define PM_FUSES_6__VddCVid_7__SHIFT 0x0 +#define PM_FUSES_6__VddCVid_6_MASK 0xff00 +#define PM_FUSES_6__VddCVid_6__SHIFT 0x8 +#define PM_FUSES_6__VddCVid_5_MASK 0xff0000 +#define PM_FUSES_6__VddCVid_5__SHIFT 0x10 +#define PM_FUSES_6__VddCVid_4_MASK 0xff000000 +#define PM_FUSES_6__VddCVid_4__SHIFT 0x18 +#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff +#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0 +#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00 +#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8 +#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000 +#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10 +#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000 +#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18 +#define PM_FUSES_8__TDC_MAWt_MASK 0xff +#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8 +#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000 +#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10 +#define PM_FUSES_9__Reserved_MASK 0xff +#define PM_FUSES_9__Reserved__SHIFT 0x0 +#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00 +#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8 +#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000 +#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10 +#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000 +#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18 +#define PM_FUSES_10__LPMLTemperatureScaler_3_MASK 0xff +#define PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT 0x0 +#define PM_FUSES_10__LPMLTemperatureScaler_2_MASK 0xff00 +#define PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT 0x8 +#define PM_FUSES_10__LPMLTemperatureScaler_1_MASK 0xff0000 +#define PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT 0x10 +#define PM_FUSES_10__LPMLTemperatureScaler_0_MASK 0xff000000 +#define PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT 0x18 +#define PM_FUSES_11__LPMLTemperatureScaler_7_MASK 0xff +#define PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT 0x0 +#define PM_FUSES_11__LPMLTemperatureScaler_6_MASK 0xff00 +#define PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT 0x8 +#define PM_FUSES_11__LPMLTemperatureScaler_5_MASK 0xff0000 +#define PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT 0x10 +#define PM_FUSES_11__LPMLTemperatureScaler_4_MASK 0xff000000 +#define PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT 0x18 +#define PM_FUSES_12__LPMLTemperatureScaler_11_MASK 0xff +#define PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT 0x0 +#define PM_FUSES_12__LPMLTemperatureScaler_10_MASK 0xff00 +#define PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT 0x8 +#define PM_FUSES_12__LPMLTemperatureScaler_9_MASK 0xff0000 +#define PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT 0x10 +#define PM_FUSES_12__LPMLTemperatureScaler_8_MASK 0xff000000 +#define PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT 0x18 +#define PM_FUSES_13__LPMLTemperatureScaler_15_MASK 0xff +#define PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT 0x0 +#define PM_FUSES_13__LPMLTemperatureScaler_14_MASK 0xff00 +#define PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT 0x8 +#define PM_FUSES_13__LPMLTemperatureScaler_13_MASK 0xff0000 +#define PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT 0x10 +#define PM_FUSES_13__LPMLTemperatureScaler_12_MASK 0xff000000 +#define PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT 0x18 +#define PM_FUSES_14__GnbLPML_3_MASK 0xff +#define PM_FUSES_14__GnbLPML_3__SHIFT 0x0 +#define PM_FUSES_14__GnbLPML_2_MASK 0xff00 +#define PM_FUSES_14__GnbLPML_2__SHIFT 0x8 +#define PM_FUSES_14__GnbLPML_1_MASK 0xff0000 +#define PM_FUSES_14__GnbLPML_1__SHIFT 0x10 +#define PM_FUSES_14__GnbLPML_0_MASK 0xff000000 +#define PM_FUSES_14__GnbLPML_0__SHIFT 0x18 +#define PM_FUSES_15__GnbLPML_7_MASK 0xff +#define PM_FUSES_15__GnbLPML_7__SHIFT 0x0 +#define PM_FUSES_15__GnbLPML_6_MASK 0xff00 +#define PM_FUSES_15__GnbLPML_6__SHIFT 0x8 +#define PM_FUSES_15__GnbLPML_5_MASK 0xff0000 +#define PM_FUSES_15__GnbLPML_5__SHIFT 0x10 +#define PM_FUSES_15__GnbLPML_4_MASK 0xff000000 +#define PM_FUSES_15__GnbLPML_4__SHIFT 0x18 +#define PM_FUSES_16__GnbLPML_11_MASK 0xff +#define PM_FUSES_16__GnbLPML_11__SHIFT 0x0 +#define PM_FUSES_16__GnbLPML_10_MASK 0xff00 +#define PM_FUSES_16__GnbLPML_10__SHIFT 0x8 +#define PM_FUSES_16__GnbLPML_9_MASK 0xff0000 +#define PM_FUSES_16__GnbLPML_9__SHIFT 0x10 +#define PM_FUSES_16__GnbLPML_8_MASK 0xff000000 +#define PM_FUSES_16__GnbLPML_8__SHIFT 0x18 +#define PM_FUSES_17__GnbLPML_15_MASK 0xff +#define PM_FUSES_17__GnbLPML_15__SHIFT 0x0 +#define PM_FUSES_17__GnbLPML_14_MASK 0xff00 +#define PM_FUSES_17__GnbLPML_14__SHIFT 0x8 +#define PM_FUSES_17__GnbLPML_13_MASK 0xff0000 +#define PM_FUSES_17__GnbLPML_13__SHIFT 0x10 +#define PM_FUSES_17__GnbLPML_12_MASK 0xff000000 +#define PM_FUSES_17__GnbLPML_12__SHIFT 0x18 +#define PM_FUSES_18__Reserved1_1_MASK 0xff +#define PM_FUSES_18__Reserved1_1__SHIFT 0x0 +#define PM_FUSES_18__Reserved1_0_MASK 0xff00 +#define PM_FUSES_18__Reserved1_0__SHIFT 0x8 +#define PM_FUSES_18__GnbLPMLMinVid_MASK 0xff0000 +#define PM_FUSES_18__GnbLPMLMinVid__SHIFT 0x10 +#define PM_FUSES_18__GnbLPMLMaxVid_MASK 0xff000000 +#define PM_FUSES_18__GnbLPMLMaxVid__SHIFT 0x18 +#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd_MASK 0xffff +#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd__SHIFT 0x0 +#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000 +#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd__SHIFT 0x10 +#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_52__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0 +#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8 +#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3 +#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0 +#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4 +#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000 +#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe +#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000 +#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19 +#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000 +#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a +#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff +#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 +#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000 +#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11 +#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000 +#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12 +#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff +#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0 +#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00 +#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8 +#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000 +#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10 +#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000 +#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18 +#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf +#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 +#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0 +#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 +#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff +#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 +#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff +#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 +#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00 +#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL1__M_MASK 0xff0000 +#define CG_FDO_CTRL1__M__SHIFT 0x10 +#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000 +#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 +#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000 +#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e +#define CG_FDO_CTRL2__TMIN_MASK 0xff +#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 +#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800 +#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb +#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000 +#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe +#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000 +#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 +#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7 +#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 +#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8 +#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 +#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff +#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 +#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe +#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1 +#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00 +#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11 +#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000 +#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12 +#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000 +#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18 +#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000 +#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19 +#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000 +#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a +#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000 +#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b +#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000 +#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c +#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000 +#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d +#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000 +#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_INT_DATA__Z_MASK 0x7ff +#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON0_INT_DATA__VALID_MASK 0x800 +#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40 +#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17 +#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000 +#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf +#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 +#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 +#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 +#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 +#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 +#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf +#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 +#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1 +#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0 +#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe +#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0 +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2 +#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1 +#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4 +#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10 +#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000 +#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a +#define ROM_STATUS__ROM_BUSY_MASK 0x1 +#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf +#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define ROM_INDEX__ROM_INDEX_MASK 0xffffff +#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 +#define ROM_DATA__ROM_DATA_MASK 0xffffffff +#define ROM_DATA__ROM_DATA__SHIFT 0x0 +#define ROM_START__ROM_START_MASK 0xffffff +#define ROM_START__ROM_START__SHIFT 0x0 +#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff +#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 +#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000 +#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 +#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1 +#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 +#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 + +#endif /* SMU_7_0_1_SH_MASK_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h new file mode 100644 index 000000000000..57588b11ff1a --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h @@ -0,0 +1,1344 @@ +/* + * SMU_7_1_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_0_D_H +#define SMU_7_1_0_D_H + +#define mmGCK_SMC_IND_INDEX 0x80 +#define mmGCK0_GCK_SMC_IND_INDEX 0x80 +#define mmGCK1_GCK_SMC_IND_INDEX 0x82 +#define mmGCK2_GCK_SMC_IND_INDEX 0x84 +#define mmGCK3_GCK_SMC_IND_INDEX 0x86 +#define mmGCK_SMC_IND_DATA 0x81 +#define mmGCK0_GCK_SMC_IND_DATA 0x81 +#define mmGCK1_GCK_SMC_IND_DATA 0x83 +#define mmGCK2_GCK_SMC_IND_DATA 0x85 +#define mmGCK3_GCK_SMC_IND_DATA 0x87 +#define ixCG_DCLK_CNTL 0xc050009c +#define ixCG_DCLK_STATUS 0xc05000a0 +#define ixCG_VCLK_CNTL 0xc05000a4 +#define ixCG_VCLK_STATUS 0xc05000a8 +#define ixCG_ECLK_CNTL 0xc05000ac +#define ixCG_ECLK_STATUS 0xc05000b0 +#define ixCG_ACLK_CNTL 0xc05000dc +#define ixGCK_DFS_BYPASS_CNTL 0xc0500118 +#define ixCG_SPLL_FUNC_CNTL 0xc0500140 +#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 +#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 +#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c +#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 +#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 +#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 +#define ixSPLL_CNTL_MODE 0xc0500160 +#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 +#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +#define ixMPLL_BYPASSCLK_SEL 0xc050019c +#define ixCG_CLKPIN_CNTL 0xc05001a0 +#define ixCG_CLKPIN_CNTL_2 0xc05001a4 +#define ixCG_CLKPIN_CNTL_DC 0xc0500204 +#define ixTHM_CLK_CNTL 0xc05001a8 +#define ixMISC_CLK_CTRL 0xc05001ac +#define ixGCK_PLL_TEST_CNTL 0xc05001c0 +#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 +#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 +#define mmSMC_IND_INDEX 0x80 +#define mmSMC0_SMC_IND_INDEX 0x80 +#define mmSMC1_SMC_IND_INDEX 0x82 +#define mmSMC2_SMC_IND_INDEX 0x84 +#define mmSMC3_SMC_IND_INDEX 0x86 +#define mmSMC_IND_DATA 0x81 +#define mmSMC0_SMC_IND_DATA 0x81 +#define mmSMC1_SMC_IND_DATA 0x83 +#define mmSMC2_SMC_IND_DATA 0x85 +#define mmSMC3_SMC_IND_DATA 0x87 +#define mmSMC_IND_INDEX_0 0x80 +#define mmSMC_IND_DATA_0 0x81 +#define mmSMC_IND_INDEX_1 0x82 +#define mmSMC_IND_DATA_1 0x83 +#define mmSMC_IND_INDEX_2 0x84 +#define mmSMC_IND_DATA_2 0x85 +#define mmSMC_IND_INDEX_3 0x86 +#define mmSMC_IND_DATA_3 0x87 +#define mmSMC_IND_INDEX_4 0x88 +#define mmSMC_IND_DATA_4 0x89 +#define mmSMC_IND_INDEX_5 0x8a +#define mmSMC_IND_DATA_5 0x8b +#define mmSMC_IND_INDEX_6 0x8c +#define mmSMC_IND_DATA_6 0x8d +#define mmSMC_IND_INDEX_7 0x8e +#define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_ACCESS_CNTL 0x90 +#define mmSMC_MESSAGE_0 0x94 +#define mmSMC_RESP_0 0x95 +#define mmSMC_MESSAGE_1 0x96 +#define mmSMC_RESP_1 0x97 +#define mmSMC_MESSAGE_2 0x98 +#define mmSMC_RESP_2 0x99 +#define mmSMC_MESSAGE_3 0x9a +#define mmSMC_RESP_3 0x9b +#define mmSMC_MESSAGE_4 0x9c +#define mmSMC_RESP_4 0x9d +#define mmSMC_MESSAGE_5 0x9e +#define mmSMC_RESP_5 0x9f +#define mmSMC_MESSAGE_6 0xa0 +#define mmSMC_RESP_6 0xa1 +#define mmSMC_MESSAGE_7 0xa2 +#define mmSMC_RESP_7 0xa3 +#define mmSMC_MSG_ARG_0 0xa4 +#define mmSMC_MSG_ARG_1 0xa5 +#define mmSMC_MSG_ARG_2 0xa6 +#define mmSMC_MSG_ARG_3 0xa7 +#define mmSMC_MSG_ARG_4 0xa8 +#define mmSMC_MSG_ARG_5 0xa9 +#define mmSMC_MSG_ARG_6 0xaa +#define mmSMC_MSG_ARG_7 0xab +#define mmSMC_MESSAGE_8 0xb5 +#define mmSMC_RESP_8 0xb6 +#define mmSMC_MESSAGE_9 0xb7 +#define mmSMC_RESP_9 0xb8 +#define mmSMC_MESSAGE_10 0xb9 +#define mmSMC_RESP_10 0xba +#define mmSMC_MESSAGE_11 0xbb +#define mmSMC_RESP_11 0xbc +#define mmSMC_MSG_ARG_8 0xbd +#define mmSMC_MSG_ARG_9 0xbe +#define mmSMC_MSG_ARG_10 0xbf +#define mmSMC_MSG_ARG_11 0x91 +#define ixSMC_SYSCON_RESET_CNTL 0x80000000 +#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 +#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 +#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c +#define ixSMC_SYSCON_MISC_CNTL 0x80000010 +#define ixSMC_SYSCON_MSG_ARG_0 0x80000068 +#define ixSMC_PC_C 0x80000370 +#define ixSMC_SCRATCH9 0x80000424 +#define mmGPIOPAD_SW_INT_STAT 0x180 +#define mmGPIOPAD_STRENGTH 0x181 +#define mmGPIOPAD_MASK 0x182 +#define mmGPIOPAD_A 0x183 +#define mmGPIOPAD_EN 0x184 +#define mmGPIOPAD_Y 0x185 +#define mmGPIOPAD_PINSTRAPS 0x186 +#define mmGPIOPAD_INT_STAT_EN 0x187 +#define mmGPIOPAD_INT_STAT 0x188 +#define mmGPIOPAD_INT_STAT_AK 0x189 +#define mmGPIOPAD_INT_EN 0x18a +#define mmGPIOPAD_INT_TYPE 0x18b +#define mmGPIOPAD_INT_POLARITY 0x18c +#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d +#define mmGPIOPAD_RCVR_SEL 0x191 +#define mmGPIOPAD_PU_EN 0x192 +#define mmGPIOPAD_PD_EN 0x193 +#define mmCG_FPS_CNT 0x1a4 +#define mmSMU_SMC_IND_INDEX 0x80 +#define mmSMU0_SMU_SMC_IND_INDEX 0x80 +#define mmSMU1_SMU_SMC_IND_INDEX 0x82 +#define mmSMU2_SMU_SMC_IND_INDEX 0x84 +#define mmSMU3_SMU_SMC_IND_INDEX 0x86 +#define mmSMU_SMC_IND_DATA 0x81 +#define mmSMU0_SMU_SMC_IND_DATA 0x81 +#define mmSMU1_SMU_SMC_IND_DATA 0x83 +#define mmSMU2_SMU_SMC_IND_DATA 0x85 +#define mmSMU3_SMU_SMC_IND_DATA 0x87 +#define ixRCU_UC_EVENTS 0xc0000004 +#define ixRCU_MISC_CTRL 0xc0000010 +#define ixCC_RCU_FUSES 0xc00c0000 +#define ixCC_SMU_MISC_FUSES 0xc00c0004 +#define ixCC_SCLK_VID_FUSES 0xc00c0008 +#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c +#define ixCC_GIO_IOC_FUSES 0xc00c0010 +#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c +#define ixCC_TST_ID_STRAPS 0xc00c0020 +#define ixCC_FCTRL_FUSES 0xc00c0024 +#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 +#define ixSMU_STATUS 0xe0003088 +#define ixSMU_FIRMWARE 0xe00030a4 +#define ixSMU_INPUT_DATA 0xe00030b8 +#define ixSMU_EFUSE_0 0xc0100000 +#define ixDPM_TABLE_1 0x3f000 +#define ixDPM_TABLE_2 0x3f004 +#define ixDPM_TABLE_3 0x3f008 +#define ixDPM_TABLE_4 0x3f00c +#define ixDPM_TABLE_5 0x3f010 +#define ixDPM_TABLE_6 0x3f014 +#define ixDPM_TABLE_7 0x3f018 +#define ixDPM_TABLE_8 0x3f01c +#define ixDPM_TABLE_9 0x3f020 +#define ixDPM_TABLE_10 0x3f024 +#define ixDPM_TABLE_11 0x3f028 +#define ixDPM_TABLE_12 0x3f02c +#define ixDPM_TABLE_13 0x3f030 +#define ixDPM_TABLE_14 0x3f034 +#define ixDPM_TABLE_15 0x3f038 +#define ixDPM_TABLE_16 0x3f03c +#define ixDPM_TABLE_17 0x3f040 +#define ixDPM_TABLE_18 0x3f044 +#define ixDPM_TABLE_19 0x3f048 +#define ixDPM_TABLE_20 0x3f04c +#define ixDPM_TABLE_21 0x3f050 +#define ixDPM_TABLE_22 0x3f054 +#define ixDPM_TABLE_23 0x3f058 +#define ixDPM_TABLE_24 0x3f05c +#define ixDPM_TABLE_25 0x3f060 +#define ixDPM_TABLE_26 0x3f064 +#define ixDPM_TABLE_27 0x3f068 +#define ixDPM_TABLE_28 0x3f06c +#define ixDPM_TABLE_29 0x3f070 +#define ixDPM_TABLE_30 0x3f074 +#define ixDPM_TABLE_31 0x3f078 +#define ixDPM_TABLE_32 0x3f07c +#define ixDPM_TABLE_33 0x3f080 +#define ixDPM_TABLE_34 0x3f084 +#define ixDPM_TABLE_35 0x3f088 +#define ixDPM_TABLE_36 0x3f08c +#define ixDPM_TABLE_37 0x3f090 +#define ixDPM_TABLE_38 0x3f094 +#define ixDPM_TABLE_39 0x3f098 +#define ixDPM_TABLE_40 0x3f09c +#define ixDPM_TABLE_41 0x3f0a0 +#define ixDPM_TABLE_42 0x3f0a4 +#define ixDPM_TABLE_43 0x3f0a8 +#define ixDPM_TABLE_44 0x3f0ac +#define ixDPM_TABLE_45 0x3f0b0 +#define ixDPM_TABLE_46 0x3f0b4 +#define ixDPM_TABLE_47 0x3f0b8 +#define ixDPM_TABLE_48 0x3f0bc +#define ixDPM_TABLE_49 0x3f0c0 +#define ixDPM_TABLE_50 0x3f0c4 +#define ixDPM_TABLE_51 0x3f0c8 +#define ixDPM_TABLE_52 0x3f0cc +#define ixDPM_TABLE_53 0x3f0d0 +#define ixDPM_TABLE_54 0x3f0d4 +#define ixDPM_TABLE_55 0x3f0d8 +#define ixDPM_TABLE_56 0x3f0dc +#define ixDPM_TABLE_57 0x3f0e0 +#define ixDPM_TABLE_58 0x3f0e4 +#define ixDPM_TABLE_59 0x3f0e8 +#define ixDPM_TABLE_60 0x3f0ec +#define ixDPM_TABLE_61 0x3f0f0 +#define ixDPM_TABLE_62 0x3f0f4 +#define ixDPM_TABLE_63 0x3f0f8 +#define ixDPM_TABLE_64 0x3f0fc +#define ixDPM_TABLE_65 0x3f100 +#define ixDPM_TABLE_66 0x3f104 +#define ixDPM_TABLE_67 0x3f108 +#define ixDPM_TABLE_68 0x3f10c +#define ixDPM_TABLE_69 0x3f110 +#define ixDPM_TABLE_70 0x3f114 +#define ixDPM_TABLE_71 0x3f118 +#define ixDPM_TABLE_72 0x3f11c +#define ixDPM_TABLE_73 0x3f120 +#define ixDPM_TABLE_74 0x3f124 +#define ixDPM_TABLE_75 0x3f128 +#define ixDPM_TABLE_76 0x3f12c +#define ixDPM_TABLE_77 0x3f130 +#define ixDPM_TABLE_78 0x3f134 +#define ixDPM_TABLE_79 0x3f138 +#define ixDPM_TABLE_80 0x3f13c +#define ixDPM_TABLE_81 0x3f140 +#define ixDPM_TABLE_82 0x3f144 +#define ixDPM_TABLE_83 0x3f148 +#define ixDPM_TABLE_84 0x3f14c +#define ixDPM_TABLE_85 0x3f150 +#define ixDPM_TABLE_86 0x3f154 +#define ixDPM_TABLE_87 0x3f158 +#define ixDPM_TABLE_88 0x3f15c +#define ixDPM_TABLE_89 0x3f160 +#define ixDPM_TABLE_90 0x3f164 +#define ixDPM_TABLE_91 0x3f168 +#define ixDPM_TABLE_92 0x3f16c +#define ixDPM_TABLE_93 0x3f170 +#define ixDPM_TABLE_94 0x3f174 +#define ixDPM_TABLE_95 0x3f178 +#define ixDPM_TABLE_96 0x3f17c +#define ixDPM_TABLE_97 0x3f180 +#define ixDPM_TABLE_98 0x3f184 +#define ixDPM_TABLE_99 0x3f188 +#define ixDPM_TABLE_100 0x3f18c +#define ixDPM_TABLE_101 0x3f190 +#define ixDPM_TABLE_102 0x3f194 +#define ixDPM_TABLE_103 0x3f198 +#define ixDPM_TABLE_104 0x3f19c +#define ixDPM_TABLE_105 0x3f1a0 +#define ixDPM_TABLE_106 0x3f1a4 +#define ixDPM_TABLE_107 0x3f1a8 +#define ixDPM_TABLE_108 0x3f1ac +#define ixDPM_TABLE_109 0x3f1b0 +#define ixDPM_TABLE_110 0x3f1b4 +#define ixDPM_TABLE_111 0x3f1b8 +#define ixDPM_TABLE_112 0x3f1bc +#define ixDPM_TABLE_113 0x3f1c0 +#define ixDPM_TABLE_114 0x3f1c4 +#define ixDPM_TABLE_115 0x3f1c8 +#define ixDPM_TABLE_116 0x3f1cc +#define ixDPM_TABLE_117 0x3f1d0 +#define ixDPM_TABLE_118 0x3f1d4 +#define ixDPM_TABLE_119 0x3f1d8 +#define ixDPM_TABLE_120 0x3f1dc +#define ixDPM_TABLE_121 0x3f1e0 +#define ixDPM_TABLE_122 0x3f1e4 +#define ixDPM_TABLE_123 0x3f1e8 +#define ixDPM_TABLE_124 0x3f1ec +#define ixDPM_TABLE_125 0x3f1f0 +#define ixDPM_TABLE_126 0x3f1f4 +#define ixDPM_TABLE_127 0x3f1f8 +#define ixDPM_TABLE_128 0x3f1fc +#define ixDPM_TABLE_129 0x3f200 +#define ixDPM_TABLE_130 0x3f204 +#define ixDPM_TABLE_131 0x3f208 +#define ixDPM_TABLE_132 0x3f20c +#define ixDPM_TABLE_133 0x3f210 +#define ixDPM_TABLE_134 0x3f214 +#define ixDPM_TABLE_135 0x3f218 +#define ixDPM_TABLE_136 0x3f21c +#define ixDPM_TABLE_137 0x3f220 +#define ixDPM_TABLE_138 0x3f224 +#define ixDPM_TABLE_139 0x3f228 +#define ixDPM_TABLE_140 0x3f22c +#define ixDPM_TABLE_141 0x3f230 +#define ixDPM_TABLE_142 0x3f234 +#define ixDPM_TABLE_143 0x3f238 +#define ixDPM_TABLE_144 0x3f23c +#define ixDPM_TABLE_145 0x3f240 +#define ixDPM_TABLE_146 0x3f244 +#define ixDPM_TABLE_147 0x3f248 +#define ixDPM_TABLE_148 0x3f24c +#define ixDPM_TABLE_149 0x3f250 +#define ixDPM_TABLE_150 0x3f254 +#define ixDPM_TABLE_151 0x3f258 +#define ixDPM_TABLE_152 0x3f25c +#define ixDPM_TABLE_153 0x3f260 +#define ixDPM_TABLE_154 0x3f264 +#define ixDPM_TABLE_155 0x3f268 +#define ixDPM_TABLE_156 0x3f26c +#define ixDPM_TABLE_157 0x3f270 +#define ixDPM_TABLE_158 0x3f274 +#define ixDPM_TABLE_159 0x3f278 +#define ixDPM_TABLE_160 0x3f27c +#define ixDPM_TABLE_161 0x3f280 +#define ixDPM_TABLE_162 0x3f284 +#define ixDPM_TABLE_163 0x3f288 +#define ixDPM_TABLE_164 0x3f28c +#define ixDPM_TABLE_165 0x3f290 +#define ixDPM_TABLE_166 0x3f294 +#define ixDPM_TABLE_167 0x3f298 +#define ixDPM_TABLE_168 0x3f29c +#define ixDPM_TABLE_169 0x3f2a0 +#define ixDPM_TABLE_170 0x3f2a4 +#define ixDPM_TABLE_171 0x3f2a8 +#define ixDPM_TABLE_172 0x3f2ac +#define ixDPM_TABLE_173 0x3f2b0 +#define ixDPM_TABLE_174 0x3f2b4 +#define ixDPM_TABLE_175 0x3f2b8 +#define ixDPM_TABLE_176 0x3f2bc +#define ixDPM_TABLE_177 0x3f2c0 +#define ixDPM_TABLE_178 0x3f2c4 +#define ixDPM_TABLE_179 0x3f2c8 +#define ixDPM_TABLE_180 0x3f2cc +#define ixDPM_TABLE_181 0x3f2d0 +#define ixDPM_TABLE_182 0x3f2d4 +#define ixDPM_TABLE_183 0x3f2d8 +#define ixDPM_TABLE_184 0x3f2dc +#define ixDPM_TABLE_185 0x3f2e0 +#define ixDPM_TABLE_186 0x3f2e4 +#define ixDPM_TABLE_187 0x3f2e8 +#define ixDPM_TABLE_188 0x3f2ec +#define ixDPM_TABLE_189 0x3f2f0 +#define ixDPM_TABLE_190 0x3f2f4 +#define ixDPM_TABLE_191 0x3f2f8 +#define ixDPM_TABLE_192 0x3f2fc +#define ixDPM_TABLE_193 0x3f300 +#define ixDPM_TABLE_194 0x3f304 +#define ixDPM_TABLE_195 0x3f308 +#define ixDPM_TABLE_196 0x3f30c +#define ixDPM_TABLE_197 0x3f310 +#define ixDPM_TABLE_198 0x3f314 +#define ixDPM_TABLE_199 0x3f318 +#define ixDPM_TABLE_200 0x3f31c +#define ixDPM_TABLE_201 0x3f320 +#define ixDPM_TABLE_202 0x3f324 +#define ixDPM_TABLE_203 0x3f328 +#define ixDPM_TABLE_204 0x3f32c +#define ixDPM_TABLE_205 0x3f330 +#define ixDPM_TABLE_206 0x3f334 +#define ixDPM_TABLE_207 0x3f338 +#define ixDPM_TABLE_208 0x3f33c +#define ixDPM_TABLE_209 0x3f340 +#define ixDPM_TABLE_210 0x3f344 +#define ixDPM_TABLE_211 0x3f348 +#define ixDPM_TABLE_212 0x3f34c +#define ixDPM_TABLE_213 0x3f350 +#define ixDPM_TABLE_214 0x3f354 +#define ixDPM_TABLE_215 0x3f358 +#define ixDPM_TABLE_216 0x3f35c +#define ixDPM_TABLE_217 0x3f360 +#define ixDPM_TABLE_218 0x3f364 +#define ixDPM_TABLE_219 0x3f368 +#define ixDPM_TABLE_220 0x3f36c +#define ixDPM_TABLE_221 0x3f370 +#define ixDPM_TABLE_222 0x3f374 +#define ixDPM_TABLE_223 0x3f378 +#define ixDPM_TABLE_224 0x3f37c +#define ixDPM_TABLE_225 0x3f380 +#define ixDPM_TABLE_226 0x3f384 +#define ixDPM_TABLE_227 0x3f388 +#define ixDPM_TABLE_228 0x3f38c +#define ixDPM_TABLE_229 0x3f390 +#define ixDPM_TABLE_230 0x3f394 +#define ixDPM_TABLE_231 0x3f398 +#define ixDPM_TABLE_232 0x3f39c +#define ixDPM_TABLE_233 0x3f3a0 +#define ixDPM_TABLE_234 0x3f3a4 +#define ixDPM_TABLE_235 0x3f3a8 +#define ixDPM_TABLE_236 0x3f3ac +#define ixDPM_TABLE_237 0x3f3b0 +#define ixDPM_TABLE_238 0x3f3b4 +#define ixDPM_TABLE_239 0x3f3b8 +#define ixDPM_TABLE_240 0x3f3bc +#define ixDPM_TABLE_241 0x3f3c0 +#define ixDPM_TABLE_242 0x3f3c4 +#define ixDPM_TABLE_243 0x3f3c8 +#define ixDPM_TABLE_244 0x3f3cc +#define ixDPM_TABLE_245 0x3f3d0 +#define ixDPM_TABLE_246 0x3f3d4 +#define ixDPM_TABLE_247 0x3f3d8 +#define ixDPM_TABLE_248 0x3f3dc +#define ixDPM_TABLE_249 0x3f3e0 +#define ixDPM_TABLE_250 0x3f3e4 +#define ixDPM_TABLE_251 0x3f3e8 +#define ixDPM_TABLE_252 0x3f3ec +#define ixDPM_TABLE_253 0x3f3f0 +#define ixDPM_TABLE_254 0x3f3f4 +#define ixDPM_TABLE_255 0x3f3f8 +#define ixDPM_TABLE_256 0x3f3fc +#define ixDPM_TABLE_257 0x3f400 +#define ixDPM_TABLE_258 0x3f404 +#define ixDPM_TABLE_259 0x3f408 +#define ixDPM_TABLE_260 0x3f40c +#define ixDPM_TABLE_261 0x3f410 +#define ixDPM_TABLE_262 0x3f414 +#define ixDPM_TABLE_263 0x3f418 +#define ixDPM_TABLE_264 0x3f41c +#define ixDPM_TABLE_265 0x3f420 +#define ixDPM_TABLE_266 0x3f424 +#define ixDPM_TABLE_267 0x3f428 +#define ixDPM_TABLE_268 0x3f42c +#define ixDPM_TABLE_269 0x3f430 +#define ixDPM_TABLE_270 0x3f434 +#define ixDPM_TABLE_271 0x3f438 +#define ixDPM_TABLE_272 0x3f43c +#define ixDPM_TABLE_273 0x3f440 +#define ixDPM_TABLE_274 0x3f444 +#define ixDPM_TABLE_275 0x3f448 +#define ixDPM_TABLE_276 0x3f44c +#define ixDPM_TABLE_277 0x3f450 +#define ixDPM_TABLE_278 0x3f454 +#define ixDPM_TABLE_279 0x3f458 +#define ixDPM_TABLE_280 0x3f45c +#define ixDPM_TABLE_281 0x3f460 +#define ixDPM_TABLE_282 0x3f464 +#define ixDPM_TABLE_283 0x3f468 +#define ixDPM_TABLE_284 0x3f46c +#define ixDPM_TABLE_285 0x3f470 +#define ixDPM_TABLE_286 0x3f474 +#define ixDPM_TABLE_287 0x3f478 +#define ixDPM_TABLE_288 0x3f47c +#define ixDPM_TABLE_289 0x3f480 +#define ixDPM_TABLE_290 0x3f484 +#define ixDPM_TABLE_291 0x3f488 +#define ixDPM_TABLE_292 0x3f48c +#define ixDPM_TABLE_293 0x3f490 +#define ixDPM_TABLE_294 0x3f494 +#define ixDPM_TABLE_295 0x3f498 +#define ixDPM_TABLE_296 0x3f49c +#define ixDPM_TABLE_297 0x3f4a0 +#define ixDPM_TABLE_298 0x3f4a4 +#define ixDPM_TABLE_299 0x3f4a8 +#define ixDPM_TABLE_300 0x3f4ac +#define ixDPM_TABLE_301 0x3f4b0 +#define ixDPM_TABLE_302 0x3f4b4 +#define ixDPM_TABLE_303 0x3f4b8 +#define ixDPM_TABLE_304 0x3f4bc +#define ixDPM_TABLE_305 0x3f4c0 +#define ixDPM_TABLE_306 0x3f4c4 +#define ixDPM_TABLE_307 0x3f4c8 +#define ixDPM_TABLE_308 0x3f4cc +#define ixDPM_TABLE_309 0x3f4d0 +#define ixDPM_TABLE_310 0x3f4d4 +#define ixDPM_TABLE_311 0x3f4d8 +#define ixDPM_TABLE_312 0x3f4dc +#define ixDPM_TABLE_313 0x3f4e0 +#define ixDPM_TABLE_314 0x3f4e4 +#define ixDPM_TABLE_315 0x3f4e8 +#define ixDPM_TABLE_316 0x3f4ec +#define ixDPM_TABLE_317 0x3f4f0 +#define ixDPM_TABLE_318 0x3f4f4 +#define ixDPM_TABLE_319 0x3f4f8 +#define ixDPM_TABLE_320 0x3f4fc +#define ixDPM_TABLE_321 0x3f500 +#define ixDPM_TABLE_322 0x3f504 +#define ixDPM_TABLE_323 0x3f508 +#define ixDPM_TABLE_324 0x3f50c +#define ixDPM_TABLE_325 0x3f510 +#define ixDPM_TABLE_326 0x3f514 +#define ixDPM_TABLE_327 0x3f518 +#define ixDPM_TABLE_328 0x3f51c +#define ixDPM_TABLE_329 0x3f520 +#define ixDPM_TABLE_330 0x3f524 +#define ixDPM_TABLE_331 0x3f528 +#define ixDPM_TABLE_332 0x3f52c +#define ixDPM_TABLE_333 0x3f530 +#define ixDPM_TABLE_334 0x3f534 +#define ixDPM_TABLE_335 0x3f538 +#define ixDPM_TABLE_336 0x3f53c +#define ixDPM_TABLE_337 0x3f540 +#define ixDPM_TABLE_338 0x3f544 +#define ixDPM_TABLE_339 0x3f548 +#define ixDPM_TABLE_340 0x3f54c +#define ixDPM_TABLE_341 0x3f550 +#define ixDPM_TABLE_342 0x3f554 +#define ixDPM_TABLE_343 0x3f558 +#define ixDPM_TABLE_344 0x3f55c +#define ixDPM_TABLE_345 0x3f560 +#define ixDPM_TABLE_346 0x3f564 +#define ixDPM_TABLE_347 0x3f568 +#define ixDPM_TABLE_348 0x3f56c +#define ixDPM_TABLE_349 0x3f570 +#define ixDPM_TABLE_350 0x3f574 +#define ixDPM_TABLE_351 0x3f578 +#define ixDPM_TABLE_352 0x3f57c +#define ixDPM_TABLE_353 0x3f580 +#define ixDPM_TABLE_354 0x3f584 +#define ixDPM_TABLE_355 0x3f588 +#define ixDPM_TABLE_356 0x3f58c +#define ixDPM_TABLE_357 0x3f590 +#define ixDPM_TABLE_358 0x3f594 +#define ixDPM_TABLE_359 0x3f598 +#define ixDPM_TABLE_360 0x3f59c +#define ixDPM_TABLE_361 0x3f5a0 +#define ixDPM_TABLE_362 0x3f5a4 +#define ixDPM_TABLE_363 0x3f5a8 +#define ixDPM_TABLE_364 0x3f5ac +#define ixDPM_TABLE_365 0x3f5b0 +#define ixDPM_TABLE_366 0x3f5b4 +#define ixDPM_TABLE_367 0x3f5b8 +#define ixDPM_TABLE_368 0x3f5bc +#define ixDPM_TABLE_369 0x3f5c0 +#define ixDPM_TABLE_370 0x3f5c4 +#define ixDPM_TABLE_371 0x3f5c8 +#define ixDPM_TABLE_372 0x3f5cc +#define ixDPM_TABLE_373 0x3f5d0 +#define ixDPM_TABLE_374 0x3f5d4 +#define ixDPM_TABLE_375 0x3f5d8 +#define ixDPM_TABLE_376 0x3f5dc +#define ixDPM_TABLE_377 0x3f5e0 +#define ixDPM_TABLE_378 0x3f5e4 +#define ixDPM_TABLE_379 0x3f5e8 +#define ixDPM_TABLE_380 0x3f5ec +#define ixDPM_TABLE_381 0x3f5f0 +#define ixDPM_TABLE_382 0x3f5f4 +#define ixDPM_TABLE_383 0x3f5f8 +#define ixDPM_TABLE_384 0x3f5fc +#define ixDPM_TABLE_385 0x3f600 +#define ixDPM_TABLE_386 0x3f604 +#define ixDPM_TABLE_387 0x3f608 +#define ixDPM_TABLE_388 0x3f60c +#define ixDPM_TABLE_389 0x3f610 +#define ixDPM_TABLE_390 0x3f614 +#define ixDPM_TABLE_391 0x3f618 +#define ixDPM_TABLE_392 0x3f61c +#define ixDPM_TABLE_393 0x3f620 +#define ixDPM_TABLE_394 0x3f624 +#define ixDPM_TABLE_395 0x3f628 +#define ixDPM_TABLE_396 0x3f62c +#define ixDPM_TABLE_397 0x3f630 +#define ixDPM_TABLE_398 0x3f634 +#define ixDPM_TABLE_399 0x3f638 +#define ixDPM_TABLE_400 0x3f63c +#define ixDPM_TABLE_401 0x3f640 +#define ixDPM_TABLE_402 0x3f644 +#define ixDPM_TABLE_403 0x3f648 +#define ixDPM_TABLE_404 0x3f64c +#define ixDPM_TABLE_405 0x3f650 +#define ixDPM_TABLE_406 0x3f654 +#define ixDPM_TABLE_407 0x3f658 +#define ixDPM_TABLE_408 0x3f65c +#define ixDPM_TABLE_409 0x3f660 +#define ixDPM_TABLE_410 0x3f664 +#define ixDPM_TABLE_411 0x3f668 +#define ixDPM_TABLE_412 0x3f66c +#define ixDPM_TABLE_413 0x3f670 +#define ixDPM_TABLE_414 0x3f674 +#define ixDPM_TABLE_415 0x3f678 +#define ixDPM_TABLE_416 0x3f67c +#define ixDPM_TABLE_417 0x3f680 +#define ixDPM_TABLE_418 0x3f684 +#define ixDPM_TABLE_419 0x3f688 +#define ixDPM_TABLE_420 0x3f68c +#define ixDPM_TABLE_421 0x3f690 +#define ixDPM_TABLE_422 0x3f694 +#define ixDPM_TABLE_423 0x3f698 +#define ixDPM_TABLE_424 0x3f69c +#define ixDPM_TABLE_425 0x3f6a0 +#define ixDPM_TABLE_426 0x3f6a4 +#define ixDPM_TABLE_427 0x3f6a8 +#define ixDPM_TABLE_428 0x3f6ac +#define ixDPM_TABLE_429 0x3f6b0 +#define ixDPM_TABLE_430 0x3f6b4 +#define ixDPM_TABLE_431 0x3f6b8 +#define ixDPM_TABLE_432 0x3f6bc +#define ixDPM_TABLE_433 0x3f6c0 +#define ixDPM_TABLE_434 0x3f6c4 +#define ixDPM_TABLE_435 0x3f6c8 +#define ixDPM_TABLE_436 0x3f6cc +#define ixDPM_TABLE_437 0x3f6d0 +#define ixDPM_TABLE_438 0x3f6d4 +#define ixDPM_TABLE_439 0x3f6d8 +#define ixDPM_TABLE_440 0x3f6dc +#define ixDPM_TABLE_441 0x3f6e0 +#define ixDPM_TABLE_442 0x3f6e4 +#define ixDPM_TABLE_443 0x3f6e8 +#define ixDPM_TABLE_444 0x3f6ec +#define ixDPM_TABLE_445 0x3f6f0 +#define ixDPM_TABLE_446 0x3f6f4 +#define ixDPM_TABLE_447 0x3f6f8 +#define ixDPM_TABLE_448 0x3f6fc +#define ixDPM_TABLE_449 0x3f700 +#define ixDPM_TABLE_450 0x3f704 +#define ixDPM_TABLE_451 0x3f708 +#define ixDPM_TABLE_452 0x3f70c +#define ixDPM_TABLE_453 0x3f710 +#define ixDPM_TABLE_454 0x3f714 +#define ixDPM_TABLE_455 0x3f718 +#define ixDPM_TABLE_456 0x3f71c +#define ixDPM_TABLE_457 0x3f720 +#define ixDPM_TABLE_458 0x3f724 +#define ixDPM_TABLE_459 0x3f728 +#define ixDPM_TABLE_460 0x3f72c +#define ixDPM_TABLE_461 0x3f730 +#define ixDPM_TABLE_462 0x3f734 +#define ixDPM_TABLE_463 0x3f738 +#define ixDPM_TABLE_464 0x3f73c +#define ixDPM_TABLE_465 0x3f740 +#define ixDPM_TABLE_466 0x3f744 +#define ixDPM_TABLE_467 0x3f748 +#define ixDPM_TABLE_468 0x3f74c +#define ixDPM_TABLE_469 0x3f750 +#define ixDPM_TABLE_470 0x3f754 +#define ixDPM_TABLE_471 0x3f758 +#define ixDPM_TABLE_472 0x3f75c +#define ixDPM_TABLE_473 0x3f760 +#define ixDPM_TABLE_474 0x3f764 +#define ixDPM_TABLE_475 0x3f768 +#define ixDPM_TABLE_476 0x3f76c +#define ixDPM_TABLE_477 0x3f770 +#define ixDPM_TABLE_478 0x3f774 +#define ixDPM_TABLE_479 0x3f778 +#define ixDPM_TABLE_480 0x3f77c +#define ixDPM_TABLE_481 0x3f780 +#define ixDPM_TABLE_482 0x3f784 +#define ixDPM_TABLE_483 0x3f788 +#define ixDPM_TABLE_484 0x3f78c +#define ixDPM_TABLE_485 0x3f790 +#define ixDPM_TABLE_486 0x3f794 +#define ixDPM_TABLE_487 0x3f798 +#define ixDPM_TABLE_488 0x3f79c +#define ixDPM_TABLE_489 0x3f7a0 +#define ixDPM_TABLE_490 0x3f7a4 +#define ixDPM_TABLE_491 0x3f7a8 +#define ixDPM_TABLE_492 0x3f7ac +#define ixDPM_TABLE_493 0x3f7b0 +#define ixDPM_TABLE_494 0x3f7b4 +#define ixDPM_TABLE_495 0x3f7b8 +#define ixDPM_TABLE_496 0x3f7bc +#define ixDPM_TABLE_497 0x3f7c0 +#define ixDPM_TABLE_498 0x3f7c4 +#define ixDPM_TABLE_499 0x3f7c8 +#define ixDPM_TABLE_500 0x3f7cc +#define ixDPM_TABLE_501 0x3f7d0 +#define ixDPM_TABLE_502 0x3f7d4 +#define ixDPM_TABLE_503 0x3f7d8 +#define ixDPM_TABLE_504 0x3f7dc +#define ixDPM_TABLE_505 0x3f7e0 +#define ixDPM_TABLE_506 0x3f7e4 +#define ixFIRMWARE_FLAGS 0x3f800 +#define ixTDC_STATUS 0x3f808 +#define ixTDC_MV_AVERAGE 0x3f80c +#define ixTDC_VRM_LIMIT 0x3f810 +#define ixFEATURE_STATUS 0x3f818 +#define ixENTITY_TEMPERATURES_1 0x3f81c +#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f900 +#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f904 +#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f908 +#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f90c +#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f910 +#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f914 +#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f918 +#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f91c +#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f920 +#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f924 +#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f928 +#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f92c +#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f930 +#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f934 +#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f938 +#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f93c +#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f940 +#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f944 +#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f948 +#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f94c +#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f950 +#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f954 +#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f958 +#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f95c +#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f960 +#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f964 +#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f968 +#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f96c +#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f970 +#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f974 +#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f978 +#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f97c +#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f980 +#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f984 +#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f988 +#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f98c +#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f990 +#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f994 +#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f998 +#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f99c +#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f9a0 +#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f9a4 +#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f9a8 +#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f9ac +#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f9b0 +#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f9b4 +#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f9b8 +#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f9bc +#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f9c0 +#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f9c4 +#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f9c8 +#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f9cc +#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f9d0 +#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f9d4 +#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f9d8 +#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f9dc +#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f9e0 +#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f9e4 +#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f9e8 +#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f9ec +#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f9f0 +#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f9f4 +#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f9f8 +#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f9fc +#define ixMCARB_DRAM_TIMING_TABLE_65 0x3fa00 +#define ixMCARB_DRAM_TIMING_TABLE_66 0x3fa04 +#define ixMCARB_DRAM_TIMING_TABLE_67 0x3fa08 +#define ixMCARB_DRAM_TIMING_TABLE_68 0x3fa0c +#define ixMCARB_DRAM_TIMING_TABLE_69 0x3fa10 +#define ixMCARB_DRAM_TIMING_TABLE_70 0x3fa14 +#define ixMCARB_DRAM_TIMING_TABLE_71 0x3fa18 +#define ixMCARB_DRAM_TIMING_TABLE_72 0x3fa1c +#define ixMCARB_DRAM_TIMING_TABLE_73 0x3fa20 +#define ixMCARB_DRAM_TIMING_TABLE_74 0x3fa24 +#define ixMCARB_DRAM_TIMING_TABLE_75 0x3fa28 +#define ixMCARB_DRAM_TIMING_TABLE_76 0x3fa2c +#define ixMCARB_DRAM_TIMING_TABLE_77 0x3fa30 +#define ixMCARB_DRAM_TIMING_TABLE_78 0x3fa34 +#define ixMCARB_DRAM_TIMING_TABLE_79 0x3fa38 +#define ixMCARB_DRAM_TIMING_TABLE_80 0x3fa3c +#define ixMCARB_DRAM_TIMING_TABLE_81 0x3fa40 +#define ixMCARB_DRAM_TIMING_TABLE_82 0x3fa44 +#define ixMCARB_DRAM_TIMING_TABLE_83 0x3fa48 +#define ixMCARB_DRAM_TIMING_TABLE_84 0x3fa4c +#define ixMCARB_DRAM_TIMING_TABLE_85 0x3fa50 +#define ixMCARB_DRAM_TIMING_TABLE_86 0x3fa54 +#define ixMCARB_DRAM_TIMING_TABLE_87 0x3fa58 +#define ixMCARB_DRAM_TIMING_TABLE_88 0x3fa5c +#define ixMCARB_DRAM_TIMING_TABLE_89 0x3fa60 +#define ixMCARB_DRAM_TIMING_TABLE_90 0x3fa64 +#define ixMCARB_DRAM_TIMING_TABLE_91 0x3fa68 +#define ixMCARB_DRAM_TIMING_TABLE_92 0x3fa6c +#define ixMCARB_DRAM_TIMING_TABLE_93 0x3fa70 +#define ixMCARB_DRAM_TIMING_TABLE_94 0x3fa74 +#define ixMCARB_DRAM_TIMING_TABLE_95 0x3fa78 +#define ixMCARB_DRAM_TIMING_TABLE_96 0x3fa7c +#define ixMCARB_DRAM_TIMING_TABLE_97 0x3fa80 +#define ixMCARB_DRAM_TIMING_TABLE_98 0x3fa84 +#define ixMCARB_DRAM_TIMING_TABLE_99 0x3fa88 +#define ixMCARB_DRAM_TIMING_TABLE_100 0x3fa8c +#define ixMCARB_DRAM_TIMING_TABLE_101 0x3fa90 +#define ixMCARB_DRAM_TIMING_TABLE_102 0x3fa94 +#define ixMCARB_DRAM_TIMING_TABLE_103 0x3fa98 +#define ixMCARB_DRAM_TIMING_TABLE_104 0x3fa9c +#define ixMCARB_DRAM_TIMING_TABLE_105 0x3faa0 +#define ixMCARB_DRAM_TIMING_TABLE_106 0x3faa4 +#define ixMCARB_DRAM_TIMING_TABLE_107 0x3faa8 +#define ixMCARB_DRAM_TIMING_TABLE_108 0x3faac +#define ixMCARB_DRAM_TIMING_TABLE_109 0x3fab0 +#define ixMCARB_DRAM_TIMING_TABLE_110 0x3fab4 +#define ixMCARB_DRAM_TIMING_TABLE_111 0x3fab8 +#define ixMCARB_DRAM_TIMING_TABLE_112 0x3fabc +#define ixMCARB_DRAM_TIMING_TABLE_113 0x3fac0 +#define ixMCARB_DRAM_TIMING_TABLE_114 0x3fac4 +#define ixMCARB_DRAM_TIMING_TABLE_115 0x3fac8 +#define ixMCARB_DRAM_TIMING_TABLE_116 0x3facc +#define ixMCARB_DRAM_TIMING_TABLE_117 0x3fad0 +#define ixMCARB_DRAM_TIMING_TABLE_118 0x3fad4 +#define ixMCARB_DRAM_TIMING_TABLE_119 0x3fad8 +#define ixMCARB_DRAM_TIMING_TABLE_120 0x3fadc +#define ixMCARB_DRAM_TIMING_TABLE_121 0x3fae0 +#define ixMCARB_DRAM_TIMING_TABLE_122 0x3fae4 +#define ixMCARB_DRAM_TIMING_TABLE_123 0x3fae8 +#define ixMCARB_DRAM_TIMING_TABLE_124 0x3faec +#define ixMCARB_DRAM_TIMING_TABLE_125 0x3faf0 +#define ixMCARB_DRAM_TIMING_TABLE_126 0x3faf4 +#define ixMCARB_DRAM_TIMING_TABLE_127 0x3faf8 +#define ixMCARB_DRAM_TIMING_TABLE_128 0x3fafc +#define ixMCARB_DRAM_TIMING_TABLE_129 0x3fb00 +#define ixMCARB_DRAM_TIMING_TABLE_130 0x3fb04 +#define ixMCARB_DRAM_TIMING_TABLE_131 0x3fb08 +#define ixMCARB_DRAM_TIMING_TABLE_132 0x3fb0c +#define ixMCARB_DRAM_TIMING_TABLE_133 0x3fb10 +#define ixMCARB_DRAM_TIMING_TABLE_134 0x3fb14 +#define ixMCARB_DRAM_TIMING_TABLE_135 0x3fb18 +#define ixMCARB_DRAM_TIMING_TABLE_136 0x3fb1c +#define ixMCARB_DRAM_TIMING_TABLE_137 0x3fb20 +#define ixMCARB_DRAM_TIMING_TABLE_138 0x3fb24 +#define ixMCARB_DRAM_TIMING_TABLE_139 0x3fb28 +#define ixMCARB_DRAM_TIMING_TABLE_140 0x3fb2c +#define ixMCARB_DRAM_TIMING_TABLE_141 0x3fb30 +#define ixMCARB_DRAM_TIMING_TABLE_142 0x3fb34 +#define ixMCARB_DRAM_TIMING_TABLE_143 0x3fb38 +#define ixMCARB_DRAM_TIMING_TABLE_144 0x3fb3c +#define ixMC_REGISTERS_TABLE_1 0x3fb40 +#define ixMC_REGISTERS_TABLE_2 0x3fb44 +#define ixMC_REGISTERS_TABLE_3 0x3fb48 +#define ixMC_REGISTERS_TABLE_4 0x3fb4c +#define ixMC_REGISTERS_TABLE_5 0x3fb50 +#define ixMC_REGISTERS_TABLE_6 0x3fb54 +#define ixMC_REGISTERS_TABLE_7 0x3fb58 +#define ixMC_REGISTERS_TABLE_8 0x3fb5c +#define ixMC_REGISTERS_TABLE_9 0x3fb60 +#define ixMC_REGISTERS_TABLE_10 0x3fb64 +#define ixMC_REGISTERS_TABLE_11 0x3fb68 +#define ixMC_REGISTERS_TABLE_12 0x3fb6c +#define ixMC_REGISTERS_TABLE_13 0x3fb70 +#define ixMC_REGISTERS_TABLE_14 0x3fb74 +#define ixMC_REGISTERS_TABLE_15 0x3fb78 +#define ixMC_REGISTERS_TABLE_16 0x3fb7c +#define ixMC_REGISTERS_TABLE_17 0x3fb80 +#define ixMC_REGISTERS_TABLE_18 0x3fb84 +#define ixMC_REGISTERS_TABLE_19 0x3fb88 +#define ixMC_REGISTERS_TABLE_20 0x3fb8c +#define ixMC_REGISTERS_TABLE_21 0x3fb90 +#define ixMC_REGISTERS_TABLE_22 0x3fb94 +#define ixMC_REGISTERS_TABLE_23 0x3fb98 +#define ixMC_REGISTERS_TABLE_24 0x3fb9c +#define ixMC_REGISTERS_TABLE_25 0x3fba0 +#define ixMC_REGISTERS_TABLE_26 0x3fba4 +#define ixMC_REGISTERS_TABLE_27 0x3fba8 +#define ixMC_REGISTERS_TABLE_28 0x3fbac +#define ixMC_REGISTERS_TABLE_29 0x3fbb0 +#define ixMC_REGISTERS_TABLE_30 0x3fbb4 +#define ixMC_REGISTERS_TABLE_31 0x3fbb8 +#define ixMC_REGISTERS_TABLE_32 0x3fbbc +#define ixMC_REGISTERS_TABLE_33 0x3fbc0 +#define ixMC_REGISTERS_TABLE_34 0x3fbc4 +#define ixMC_REGISTERS_TABLE_35 0x3fbc8 +#define ixMC_REGISTERS_TABLE_36 0x3fbcc +#define ixMC_REGISTERS_TABLE_37 0x3fbd0 +#define ixMC_REGISTERS_TABLE_38 0x3fbd4 +#define ixMC_REGISTERS_TABLE_39 0x3fbd8 +#define ixMC_REGISTERS_TABLE_40 0x3fbdc +#define ixMC_REGISTERS_TABLE_41 0x3fbe0 +#define ixMC_REGISTERS_TABLE_42 0x3fbe4 +#define ixMC_REGISTERS_TABLE_43 0x3fbe8 +#define ixMC_REGISTERS_TABLE_44 0x3fbec +#define ixMC_REGISTERS_TABLE_45 0x3fbf0 +#define ixMC_REGISTERS_TABLE_46 0x3fbf4 +#define ixMC_REGISTERS_TABLE_47 0x3fbf8 +#define ixMC_REGISTERS_TABLE_48 0x3fbfc +#define ixMC_REGISTERS_TABLE_49 0x3fc00 +#define ixMC_REGISTERS_TABLE_50 0x3fc04 +#define ixMC_REGISTERS_TABLE_51 0x3fc08 +#define ixMC_REGISTERS_TABLE_52 0x3fc0c +#define ixMC_REGISTERS_TABLE_53 0x3fc10 +#define ixMC_REGISTERS_TABLE_54 0x3fc14 +#define ixMC_REGISTERS_TABLE_55 0x3fc18 +#define ixMC_REGISTERS_TABLE_56 0x3fc1c +#define ixMC_REGISTERS_TABLE_57 0x3fc20 +#define ixMC_REGISTERS_TABLE_58 0x3fc24 +#define ixMC_REGISTERS_TABLE_59 0x3fc28 +#define ixMC_REGISTERS_TABLE_60 0x3fc2c +#define ixMC_REGISTERS_TABLE_61 0x3fc30 +#define ixMC_REGISTERS_TABLE_62 0x3fc34 +#define ixMC_REGISTERS_TABLE_63 0x3fc38 +#define ixMC_REGISTERS_TABLE_64 0x3fc3c +#define ixMC_REGISTERS_TABLE_65 0x3fc40 +#define ixMC_REGISTERS_TABLE_66 0x3fc44 +#define ixMC_REGISTERS_TABLE_67 0x3fc48 +#define ixMC_REGISTERS_TABLE_68 0x3fc4c +#define ixMC_REGISTERS_TABLE_69 0x3fc50 +#define ixMC_REGISTERS_TABLE_70 0x3fc54 +#define ixMC_REGISTERS_TABLE_71 0x3fc58 +#define ixMC_REGISTERS_TABLE_72 0x3fc5c +#define ixMC_REGISTERS_TABLE_73 0x3fc60 +#define ixMC_REGISTERS_TABLE_74 0x3fc64 +#define ixMC_REGISTERS_TABLE_75 0x3fc68 +#define ixMC_REGISTERS_TABLE_76 0x3fc6c +#define ixMC_REGISTERS_TABLE_77 0x3fc70 +#define ixMC_REGISTERS_TABLE_78 0x3fc74 +#define ixMC_REGISTERS_TABLE_79 0x3fc78 +#define ixMC_REGISTERS_TABLE_80 0x3fc7c +#define ixMC_REGISTERS_TABLE_81 0x3fc80 +#define ixMC_REGISTERS_TABLE_82 0x3fc84 +#define ixMC_REGISTERS_TABLE_83 0x3fc88 +#define ixMC_REGISTERS_TABLE_84 0x3fc8c +#define ixMC_REGISTERS_TABLE_85 0x3fc90 +#define ixMC_REGISTERS_TABLE_86 0x3fc94 +#define ixMC_REGISTERS_TABLE_87 0x3fc98 +#define ixMC_REGISTERS_TABLE_88 0x3fc9c +#define ixMC_REGISTERS_TABLE_89 0x3fca0 +#define ixMC_REGISTERS_TABLE_90 0x3fca4 +#define ixMC_REGISTERS_TABLE_91 0x3fca8 +#define ixMC_REGISTERS_TABLE_92 0x3fcac +#define ixMC_REGISTERS_TABLE_93 0x3fcb0 +#define ixMC_REGISTERS_TABLE_94 0x3fcb4 +#define ixMC_REGISTERS_TABLE_95 0x3fcb8 +#define ixMC_REGISTERS_TABLE_96 0x3fcbc +#define ixMC_REGISTERS_TABLE_97 0x3fcc0 +#define ixMC_REGISTERS_TABLE_98 0x3fcc4 +#define ixMC_REGISTERS_TABLE_99 0x3fcc8 +#define ixMC_REGISTERS_TABLE_100 0x3fccc +#define ixMC_REGISTERS_TABLE_101 0x3fcd0 +#define ixMC_REGISTERS_TABLE_102 0x3fcd4 +#define ixMC_REGISTERS_TABLE_103 0x3fcd8 +#define ixMC_REGISTERS_TABLE_104 0x3fcdc +#define ixMC_REGISTERS_TABLE_105 0x3fce0 +#define ixMC_REGISTERS_TABLE_106 0x3fce4 +#define ixMC_REGISTERS_TABLE_107 0x3fce8 +#define ixMC_REGISTERS_TABLE_108 0x3fcec +#define ixMC_REGISTERS_TABLE_109 0x3fcf0 +#define ixMC_REGISTERS_TABLE_110 0x3fcf4 +#define ixMC_REGISTERS_TABLE_111 0x3fcf8 +#define ixMC_REGISTERS_TABLE_112 0x3fcfc +#define ixMC_REGISTERS_TABLE_113 0x3fd00 +#define ixFAN_TABLE_1 0x3fd04 +#define ixFAN_TABLE_2 0x3fd08 +#define ixFAN_TABLE_3 0x3fd0c +#define ixFAN_TABLE_4 0x3fd10 +#define ixFAN_TABLE_5 0x3fd14 +#define ixFAN_TABLE_6 0x3fd18 +#define ixFAN_TABLE_7 0x3fd1c +#define ixFAN_TABLE_8 0x3fd20 +#define ixFAN_TABLE_9 0x3fd24 +#define ixSOFT_REGISTERS_TABLE_1 0x3fd28 +#define ixSOFT_REGISTERS_TABLE_2 0x3fd2c +#define ixSOFT_REGISTERS_TABLE_3 0x3fd30 +#define ixSOFT_REGISTERS_TABLE_4 0x3fd34 +#define ixSOFT_REGISTERS_TABLE_5 0x3fd38 +#define ixSOFT_REGISTERS_TABLE_6 0x3fd3c +#define ixSOFT_REGISTERS_TABLE_7 0x3fd40 +#define ixSOFT_REGISTERS_TABLE_8 0x3fd44 +#define ixSOFT_REGISTERS_TABLE_9 0x3fd48 +#define ixSOFT_REGISTERS_TABLE_10 0x3fd4c +#define ixSOFT_REGISTERS_TABLE_11 0x3fd50 +#define ixSOFT_REGISTERS_TABLE_12 0x3fd54 +#define ixSOFT_REGISTERS_TABLE_13 0x3fd58 +#define ixSOFT_REGISTERS_TABLE_14 0x3fd5c +#define ixSOFT_REGISTERS_TABLE_15 0x3fd60 +#define ixSOFT_REGISTERS_TABLE_16 0x3fd64 +#define ixSOFT_REGISTERS_TABLE_17 0x3fd68 +#define ixSOFT_REGISTERS_TABLE_18 0x3fd6c +#define ixSOFT_REGISTERS_TABLE_19 0x3fd70 +#define ixSOFT_REGISTERS_TABLE_20 0x3fd74 +#define ixSOFT_REGISTERS_TABLE_21 0x3fd78 +#define ixSOFT_REGISTERS_TABLE_22 0x3fd7c +#define ixSOFT_REGISTERS_TABLE_23 0x3fd80 +#define ixSOFT_REGISTERS_TABLE_24 0x3fd84 +#define ixSOFT_REGISTERS_TABLE_25 0x3fd88 +#define ixSOFT_REGISTERS_TABLE_26 0x3fd8c +#define ixSOFT_REGISTERS_TABLE_27 0x3fd90 +#define ixSOFT_REGISTERS_TABLE_28 0x3fd94 +#define ixSOFT_REGISTERS_TABLE_29 0x3fd98 +#define ixSOFT_REGISTERS_TABLE_30 0x3fd9c +#define ixPM_FUSES_1 0x3fda0 +#define ixPM_FUSES_2 0x3fda4 +#define ixPM_FUSES_3 0x3fda8 +#define ixPM_FUSES_4 0x3fdac +#define ixPM_FUSES_5 0x3fdb0 +#define ixPM_FUSES_6 0x3fdb4 +#define ixPM_FUSES_7 0x3fdb8 +#define ixPM_FUSES_8 0x3fdbc +#define ixPM_FUSES_9 0x3fdc0 +#define ixPM_FUSES_10 0x3fdc4 +#define ixPM_FUSES_11 0x3fdc8 +#define ixPM_FUSES_12 0x3fdcc +#define ixPM_FUSES_13 0x3fdd0 +#define ixPM_FUSES_14 0x3fdd4 +#define ixPM_FUSES_15 0x3fdd8 +#define ixPM_FUSES_16 0x3fddc +#define ixPM_FUSES_17 0x3fde0 +#define ixPM_FUSES_18 0x3fde4 +#define ixPM_FUSES_19 0x3fde8 +#define ixSMU_PM_STATUS_0 0x3fe00 +#define ixSMU_PM_STATUS_1 0x3fe04 +#define ixSMU_PM_STATUS_2 0x3fe08 +#define ixSMU_PM_STATUS_3 0x3fe0c +#define ixSMU_PM_STATUS_4 0x3fe10 +#define ixSMU_PM_STATUS_5 0x3fe14 +#define ixSMU_PM_STATUS_6 0x3fe18 +#define ixSMU_PM_STATUS_7 0x3fe1c +#define ixSMU_PM_STATUS_8 0x3fe20 +#define ixSMU_PM_STATUS_9 0x3fe24 +#define ixSMU_PM_STATUS_10 0x3fe28 +#define ixSMU_PM_STATUS_11 0x3fe2c +#define ixSMU_PM_STATUS_12 0x3fe30 +#define ixSMU_PM_STATUS_13 0x3fe34 +#define ixSMU_PM_STATUS_14 0x3fe38 +#define ixSMU_PM_STATUS_15 0x3fe3c +#define ixSMU_PM_STATUS_16 0x3fe40 +#define ixSMU_PM_STATUS_17 0x3fe44 +#define ixSMU_PM_STATUS_18 0x3fe48 +#define ixSMU_PM_STATUS_19 0x3fe4c +#define ixSMU_PM_STATUS_20 0x3fe50 +#define ixSMU_PM_STATUS_21 0x3fe54 +#define ixSMU_PM_STATUS_22 0x3fe58 +#define ixSMU_PM_STATUS_23 0x3fe5c +#define ixSMU_PM_STATUS_24 0x3fe60 +#define ixSMU_PM_STATUS_25 0x3fe64 +#define ixSMU_PM_STATUS_26 0x3fe68 +#define ixSMU_PM_STATUS_27 0x3fe6c +#define ixSMU_PM_STATUS_28 0x3fe70 +#define ixSMU_PM_STATUS_29 0x3fe74 +#define ixSMU_PM_STATUS_30 0x3fe78 +#define ixSMU_PM_STATUS_31 0x3fe7c +#define ixSMU_PM_STATUS_32 0x3fe80 +#define ixSMU_PM_STATUS_33 0x3fe84 +#define ixSMU_PM_STATUS_34 0x3fe88 +#define ixSMU_PM_STATUS_35 0x3fe8c +#define ixSMU_PM_STATUS_36 0x3fe90 +#define ixSMU_PM_STATUS_37 0x3fe94 +#define ixSMU_PM_STATUS_38 0x3fe98 +#define ixSMU_PM_STATUS_39 0x3fe9c +#define ixSMU_PM_STATUS_40 0x3fea0 +#define ixSMU_PM_STATUS_41 0x3fea4 +#define ixSMU_PM_STATUS_42 0x3fea8 +#define ixSMU_PM_STATUS_43 0x3feac +#define ixSMU_PM_STATUS_44 0x3feb0 +#define ixSMU_PM_STATUS_45 0x3feb4 +#define ixSMU_PM_STATUS_46 0x3feb8 +#define ixSMU_PM_STATUS_47 0x3febc +#define ixSMU_PM_STATUS_48 0x3fec0 +#define ixSMU_PM_STATUS_49 0x3fec4 +#define ixSMU_PM_STATUS_50 0x3fec8 +#define ixSMU_PM_STATUS_51 0x3fecc +#define ixSMU_PM_STATUS_52 0x3fed0 +#define ixSMU_PM_STATUS_53 0x3fed4 +#define ixSMU_PM_STATUS_54 0x3fed8 +#define ixSMU_PM_STATUS_55 0x3fedc +#define ixSMU_PM_STATUS_56 0x3fee0 +#define ixSMU_PM_STATUS_57 0x3fee4 +#define ixSMU_PM_STATUS_58 0x3fee8 +#define ixSMU_PM_STATUS_59 0x3feec +#define ixSMU_PM_STATUS_60 0x3fef0 +#define ixSMU_PM_STATUS_61 0x3fef4 +#define ixSMU_PM_STATUS_62 0x3fef8 +#define ixSMU_PM_STATUS_63 0x3fefc +#define ixSMU_PM_STATUS_64 0x3ff00 +#define ixSMU_PM_STATUS_65 0x3ff04 +#define ixSMU_PM_STATUS_66 0x3ff08 +#define ixSMU_PM_STATUS_67 0x3ff0c +#define ixSMU_PM_STATUS_68 0x3ff10 +#define ixSMU_PM_STATUS_69 0x3ff14 +#define ixSMU_PM_STATUS_70 0x3ff18 +#define ixSMU_PM_STATUS_71 0x3ff1c +#define ixSMU_PM_STATUS_72 0x3ff20 +#define ixSMU_PM_STATUS_73 0x3ff24 +#define ixSMU_PM_STATUS_74 0x3ff28 +#define ixSMU_PM_STATUS_75 0x3ff2c +#define ixSMU_PM_STATUS_76 0x3ff30 +#define ixSMU_PM_STATUS_77 0x3ff34 +#define ixSMU_PM_STATUS_78 0x3ff38 +#define ixSMU_PM_STATUS_79 0x3ff3c +#define ixSMU_PM_STATUS_80 0x3ff40 +#define ixSMU_PM_STATUS_81 0x3ff44 +#define ixSMU_PM_STATUS_82 0x3ff48 +#define ixSMU_PM_STATUS_83 0x3ff4c +#define ixSMU_PM_STATUS_84 0x3ff50 +#define ixSMU_PM_STATUS_85 0x3ff54 +#define ixSMU_PM_STATUS_86 0x3ff58 +#define ixSMU_PM_STATUS_87 0x3ff5c +#define ixSMU_PM_STATUS_88 0x3ff60 +#define ixSMU_PM_STATUS_89 0x3ff64 +#define ixSMU_PM_STATUS_90 0x3ff68 +#define ixSMU_PM_STATUS_91 0x3ff6c +#define ixSMU_PM_STATUS_92 0x3ff70 +#define ixSMU_PM_STATUS_93 0x3ff74 +#define ixSMU_PM_STATUS_94 0x3ff78 +#define ixSMU_PM_STATUS_95 0x3ff7c +#define ixSMU_PM_STATUS_96 0x3ff80 +#define ixSMU_PM_STATUS_97 0x3ff84 +#define ixSMU_PM_STATUS_98 0x3ff88 +#define ixSMU_PM_STATUS_99 0x3ff8c +#define ixSMU_PM_STATUS_100 0x3ff90 +#define ixSMU_PM_STATUS_101 0x3ff94 +#define ixSMU_PM_STATUS_102 0x3ff98 +#define ixSMU_PM_STATUS_103 0x3ff9c +#define ixSMU_PM_STATUS_104 0x3ffa0 +#define ixSMU_PM_STATUS_105 0x3ffa4 +#define ixSMU_PM_STATUS_106 0x3ffa8 +#define ixSMU_PM_STATUS_107 0x3ffac +#define ixSMU_PM_STATUS_108 0x3ffb0 +#define ixSMU_PM_STATUS_109 0x3ffb4 +#define ixSMU_PM_STATUS_110 0x3ffb8 +#define ixSMU_PM_STATUS_111 0x3ffbc +#define ixSMU_PM_STATUS_112 0x3ffc0 +#define ixSMU_PM_STATUS_113 0x3ffc4 +#define ixSMU_PM_STATUS_114 0x3ffc8 +#define ixSMU_PM_STATUS_115 0x3ffcc +#define ixSMU_PM_STATUS_116 0x3ffd0 +#define ixSMU_PM_STATUS_117 0x3ffd4 +#define ixSMU_PM_STATUS_118 0x3ffd8 +#define ixSMU_PM_STATUS_119 0x3ffdc +#define ixSMU_PM_STATUS_120 0x3ffe0 +#define ixSMU_PM_STATUS_121 0x3ffe4 +#define ixSMU_PM_STATUS_122 0x3ffe8 +#define ixSMU_PM_STATUS_123 0x3ffec +#define ixSMU_PM_STATUS_124 0x3fff0 +#define ixSMU_PM_STATUS_125 0x3fff4 +#define ixSMU_PM_STATUS_126 0x3fff8 +#define ixSMU_PM_STATUS_127 0x3fffc +#define ixCG_THERMAL_INT_ENA 0xc2100024 +#define ixCG_THERMAL_INT_CTRL 0xc2100028 +#define ixCG_THERMAL_INT_STATUS 0xc210002c +#define ixCG_THERMAL_CTRL 0xc0300004 +#define ixCG_THERMAL_STATUS 0xc0300008 +#define ixCG_THERMAL_INT 0xc030000c +#define ixCG_MULT_THERMAL_CTRL 0xc0300010 +#define ixCG_MULT_THERMAL_STATUS 0xc0300014 +#define ixCG_FDO_CTRL0 0xc0300064 +#define ixCG_FDO_CTRL1 0xc0300068 +#define ixCG_FDO_CTRL2 0xc030006c +#define ixCG_TACH_CTRL 0xc0300070 +#define ixCG_TACH_STATUS 0xc0300074 +#define ixCC_THM_STRAPS0 0xc0300080 +#define ixTHM_TMON0_RDIL0_DATA 0xc0300100 +#define ixTHM_TMON0_RDIL1_DATA 0xc0300104 +#define ixTHM_TMON0_RDIL2_DATA 0xc0300108 +#define ixTHM_TMON0_RDIL3_DATA 0xc030010c +#define ixTHM_TMON0_RDIL4_DATA 0xc0300110 +#define ixTHM_TMON0_RDIL5_DATA 0xc0300114 +#define ixTHM_TMON0_RDIL6_DATA 0xc0300118 +#define ixTHM_TMON0_RDIL7_DATA 0xc030011c +#define ixTHM_TMON0_RDIL8_DATA 0xc0300120 +#define ixTHM_TMON0_RDIL9_DATA 0xc0300124 +#define ixTHM_TMON0_RDIL10_DATA 0xc0300128 +#define ixTHM_TMON0_RDIL11_DATA 0xc030012c +#define ixTHM_TMON0_RDIL12_DATA 0xc0300130 +#define ixTHM_TMON0_RDIL13_DATA 0xc0300134 +#define ixTHM_TMON0_RDIL14_DATA 0xc0300138 +#define ixTHM_TMON0_RDIL15_DATA 0xc030013c +#define ixTHM_TMON0_RDIR0_DATA 0xc0300140 +#define ixTHM_TMON0_RDIR1_DATA 0xc0300144 +#define ixTHM_TMON0_RDIR2_DATA 0xc0300148 +#define ixTHM_TMON0_RDIR3_DATA 0xc030014c +#define ixTHM_TMON0_RDIR4_DATA 0xc0300150 +#define ixTHM_TMON0_RDIR5_DATA 0xc0300154 +#define ixTHM_TMON0_RDIR6_DATA 0xc0300158 +#define ixTHM_TMON0_RDIR7_DATA 0xc030015c +#define ixTHM_TMON0_RDIR8_DATA 0xc0300160 +#define ixTHM_TMON0_RDIR9_DATA 0xc0300164 +#define ixTHM_TMON0_RDIR10_DATA 0xc0300168 +#define ixTHM_TMON0_RDIR11_DATA 0xc030016c +#define ixTHM_TMON0_RDIR12_DATA 0xc0300170 +#define ixTHM_TMON0_RDIR13_DATA 0xc0300174 +#define ixTHM_TMON0_RDIR14_DATA 0xc0300178 +#define ixTHM_TMON0_RDIR15_DATA 0xc030017c +#define ixTHM_TMON1_RDIL0_DATA 0xc0300180 +#define ixTHM_TMON1_RDIL1_DATA 0xc0300184 +#define ixTHM_TMON1_RDIL2_DATA 0xc0300188 +#define ixTHM_TMON1_RDIL3_DATA 0xc030018c +#define ixTHM_TMON1_RDIL4_DATA 0xc0300190 +#define ixTHM_TMON1_RDIL5_DATA 0xc0300194 +#define ixTHM_TMON1_RDIL6_DATA 0xc0300198 +#define ixTHM_TMON1_RDIL7_DATA 0xc030019c +#define ixTHM_TMON1_RDIL8_DATA 0xc03001a0 +#define ixTHM_TMON1_RDIL9_DATA 0xc03001a4 +#define ixTHM_TMON1_RDIL10_DATA 0xc03001a8 +#define ixTHM_TMON1_RDIL11_DATA 0xc03001ac +#define ixTHM_TMON1_RDIL12_DATA 0xc03001b0 +#define ixTHM_TMON1_RDIL13_DATA 0xc03001b4 +#define ixTHM_TMON1_RDIL14_DATA 0xc03001b8 +#define ixTHM_TMON1_RDIL15_DATA 0xc03001bc +#define ixTHM_TMON1_RDIR0_DATA 0xc03001c0 +#define ixTHM_TMON1_RDIR1_DATA 0xc03001c4 +#define ixTHM_TMON1_RDIR2_DATA 0xc03001c8 +#define ixTHM_TMON1_RDIR3_DATA 0xc03001cc +#define ixTHM_TMON1_RDIR4_DATA 0xc03001d0 +#define ixTHM_TMON1_RDIR5_DATA 0xc03001d4 +#define ixTHM_TMON1_RDIR6_DATA 0xc03001d8 +#define ixTHM_TMON1_RDIR7_DATA 0xc03001dc +#define ixTHM_TMON1_RDIR8_DATA 0xc03001e0 +#define ixTHM_TMON1_RDIR9_DATA 0xc03001e4 +#define ixTHM_TMON1_RDIR10_DATA 0xc03001e8 +#define ixTHM_TMON1_RDIR11_DATA 0xc03001ec +#define ixTHM_TMON1_RDIR12_DATA 0xc03001f0 +#define ixTHM_TMON1_RDIR13_DATA 0xc03001f4 +#define ixTHM_TMON1_RDIR14_DATA 0xc03001f8 +#define ixTHM_TMON1_RDIR15_DATA 0xc03001fc +#define ixTHM_TMON0_INT_DATA 0xc0300300 +#define ixTHM_TMON1_INT_DATA 0xc0300304 +#define ixTHM_TMON0_DEBUG 0xc0300310 +#define ixTHM_TMON1_DEBUG 0xc0300314 +#define ixGENERAL_PWRMGT 0xc0200000 +#define ixCNB_PWRMGT_CNTL 0xc0200004 +#define ixSCLK_PWRMGT_CNTL 0xc0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 +#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 +#define ixPLL_TEST_CNTL 0xc020003c +#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 +#define ixCG_DISPLAY_GAP_CNTL 0xc0200060 +#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 +#define ixCG_ACPI_CNTL 0xc0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 +#define ixCG_ULV_PARAMETER 0xc020015c +#define ixSCLK_MIN_DIV 0xc0200308 +#define ixLCAC_SX0_CNTL 0xc0400d00 +#define ixLCAC_SX0_OVR_SEL 0xc0400d04 +#define ixLCAC_SX0_OVR_VAL 0xc0400d08 +#define ixLCAC_MC0_CNTL 0xc0400d30 +#define ixLCAC_MC0_OVR_SEL 0xc0400d34 +#define ixLCAC_MC0_OVR_VAL 0xc0400d38 +#define ixLCAC_MC1_CNTL 0xc0400d3c +#define ixLCAC_MC1_OVR_SEL 0xc0400d40 +#define ixLCAC_MC1_OVR_VAL 0xc0400d44 +#define ixLCAC_MC2_CNTL 0xc0400d48 +#define ixLCAC_MC2_OVR_SEL 0xc0400d4c +#define ixLCAC_MC2_OVR_VAL 0xc0400d50 +#define ixLCAC_MC3_CNTL 0xc0400d54 +#define ixLCAC_MC3_OVR_SEL 0xc0400d58 +#define ixLCAC_MC3_OVR_VAL 0xc0400d5c +#define ixLCAC_CPL_CNTL 0xc0400d80 +#define ixLCAC_CPL_OVR_SEL 0xc0400d84 +#define ixLCAC_CPL_OVR_VAL 0xc0400d88 +#define mmROM_SMC_IND_INDEX 0x80 +#define mmROM0_ROM_SMC_IND_INDEX 0x80 +#define mmROM1_ROM_SMC_IND_INDEX 0x82 +#define mmROM2_ROM_SMC_IND_INDEX 0x84 +#define mmROM3_ROM_SMC_IND_INDEX 0x86 +#define mmROM_SMC_IND_DATA 0x81 +#define mmROM0_ROM_SMC_IND_DATA 0x81 +#define mmROM1_ROM_SMC_IND_DATA 0x83 +#define mmROM2_ROM_SMC_IND_DATA 0x85 +#define mmROM3_ROM_SMC_IND_DATA 0x87 +#define ixROM_CNTL 0xc0600000 +#define ixPAGE_MIRROR_CNTL 0xc0600004 +#define ixROM_STATUS 0xc0600008 +#define ixCGTT_ROM_CLK_CTRL0 0xc060000c +#define ixROM_INDEX 0xc0600010 +#define ixROM_DATA 0xc0600014 +#define ixROM_START 0xc0600018 +#define ixROM_SW_CNTL 0xc060001c +#define ixROM_SW_STATUS 0xc0600020 +#define ixROM_SW_COMMAND 0xc0600024 +#define ixROM_SW_DATA_1 0xc0600028 +#define ixROM_SW_DATA_2 0xc060002c +#define ixROM_SW_DATA_3 0xc0600030 +#define ixROM_SW_DATA_4 0xc0600034 +#define ixROM_SW_DATA_5 0xc0600038 +#define ixROM_SW_DATA_6 0xc060003c +#define ixROM_SW_DATA_7 0xc0600040 +#define ixROM_SW_DATA_8 0xc0600044 +#define ixROM_SW_DATA_9 0xc0600048 +#define ixROM_SW_DATA_10 0xc060004c +#define ixROM_SW_DATA_11 0xc0600050 +#define ixROM_SW_DATA_12 0xc0600054 +#define ixROM_SW_DATA_13 0xc0600058 +#define ixROM_SW_DATA_14 0xc060005c +#define ixROM_SW_DATA_15 0xc0600060 +#define ixROM_SW_DATA_16 0xc0600064 +#define ixROM_SW_DATA_17 0xc0600068 +#define ixROM_SW_DATA_18 0xc060006c +#define ixROM_SW_DATA_19 0xc0600070 +#define ixROM_SW_DATA_20 0xc0600074 +#define ixROM_SW_DATA_21 0xc0600078 +#define ixROM_SW_DATA_22 0xc060007c +#define ixROM_SW_DATA_23 0xc0600080 +#define ixROM_SW_DATA_24 0xc0600084 +#define ixROM_SW_DATA_25 0xc0600088 +#define ixROM_SW_DATA_26 0xc060008c +#define ixROM_SW_DATA_27 0xc0600090 +#define ixROM_SW_DATA_28 0xc0600094 +#define ixROM_SW_DATA_29 0xc0600098 +#define ixROM_SW_DATA_30 0xc060009c +#define ixROM_SW_DATA_31 0xc06000a0 +#define ixROM_SW_DATA_32 0xc06000a4 +#define ixROM_SW_DATA_33 0xc06000a8 +#define ixROM_SW_DATA_34 0xc06000ac +#define ixROM_SW_DATA_35 0xc06000b0 +#define ixROM_SW_DATA_36 0xc06000b4 +#define ixROM_SW_DATA_37 0xc06000b8 +#define ixROM_SW_DATA_38 0xc06000bc +#define ixROM_SW_DATA_39 0xc06000c0 +#define ixROM_SW_DATA_40 0xc06000c4 +#define ixROM_SW_DATA_41 0xc06000c8 +#define ixROM_SW_DATA_42 0xc06000cc +#define ixROM_SW_DATA_43 0xc06000d0 +#define ixROM_SW_DATA_44 0xc06000d4 +#define ixROM_SW_DATA_45 0xc06000d8 +#define ixROM_SW_DATA_46 0xc06000dc +#define ixROM_SW_DATA_47 0xc06000e0 +#define ixROM_SW_DATA_48 0xc06000e4 +#define ixROM_SW_DATA_49 0xc06000e8 +#define ixROM_SW_DATA_50 0xc06000ec +#define ixROM_SW_DATA_51 0xc06000f0 +#define ixROM_SW_DATA_52 0xc06000f4 +#define ixROM_SW_DATA_53 0xc06000f8 +#define ixROM_SW_DATA_54 0xc06000fc +#define ixROM_SW_DATA_55 0xc0600100 +#define ixROM_SW_DATA_56 0xc0600104 +#define ixROM_SW_DATA_57 0xc0600108 +#define ixROM_SW_DATA_58 0xc060010c +#define ixROM_SW_DATA_59 0xc0600110 +#define ixROM_SW_DATA_60 0xc0600114 +#define ixROM_SW_DATA_61 0xc0600118 +#define ixROM_SW_DATA_62 0xc060011c +#define ixROM_SW_DATA_63 0xc0600120 +#define ixROM_SW_DATA_64 0xc0600124 + +#endif /* SMU_7_1_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h new file mode 100644 index 000000000000..61face1d0d8d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h @@ -0,0 +1,1191 @@ +/* + * SMU_7_1_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_0_ENUM_H +#define SMU_7_1_0_ENUM_H + +#define CG_SRBM_START_ADDR 0x600 +#define CG_SRBM_END_ADDR 0x8ff +#define RCU_CCF_DWORDS0 0x28 +#define RCU_CCF_BITS0 0x500 +#define RCU_CCF_DWORDS1 0x7f +#define RCU_CCF_BITS1 0x1000 +#define RCU_SAM_BYTES 0x40 +#define RCU_SAM_RTL_BYTES 0x40 +#define KEYS_CHAIN_ADR 0x0 +#define SAMU_KEY_SADR 0xa0 +#define SAMU_KEY_EADR 0xdf +#define RCU_SMU_BYTES 0x11 +#define RCU_SMU_RTL_BYTES 0x11 +#define SMC_MSG_TEST 0x1 +#define SMC_MSG_PHY_LN_OFF 0x2 +#define SMC_MSG_PHY_LN_ON 0x3 +#define SMC_MSG_DDI_PHY_OFF 0x4 +#define SMC_MSG_DDI_PHY_ON 0x5 +#define SMC_MSG_CASCADE_PLL_OFF 0x6 +#define SMC_MSG_CASCADE_PLL_ON 0x7 +#define SMC_MSG_PWR_OFF_x16 0x8 +#define SMC_MSG_CONFIG_LCLK_DPM 0x9 +#define SMC_MSG_FLUSH_DATA_CACHE 0xa +#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb +#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc +#define SMC_MSG_CONFIG_BAPM 0xd +#define SMC_MSG_CONFIG_TDC_LIMIT 0xe +#define SMC_MSG_CONFIG_LPMx 0xf +#define SMC_MSG_CONFIG_HTC_LIMIT 0x10 +#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11 +#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12 +#define SMC_MSG_CONFIG_TDP_CNTL 0x13 +#define SMC_MSG_EN_PM_CNTL 0x14 +#define SMC_MSG_DIS_PM_CNTL 0x15 +#define SMC_MSG_CONFIG_NBDPM 0x16 +#define SMC_MSG_CONFIG_LOADLINE 0x17 +#define SMC_MSG_ADJUST_LOADLINE 0x18 +#define SMC_MSG_RESET 0x20 +#define SMC_MSG_VOLTAGE 0x25 +#define SMC_VERSION_MAJOR 0x7 +#define SMC_VERSION_MINOR 0x0 +#define SMC_HEADER_SIZE 0x40 +#define ROM_SIGNATURE 0xaa55 +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, + ADDR_CONFIG_16_PIPE = 0x4, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_dco0 = 0x2, + DBG_CLIENT_BLKID_wd = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_scf2 = 0x5, + DBG_CLIENT_BLKID_spim3 = 0x6, + DBG_CLIENT_BLKID_cb3 = 0x7, + DBG_CLIENT_BLKID_sx0 = 0x8, + DBG_CLIENT_BLKID_cb2 = 0x9, + DBG_CLIENT_BLKID_bci1 = 0xa, + DBG_CLIENT_BLKID_xdma = 0xb, + DBG_CLIENT_BLKID_bci0 = 0xc, + DBG_CLIENT_BLKID_spim0 = 0xd, + DBG_CLIENT_BLKID_mcd0 = 0xe, + DBG_CLIENT_BLKID_mcc0 = 0xf, + DBG_CLIENT_BLKID_cb0 = 0x10, + DBG_CLIENT_BLKID_cb1 = 0x11, + DBG_CLIENT_BLKID_cpc_0 = 0x12, + DBG_CLIENT_BLKID_cpc_1 = 0x13, + DBG_CLIENT_BLKID_cpf = 0x14, + DBG_CLIENT_BLKID_rlc = 0x15, + DBG_CLIENT_BLKID_grbm = 0x16, + DBG_CLIENT_BLKID_bif = 0x17, + DBG_CLIENT_BLKID_scf1 = 0x18, + DBG_CLIENT_BLKID_sam = 0x19, + DBG_CLIENT_BLKID_mcd4 = 0x1a, + DBG_CLIENT_BLKID_mcc4 = 0x1b, + DBG_CLIENT_BLKID_gmcon = 0x1c, + DBG_CLIENT_BLKID_mcb = 0x1d, + DBG_CLIENT_BLKID_vgt0 = 0x1e, + DBG_CLIENT_BLKID_pc0 = 0x1f, + DBG_CLIENT_BLKID_spim1 = 0x20, + DBG_CLIENT_BLKID_bci2 = 0x21, + DBG_CLIENT_BLKID_mcd6 = 0x22, + DBG_CLIENT_BLKID_mcc6 = 0x23, + DBG_CLIENT_BLKID_mcd3 = 0x24, + DBG_CLIENT_BLKID_mcc3 = 0x25, + DBG_CLIENT_BLKID_uvdm_0 = 0x26, + DBG_CLIENT_BLKID_uvdm_1 = 0x27, + DBG_CLIENT_BLKID_uvdm_2 = 0x28, + DBG_CLIENT_BLKID_uvdm_3 = 0x29, + DBG_CLIENT_BLKID_spim2 = 0x2a, + DBG_CLIENT_BLKID_ds = 0x2b, + DBG_CLIENT_BLKID_srbm = 0x2c, + DBG_CLIENT_BLKID_ih = 0x2d, + DBG_CLIENT_BLKID_sem = 0x2e, + DBG_CLIENT_BLKID_sdma_0 = 0x2f, + DBG_CLIENT_BLKID_sdma_1 = 0x30, + DBG_CLIENT_BLKID_hdp = 0x31, + DBG_CLIENT_BLKID_acp_0 = 0x32, + DBG_CLIENT_BLKID_acp_1 = 0x33, + DBG_CLIENT_BLKID_vceb_0 = 0x34, + DBG_CLIENT_BLKID_vceb_1 = 0x35, + DBG_CLIENT_BLKID_vceb_2 = 0x36, + DBG_CLIENT_BLKID_mcd2 = 0x37, + DBG_CLIENT_BLKID_mcc2 = 0x38, + DBG_CLIENT_BLKID_scf3 = 0x39, + DBG_CLIENT_BLKID_bci3 = 0x3a, + DBG_CLIENT_BLKID_mcd5 = 0x3b, + DBG_CLIENT_BLKID_mcc5 = 0x3c, + DBG_CLIENT_BLKID_vgt2 = 0x3d, + DBG_CLIENT_BLKID_pc2 = 0x3e, + DBG_CLIENT_BLKID_smu_0 = 0x3f, + DBG_CLIENT_BLKID_smu_1 = 0x40, + DBG_CLIENT_BLKID_smu_2 = 0x41, + DBG_CLIENT_BLKID_vcea_0 = 0x42, + DBG_CLIENT_BLKID_vcea_1 = 0x43, + DBG_CLIENT_BLKID_vcea_2 = 0x44, + DBG_CLIENT_BLKID_vcea_3 = 0x45, + DBG_CLIENT_BLKID_vcea_4 = 0x46, + DBG_CLIENT_BLKID_vcea_5 = 0x47, + DBG_CLIENT_BLKID_vcea_6 = 0x48, + DBG_CLIENT_BLKID_scf0 = 0x49, + DBG_CLIENT_BLKID_vgt1 = 0x4a, + DBG_CLIENT_BLKID_pc1 = 0x4b, + DBG_CLIENT_BLKID_gdc_0 = 0x4c, + DBG_CLIENT_BLKID_gdc_1 = 0x4d, + DBG_CLIENT_BLKID_gdc_2 = 0x4e, + DBG_CLIENT_BLKID_gdc_3 = 0x4f, + DBG_CLIENT_BLKID_gdc_4 = 0x50, + DBG_CLIENT_BLKID_gdc_5 = 0x51, + DBG_CLIENT_BLKID_gdc_6 = 0x52, + DBG_CLIENT_BLKID_gdc_7 = 0x53, + DBG_CLIENT_BLKID_gdc_8 = 0x54, + DBG_CLIENT_BLKID_gdc_9 = 0x55, + DBG_CLIENT_BLKID_gdc_10 = 0x56, + DBG_CLIENT_BLKID_gdc_11 = 0x57, + DBG_CLIENT_BLKID_gdc_12 = 0x58, + DBG_CLIENT_BLKID_gdc_13 = 0x59, + DBG_CLIENT_BLKID_gdc_14 = 0x5a, + DBG_CLIENT_BLKID_gdc_15 = 0x5b, + DBG_CLIENT_BLKID_gdc_16 = 0x5c, + DBG_CLIENT_BLKID_gdc_17 = 0x5d, + DBG_CLIENT_BLKID_gdc_18 = 0x5e, + DBG_CLIENT_BLKID_gdc_19 = 0x5f, + DBG_CLIENT_BLKID_gdc_20 = 0x60, + DBG_CLIENT_BLKID_gdc_21 = 0x61, + DBG_CLIENT_BLKID_gdc_22 = 0x62, + DBG_CLIENT_BLKID_vgt3 = 0x63, + DBG_CLIENT_BLKID_pc3 = 0x64, + DBG_CLIENT_BLKID_uvdu_0 = 0x65, + DBG_CLIENT_BLKID_uvdu_1 = 0x66, + DBG_CLIENT_BLKID_uvdu_2 = 0x67, + DBG_CLIENT_BLKID_uvdu_3 = 0x68, + DBG_CLIENT_BLKID_uvdu_4 = 0x69, + DBG_CLIENT_BLKID_uvdu_5 = 0x6a, + DBG_CLIENT_BLKID_uvdu_6 = 0x6b, + DBG_CLIENT_BLKID_mcd7 = 0x6c, + DBG_CLIENT_BLKID_mcc7 = 0x6d, + DBG_CLIENT_BLKID_cpg_0 = 0x6e, + DBG_CLIENT_BLKID_cpg_1 = 0x6f, + DBG_CLIENT_BLKID_gck = 0x70, + DBG_CLIENT_BLKID_mcd1 = 0x71, + DBG_CLIENT_BLKID_mcc1 = 0x72, + DBG_CLIENT_BLKID_cb101 = 0x73, + DBG_CLIENT_BLKID_cb103 = 0x74, + DBG_CLIENT_BLKID_sx10 = 0x75, + DBG_CLIENT_BLKID_cb102 = 0x76, + DBG_CLIENT_BLKID_cb002 = 0x77, + DBG_CLIENT_BLKID_cb100 = 0x78, + DBG_CLIENT_BLKID_cb000 = 0x79, + DBG_CLIENT_BLKID_pa00 = 0x7a, + DBG_CLIENT_BLKID_pa10 = 0x7b, + DBG_CLIENT_BLKID_ia0 = 0x7c, + DBG_CLIENT_BLKID_ia1 = 0x7d, + DBG_CLIENT_BLKID_tmonw00 = 0x7e, + DBG_CLIENT_BLKID_cb001 = 0x7f, + DBG_CLIENT_BLKID_cb003 = 0x80, + DBG_CLIENT_BLKID_sx00 = 0x81, + DBG_CLIENT_BLKID_sx20 = 0x82, + DBG_CLIENT_BLKID_cb203 = 0x83, + DBG_CLIENT_BLKID_cb201 = 0x84, + DBG_CLIENT_BLKID_cb302 = 0x85, + DBG_CLIENT_BLKID_cb202 = 0x86, + DBG_CLIENT_BLKID_cb300 = 0x87, + DBG_CLIENT_BLKID_cb200 = 0x88, + DBG_CLIENT_BLKID_pa01 = 0x89, + DBG_CLIENT_BLKID_pa11 = 0x8a, + DBG_CLIENT_BLKID_sx30 = 0x8b, + DBG_CLIENT_BLKID_cb303 = 0x8c, + DBG_CLIENT_BLKID_cb301 = 0x8d, + DBG_CLIENT_BLKID_dco = 0x8e, + DBG_CLIENT_BLKID_scb0 = 0x8f, + DBG_CLIENT_BLKID_scb1 = 0x90, + DBG_CLIENT_BLKID_scb2 = 0x91, + DBG_CLIENT_BLKID_scb3 = 0x92, + DBG_CLIENT_BLKID_tmonw01 = 0x93, + DBG_CLIENT_BLKID_RESERVED_LAST = 0x94, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_SNORM_OGL = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_SNORM_OGL = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_UBNORM = 0xa, + IMG_NUM_FORMAT_UBNORM_OGL = 0xb, + IMG_NUM_FORMAT_UBINT = 0xc, + IMG_NUM_FORMAT_UBSCALED = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, + TCC_CACHE_POLICY_BYPASS = 0x2, +} TCC_CACHE_POLICIES; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; + +#endif /* SMU_7_1_0_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h new file mode 100644 index 000000000000..cd7893065a4b --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h @@ -0,0 +1,5648 @@ +/* + * SMU_7_1_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_0_SH_MASK_H +#define SMU_7_1_0_SH_MASK_H + +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f +#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 +#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f +#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 +#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f +#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 +#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f +#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d +#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 +#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 +#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 +#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 +#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 +#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 +#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1 +#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa +#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff +#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 +#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 +#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 +#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 +#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa +#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 +#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_0__SMC_RESP_MASK 0xffff +#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_1__SMC_RESP_MASK 0xffff +#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_2__SMC_RESP_MASK 0xffff +#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_3__SMC_RESP_MASK 0xffff +#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_4__SMC_RESP_MASK 0xffff +#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_5__SMC_RESP_MASK 0xffff +#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_6__SMC_RESP_MASK 0xffff +#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_7__SMC_RESP_MASK 0xffff +#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_8__SMC_RESP_MASK 0xffff +#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_9__SMC_RESP_MASK 0xffff +#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_10__SMC_RESP_MASK 0xffff +#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_11__SMC_RESP_MASK 0xffff +#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 +#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 +#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 +#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 +#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 +#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffff +#define SMC_PC_C__smc_pc_c__SHIFT 0x0 +#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff +#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4 +#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff +#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 +#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff +#define GPIOPAD_A__GPIO_A__SHIFT 0x0 +#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff +#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0 +#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff +#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f +#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff +#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000 +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f +#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6 +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0 +#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff +#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 +#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff +#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 +#define CG_FPS_CNT__FPS_CNT_MASK 0xff +#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 +#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 +#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3 +#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 +#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 +#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 +#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa +#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 +#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 +#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 +#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 +#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 +#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 +#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 +#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 +#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 +#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 +#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 +#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 +#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 +#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 +#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 +#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 +#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 +#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 +#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 +#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 +#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 +#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 +#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 +#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa +#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000 +#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000 +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000 +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11 +#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000 +#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14 +#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000 +#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17 +#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000 +#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18 +#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfe000000 +#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 +#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc +#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 +#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 +#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 +#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 +#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c +#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 +#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d +#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff +#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 +#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 +#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 +#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 +#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 +#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 +#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 +#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e +#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 +#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a +#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 +#define SMU_STATUS__SMU_DONE_MASK 0x1 +#define SMU_STATUS__SMU_DONE__SHIFT 0x0 +#define SMU_STATUS__SMU_PASS_MASK 0x2 +#define SMU_STATUS__SMU_PASS__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 +#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 +#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 +#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 +#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 +#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 +#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 +#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 +#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 +#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff +#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 +#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 +#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f +#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff +#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 +#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff +#define DPM_TABLE_28__SystemFlags__SHIFT 0x0 +#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff +#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0 +#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff +#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0 +#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff +#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0 +#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff +#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0 +#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff +#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0 +#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff +#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0 +#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff +#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff +#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff +#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff +#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff +#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000 +#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10 +#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff +#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0 +#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00 +#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000 +#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10 +#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff +#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0 +#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00 +#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000 +#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10 +#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff +#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0 +#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00 +#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000 +#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10 +#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff +#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0 +#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00 +#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff +#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff +#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff +#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff +#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff +#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff +#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff +#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff +#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_68__UvdLevelCount_MASK 0xff +#define DPM_TABLE_68__UvdLevelCount__SHIFT 0x0 +#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00 +#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8 +#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000 +#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10 +#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000 +#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18 +#define DPM_TABLE_69__MasterDeepSleepControl_MASK 0xff +#define DPM_TABLE_69__MasterDeepSleepControl__SHIFT 0x0 +#define DPM_TABLE_69__SamuLevelCount_MASK 0xff00 +#define DPM_TABLE_69__SamuLevelCount__SHIFT 0x8 +#define DPM_TABLE_69__AcpLevelCount_MASK 0xff0000 +#define DPM_TABLE_69__AcpLevelCount__SHIFT 0x10 +#define DPM_TABLE_69__VceLevelCount_MASK 0xff000000 +#define DPM_TABLE_69__VceLevelCount__SHIFT 0x18 +#define DPM_TABLE_70__DefaultTdp_MASK 0xffff +#define DPM_TABLE_70__DefaultTdp__SHIFT 0x0 +#define DPM_TABLE_70__TargetTdp_MASK 0xffff0000 +#define DPM_TABLE_70__TargetTdp__SHIFT 0x10 +#define DPM_TABLE_71__Reserved_1_MASK 0xffffffff +#define DPM_TABLE_71__Reserved_1__SHIFT 0x0 +#define DPM_TABLE_72__Reserved_2_MASK 0xffffffff +#define DPM_TABLE_72__Reserved_2__SHIFT 0x0 +#define DPM_TABLE_73__Reserved_3_MASK 0xffffffff +#define DPM_TABLE_73__Reserved_3__SHIFT 0x0 +#define DPM_TABLE_74__Reserved_4_MASK 0xffffffff +#define DPM_TABLE_74__Reserved_4__SHIFT 0x0 +#define DPM_TABLE_75__GraphicsLevel_0_Flags_MASK 0xffffffff +#define DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT 0x0 +#define DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK 0xffff +#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_79__GraphicsLevel_0_padding1_MASK 0xff0000 +#define DPM_TABLE_79__GraphicsLevel_0_padding1__SHIFT 0x10 +#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK 0xff000000 +#define DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT 0x18 +#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK 0xff +#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_89__GraphicsLevel_1_Flags_MASK 0xffffffff +#define DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT 0x0 +#define DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK 0xffff +#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_93__GraphicsLevel_1_padding1_MASK 0xff0000 +#define DPM_TABLE_93__GraphicsLevel_1_padding1__SHIFT 0x10 +#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK 0xff000000 +#define DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT 0x18 +#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK 0xff +#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_103__GraphicsLevel_2_Flags_MASK 0xffffffff +#define DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT 0x0 +#define DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK 0xffff +#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_107__GraphicsLevel_2_padding1_MASK 0xff0000 +#define DPM_TABLE_107__GraphicsLevel_2_padding1__SHIFT 0x10 +#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK 0xff000000 +#define DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT 0x18 +#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK 0xff +#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_117__GraphicsLevel_3_Flags_MASK 0xffffffff +#define DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT 0x0 +#define DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK 0xffff +#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_3_padding1_MASK 0xff0000 +#define DPM_TABLE_121__GraphicsLevel_3_padding1__SHIFT 0x10 +#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK 0xff000000 +#define DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT 0x18 +#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK 0xff +#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_131__GraphicsLevel_4_Flags_MASK 0xffffffff +#define DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT 0x0 +#define DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK 0xffffffff +#define DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT 0x0 +#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK 0xffff +#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_4_padding1_MASK 0xff0000 +#define DPM_TABLE_135__GraphicsLevel_4_padding1__SHIFT 0x10 +#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK 0xff000000 +#define DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT 0x18 +#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK 0xff +#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_145__GraphicsLevel_5_Flags_MASK 0xffffffff +#define DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT 0x0 +#define DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK 0xffffffff +#define DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT 0x0 +#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK 0xffff +#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_5_padding1_MASK 0xff0000 +#define DPM_TABLE_149__GraphicsLevel_5_padding1__SHIFT 0x10 +#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK 0xff000000 +#define DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT 0x18 +#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK 0xff +#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_159__GraphicsLevel_6_Flags_MASK 0xffffffff +#define DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT 0x0 +#define DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK 0xffffffff +#define DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT 0x0 +#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_padding1_MASK 0xff0000 +#define DPM_TABLE_163__GraphicsLevel_6_padding1__SHIFT 0x10 +#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18 +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18 +#define DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_173__GraphicsLevel_7_Flags_MASK 0xffffffff +#define DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT 0x0 +#define DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK 0xffffffff +#define DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT 0x0 +#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK 0xffff +#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_177__GraphicsLevel_7_padding1_MASK 0xff0000 +#define DPM_TABLE_177__GraphicsLevel_7_padding1__SHIFT 0x10 +#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK 0xff000000 +#define DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT 0x18 +#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK 0xff +#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK 0xff0000 +#define DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT 0x10 +#define DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK 0xff000000 +#define DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT 0x18 +#define DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK 0xff000000 +#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x18 +#define DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK 0xffffffff +#define DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT 0x0 +#define DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK 0xff +#define DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK 0xff00 +#define DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT 0x8 +#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK 0xff +#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_194__MemoryACPILevel_padding_MASK 0xff +#define DPM_TABLE_194__MemoryACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK 0xff0000 +#define DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT 0x10 +#define DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK 0xff000000 +#define DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT 0x18 +#define DPM_TABLE_195__MemoryACPILevel_padding1_MASK 0xff +#define DPM_TABLE_195__MemoryACPILevel_padding1__SHIFT 0x0 +#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK 0xffffffff +#define DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT 0x0 +#define DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK 0xffffffff +#define DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT 0x0 +#define DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK 0xff +#define DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK 0xff00 +#define DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT 0x8 +#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK 0xff +#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_212__MemoryLevel_0_padding_MASK 0xff +#define DPM_TABLE_212__MemoryLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_213__MemoryLevel_0_padding1_MASK 0xff +#define DPM_TABLE_213__MemoryLevel_0_padding1__SHIFT 0x0 +#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK 0xffffffff +#define DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT 0x0 +#define DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK 0xffffffff +#define DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT 0x0 +#define DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK 0xff +#define DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK 0xff00 +#define DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT 0x8 +#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK 0xff +#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_230__MemoryLevel_1_padding_MASK 0xff +#define DPM_TABLE_230__MemoryLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_231__MemoryLevel_1_padding1_MASK 0xff +#define DPM_TABLE_231__MemoryLevel_1_padding1__SHIFT 0x0 +#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK 0xffffffff +#define DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT 0x0 +#define DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK 0xffffffff +#define DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT 0x0 +#define DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK 0xff +#define DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK 0xff00 +#define DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT 0x8 +#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK 0xff +#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_248__MemoryLevel_2_padding_MASK 0xff +#define DPM_TABLE_248__MemoryLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_249__MemoryLevel_2_padding1_MASK 0xff +#define DPM_TABLE_249__MemoryLevel_2_padding1__SHIFT 0x0 +#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK 0xffffffff +#define DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT 0x0 +#define DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK 0xffffffff +#define DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT 0x0 +#define DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK 0xff +#define DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK 0xff00 +#define DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT 0x8 +#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK 0xff +#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_266__MemoryLevel_3_padding_MASK 0xff +#define DPM_TABLE_266__MemoryLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_267__MemoryLevel_3_padding1_MASK 0xff +#define DPM_TABLE_267__MemoryLevel_3_padding1__SHIFT 0x0 +#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK 0xffffffff +#define DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT 0x0 +#define DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK 0xffffffff +#define DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT 0x0 +#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK 0xffffffff +#define DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT 0x0 +#define DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK 0xff +#define DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK 0xff00 +#define DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT 0x8 +#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK 0xff +#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_284__MemoryLevel_4_padding_MASK 0xff +#define DPM_TABLE_284__MemoryLevel_4_padding__SHIFT 0x0 +#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_285__MemoryLevel_4_padding1_MASK 0xff +#define DPM_TABLE_285__MemoryLevel_4_padding1__SHIFT 0x0 +#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK 0xffffffff +#define DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT 0x0 +#define DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK 0xffffffff +#define DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT 0x0 +#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK 0xffffffff +#define DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT 0x0 +#define DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK 0xff +#define DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK 0xff00 +#define DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT 0x8 +#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK 0xff +#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_302__MemoryLevel_5_padding_MASK 0xff +#define DPM_TABLE_302__MemoryLevel_5_padding__SHIFT 0x0 +#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_303__MemoryLevel_5_padding1_MASK 0xff +#define DPM_TABLE_303__MemoryLevel_5_padding1__SHIFT 0x0 +#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK 0xffffffff +#define DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT 0x0 +#define DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_313__LinkLevel_0_Padding_MASK 0xff +#define DPM_TABLE_313__LinkLevel_0_Padding__SHIFT 0x0 +#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_316__LinkLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_317__LinkLevel_1_Padding_MASK 0xff +#define DPM_TABLE_317__LinkLevel_1_Padding__SHIFT 0x0 +#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_320__LinkLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_321__LinkLevel_2_Padding_MASK 0xff +#define DPM_TABLE_321__LinkLevel_2_Padding__SHIFT 0x0 +#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_324__LinkLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_325__LinkLevel_3_Padding_MASK 0xff +#define DPM_TABLE_325__LinkLevel_3_Padding__SHIFT 0x0 +#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_328__LinkLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_329__LinkLevel_4_Padding_MASK 0xff +#define DPM_TABLE_329__LinkLevel_4_Padding__SHIFT 0x0 +#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_332__LinkLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_333__LinkLevel_5_Padding_MASK 0xff +#define DPM_TABLE_333__LinkLevel_5_Padding__SHIFT 0x0 +#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_336__LinkLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_337__LinkLevel_6_Padding_MASK 0xff +#define DPM_TABLE_337__LinkLevel_6_Padding__SHIFT 0x0 +#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_340__LinkLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_341__LinkLevel_7_Padding_MASK 0xff +#define DPM_TABLE_341__LinkLevel_7_Padding__SHIFT 0x0 +#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_344__LinkLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_345__ACPILevel_Flags_MASK 0xffffffff +#define DPM_TABLE_345__ACPILevel_Flags__SHIFT 0x0 +#define DPM_TABLE_346__ACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_346__ACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_348__ACPILevel_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_349__ACPILevel_padding_MASK 0xff +#define DPM_TABLE_349__ACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_349__ACPILevel_SclkDid_MASK 0xff000000 +#define DPM_TABLE_349__ACPILevel_SclkDid__SHIFT 0x18 +#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff +#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0 +#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK 0xff +#define DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_360__UvdLevel_0_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT 0x10 +#define DPM_TABLE_361__UvdLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_361__UvdLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_361__UvdLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK 0xff +#define DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_364__UvdLevel_1_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT 0x10 +#define DPM_TABLE_365__UvdLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_365__UvdLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_365__UvdLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK 0xff +#define DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_368__UvdLevel_2_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT 0x10 +#define DPM_TABLE_369__UvdLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_369__UvdLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_369__UvdLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK 0xff +#define DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_372__UvdLevel_3_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT 0x10 +#define DPM_TABLE_373__UvdLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_373__UvdLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_373__UvdLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK 0xff +#define DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_376__UvdLevel_4_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT 0x10 +#define DPM_TABLE_377__UvdLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_377__UvdLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_377__UvdLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK 0xff +#define DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_380__UvdLevel_5_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT 0x10 +#define DPM_TABLE_381__UvdLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_381__UvdLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_381__UvdLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK 0xff +#define DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_384__UvdLevel_6_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT 0x10 +#define DPM_TABLE_385__UvdLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_385__UvdLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_385__UvdLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK 0xff +#define DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT 0x0 +#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00 +#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT 0x8 +#define DPM_TABLE_388__UvdLevel_7_MinVddc_MASK 0xffff0000 +#define DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT 0x10 +#define DPM_TABLE_389__UvdLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_389__UvdLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_389__UvdLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK 0xff000000 +#define DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT 0x18 +#define DPM_TABLE_390__VceLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_390__VceLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_391__VceLevel_0_Divider_MASK 0xff +#define DPM_TABLE_391__VceLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_391__VceLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_391__VceLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_392__VceLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_392__VceLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_393__VceLevel_1_Divider_MASK 0xff +#define DPM_TABLE_393__VceLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_393__VceLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_393__VceLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_394__VceLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_394__VceLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_395__VceLevel_2_Divider_MASK 0xff +#define DPM_TABLE_395__VceLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_395__VceLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_395__VceLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_396__VceLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_396__VceLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_397__VceLevel_3_Divider_MASK 0xff +#define DPM_TABLE_397__VceLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_397__VceLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_397__VceLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_398__VceLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_398__VceLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_399__VceLevel_4_Divider_MASK 0xff +#define DPM_TABLE_399__VceLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_399__VceLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_399__VceLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_400__VceLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_400__VceLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_401__VceLevel_5_Divider_MASK 0xff +#define DPM_TABLE_401__VceLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_401__VceLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_401__VceLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_402__VceLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_402__VceLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_403__VceLevel_6_Divider_MASK 0xff +#define DPM_TABLE_403__VceLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_403__VceLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_403__VceLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_404__VceLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_404__VceLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_405__VceLevel_7_Divider_MASK 0xff +#define DPM_TABLE_405__VceLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_405__VceLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_405__VceLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_406__AcpLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_407__AcpLevel_0_Divider_MASK 0xff +#define DPM_TABLE_407__AcpLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_407__AcpLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_408__AcpLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_409__AcpLevel_1_Divider_MASK 0xff +#define DPM_TABLE_409__AcpLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_409__AcpLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_410__AcpLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_411__AcpLevel_2_Divider_MASK 0xff +#define DPM_TABLE_411__AcpLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_411__AcpLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_412__AcpLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_413__AcpLevel_3_Divider_MASK 0xff +#define DPM_TABLE_413__AcpLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_413__AcpLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_414__AcpLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_415__AcpLevel_4_Divider_MASK 0xff +#define DPM_TABLE_415__AcpLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_415__AcpLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_416__AcpLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_417__AcpLevel_5_Divider_MASK 0xff +#define DPM_TABLE_417__AcpLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_417__AcpLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_418__AcpLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_419__AcpLevel_6_Divider_MASK 0xff +#define DPM_TABLE_419__AcpLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_419__AcpLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_420__AcpLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_421__AcpLevel_7_Divider_MASK 0xff +#define DPM_TABLE_421__AcpLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_421__AcpLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_422__SamuLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_423__SamuLevel_0_Divider_MASK 0xff +#define DPM_TABLE_423__SamuLevel_0_Divider__SHIFT 0x0 +#define DPM_TABLE_423__SamuLevel_0_MinPhases_MASK 0xff00 +#define DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT 0x8 +#define DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_424__SamuLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_425__SamuLevel_1_Divider_MASK 0xff +#define DPM_TABLE_425__SamuLevel_1_Divider__SHIFT 0x0 +#define DPM_TABLE_425__SamuLevel_1_MinPhases_MASK 0xff00 +#define DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT 0x8 +#define DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_426__SamuLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_427__SamuLevel_2_Divider_MASK 0xff +#define DPM_TABLE_427__SamuLevel_2_Divider__SHIFT 0x0 +#define DPM_TABLE_427__SamuLevel_2_MinPhases_MASK 0xff00 +#define DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT 0x8 +#define DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_428__SamuLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_429__SamuLevel_3_Divider_MASK 0xff +#define DPM_TABLE_429__SamuLevel_3_Divider__SHIFT 0x0 +#define DPM_TABLE_429__SamuLevel_3_MinPhases_MASK 0xff00 +#define DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT 0x8 +#define DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_430__SamuLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_431__SamuLevel_4_Divider_MASK 0xff +#define DPM_TABLE_431__SamuLevel_4_Divider__SHIFT 0x0 +#define DPM_TABLE_431__SamuLevel_4_MinPhases_MASK 0xff00 +#define DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT 0x8 +#define DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_432__SamuLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_433__SamuLevel_5_Divider_MASK 0xff +#define DPM_TABLE_433__SamuLevel_5_Divider__SHIFT 0x0 +#define DPM_TABLE_433__SamuLevel_5_MinPhases_MASK 0xff00 +#define DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT 0x8 +#define DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_434__SamuLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_435__SamuLevel_6_Divider_MASK 0xff +#define DPM_TABLE_435__SamuLevel_6_Divider__SHIFT 0x0 +#define DPM_TABLE_435__SamuLevel_6_MinPhases_MASK 0xff00 +#define DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT 0x8 +#define DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_436__SamuLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_437__SamuLevel_7_Divider_MASK 0xff +#define DPM_TABLE_437__SamuLevel_7_Divider__SHIFT 0x0 +#define DPM_TABLE_437__SamuLevel_7_MinPhases_MASK 0xff00 +#define DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT 0x8 +#define DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK 0xffff0000 +#define DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT 0x10 +#define DPM_TABLE_438__Ulv_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_440__Ulv_VddcPhase_MASK 0xff +#define DPM_TABLE_440__Ulv_VddcPhase__SHIFT 0x0 +#define DPM_TABLE_440__Ulv_VddcOffsetVid_MASK 0xff00 +#define DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT 0x8 +#define DPM_TABLE_440__Ulv_VddcOffset_MASK 0xffff0000 +#define DPM_TABLE_440__Ulv_VddcOffset__SHIFT 0x10 +#define DPM_TABLE_441__Ulv_Reserved_MASK 0xffffffff +#define DPM_TABLE_441__Ulv_Reserved__SHIFT 0x0 +#define DPM_TABLE_442__SclkStepSize_MASK 0xffffffff +#define DPM_TABLE_442__SclkStepSize__SHIFT 0x0 +#define DPM_TABLE_443__Smio_0_MASK 0xffffffff +#define DPM_TABLE_443__Smio_0__SHIFT 0x0 +#define DPM_TABLE_444__Smio_1_MASK 0xffffffff +#define DPM_TABLE_444__Smio_1__SHIFT 0x0 +#define DPM_TABLE_445__Smio_2_MASK 0xffffffff +#define DPM_TABLE_445__Smio_2__SHIFT 0x0 +#define DPM_TABLE_446__Smio_3_MASK 0xffffffff +#define DPM_TABLE_446__Smio_3__SHIFT 0x0 +#define DPM_TABLE_447__Smio_4_MASK 0xffffffff +#define DPM_TABLE_447__Smio_4__SHIFT 0x0 +#define DPM_TABLE_448__Smio_5_MASK 0xffffffff +#define DPM_TABLE_448__Smio_5__SHIFT 0x0 +#define DPM_TABLE_449__Smio_6_MASK 0xffffffff +#define DPM_TABLE_449__Smio_6__SHIFT 0x0 +#define DPM_TABLE_450__Smio_7_MASK 0xffffffff +#define DPM_TABLE_450__Smio_7__SHIFT 0x0 +#define DPM_TABLE_451__Smio_8_MASK 0xffffffff +#define DPM_TABLE_451__Smio_8__SHIFT 0x0 +#define DPM_TABLE_452__Smio_9_MASK 0xffffffff +#define DPM_TABLE_452__Smio_9__SHIFT 0x0 +#define DPM_TABLE_453__Smio_10_MASK 0xffffffff +#define DPM_TABLE_453__Smio_10__SHIFT 0x0 +#define DPM_TABLE_454__Smio_11_MASK 0xffffffff +#define DPM_TABLE_454__Smio_11__SHIFT 0x0 +#define DPM_TABLE_455__Smio_12_MASK 0xffffffff +#define DPM_TABLE_455__Smio_12__SHIFT 0x0 +#define DPM_TABLE_456__Smio_13_MASK 0xffffffff +#define DPM_TABLE_456__Smio_13__SHIFT 0x0 +#define DPM_TABLE_457__Smio_14_MASK 0xffffffff +#define DPM_TABLE_457__Smio_14__SHIFT 0x0 +#define DPM_TABLE_458__Smio_15_MASK 0xffffffff +#define DPM_TABLE_458__Smio_15__SHIFT 0x0 +#define DPM_TABLE_459__Smio_16_MASK 0xffffffff +#define DPM_TABLE_459__Smio_16__SHIFT 0x0 +#define DPM_TABLE_460__Smio_17_MASK 0xffffffff +#define DPM_TABLE_460__Smio_17__SHIFT 0x0 +#define DPM_TABLE_461__Smio_18_MASK 0xffffffff +#define DPM_TABLE_461__Smio_18__SHIFT 0x0 +#define DPM_TABLE_462__Smio_19_MASK 0xffffffff +#define DPM_TABLE_462__Smio_19__SHIFT 0x0 +#define DPM_TABLE_463__Smio_20_MASK 0xffffffff +#define DPM_TABLE_463__Smio_20__SHIFT 0x0 +#define DPM_TABLE_464__Smio_21_MASK 0xffffffff +#define DPM_TABLE_464__Smio_21__SHIFT 0x0 +#define DPM_TABLE_465__Smio_22_MASK 0xffffffff +#define DPM_TABLE_465__Smio_22__SHIFT 0x0 +#define DPM_TABLE_466__Smio_23_MASK 0xffffffff +#define DPM_TABLE_466__Smio_23__SHIFT 0x0 +#define DPM_TABLE_467__Smio_24_MASK 0xffffffff +#define DPM_TABLE_467__Smio_24__SHIFT 0x0 +#define DPM_TABLE_468__Smio_25_MASK 0xffffffff +#define DPM_TABLE_468__Smio_25__SHIFT 0x0 +#define DPM_TABLE_469__Smio_26_MASK 0xffffffff +#define DPM_TABLE_469__Smio_26__SHIFT 0x0 +#define DPM_TABLE_470__Smio_27_MASK 0xffffffff +#define DPM_TABLE_470__Smio_27__SHIFT 0x0 +#define DPM_TABLE_471__Smio_28_MASK 0xffffffff +#define DPM_TABLE_471__Smio_28__SHIFT 0x0 +#define DPM_TABLE_472__Smio_29_MASK 0xffffffff +#define DPM_TABLE_472__Smio_29__SHIFT 0x0 +#define DPM_TABLE_473__Smio_30_MASK 0xffffffff +#define DPM_TABLE_473__Smio_30__SHIFT 0x0 +#define DPM_TABLE_474__Smio_31_MASK 0xffffffff +#define DPM_TABLE_474__Smio_31__SHIFT 0x0 +#define DPM_TABLE_475__SamuBootLevel_MASK 0xff +#define DPM_TABLE_475__SamuBootLevel__SHIFT 0x0 +#define DPM_TABLE_475__AcpBootLevel_MASK 0xff00 +#define DPM_TABLE_475__AcpBootLevel__SHIFT 0x8 +#define DPM_TABLE_475__VceBootLevel_MASK 0xff0000 +#define DPM_TABLE_475__VceBootLevel__SHIFT 0x10 +#define DPM_TABLE_475__UvdBootLevel_MASK 0xff000000 +#define DPM_TABLE_475__UvdBootLevel__SHIFT 0x18 +#define DPM_TABLE_476__SAMUInterval_MASK 0xff +#define DPM_TABLE_476__SAMUInterval__SHIFT 0x0 +#define DPM_TABLE_476__ACPInterval_MASK 0xff00 +#define DPM_TABLE_476__ACPInterval__SHIFT 0x8 +#define DPM_TABLE_476__VCEInterval_MASK 0xff0000 +#define DPM_TABLE_476__VCEInterval__SHIFT 0x10 +#define DPM_TABLE_476__UVDInterval_MASK 0xff000000 +#define DPM_TABLE_476__UVDInterval__SHIFT 0x18 +#define DPM_TABLE_477__GraphicsInterval_MASK 0xff +#define DPM_TABLE_477__GraphicsInterval__SHIFT 0x0 +#define DPM_TABLE_477__GraphicsThermThrottleEnable_MASK 0xff00 +#define DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT 0x8 +#define DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK 0xff0000 +#define DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT 0x10 +#define DPM_TABLE_477__GraphicsBootLevel_MASK 0xff000000 +#define DPM_TABLE_477__GraphicsBootLevel__SHIFT 0x18 +#define DPM_TABLE_478__TemperatureLimitHigh_MASK 0xffff +#define DPM_TABLE_478__TemperatureLimitHigh__SHIFT 0x0 +#define DPM_TABLE_478__ThermalInterval_MASK 0xff0000 +#define DPM_TABLE_478__ThermalInterval__SHIFT 0x10 +#define DPM_TABLE_478__VoltageInterval_MASK 0xff000000 +#define DPM_TABLE_478__VoltageInterval__SHIFT 0x18 +#define DPM_TABLE_479__MemoryVoltageChangeEnable_MASK 0xff +#define DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT 0x0 +#define DPM_TABLE_479__MemoryBootLevel_MASK 0xff00 +#define DPM_TABLE_479__MemoryBootLevel__SHIFT 0x8 +#define DPM_TABLE_479__TemperatureLimitLow_MASK 0xffff0000 +#define DPM_TABLE_479__TemperatureLimitLow__SHIFT 0x10 +#define DPM_TABLE_480__VddcVddciDelta_MASK 0xffff +#define DPM_TABLE_480__VddcVddciDelta__SHIFT 0x0 +#define DPM_TABLE_480__MemoryThermThrottleEnable_MASK 0xff0000 +#define DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT 0x10 +#define DPM_TABLE_480__MemoryInterval_MASK 0xff000000 +#define DPM_TABLE_480__MemoryInterval__SHIFT 0x18 +#define DPM_TABLE_481__PhaseResponseTime_MASK 0xffff +#define DPM_TABLE_481__PhaseResponseTime__SHIFT 0x0 +#define DPM_TABLE_481__VoltageResponseTime_MASK 0xffff0000 +#define DPM_TABLE_481__VoltageResponseTime__SHIFT 0x10 +#define DPM_TABLE_482__DTEMode_MASK 0xff +#define DPM_TABLE_482__DTEMode__SHIFT 0x0 +#define DPM_TABLE_482__DTEInterval_MASK 0xff00 +#define DPM_TABLE_482__DTEInterval__SHIFT 0x8 +#define DPM_TABLE_482__PCIeGenInterval_MASK 0xff0000 +#define DPM_TABLE_482__PCIeGenInterval__SHIFT 0x10 +#define DPM_TABLE_482__PCIeBootLinkLevel_MASK 0xff000000 +#define DPM_TABLE_482__PCIeBootLinkLevel__SHIFT 0x18 +#define DPM_TABLE_483__ThermGpio_MASK 0xff +#define DPM_TABLE_483__ThermGpio__SHIFT 0x0 +#define DPM_TABLE_483__AcDcGpio_MASK 0xff00 +#define DPM_TABLE_483__AcDcGpio__SHIFT 0x8 +#define DPM_TABLE_483__VRHotGpio_MASK 0xff0000 +#define DPM_TABLE_483__VRHotGpio__SHIFT 0x10 +#define DPM_TABLE_483__SVI2Enable_MASK 0xff000000 +#define DPM_TABLE_483__SVI2Enable__SHIFT 0x18 +#define DPM_TABLE_484__PPM_TemperatureLimit_MASK 0xffff +#define DPM_TABLE_484__PPM_TemperatureLimit__SHIFT 0x0 +#define DPM_TABLE_484__PPM_PkgPwrLimit_MASK 0xffff0000 +#define DPM_TABLE_484__PPM_PkgPwrLimit__SHIFT 0x10 +#define DPM_TABLE_485__TargetTdp_MASK 0xffff +#define DPM_TABLE_485__TargetTdp__SHIFT 0x0 +#define DPM_TABLE_485__DefaultTdp_MASK 0xffff0000 +#define DPM_TABLE_485__DefaultTdp__SHIFT 0x10 +#define DPM_TABLE_486__FpsLowThreshold_MASK 0xffff +#define DPM_TABLE_486__FpsLowThreshold__SHIFT 0x0 +#define DPM_TABLE_486__FpsHighThreshold_MASK 0xffff0000 +#define DPM_TABLE_486__FpsHighThreshold__SHIFT 0x10 +#define DPM_TABLE_487__BAPMTI_R_0_1_0_MASK 0xffff +#define DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT 0x0 +#define DPM_TABLE_487__BAPMTI_R_0_0_0_MASK 0xffff0000 +#define DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT 0x10 +#define DPM_TABLE_488__BAPMTI_R_1_0_0_MASK 0xffff +#define DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT 0x0 +#define DPM_TABLE_488__BAPMTI_R_0_2_0_MASK 0xffff0000 +#define DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT 0x10 +#define DPM_TABLE_489__BAPMTI_R_1_2_0_MASK 0xffff +#define DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT 0x0 +#define DPM_TABLE_489__BAPMTI_R_1_1_0_MASK 0xffff0000 +#define DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT 0x10 +#define DPM_TABLE_490__BAPMTI_R_2_1_0_MASK 0xffff +#define DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT 0x0 +#define DPM_TABLE_490__BAPMTI_R_2_0_0_MASK 0xffff0000 +#define DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT 0x10 +#define DPM_TABLE_491__BAPMTI_R_3_0_0_MASK 0xffff +#define DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT 0x0 +#define DPM_TABLE_491__BAPMTI_R_2_2_0_MASK 0xffff0000 +#define DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT 0x10 +#define DPM_TABLE_492__BAPMTI_R_3_2_0_MASK 0xffff +#define DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT 0x0 +#define DPM_TABLE_492__BAPMTI_R_3_1_0_MASK 0xffff0000 +#define DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT 0x10 +#define DPM_TABLE_493__BAPMTI_R_4_1_0_MASK 0xffff +#define DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT 0x0 +#define DPM_TABLE_493__BAPMTI_R_4_0_0_MASK 0xffff0000 +#define DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT 0x10 +#define DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK 0xffff +#define DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT 0x0 +#define DPM_TABLE_494__BAPMTI_R_4_2_0_MASK 0xffff0000 +#define DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT 0x10 +#define DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK 0xffff +#define DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT 0x0 +#define DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK 0xffff0000 +#define DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT 0x10 +#define DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK 0xffff +#define DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT 0x0 +#define DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK 0xffff0000 +#define DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT 0x10 +#define DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK 0xffff +#define DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT 0x0 +#define DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK 0xffff0000 +#define DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT 0x10 +#define DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK 0xffff +#define DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT 0x0 +#define DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK 0xffff0000 +#define DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT 0x10 +#define DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK 0xffff +#define DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT 0x0 +#define DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK 0xffff0000 +#define DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT 0x10 +#define DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK 0xffff +#define DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT 0x0 +#define DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK 0xffff0000 +#define DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT 0x10 +#define DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK 0xffff +#define DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT 0x0 +#define DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK 0xffff0000 +#define DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT 0x10 +#define DPM_TABLE_502__GpuTjHyst_MASK 0xff +#define DPM_TABLE_502__GpuTjHyst__SHIFT 0x0 +#define DPM_TABLE_502__GpuTjMax_MASK 0xff00 +#define DPM_TABLE_502__GpuTjMax__SHIFT 0x8 +#define DPM_TABLE_502__DTETjOffset_MASK 0xff0000 +#define DPM_TABLE_502__DTETjOffset__SHIFT 0x10 +#define DPM_TABLE_502__DTEAmbientTempBase_MASK 0xff000000 +#define DPM_TABLE_502__DTEAmbientTempBase__SHIFT 0x18 +#define DPM_TABLE_503__BootVddci_MASK 0xffff +#define DPM_TABLE_503__BootVddci__SHIFT 0x0 +#define DPM_TABLE_503__BootVddc_MASK 0xffff0000 +#define DPM_TABLE_503__BootVddc__SHIFT 0x10 +#define DPM_TABLE_504__padding_MASK 0xff +#define DPM_TABLE_504__padding__SHIFT 0x0 +#define DPM_TABLE_504__PccGpio_MASK 0xff00 +#define DPM_TABLE_504__PccGpio__SHIFT 0x8 +#define DPM_TABLE_504__BootMVdd_MASK 0xffff0000 +#define DPM_TABLE_504__BootMVdd__SHIFT 0x10 +#define DPM_TABLE_505__BAPM_TEMP_GRADIENT_MASK 0xffffffff +#define DPM_TABLE_505__BAPM_TEMP_GRADIENT__SHIFT 0x0 +#define DPM_TABLE_506__LowSclkInterruptThreshold_MASK 0xffffffff +#define DPM_TABLE_506__LowSclkInterruptThreshold__SHIFT 0x0 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe +#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 +#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 +#define TDC_STATUS__VDD_Boost_MASK 0xff +#define TDC_STATUS__VDD_Boost__SHIFT 0x0 +#define TDC_STATUS__VDD_Throttle_MASK 0xff00 +#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 +#define TDC_STATUS__VDDC_Boost_MASK 0xff0000 +#define TDC_STATUS__VDDC_Boost__SHIFT 0x10 +#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000 +#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18 +#define TDC_MV_AVERAGE__IDD_MASK 0xffff +#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 +#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000 +#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10 +#define TDC_VRM_LIMIT__IDD_MASK 0xffff +#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 +#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000 +#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10 +#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 +#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 +#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 +#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 +#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 +#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 +#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 +#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 +#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 +#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 +#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20 +#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5 +#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40 +#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6 +#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 +#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 +#define FEATURE_STATUS__BAPM_ON_MASK 0x100 +#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 +#define FEATURE_STATUS__LPMX_ON_MASK 0x200 +#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 +#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 +#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa +#define FEATURE_STATUS__LHTC_ON_MASK 0x800 +#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb +#define FEATURE_STATUS__VPC_ON_MASK 0x1000 +#define FEATURE_STATUS__VPC_ON__SHIFT 0xc +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd +#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 +#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe +#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 +#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf +#define FEATURE_STATUS__AVS_ON_MASK 0x10000 +#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 +#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 +#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 +#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 +#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 +#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 +#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 +#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 +#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 +#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 +#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 +#define FEATURE_STATUS__RESERVED_MASK 0xffc00000 +#define FEATURE_STATUS__RESERVED__SHIFT 0x16 +#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff +#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime__SHIFT 0x18 +#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff +#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00 +#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8 +#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000 +#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000 +#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18 +#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_82__data_4_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_82__data_4_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_83__data_4_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_83__data_4_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_84__data_4_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_84__data_4_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_85__data_4_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_85__data_4_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_86__data_4_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_86__data_4_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_87__data_4_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_87__data_4_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_88__data_4_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_88__data_4_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_89__data_4_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_89__data_4_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_90__data_4_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_90__data_4_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_91__data_4_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_91__data_4_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_92__data_4_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_93__data_4_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_93__data_4_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_94__data_4_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_94__data_4_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_95__data_4_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_95__data_4_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_96__data_4_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_96__data_4_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_97__data_4_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_97__data_4_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_98__data_5_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_98__data_5_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_99__data_5_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_99__data_5_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_100__data_5_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_100__data_5_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_101__data_5_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_102__data_5_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_103__data_5_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_103__data_5_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_104__data_5_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_104__data_5_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_105__data_5_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_105__data_5_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_106__data_5_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_106__data_5_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_107__data_5_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_107__data_5_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_108__data_5_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_109__data_5_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_109__data_5_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_110__data_5_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_111__data_5_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_111__data_5_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_112__data_5_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_112__data_5_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_113__data_5_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_113__data_5_value_15__SHIFT 0x0 +#define FAN_TABLE_1__TempMin_MASK 0xffff +#define FAN_TABLE_1__TempMin__SHIFT 0x0 +#define FAN_TABLE_1__FdoMode_MASK 0xffff0000 +#define FAN_TABLE_1__FdoMode__SHIFT 0x10 +#define FAN_TABLE_2__TempMax_MASK 0xffff +#define FAN_TABLE_2__TempMax__SHIFT 0x0 +#define FAN_TABLE_2__TempMed_MASK 0xffff0000 +#define FAN_TABLE_2__TempMed__SHIFT 0x10 +#define FAN_TABLE_3__Slope2_MASK 0xffff +#define FAN_TABLE_3__Slope2__SHIFT 0x0 +#define FAN_TABLE_3__Slope1_MASK 0xffff0000 +#define FAN_TABLE_3__Slope1__SHIFT 0x10 +#define FAN_TABLE_4__HystUp_MASK 0xffff +#define FAN_TABLE_4__HystUp__SHIFT 0x0 +#define FAN_TABLE_4__FdoMin_MASK 0xffff0000 +#define FAN_TABLE_4__FdoMin__SHIFT 0x10 +#define FAN_TABLE_5__HystSlope_MASK 0xffff +#define FAN_TABLE_5__HystSlope__SHIFT 0x0 +#define FAN_TABLE_5__HystDown_MASK 0xffff0000 +#define FAN_TABLE_5__HystDown__SHIFT 0x10 +#define FAN_TABLE_6__TempCurr_MASK 0xffff +#define FAN_TABLE_6__TempCurr__SHIFT 0x0 +#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000 +#define FAN_TABLE_6__TempRespLim__SHIFT 0x10 +#define FAN_TABLE_7__PwmCurr_MASK 0xffff +#define FAN_TABLE_7__PwmCurr__SHIFT 0x0 +#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000 +#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10 +#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff +#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0 +#define FAN_TABLE_9__Padding_MASK 0xff +#define FAN_TABLE_9__Padding__SHIFT 0x0 +#define FAN_TABLE_9__TempSrc_MASK 0xff00 +#define FAN_TABLE_9__TempSrc__SHIFT 0x8 +#define FAN_TABLE_9__FdoMax_MASK 0xffff0000 +#define FAN_TABLE_9__FdoMax__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_28__Reserved_0_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_28__Reserved_0__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_29__Reserved_1_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_29__Reserved_1__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_30__Reserved_2_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_30__Reserved_2__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff +#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00 +#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8 +#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000 +#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10 +#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000 +#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18 +#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff +#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0 +#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00 +#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8 +#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000 +#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10 +#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000 +#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18 +#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff +#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0 +#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00 +#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8 +#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000 +#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10 +#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000 +#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18 +#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff +#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0 +#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00 +#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8 +#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000 +#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10 +#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000 +#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18 +#define PM_FUSES_5__VddCVid_3_MASK 0xff +#define PM_FUSES_5__VddCVid_3__SHIFT 0x0 +#define PM_FUSES_5__VddCVid_2_MASK 0xff00 +#define PM_FUSES_5__VddCVid_2__SHIFT 0x8 +#define PM_FUSES_5__VddCVid_1_MASK 0xff0000 +#define PM_FUSES_5__VddCVid_1__SHIFT 0x10 +#define PM_FUSES_5__VddCVid_0_MASK 0xff000000 +#define PM_FUSES_5__VddCVid_0__SHIFT 0x18 +#define PM_FUSES_6__VddCVid_7_MASK 0xff +#define PM_FUSES_6__VddCVid_7__SHIFT 0x0 +#define PM_FUSES_6__VddCVid_6_MASK 0xff00 +#define PM_FUSES_6__VddCVid_6__SHIFT 0x8 +#define PM_FUSES_6__VddCVid_5_MASK 0xff0000 +#define PM_FUSES_6__VddCVid_5__SHIFT 0x10 +#define PM_FUSES_6__VddCVid_4_MASK 0xff000000 +#define PM_FUSES_6__VddCVid_4__SHIFT 0x18 +#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff +#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0 +#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00 +#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8 +#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000 +#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10 +#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000 +#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18 +#define PM_FUSES_8__TDC_MAWt_MASK 0xff +#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8 +#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000 +#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10 +#define PM_FUSES_9__Reserved_MASK 0xff +#define PM_FUSES_9__Reserved__SHIFT 0x0 +#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00 +#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8 +#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000 +#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10 +#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000 +#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18 +#define PM_FUSES_10__BapmVddCVidHiSidd2_3_MASK 0xff +#define PM_FUSES_10__BapmVddCVidHiSidd2_3__SHIFT 0x0 +#define PM_FUSES_10__BapmVddCVidHiSidd2_2_MASK 0xff00 +#define PM_FUSES_10__BapmVddCVidHiSidd2_2__SHIFT 0x8 +#define PM_FUSES_10__BapmVddCVidHiSidd2_1_MASK 0xff0000 +#define PM_FUSES_10__BapmVddCVidHiSidd2_1__SHIFT 0x10 +#define PM_FUSES_10__BapmVddCVidHiSidd2_0_MASK 0xff000000 +#define PM_FUSES_10__BapmVddCVidHiSidd2_0__SHIFT 0x18 +#define PM_FUSES_11__BapmVddCVidHiSidd2_7_MASK 0xff +#define PM_FUSES_11__BapmVddCVidHiSidd2_7__SHIFT 0x0 +#define PM_FUSES_11__BapmVddCVidHiSidd2_6_MASK 0xff00 +#define PM_FUSES_11__BapmVddCVidHiSidd2_6__SHIFT 0x8 +#define PM_FUSES_11__BapmVddCVidHiSidd2_5_MASK 0xff0000 +#define PM_FUSES_11__BapmVddCVidHiSidd2_5__SHIFT 0x10 +#define PM_FUSES_11__BapmVddCVidHiSidd2_4_MASK 0xff000000 +#define PM_FUSES_11__BapmVddCVidHiSidd2_4__SHIFT 0x18 +#define PM_FUSES_12__FuzzyFan_ErrorRateSetDelta_MASK 0xffff +#define PM_FUSES_12__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0 +#define PM_FUSES_12__FuzzyFan_ErrorSetDelta_MASK 0xffff0000 +#define PM_FUSES_12__FuzzyFan_ErrorSetDelta__SHIFT 0x10 +#define PM_FUSES_13__Reserved6_MASK 0xffff +#define PM_FUSES_13__Reserved6__SHIFT 0x0 +#define PM_FUSES_13__FuzzyFan_PwmSetDelta_MASK 0xffff0000 +#define PM_FUSES_13__FuzzyFan_PwmSetDelta__SHIFT 0x10 +#define PM_FUSES_14__GnbLPML_3_MASK 0xff +#define PM_FUSES_14__GnbLPML_3__SHIFT 0x0 +#define PM_FUSES_14__GnbLPML_2_MASK 0xff00 +#define PM_FUSES_14__GnbLPML_2__SHIFT 0x8 +#define PM_FUSES_14__GnbLPML_1_MASK 0xff0000 +#define PM_FUSES_14__GnbLPML_1__SHIFT 0x10 +#define PM_FUSES_14__GnbLPML_0_MASK 0xff000000 +#define PM_FUSES_14__GnbLPML_0__SHIFT 0x18 +#define PM_FUSES_15__GnbLPML_7_MASK 0xff +#define PM_FUSES_15__GnbLPML_7__SHIFT 0x0 +#define PM_FUSES_15__GnbLPML_6_MASK 0xff00 +#define PM_FUSES_15__GnbLPML_6__SHIFT 0x8 +#define PM_FUSES_15__GnbLPML_5_MASK 0xff0000 +#define PM_FUSES_15__GnbLPML_5__SHIFT 0x10 +#define PM_FUSES_15__GnbLPML_4_MASK 0xff000000 +#define PM_FUSES_15__GnbLPML_4__SHIFT 0x18 +#define PM_FUSES_16__GnbLPML_11_MASK 0xff +#define PM_FUSES_16__GnbLPML_11__SHIFT 0x0 +#define PM_FUSES_16__GnbLPML_10_MASK 0xff00 +#define PM_FUSES_16__GnbLPML_10__SHIFT 0x8 +#define PM_FUSES_16__GnbLPML_9_MASK 0xff0000 +#define PM_FUSES_16__GnbLPML_9__SHIFT 0x10 +#define PM_FUSES_16__GnbLPML_8_MASK 0xff000000 +#define PM_FUSES_16__GnbLPML_8__SHIFT 0x18 +#define PM_FUSES_17__GnbLPML_15_MASK 0xff +#define PM_FUSES_17__GnbLPML_15__SHIFT 0x0 +#define PM_FUSES_17__GnbLPML_14_MASK 0xff00 +#define PM_FUSES_17__GnbLPML_14__SHIFT 0x8 +#define PM_FUSES_17__GnbLPML_13_MASK 0xff0000 +#define PM_FUSES_17__GnbLPML_13__SHIFT 0x10 +#define PM_FUSES_17__GnbLPML_12_MASK 0xff000000 +#define PM_FUSES_17__GnbLPML_12__SHIFT 0x18 +#define PM_FUSES_18__Reserved1_1_MASK 0xff +#define PM_FUSES_18__Reserved1_1__SHIFT 0x0 +#define PM_FUSES_18__Reserved1_0_MASK 0xff00 +#define PM_FUSES_18__Reserved1_0__SHIFT 0x8 +#define PM_FUSES_18__GnbLPMLMinVid_MASK 0xff0000 +#define PM_FUSES_18__GnbLPMLMinVid__SHIFT 0x10 +#define PM_FUSES_18__GnbLPMLMaxVid_MASK 0xff000000 +#define PM_FUSES_18__GnbLPMLMaxVid__SHIFT 0x18 +#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd_MASK 0xffff +#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd__SHIFT 0x0 +#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000 +#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd__SHIFT 0x10 +#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_52__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0 +#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8 +#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3 +#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0 +#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4 +#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000 +#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe +#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000 +#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19 +#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000 +#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a +#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff +#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 +#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000 +#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11 +#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000 +#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12 +#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff +#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0 +#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00 +#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8 +#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000 +#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10 +#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000 +#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18 +#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf +#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 +#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0 +#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 +#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff +#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 +#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff +#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 +#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00 +#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL1__M_MASK 0xff0000 +#define CG_FDO_CTRL1__M__SHIFT 0x10 +#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000 +#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 +#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000 +#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e +#define CG_FDO_CTRL2__TMIN_MASK 0xff +#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 +#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800 +#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb +#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000 +#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe +#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000 +#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 +#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7 +#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 +#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8 +#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 +#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff +#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 +#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe +#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1 +#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00 +#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11 +#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000 +#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12 +#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000 +#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18 +#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000 +#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19 +#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000 +#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a +#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000 +#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b +#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000 +#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c +#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000 +#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d +#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000 +#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_INT_DATA__Z_MASK 0x7ff +#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON0_INT_DATA__VALID_MASK 0x800 +#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_INT_DATA__Z_MASK 0x7ff +#define THM_TMON1_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON1_INT_DATA__VALID_MASK 0x800 +#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON1_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 +#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2 +#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4 +#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40 +#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80 +#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200 +#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400 +#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000 +#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000 +#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17 +#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000 +#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000 +#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000 +#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000 +#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf +#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 +#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 +#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 +#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 +#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 +#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf +#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 +#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1 +#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0 +#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe +#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff +#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0 +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff +#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2 +#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1 +#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4 +#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10 +#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000 +#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a +#define ROM_STATUS__ROM_BUSY_MASK 0x1 +#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf +#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define ROM_INDEX__ROM_INDEX_MASK 0xffffff +#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 +#define ROM_DATA__ROM_DATA_MASK 0xffffffff +#define ROM_DATA__ROM_DATA__SHIFT 0x0 +#define ROM_START__ROM_START_MASK 0xffffff +#define ROM_START__ROM_START__SHIFT 0x0 +#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff +#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 +#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000 +#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 +#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1 +#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 +#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 + +#endif /* SMU_7_1_0_SH_MASK_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h new file mode 100644 index 000000000000..3014d4a58c43 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h @@ -0,0 +1,1123 @@ +/* + * SMU_7_1_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_1_D_H +#define SMU_7_1_1_D_H + +#define mmGCK_SMC_IND_INDEX 0x80 +#define mmGCK0_GCK_SMC_IND_INDEX 0x80 +#define mmGCK1_GCK_SMC_IND_INDEX 0x82 +#define mmGCK2_GCK_SMC_IND_INDEX 0x84 +#define mmGCK3_GCK_SMC_IND_INDEX 0x86 +#define mmGCK_SMC_IND_DATA 0x81 +#define mmGCK0_GCK_SMC_IND_DATA 0x81 +#define mmGCK1_GCK_SMC_IND_DATA 0x83 +#define mmGCK2_GCK_SMC_IND_DATA 0x85 +#define mmGCK3_GCK_SMC_IND_DATA 0x87 +#define ixCG_DCLK_CNTL 0xc050009c +#define ixCG_DCLK_STATUS 0xc05000a0 +#define ixCG_VCLK_CNTL 0xc05000a4 +#define ixCG_VCLK_STATUS 0xc05000a8 +#define ixCG_ECLK_CNTL 0xc05000ac +#define ixCG_ECLK_STATUS 0xc05000b0 +#define ixCG_ACLK_CNTL 0xc05000dc +#define ixGCK_DFS_BYPASS_CNTL 0xc0500118 +#define ixCG_SPLL_FUNC_CNTL 0xc0500140 +#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 +#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 +#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c +#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 +#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 +#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 +#define ixSPLL_CNTL_MODE 0xc0500160 +#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 +#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +#define ixMPLL_BYPASSCLK_SEL 0xc050019c +#define ixCG_CLKPIN_CNTL 0xc05001a0 +#define ixCG_CLKPIN_CNTL_2 0xc05001a4 +#define ixCG_CLKPIN_CNTL_DC 0xc0500204 +#define ixTHM_CLK_CNTL 0xc05001a8 +#define ixMISC_CLK_CTRL 0xc05001ac +#define ixGCK_PLL_TEST_CNTL 0xc05001c0 +#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 +#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 +#define mmSMC_IND_INDEX 0x80 +#define mmSMC0_SMC_IND_INDEX 0x80 +#define mmSMC1_SMC_IND_INDEX 0x82 +#define mmSMC2_SMC_IND_INDEX 0x84 +#define mmSMC3_SMC_IND_INDEX 0x86 +#define mmSMC_IND_DATA 0x81 +#define mmSMC0_SMC_IND_DATA 0x81 +#define mmSMC1_SMC_IND_DATA 0x83 +#define mmSMC2_SMC_IND_DATA 0x85 +#define mmSMC3_SMC_IND_DATA 0x87 +#define mmSMC_IND_INDEX_0 0x80 +#define mmSMC_IND_DATA_0 0x81 +#define mmSMC_IND_INDEX_1 0x82 +#define mmSMC_IND_DATA_1 0x83 +#define mmSMC_IND_INDEX_2 0x84 +#define mmSMC_IND_DATA_2 0x85 +#define mmSMC_IND_INDEX_3 0x86 +#define mmSMC_IND_DATA_3 0x87 +#define mmSMC_IND_INDEX_4 0x88 +#define mmSMC_IND_DATA_4 0x89 +#define mmSMC_IND_INDEX_5 0x8a +#define mmSMC_IND_DATA_5 0x8b +#define mmSMC_IND_INDEX_6 0x8c +#define mmSMC_IND_DATA_6 0x8d +#define mmSMC_IND_INDEX_7 0x8e +#define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_ACCESS_CNTL 0x92 +#define mmSMC_MESSAGE_0 0x94 +#define mmSMC_RESP_0 0x95 +#define mmSMC_MESSAGE_1 0x96 +#define mmSMC_RESP_1 0x97 +#define mmSMC_MESSAGE_2 0x98 +#define mmSMC_RESP_2 0x99 +#define mmSMC_MESSAGE_3 0x9a +#define mmSMC_RESP_3 0x9b +#define mmSMC_MESSAGE_4 0x9c +#define mmSMC_RESP_4 0x9d +#define mmSMC_MESSAGE_5 0x9e +#define mmSMC_RESP_5 0x9f +#define mmSMC_MESSAGE_6 0xa0 +#define mmSMC_RESP_6 0xa1 +#define mmSMC_MESSAGE_7 0xa2 +#define mmSMC_RESP_7 0xa3 +#define mmSMC_MSG_ARG_0 0xa4 +#define mmSMC_MSG_ARG_1 0xa5 +#define mmSMC_MSG_ARG_2 0xa6 +#define mmSMC_MSG_ARG_3 0xa7 +#define mmSMC_MSG_ARG_4 0xa8 +#define mmSMC_MSG_ARG_5 0xa9 +#define mmSMC_MSG_ARG_6 0xaa +#define mmSMC_MSG_ARG_7 0xab +#define mmSMC_MESSAGE_8 0xb5 +#define mmSMC_RESP_8 0xb6 +#define mmSMC_MESSAGE_9 0xb7 +#define mmSMC_RESP_9 0xb8 +#define mmSMC_MESSAGE_10 0xb9 +#define mmSMC_RESP_10 0xba +#define mmSMC_MESSAGE_11 0xbb +#define mmSMC_RESP_11 0xbc +#define mmSMC_MSG_ARG_8 0xbd +#define mmSMC_MSG_ARG_9 0xbe +#define mmSMC_MSG_ARG_10 0xbf +#define mmSMC_MSG_ARG_11 0x93 +#define ixSMC_SYSCON_RESET_CNTL 0x80000000 +#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 +#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 +#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c +#define ixSMC_SYSCON_MISC_CNTL 0x80000010 +#define ixSMC_SYSCON_MSG_ARG_0 0x80000068 +#define ixSMC_PC_C 0x80000370 +#define ixSMC_SCRATCH9 0x80000424 +#define mmGPIOPAD_SW_INT_STAT 0x180 +#define mmGPIOPAD_STRENGTH 0x181 +#define mmGPIOPAD_MASK 0x182 +#define mmGPIOPAD_A 0x183 +#define mmGPIOPAD_EN 0x184 +#define mmGPIOPAD_Y 0x185 +#define mmGPIOPAD_PINSTRAPS 0x186 +#define mmGPIOPAD_INT_STAT_EN 0x187 +#define mmGPIOPAD_INT_STAT 0x188 +#define mmGPIOPAD_INT_STAT_AK 0x189 +#define mmGPIOPAD_INT_EN 0x18a +#define mmGPIOPAD_INT_TYPE 0x18b +#define mmGPIOPAD_INT_POLARITY 0x18c +#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d +#define mmGPIOPAD_RCVR_SEL 0x191 +#define mmGPIOPAD_PU_EN 0x192 +#define mmGPIOPAD_PD_EN 0x193 +#define mmCG_FPS_CNT 0x1b6 +#define mmSMU_IND_INDEX_0 0x1a6 +#define mmSMU_IND_DATA_0 0x1a7 +#define mmSMU_IND_INDEX_1 0x1a8 +#define mmSMU_IND_DATA_1 0x1a9 +#define mmSMU_IND_INDEX_2 0x1aa +#define mmSMU_IND_DATA_2 0x1ab +#define mmSMU_IND_INDEX_3 0x1ac +#define mmSMU_IND_DATA_3 0x1ad +#define mmSMU_IND_INDEX_4 0x1ae +#define mmSMU_IND_DATA_4 0x1af +#define mmSMU_IND_INDEX_5 0x1b0 +#define mmSMU_IND_DATA_5 0x1b1 +#define mmSMU_IND_INDEX_6 0x1b2 +#define mmSMU_IND_DATA_6 0x1b3 +#define mmSMU_IND_INDEX_7 0x1b4 +#define mmSMU_IND_DATA_7 0x1b5 +#define mmSMU_SMC_IND_INDEX 0x80 +#define mmSMU0_SMU_SMC_IND_INDEX 0x80 +#define mmSMU1_SMU_SMC_IND_INDEX 0x82 +#define mmSMU2_SMU_SMC_IND_INDEX 0x84 +#define mmSMU3_SMU_SMC_IND_INDEX 0x86 +#define mmSMU_SMC_IND_DATA 0x81 +#define mmSMU0_SMU_SMC_IND_DATA 0x81 +#define mmSMU1_SMU_SMC_IND_DATA 0x83 +#define mmSMU2_SMU_SMC_IND_DATA 0x85 +#define mmSMU3_SMU_SMC_IND_DATA 0x87 +#define ixRCU_UC_EVENTS 0xc0000004 +#define ixRCU_MISC_CTRL 0xc0000010 +#define ixCC_RCU_FUSES 0xc00c0000 +#define ixCC_SMU_MISC_FUSES 0xc00c0004 +#define ixCC_SCLK_VID_FUSES 0xc00c0008 +#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c +#define ixCC_GIO_IOC_FUSES 0xc00c0010 +#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c +#define ixCC_TST_ID_STRAPS 0xc00c0020 +#define ixCC_FCTRL_FUSES 0xc00c0024 +#define ixCC_HARVEST_FUSES 0xc00c0028 +#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 +#define ixSMU_STATUS 0xe0003088 +#define ixSMU_FIRMWARE 0xe00030a4 +#define ixSMU_INPUT_DATA 0xe00030b8 +#define ixSMU_EFUSE_0 0xc0100000 +#define ixMCARB_DRAM_TIMING_TABLE_1 0x33018 +#define ixMCARB_DRAM_TIMING_TABLE_2 0x3301c +#define ixMCARB_DRAM_TIMING_TABLE_3 0x33020 +#define ixMCARB_DRAM_TIMING_TABLE_4 0x33024 +#define ixMCARB_DRAM_TIMING_TABLE_5 0x33028 +#define ixMCARB_DRAM_TIMING_TABLE_6 0x3302c +#define ixMCARB_DRAM_TIMING_TABLE_7 0x33030 +#define ixMCARB_DRAM_TIMING_TABLE_8 0x33034 +#define ixMCARB_DRAM_TIMING_TABLE_9 0x33038 +#define ixMCARB_DRAM_TIMING_TABLE_10 0x3303c +#define ixMCARB_DRAM_TIMING_TABLE_11 0x33040 +#define ixMCARB_DRAM_TIMING_TABLE_12 0x33044 +#define ixMCARB_DRAM_TIMING_TABLE_13 0x33048 +#define ixMCARB_DRAM_TIMING_TABLE_14 0x3304c +#define ixMCARB_DRAM_TIMING_TABLE_15 0x33050 +#define ixMCARB_DRAM_TIMING_TABLE_16 0x33054 +#define ixMCARB_DRAM_TIMING_TABLE_17 0x33058 +#define ixMCARB_DRAM_TIMING_TABLE_18 0x3305c +#define ixMCARB_DRAM_TIMING_TABLE_19 0x33060 +#define ixMCARB_DRAM_TIMING_TABLE_20 0x33064 +#define ixMCARB_DRAM_TIMING_TABLE_21 0x33068 +#define ixMCARB_DRAM_TIMING_TABLE_22 0x3306c +#define ixMCARB_DRAM_TIMING_TABLE_23 0x33070 +#define ixMCARB_DRAM_TIMING_TABLE_24 0x33074 +#define ixMCARB_DRAM_TIMING_TABLE_25 0x33078 +#define ixMCARB_DRAM_TIMING_TABLE_26 0x3307c +#define ixMCARB_DRAM_TIMING_TABLE_27 0x33080 +#define ixMCARB_DRAM_TIMING_TABLE_28 0x33084 +#define ixMCARB_DRAM_TIMING_TABLE_29 0x33088 +#define ixMCARB_DRAM_TIMING_TABLE_30 0x3308c +#define ixMCARB_DRAM_TIMING_TABLE_31 0x33090 +#define ixMCARB_DRAM_TIMING_TABLE_32 0x33094 +#define ixMCARB_DRAM_TIMING_TABLE_33 0x33098 +#define ixMCARB_DRAM_TIMING_TABLE_34 0x3309c +#define ixMCARB_DRAM_TIMING_TABLE_35 0x330a0 +#define ixMCARB_DRAM_TIMING_TABLE_36 0x330a4 +#define ixMCARB_DRAM_TIMING_TABLE_37 0x330a8 +#define ixMCARB_DRAM_TIMING_TABLE_38 0x330ac +#define ixMCARB_DRAM_TIMING_TABLE_39 0x330b0 +#define ixMCARB_DRAM_TIMING_TABLE_40 0x330b4 +#define ixMCARB_DRAM_TIMING_TABLE_41 0x330b8 +#define ixMCARB_DRAM_TIMING_TABLE_42 0x330bc +#define ixMCARB_DRAM_TIMING_TABLE_43 0x330c0 +#define ixMCARB_DRAM_TIMING_TABLE_44 0x330c4 +#define ixMCARB_DRAM_TIMING_TABLE_45 0x330c8 +#define ixMCARB_DRAM_TIMING_TABLE_46 0x330cc +#define ixMCARB_DRAM_TIMING_TABLE_47 0x330d0 +#define ixMCARB_DRAM_TIMING_TABLE_48 0x330d4 +#define ixMCARB_DRAM_TIMING_TABLE_49 0x330d8 +#define ixMCARB_DRAM_TIMING_TABLE_50 0x330dc +#define ixMCARB_DRAM_TIMING_TABLE_51 0x330e0 +#define ixMCARB_DRAM_TIMING_TABLE_52 0x330e4 +#define ixMCARB_DRAM_TIMING_TABLE_53 0x330e8 +#define ixMCARB_DRAM_TIMING_TABLE_54 0x330ec +#define ixMCARB_DRAM_TIMING_TABLE_55 0x330f0 +#define ixMCARB_DRAM_TIMING_TABLE_56 0x330f4 +#define ixMCARB_DRAM_TIMING_TABLE_57 0x330f8 +#define ixMCARB_DRAM_TIMING_TABLE_58 0x330fc +#define ixMCARB_DRAM_TIMING_TABLE_59 0x33100 +#define ixMCARB_DRAM_TIMING_TABLE_60 0x33104 +#define ixMCARB_DRAM_TIMING_TABLE_61 0x33108 +#define ixMCARB_DRAM_TIMING_TABLE_62 0x3310c +#define ixMCARB_DRAM_TIMING_TABLE_63 0x33110 +#define ixMCARB_DRAM_TIMING_TABLE_64 0x33114 +#define ixMCARB_DRAM_TIMING_TABLE_65 0x33118 +#define ixMCARB_DRAM_TIMING_TABLE_66 0x3311c +#define ixMCARB_DRAM_TIMING_TABLE_67 0x33120 +#define ixMCARB_DRAM_TIMING_TABLE_68 0x33124 +#define ixMCARB_DRAM_TIMING_TABLE_69 0x33128 +#define ixMCARB_DRAM_TIMING_TABLE_70 0x3312c +#define ixMCARB_DRAM_TIMING_TABLE_71 0x33130 +#define ixMCARB_DRAM_TIMING_TABLE_72 0x33134 +#define ixMCARB_DRAM_TIMING_TABLE_73 0x33138 +#define ixMCARB_DRAM_TIMING_TABLE_74 0x3313c +#define ixMCARB_DRAM_TIMING_TABLE_75 0x33140 +#define ixMCARB_DRAM_TIMING_TABLE_76 0x33144 +#define ixMCARB_DRAM_TIMING_TABLE_77 0x33148 +#define ixMCARB_DRAM_TIMING_TABLE_78 0x3314c +#define ixMCARB_DRAM_TIMING_TABLE_79 0x33150 +#define ixMCARB_DRAM_TIMING_TABLE_80 0x33154 +#define ixMCARB_DRAM_TIMING_TABLE_81 0x33158 +#define ixMCARB_DRAM_TIMING_TABLE_82 0x3315c +#define ixMCARB_DRAM_TIMING_TABLE_83 0x33160 +#define ixMCARB_DRAM_TIMING_TABLE_84 0x33164 +#define ixMCARB_DRAM_TIMING_TABLE_85 0x33168 +#define ixMCARB_DRAM_TIMING_TABLE_86 0x3316c +#define ixMCARB_DRAM_TIMING_TABLE_87 0x33170 +#define ixMCARB_DRAM_TIMING_TABLE_88 0x33174 +#define ixMCARB_DRAM_TIMING_TABLE_89 0x33178 +#define ixMCARB_DRAM_TIMING_TABLE_90 0x3317c +#define ixMCARB_DRAM_TIMING_TABLE_91 0x33180 +#define ixMCARB_DRAM_TIMING_TABLE_92 0x33184 +#define ixMCARB_DRAM_TIMING_TABLE_93 0x33188 +#define ixMCARB_DRAM_TIMING_TABLE_94 0x3318c +#define ixMCARB_DRAM_TIMING_TABLE_95 0x33190 +#define ixMCARB_DRAM_TIMING_TABLE_96 0x33194 +#define ixMC_REGISTERS_TABLE_1 0x33198 +#define ixMC_REGISTERS_TABLE_2 0x3319c +#define ixMC_REGISTERS_TABLE_3 0x331a0 +#define ixMC_REGISTERS_TABLE_4 0x331a4 +#define ixMC_REGISTERS_TABLE_5 0x331a8 +#define ixMC_REGISTERS_TABLE_6 0x331ac +#define ixMC_REGISTERS_TABLE_7 0x331b0 +#define ixMC_REGISTERS_TABLE_8 0x331b4 +#define ixMC_REGISTERS_TABLE_9 0x331b8 +#define ixMC_REGISTERS_TABLE_10 0x331bc +#define ixMC_REGISTERS_TABLE_11 0x331c0 +#define ixMC_REGISTERS_TABLE_12 0x331c4 +#define ixMC_REGISTERS_TABLE_13 0x331c8 +#define ixMC_REGISTERS_TABLE_14 0x331cc +#define ixMC_REGISTERS_TABLE_15 0x331d0 +#define ixMC_REGISTERS_TABLE_16 0x331d4 +#define ixMC_REGISTERS_TABLE_17 0x331d8 +#define ixMC_REGISTERS_TABLE_18 0x331dc +#define ixMC_REGISTERS_TABLE_19 0x331e0 +#define ixMC_REGISTERS_TABLE_20 0x331e4 +#define ixMC_REGISTERS_TABLE_21 0x331e8 +#define ixMC_REGISTERS_TABLE_22 0x331ec +#define ixMC_REGISTERS_TABLE_23 0x331f0 +#define ixMC_REGISTERS_TABLE_24 0x331f4 +#define ixMC_REGISTERS_TABLE_25 0x331f8 +#define ixMC_REGISTERS_TABLE_26 0x331fc +#define ixMC_REGISTERS_TABLE_27 0x33200 +#define ixMC_REGISTERS_TABLE_28 0x33204 +#define ixMC_REGISTERS_TABLE_29 0x33208 +#define ixMC_REGISTERS_TABLE_30 0x3320c +#define ixMC_REGISTERS_TABLE_31 0x33210 +#define ixMC_REGISTERS_TABLE_32 0x33214 +#define ixMC_REGISTERS_TABLE_33 0x33218 +#define ixMC_REGISTERS_TABLE_34 0x3321c +#define ixMC_REGISTERS_TABLE_35 0x33220 +#define ixMC_REGISTERS_TABLE_36 0x33224 +#define ixMC_REGISTERS_TABLE_37 0x33228 +#define ixMC_REGISTERS_TABLE_38 0x3322c +#define ixMC_REGISTERS_TABLE_39 0x33230 +#define ixMC_REGISTERS_TABLE_40 0x33234 +#define ixMC_REGISTERS_TABLE_41 0x33238 +#define ixMC_REGISTERS_TABLE_42 0x3323c +#define ixMC_REGISTERS_TABLE_43 0x33240 +#define ixMC_REGISTERS_TABLE_44 0x33244 +#define ixMC_REGISTERS_TABLE_45 0x33248 +#define ixMC_REGISTERS_TABLE_46 0x3324c +#define ixMC_REGISTERS_TABLE_47 0x33250 +#define ixMC_REGISTERS_TABLE_48 0x33254 +#define ixMC_REGISTERS_TABLE_49 0x33258 +#define ixMC_REGISTERS_TABLE_50 0x3325c +#define ixMC_REGISTERS_TABLE_51 0x33260 +#define ixMC_REGISTERS_TABLE_52 0x33264 +#define ixMC_REGISTERS_TABLE_53 0x33268 +#define ixMC_REGISTERS_TABLE_54 0x3326c +#define ixMC_REGISTERS_TABLE_55 0x33270 +#define ixMC_REGISTERS_TABLE_56 0x33274 +#define ixMC_REGISTERS_TABLE_57 0x33278 +#define ixMC_REGISTERS_TABLE_58 0x3327c +#define ixMC_REGISTERS_TABLE_59 0x33280 +#define ixMC_REGISTERS_TABLE_60 0x33284 +#define ixMC_REGISTERS_TABLE_61 0x33288 +#define ixMC_REGISTERS_TABLE_62 0x3328c +#define ixMC_REGISTERS_TABLE_63 0x33290 +#define ixMC_REGISTERS_TABLE_64 0x33294 +#define ixMC_REGISTERS_TABLE_65 0x33298 +#define ixMC_REGISTERS_TABLE_66 0x3329c +#define ixMC_REGISTERS_TABLE_67 0x332a0 +#define ixMC_REGISTERS_TABLE_68 0x332a4 +#define ixMC_REGISTERS_TABLE_69 0x332a8 +#define ixMC_REGISTERS_TABLE_70 0x332ac +#define ixMC_REGISTERS_TABLE_71 0x332b0 +#define ixMC_REGISTERS_TABLE_72 0x332b4 +#define ixMC_REGISTERS_TABLE_73 0x332b8 +#define ixMC_REGISTERS_TABLE_74 0x332bc +#define ixMC_REGISTERS_TABLE_75 0x332c0 +#define ixMC_REGISTERS_TABLE_76 0x332c4 +#define ixMC_REGISTERS_TABLE_77 0x332c8 +#define ixMC_REGISTERS_TABLE_78 0x332cc +#define ixMC_REGISTERS_TABLE_79 0x332d0 +#define ixMC_REGISTERS_TABLE_80 0x332d4 +#define ixMC_REGISTERS_TABLE_81 0x332d8 +#define ixDPM_TABLE_1 0x332dc +#define ixDPM_TABLE_2 0x332e0 +#define ixDPM_TABLE_3 0x332e4 +#define ixDPM_TABLE_4 0x332e8 +#define ixDPM_TABLE_5 0x332ec +#define ixDPM_TABLE_6 0x332f0 +#define ixDPM_TABLE_7 0x332f4 +#define ixDPM_TABLE_8 0x332f8 +#define ixDPM_TABLE_9 0x332fc +#define ixDPM_TABLE_10 0x33300 +#define ixDPM_TABLE_11 0x33304 +#define ixDPM_TABLE_12 0x33308 +#define ixDPM_TABLE_13 0x3330c +#define ixDPM_TABLE_14 0x33310 +#define ixDPM_TABLE_15 0x33314 +#define ixDPM_TABLE_16 0x33318 +#define ixDPM_TABLE_17 0x3331c +#define ixDPM_TABLE_18 0x33320 +#define ixDPM_TABLE_19 0x33324 +#define ixDPM_TABLE_20 0x33328 +#define ixDPM_TABLE_21 0x3332c +#define ixDPM_TABLE_22 0x33330 +#define ixDPM_TABLE_23 0x33334 +#define ixDPM_TABLE_24 0x33338 +#define ixDPM_TABLE_25 0x3333c +#define ixDPM_TABLE_26 0x33340 +#define ixDPM_TABLE_27 0x33344 +#define ixDPM_TABLE_28 0x33348 +#define ixDPM_TABLE_29 0x3334c +#define ixDPM_TABLE_30 0x33350 +#define ixDPM_TABLE_31 0x33354 +#define ixDPM_TABLE_32 0x33358 +#define ixDPM_TABLE_33 0x3335c +#define ixDPM_TABLE_34 0x33360 +#define ixDPM_TABLE_35 0x33364 +#define ixDPM_TABLE_36 0x33368 +#define ixDPM_TABLE_37 0x3336c +#define ixDPM_TABLE_38 0x33370 +#define ixDPM_TABLE_39 0x33374 +#define ixDPM_TABLE_40 0x33378 +#define ixDPM_TABLE_41 0x3337c +#define ixDPM_TABLE_42 0x33380 +#define ixDPM_TABLE_43 0x33384 +#define ixDPM_TABLE_44 0x33388 +#define ixDPM_TABLE_45 0x3338c +#define ixDPM_TABLE_46 0x33390 +#define ixDPM_TABLE_47 0x33394 +#define ixDPM_TABLE_48 0x33398 +#define ixDPM_TABLE_49 0x3339c +#define ixDPM_TABLE_50 0x333a0 +#define ixDPM_TABLE_51 0x333a4 +#define ixDPM_TABLE_52 0x333a8 +#define ixDPM_TABLE_53 0x333ac +#define ixDPM_TABLE_54 0x333b0 +#define ixDPM_TABLE_55 0x333b4 +#define ixDPM_TABLE_56 0x333b8 +#define ixDPM_TABLE_57 0x333bc +#define ixDPM_TABLE_58 0x333c0 +#define ixDPM_TABLE_59 0x333c4 +#define ixDPM_TABLE_60 0x333c8 +#define ixDPM_TABLE_61 0x333cc +#define ixDPM_TABLE_62 0x333d0 +#define ixDPM_TABLE_63 0x333d4 +#define ixDPM_TABLE_64 0x333d8 +#define ixDPM_TABLE_65 0x333dc +#define ixDPM_TABLE_66 0x333e0 +#define ixDPM_TABLE_67 0x333e4 +#define ixDPM_TABLE_68 0x333e8 +#define ixDPM_TABLE_69 0x333ec +#define ixDPM_TABLE_70 0x333f0 +#define ixDPM_TABLE_71 0x333f4 +#define ixDPM_TABLE_72 0x333f8 +#define ixDPM_TABLE_73 0x333fc +#define ixDPM_TABLE_74 0x33400 +#define ixDPM_TABLE_75 0x33404 +#define ixDPM_TABLE_76 0x33408 +#define ixDPM_TABLE_77 0x3340c +#define ixDPM_TABLE_78 0x33410 +#define ixDPM_TABLE_79 0x33414 +#define ixDPM_TABLE_80 0x33418 +#define ixDPM_TABLE_81 0x3341c +#define ixDPM_TABLE_82 0x33420 +#define ixDPM_TABLE_83 0x33424 +#define ixDPM_TABLE_84 0x33428 +#define ixDPM_TABLE_85 0x3342c +#define ixDPM_TABLE_86 0x33430 +#define ixDPM_TABLE_87 0x33434 +#define ixDPM_TABLE_88 0x33438 +#define ixDPM_TABLE_89 0x3343c +#define ixDPM_TABLE_90 0x33440 +#define ixDPM_TABLE_91 0x33444 +#define ixDPM_TABLE_92 0x33448 +#define ixDPM_TABLE_93 0x3344c +#define ixDPM_TABLE_94 0x33450 +#define ixDPM_TABLE_95 0x33454 +#define ixDPM_TABLE_96 0x33458 +#define ixDPM_TABLE_97 0x3345c +#define ixDPM_TABLE_98 0x33460 +#define ixDPM_TABLE_99 0x33464 +#define ixDPM_TABLE_100 0x33468 +#define ixDPM_TABLE_101 0x3346c +#define ixDPM_TABLE_102 0x33470 +#define ixDPM_TABLE_103 0x33474 +#define ixDPM_TABLE_104 0x33478 +#define ixDPM_TABLE_105 0x3347c +#define ixDPM_TABLE_106 0x33480 +#define ixDPM_TABLE_107 0x33484 +#define ixDPM_TABLE_108 0x33488 +#define ixDPM_TABLE_109 0x3348c +#define ixDPM_TABLE_110 0x33490 +#define ixDPM_TABLE_111 0x33494 +#define ixDPM_TABLE_112 0x33498 +#define ixDPM_TABLE_113 0x3349c +#define ixDPM_TABLE_114 0x334a0 +#define ixDPM_TABLE_115 0x334a4 +#define ixDPM_TABLE_116 0x334a8 +#define ixDPM_TABLE_117 0x334ac +#define ixDPM_TABLE_118 0x334b0 +#define ixDPM_TABLE_119 0x334b4 +#define ixDPM_TABLE_120 0x334b8 +#define ixDPM_TABLE_121 0x334bc +#define ixDPM_TABLE_122 0x334c0 +#define ixDPM_TABLE_123 0x334c4 +#define ixDPM_TABLE_124 0x334c8 +#define ixDPM_TABLE_125 0x334cc +#define ixDPM_TABLE_126 0x334d0 +#define ixDPM_TABLE_127 0x334d4 +#define ixDPM_TABLE_128 0x334d8 +#define ixDPM_TABLE_129 0x334dc +#define ixDPM_TABLE_130 0x334e0 +#define ixDPM_TABLE_131 0x334e4 +#define ixDPM_TABLE_132 0x334e8 +#define ixDPM_TABLE_133 0x334ec +#define ixDPM_TABLE_134 0x334f0 +#define ixDPM_TABLE_135 0x334f4 +#define ixDPM_TABLE_136 0x334f8 +#define ixDPM_TABLE_137 0x334fc +#define ixDPM_TABLE_138 0x33500 +#define ixDPM_TABLE_139 0x33504 +#define ixDPM_TABLE_140 0x33508 +#define ixDPM_TABLE_141 0x3350c +#define ixDPM_TABLE_142 0x33510 +#define ixDPM_TABLE_143 0x33514 +#define ixDPM_TABLE_144 0x33518 +#define ixDPM_TABLE_145 0x3351c +#define ixDPM_TABLE_146 0x33520 +#define ixDPM_TABLE_147 0x33524 +#define ixDPM_TABLE_148 0x33528 +#define ixDPM_TABLE_149 0x3352c +#define ixDPM_TABLE_150 0x33530 +#define ixDPM_TABLE_151 0x33534 +#define ixDPM_TABLE_152 0x33538 +#define ixDPM_TABLE_153 0x3353c +#define ixDPM_TABLE_154 0x33540 +#define ixDPM_TABLE_155 0x33544 +#define ixDPM_TABLE_156 0x33548 +#define ixDPM_TABLE_157 0x3354c +#define ixDPM_TABLE_158 0x33550 +#define ixDPM_TABLE_159 0x33554 +#define ixDPM_TABLE_160 0x33558 +#define ixDPM_TABLE_161 0x3355c +#define ixDPM_TABLE_162 0x33560 +#define ixDPM_TABLE_163 0x33564 +#define ixDPM_TABLE_164 0x33568 +#define ixDPM_TABLE_165 0x3356c +#define ixDPM_TABLE_166 0x33570 +#define ixDPM_TABLE_167 0x33574 +#define ixDPM_TABLE_168 0x33578 +#define ixDPM_TABLE_169 0x3357c +#define ixDPM_TABLE_170 0x33580 +#define ixDPM_TABLE_171 0x33584 +#define ixDPM_TABLE_172 0x33588 +#define ixDPM_TABLE_173 0x3358c +#define ixDPM_TABLE_174 0x33590 +#define ixDPM_TABLE_175 0x33594 +#define ixDPM_TABLE_176 0x33598 +#define ixDPM_TABLE_177 0x3359c +#define ixDPM_TABLE_178 0x335a0 +#define ixDPM_TABLE_179 0x335a4 +#define ixDPM_TABLE_180 0x335a8 +#define ixDPM_TABLE_181 0x335ac +#define ixDPM_TABLE_182 0x335b0 +#define ixDPM_TABLE_183 0x335b4 +#define ixDPM_TABLE_184 0x335b8 +#define ixDPM_TABLE_185 0x335bc +#define ixDPM_TABLE_186 0x335c0 +#define ixDPM_TABLE_187 0x335c4 +#define ixDPM_TABLE_188 0x335c8 +#define ixDPM_TABLE_189 0x335cc +#define ixDPM_TABLE_190 0x335d0 +#define ixDPM_TABLE_191 0x335d4 +#define ixDPM_TABLE_192 0x335d8 +#define ixDPM_TABLE_193 0x335dc +#define ixDPM_TABLE_194 0x335e0 +#define ixDPM_TABLE_195 0x335e4 +#define ixDPM_TABLE_196 0x335e8 +#define ixDPM_TABLE_197 0x335ec +#define ixDPM_TABLE_198 0x335f0 +#define ixDPM_TABLE_199 0x335f4 +#define ixDPM_TABLE_200 0x335f8 +#define ixDPM_TABLE_201 0x335fc +#define ixDPM_TABLE_202 0x33600 +#define ixDPM_TABLE_203 0x33604 +#define ixDPM_TABLE_204 0x33608 +#define ixDPM_TABLE_205 0x3360c +#define ixDPM_TABLE_206 0x33610 +#define ixDPM_TABLE_207 0x33614 +#define ixDPM_TABLE_208 0x33618 +#define ixDPM_TABLE_209 0x3361c +#define ixDPM_TABLE_210 0x33620 +#define ixDPM_TABLE_211 0x33624 +#define ixDPM_TABLE_212 0x33628 +#define ixDPM_TABLE_213 0x3362c +#define ixDPM_TABLE_214 0x33630 +#define ixDPM_TABLE_215 0x33634 +#define ixDPM_TABLE_216 0x33638 +#define ixDPM_TABLE_217 0x3363c +#define ixDPM_TABLE_218 0x33640 +#define ixDPM_TABLE_219 0x33644 +#define ixDPM_TABLE_220 0x33648 +#define ixDPM_TABLE_221 0x3364c +#define ixDPM_TABLE_222 0x33650 +#define ixDPM_TABLE_223 0x33654 +#define ixDPM_TABLE_224 0x33658 +#define ixDPM_TABLE_225 0x3365c +#define ixDPM_TABLE_226 0x33660 +#define ixDPM_TABLE_227 0x33664 +#define ixDPM_TABLE_228 0x33668 +#define ixDPM_TABLE_229 0x3366c +#define ixDPM_TABLE_230 0x33670 +#define ixDPM_TABLE_231 0x33674 +#define ixDPM_TABLE_232 0x33678 +#define ixDPM_TABLE_233 0x3367c +#define ixDPM_TABLE_234 0x33680 +#define ixDPM_TABLE_235 0x33684 +#define ixDPM_TABLE_236 0x33688 +#define ixDPM_TABLE_237 0x3368c +#define ixDPM_TABLE_238 0x33690 +#define ixDPM_TABLE_239 0x33694 +#define ixDPM_TABLE_240 0x33698 +#define ixDPM_TABLE_241 0x3369c +#define ixDPM_TABLE_242 0x336a0 +#define ixDPM_TABLE_243 0x336a4 +#define ixDPM_TABLE_244 0x336a8 +#define ixDPM_TABLE_245 0x336ac +#define ixDPM_TABLE_246 0x336b0 +#define ixDPM_TABLE_247 0x336b4 +#define ixDPM_TABLE_248 0x336b8 +#define ixDPM_TABLE_249 0x336bc +#define ixDPM_TABLE_250 0x336c0 +#define ixDPM_TABLE_251 0x336c4 +#define ixDPM_TABLE_252 0x336c8 +#define ixDPM_TABLE_253 0x336cc +#define ixDPM_TABLE_254 0x336d0 +#define ixDPM_TABLE_255 0x336d4 +#define ixDPM_TABLE_256 0x336d8 +#define ixDPM_TABLE_257 0x336dc +#define ixDPM_TABLE_258 0x336e0 +#define ixDPM_TABLE_259 0x336e4 +#define ixDPM_TABLE_260 0x336e8 +#define ixDPM_TABLE_261 0x336ec +#define ixDPM_TABLE_262 0x336f0 +#define ixDPM_TABLE_263 0x336f4 +#define ixDPM_TABLE_264 0x336f8 +#define ixDPM_TABLE_265 0x336fc +#define ixDPM_TABLE_266 0x33700 +#define ixDPM_TABLE_267 0x33704 +#define ixDPM_TABLE_268 0x33708 +#define ixDPM_TABLE_269 0x3370c +#define ixDPM_TABLE_270 0x33710 +#define ixDPM_TABLE_271 0x33714 +#define ixDPM_TABLE_272 0x33718 +#define ixDPM_TABLE_273 0x3371c +#define ixDPM_TABLE_274 0x33720 +#define ixDPM_TABLE_275 0x33724 +#define ixDPM_TABLE_276 0x33728 +#define ixDPM_TABLE_277 0x3372c +#define ixDPM_TABLE_278 0x33730 +#define ixDPM_TABLE_279 0x33734 +#define ixDPM_TABLE_280 0x33738 +#define ixDPM_TABLE_281 0x3373c +#define ixDPM_TABLE_282 0x33740 +#define ixDPM_TABLE_283 0x33744 +#define ixDPM_TABLE_284 0x33748 +#define ixDPM_TABLE_285 0x3374c +#define ixDPM_TABLE_286 0x33750 +#define ixDPM_TABLE_287 0x33754 +#define ixDPM_TABLE_288 0x33758 +#define ixDPM_TABLE_289 0x3375c +#define ixDPM_TABLE_290 0x33760 +#define ixDPM_TABLE_291 0x33764 +#define ixDPM_TABLE_292 0x33768 +#define ixDPM_TABLE_293 0x3376c +#define ixDPM_TABLE_294 0x33770 +#define ixDPM_TABLE_295 0x33774 +#define ixDPM_TABLE_296 0x33778 +#define ixDPM_TABLE_297 0x3377c +#define ixDPM_TABLE_298 0x33780 +#define ixDPM_TABLE_299 0x33784 +#define ixDPM_TABLE_300 0x33788 +#define ixDPM_TABLE_301 0x3378c +#define ixDPM_TABLE_302 0x33790 +#define ixDPM_TABLE_303 0x33794 +#define ixDPM_TABLE_304 0x33798 +#define ixDPM_TABLE_305 0x3379c +#define ixDPM_TABLE_306 0x337a0 +#define ixDPM_TABLE_307 0x337a4 +#define ixDPM_TABLE_308 0x337a8 +#define ixDPM_TABLE_309 0x337ac +#define ixDPM_TABLE_310 0x337b0 +#define ixDPM_TABLE_311 0x337b4 +#define ixDPM_TABLE_312 0x337b8 +#define ixDPM_TABLE_313 0x337bc +#define ixDPM_TABLE_314 0x337c0 +#define ixDPM_TABLE_315 0x337c4 +#define ixDPM_TABLE_316 0x337c8 +#define ixDPM_TABLE_317 0x337cc +#define ixDPM_TABLE_318 0x337d0 +#define ixDPM_TABLE_319 0x337d4 +#define ixDPM_TABLE_320 0x337d8 +#define ixDPM_TABLE_321 0x337dc +#define ixDPM_TABLE_322 0x337e0 +#define ixDPM_TABLE_323 0x337e4 +#define ixDPM_TABLE_324 0x337e8 +#define ixDPM_TABLE_325 0x337ec +#define ixDPM_TABLE_326 0x337f0 +#define ixDPM_TABLE_327 0x337f4 +#define ixDPM_TABLE_328 0x337f8 +#define ixDPM_TABLE_329 0x337fc +#define ixDPM_TABLE_330 0x33800 +#define ixDPM_TABLE_331 0x33804 +#define ixDPM_TABLE_332 0x33808 +#define ixDPM_TABLE_333 0x3380c +#define ixDPM_TABLE_334 0x33810 +#define ixDPM_TABLE_335 0x33814 +#define ixDPM_TABLE_336 0x33818 +#define ixDPM_TABLE_337 0x3381c +#define ixDPM_TABLE_338 0x33820 +#define ixDPM_TABLE_339 0x33824 +#define ixDPM_TABLE_340 0x33828 +#define ixDPM_TABLE_341 0x3382c +#define ixDPM_TABLE_342 0x33830 +#define ixDPM_TABLE_343 0x33834 +#define ixDPM_TABLE_344 0x33838 +#define ixDPM_TABLE_345 0x3383c +#define ixDPM_TABLE_346 0x33840 +#define ixDPM_TABLE_347 0x33844 +#define ixDPM_TABLE_348 0x33848 +#define ixDPM_TABLE_349 0x3384c +#define ixDPM_TABLE_350 0x33850 +#define ixDPM_TABLE_351 0x33854 +#define ixDPM_TABLE_352 0x33858 +#define ixDPM_TABLE_353 0x3385c +#define ixDPM_TABLE_354 0x33860 +#define ixDPM_TABLE_355 0x33864 +#define ixDPM_TABLE_356 0x33868 +#define ixDPM_TABLE_357 0x3386c +#define ixDPM_TABLE_358 0x33870 +#define ixDPM_TABLE_359 0x33874 +#define ixDPM_TABLE_360 0x33878 +#define ixDPM_TABLE_361 0x3387c +#define ixDPM_TABLE_362 0x33880 +#define ixDPM_TABLE_363 0x33884 +#define ixDPM_TABLE_364 0x33888 +#define ixDPM_TABLE_365 0x3388c +#define ixDPM_TABLE_366 0x33890 +#define ixDPM_TABLE_367 0x33894 +#define ixDPM_TABLE_368 0x33898 +#define ixDPM_TABLE_369 0x3389c +#define ixDPM_TABLE_370 0x338a0 +#define ixSOFT_REGISTERS_TABLE_1 0x338c8 +#define ixSOFT_REGISTERS_TABLE_2 0x338cc +#define ixSOFT_REGISTERS_TABLE_3 0x338d0 +#define ixSOFT_REGISTERS_TABLE_4 0x338d4 +#define ixSOFT_REGISTERS_TABLE_5 0x338d8 +#define ixSOFT_REGISTERS_TABLE_6 0x338dc +#define ixSOFT_REGISTERS_TABLE_7 0x338e0 +#define ixSOFT_REGISTERS_TABLE_8 0x338e4 +#define ixSOFT_REGISTERS_TABLE_9 0x338e8 +#define ixSOFT_REGISTERS_TABLE_10 0x338ec +#define ixSOFT_REGISTERS_TABLE_11 0x338f0 +#define ixSOFT_REGISTERS_TABLE_12 0x338f4 +#define ixSOFT_REGISTERS_TABLE_13 0x338f8 +#define ixSOFT_REGISTERS_TABLE_14 0x338fc +#define ixSOFT_REGISTERS_TABLE_15 0x33900 +#define ixSOFT_REGISTERS_TABLE_16 0x33904 +#define ixSOFT_REGISTERS_TABLE_17 0x33908 +#define ixSOFT_REGISTERS_TABLE_18 0x3390c +#define ixSOFT_REGISTERS_TABLE_19 0x33910 +#define ixSOFT_REGISTERS_TABLE_20 0x33914 +#define ixSOFT_REGISTERS_TABLE_21 0x33918 +#define ixSOFT_REGISTERS_TABLE_22 0x3391c +#define ixSOFT_REGISTERS_TABLE_23 0x33920 +#define ixSOFT_REGISTERS_TABLE_24 0x33924 +#define ixSOFT_REGISTERS_TABLE_25 0x33928 +#define ixSOFT_REGISTERS_TABLE_26 0x3392c +#define ixSOFT_REGISTERS_TABLE_27 0x33930 +#define ixSOFT_REGISTERS_TABLE_28 0x33934 +#define ixSOFT_REGISTERS_TABLE_29 0x33938 +#define ixFIRMWARE_FLAGS 0x33000 +#define ixTDC_STATUS 0x33004 +#define ixTDC_MV_AVERAGE 0x33008 +#define ixTDC_VRM_LIMIT 0x3300c +#define ixFEATURE_STATUS 0x33010 +#define ixENTITY_TEMPERATURES_1 0x33014 +#define ixPM_FUSES_1 0x3394c +#define ixPM_FUSES_2 0x33950 +#define ixPM_FUSES_3 0x33954 +#define ixPM_FUSES_4 0x33958 +#define ixPM_FUSES_5 0x3395c +#define ixPM_FUSES_6 0x33960 +#define ixPM_FUSES_7 0x33964 +#define ixPM_FUSES_8 0x33968 +#define ixPM_FUSES_9 0x3396c +#define ixPM_FUSES_10 0x33970 +#define ixPM_FUSES_11 0x33974 +#define ixPM_FUSES_12 0x33978 +#define ixPM_FUSES_13 0x3397c +#define ixPM_FUSES_14 0x33980 +#define ixPM_FUSES_15 0x33984 +#define ixPM_FUSES_16 0x33988 +#define ixPM_FUSES_17 0x3398c +#define ixPM_FUSES_18 0x33990 +#define ixPM_FUSES_19 0x33994 +#define ixPM_FUSES_20 0x33998 +#define ixPM_FUSES_21 0x3399c +#define ixSMU_PM_STATUS_0 0x33e00 +#define ixSMU_PM_STATUS_1 0x33e04 +#define ixSMU_PM_STATUS_2 0x33e08 +#define ixSMU_PM_STATUS_3 0x33e0c +#define ixSMU_PM_STATUS_4 0x33e10 +#define ixSMU_PM_STATUS_5 0x33e14 +#define ixSMU_PM_STATUS_6 0x33e18 +#define ixSMU_PM_STATUS_7 0x33e1c +#define ixSMU_PM_STATUS_8 0x33e20 +#define ixSMU_PM_STATUS_9 0x33e24 +#define ixSMU_PM_STATUS_10 0x33e28 +#define ixSMU_PM_STATUS_11 0x33e2c +#define ixSMU_PM_STATUS_12 0x33e30 +#define ixSMU_PM_STATUS_13 0x33e34 +#define ixSMU_PM_STATUS_14 0x33e38 +#define ixSMU_PM_STATUS_15 0x33e3c +#define ixSMU_PM_STATUS_16 0x33e40 +#define ixSMU_PM_STATUS_17 0x33e44 +#define ixSMU_PM_STATUS_18 0x33e48 +#define ixSMU_PM_STATUS_19 0x33e4c +#define ixSMU_PM_STATUS_20 0x33e50 +#define ixSMU_PM_STATUS_21 0x33e54 +#define ixSMU_PM_STATUS_22 0x33e58 +#define ixSMU_PM_STATUS_23 0x33e5c +#define ixSMU_PM_STATUS_24 0x33e60 +#define ixSMU_PM_STATUS_25 0x33e64 +#define ixSMU_PM_STATUS_26 0x33e68 +#define ixSMU_PM_STATUS_27 0x33e6c +#define ixSMU_PM_STATUS_28 0x33e70 +#define ixSMU_PM_STATUS_29 0x33e74 +#define ixSMU_PM_STATUS_30 0x33e78 +#define ixSMU_PM_STATUS_31 0x33e7c +#define ixSMU_PM_STATUS_32 0x33e80 +#define ixSMU_PM_STATUS_33 0x33e84 +#define ixSMU_PM_STATUS_34 0x33e88 +#define ixSMU_PM_STATUS_35 0x33e8c +#define ixSMU_PM_STATUS_36 0x33e90 +#define ixSMU_PM_STATUS_37 0x33e94 +#define ixSMU_PM_STATUS_38 0x33e98 +#define ixSMU_PM_STATUS_39 0x33e9c +#define ixSMU_PM_STATUS_40 0x33ea0 +#define ixSMU_PM_STATUS_41 0x33ea4 +#define ixSMU_PM_STATUS_42 0x33ea8 +#define ixSMU_PM_STATUS_43 0x33eac +#define ixSMU_PM_STATUS_44 0x33eb0 +#define ixSMU_PM_STATUS_45 0x33eb4 +#define ixSMU_PM_STATUS_46 0x33eb8 +#define ixSMU_PM_STATUS_47 0x33ebc +#define ixSMU_PM_STATUS_48 0x33ec0 +#define ixSMU_PM_STATUS_49 0x33ec4 +#define ixSMU_PM_STATUS_50 0x33ec8 +#define ixSMU_PM_STATUS_51 0x33ecc +#define ixSMU_PM_STATUS_52 0x33ed0 +#define ixSMU_PM_STATUS_53 0x33ed4 +#define ixSMU_PM_STATUS_54 0x33ed8 +#define ixSMU_PM_STATUS_55 0x33edc +#define ixSMU_PM_STATUS_56 0x33ee0 +#define ixSMU_PM_STATUS_57 0x33ee4 +#define ixSMU_PM_STATUS_58 0x33ee8 +#define ixSMU_PM_STATUS_59 0x33eec +#define ixSMU_PM_STATUS_60 0x33ef0 +#define ixSMU_PM_STATUS_61 0x33ef4 +#define ixSMU_PM_STATUS_62 0x33ef8 +#define ixSMU_PM_STATUS_63 0x33efc +#define ixSMU_PM_STATUS_64 0x33f00 +#define ixSMU_PM_STATUS_65 0x33f04 +#define ixSMU_PM_STATUS_66 0x33f08 +#define ixSMU_PM_STATUS_67 0x33f0c +#define ixSMU_PM_STATUS_68 0x33f10 +#define ixSMU_PM_STATUS_69 0x33f14 +#define ixSMU_PM_STATUS_70 0x33f18 +#define ixSMU_PM_STATUS_71 0x33f1c +#define ixSMU_PM_STATUS_72 0x33f20 +#define ixSMU_PM_STATUS_73 0x33f24 +#define ixSMU_PM_STATUS_74 0x33f28 +#define ixSMU_PM_STATUS_75 0x33f2c +#define ixSMU_PM_STATUS_76 0x33f30 +#define ixSMU_PM_STATUS_77 0x33f34 +#define ixSMU_PM_STATUS_78 0x33f38 +#define ixSMU_PM_STATUS_79 0x33f3c +#define ixSMU_PM_STATUS_80 0x33f40 +#define ixSMU_PM_STATUS_81 0x33f44 +#define ixSMU_PM_STATUS_82 0x33f48 +#define ixSMU_PM_STATUS_83 0x33f4c +#define ixSMU_PM_STATUS_84 0x33f50 +#define ixSMU_PM_STATUS_85 0x33f54 +#define ixSMU_PM_STATUS_86 0x33f58 +#define ixSMU_PM_STATUS_87 0x33f5c +#define ixSMU_PM_STATUS_88 0x33f60 +#define ixSMU_PM_STATUS_89 0x33f64 +#define ixSMU_PM_STATUS_90 0x33f68 +#define ixSMU_PM_STATUS_91 0x33f6c +#define ixSMU_PM_STATUS_92 0x33f70 +#define ixSMU_PM_STATUS_93 0x33f74 +#define ixSMU_PM_STATUS_94 0x33f78 +#define ixSMU_PM_STATUS_95 0x33f7c +#define ixSMU_PM_STATUS_96 0x33f80 +#define ixSMU_PM_STATUS_97 0x33f84 +#define ixSMU_PM_STATUS_98 0x33f88 +#define ixSMU_PM_STATUS_99 0x33f8c +#define ixSMU_PM_STATUS_100 0x33f90 +#define ixSMU_PM_STATUS_101 0x33f94 +#define ixSMU_PM_STATUS_102 0x33f98 +#define ixSMU_PM_STATUS_103 0x33f9c +#define ixSMU_PM_STATUS_104 0x33fa0 +#define ixSMU_PM_STATUS_105 0x33fa4 +#define ixSMU_PM_STATUS_106 0x33fa8 +#define ixSMU_PM_STATUS_107 0x33fac +#define ixSMU_PM_STATUS_108 0x33fb0 +#define ixSMU_PM_STATUS_109 0x33fb4 +#define ixSMU_PM_STATUS_110 0x33fb8 +#define ixSMU_PM_STATUS_111 0x33fbc +#define ixSMU_PM_STATUS_112 0x33fc0 +#define ixSMU_PM_STATUS_113 0x33fc4 +#define ixSMU_PM_STATUS_114 0x33fc8 +#define ixSMU_PM_STATUS_115 0x33fcc +#define ixSMU_PM_STATUS_116 0x33fd0 +#define ixSMU_PM_STATUS_117 0x33fd4 +#define ixSMU_PM_STATUS_118 0x33fd8 +#define ixSMU_PM_STATUS_119 0x33fdc +#define ixSMU_PM_STATUS_120 0x33fe0 +#define ixSMU_PM_STATUS_121 0x33fe4 +#define ixSMU_PM_STATUS_122 0x33fe8 +#define ixSMU_PM_STATUS_123 0x33fec +#define ixSMU_PM_STATUS_124 0x33ff0 +#define ixSMU_PM_STATUS_125 0x33ff4 +#define ixSMU_PM_STATUS_126 0x33ff8 +#define ixSMU_PM_STATUS_127 0x33ffc +#define ixCG_THERMAL_INT_ENA 0xc2100024 +#define ixCG_THERMAL_INT_CTRL 0xc2100028 +#define ixCG_THERMAL_INT_STATUS 0xc210002c +#define ixCG_THERMAL_CTRL 0xc0300004 +#define ixCG_THERMAL_STATUS 0xc0300008 +#define ixCG_THERMAL_INT 0xc030000c +#define ixCG_MULT_THERMAL_CTRL 0xc0300010 +#define ixCG_MULT_THERMAL_STATUS 0xc0300014 +#define ixCG_FDO_CTRL0 0xc0300064 +#define ixCG_FDO_CTRL1 0xc0300068 +#define ixCG_FDO_CTRL2 0xc030006c +#define ixCG_TACH_CTRL 0xc0300070 +#define ixCG_TACH_STATUS 0xc0300074 +#define ixCC_THM_STRAPS0 0xc0300080 +#define ixTHM_TMON0_RDIL0_DATA 0xc0300100 +#define ixTHM_TMON0_RDIL1_DATA 0xc0300104 +#define ixTHM_TMON0_RDIL2_DATA 0xc0300108 +#define ixTHM_TMON0_RDIL3_DATA 0xc030010c +#define ixTHM_TMON0_RDIL4_DATA 0xc0300110 +#define ixTHM_TMON0_RDIL5_DATA 0xc0300114 +#define ixTHM_TMON0_RDIL6_DATA 0xc0300118 +#define ixTHM_TMON0_RDIL7_DATA 0xc030011c +#define ixTHM_TMON0_RDIL8_DATA 0xc0300120 +#define ixTHM_TMON0_RDIL9_DATA 0xc0300124 +#define ixTHM_TMON0_RDIL10_DATA 0xc0300128 +#define ixTHM_TMON0_RDIL11_DATA 0xc030012c +#define ixTHM_TMON0_RDIL12_DATA 0xc0300130 +#define ixTHM_TMON0_RDIL13_DATA 0xc0300134 +#define ixTHM_TMON0_RDIL14_DATA 0xc0300138 +#define ixTHM_TMON0_RDIL15_DATA 0xc030013c +#define ixTHM_TMON0_RDIR0_DATA 0xc0300140 +#define ixTHM_TMON0_RDIR1_DATA 0xc0300144 +#define ixTHM_TMON0_RDIR2_DATA 0xc0300148 +#define ixTHM_TMON0_RDIR3_DATA 0xc030014c +#define ixTHM_TMON0_RDIR4_DATA 0xc0300150 +#define ixTHM_TMON0_RDIR5_DATA 0xc0300154 +#define ixTHM_TMON0_RDIR6_DATA 0xc0300158 +#define ixTHM_TMON0_RDIR7_DATA 0xc030015c +#define ixTHM_TMON0_RDIR8_DATA 0xc0300160 +#define ixTHM_TMON0_RDIR9_DATA 0xc0300164 +#define ixTHM_TMON0_RDIR10_DATA 0xc0300168 +#define ixTHM_TMON0_RDIR11_DATA 0xc030016c +#define ixTHM_TMON0_RDIR12_DATA 0xc0300170 +#define ixTHM_TMON0_RDIR13_DATA 0xc0300174 +#define ixTHM_TMON0_RDIR14_DATA 0xc0300178 +#define ixTHM_TMON0_RDIR15_DATA 0xc030017c +#define ixTHM_TMON0_INT_DATA 0xc0300300 +#define ixTHM_TMON0_DEBUG 0xc0300310 +#define ixTHM_TMON0_STATUS 0xc0300320 +#define ixGENERAL_PWRMGT 0xc0200000 +#define ixCNB_PWRMGT_CNTL 0xc0200004 +#define ixSCLK_PWRMGT_CNTL 0xc0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 +#define ixPWR_PCC_CONTROL 0xc0200018 +#define ixPWR_PCC_GPIO_SELECT 0xc020001c +#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 +#define ixPLL_TEST_CNTL 0xc020003c +#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 +#define ixCG_DISPLAY_GAP_CNTL 0xc0200060 +#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 +#define ixCG_ACPI_CNTL 0xc0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 +#define ixCG_ULV_PARAMETER 0xc020015c +#define ixSCLK_MIN_DIV 0xc02003ac +#define ixPWR_DISP_TIMER_0_CONTROL 0xc0200390 +#define ixPWR_DISP_TIMER_1_CONTROL 0xc020037c +#define ixPWR_DISP_TIMER_2_CONTROL 0xc02003d0 +#define ixPWR_DISP_TIMER_3_CONTROL 0xc02003d4 +#define ixPWR_DISP_TIMER_4_CONTROL 0xc02003d8 +#define ixPWR_DISP_TIMER_5_CONTROL 0xc02003dc +#define ixPWR_DISP_TIMER_6_CONTROL 0xc02003e0 +#define ixPWR_DISP_TIMER_7_CONTROL 0xc02003e4 +#define ixPWR_DISP_TIMER_8_CONTROL 0xc02003e8 +#define ixPWR_DISP_TIMER_9_CONTROL 0xc02003ec +#define ixPWR_DISP_TIMER_10_CONTROL 0xc02003f0 +#define ixPWR_DISP_TIMER_11_CONTROL 0xc02003f4 +#define ixPWR_DISP_TIMER_12_CONTROL 0xc02003f8 +#define ixPWR_DISP_TIMER_13_CONTROL 0xc02003fc +#define ixPWR_DISP_TIMER_14_CONTROL 0xc0200074 +#define ixPWR_DISP_TIMER_15_CONTROL 0xc0200078 +#define ixPWR_DISP_TIMER_CONTROL2 0xc0200378 +#define ixVDDGFX_IDLE_PARAMETER 0xc020036c +#define ixVDDGFX_IDLE_CONTROL 0xc0200370 +#define ixVDDGFX_IDLE_EXIT 0xc0200374 +#define ixLCAC_MC0_CNTL 0xc0400130 +#define ixLCAC_MC0_OVR_SEL 0xc0400134 +#define ixLCAC_MC0_OVR_VAL 0xc0400138 +#define ixLCAC_MC1_CNTL 0xc040013c +#define ixLCAC_MC1_OVR_SEL 0xc0400140 +#define ixLCAC_MC1_OVR_VAL 0xc0400144 +#define ixLCAC_MC2_CNTL 0xc0400148 +#define ixLCAC_MC2_OVR_SEL 0xc040014c +#define ixLCAC_MC2_OVR_VAL 0xc0400150 +#define ixLCAC_MC3_CNTL 0xc0400154 +#define ixLCAC_MC3_OVR_SEL 0xc0400158 +#define ixLCAC_MC3_OVR_VAL 0xc040015c +#define ixLCAC_CPL_CNTL 0xc0400160 +#define ixLCAC_CPL_OVR_SEL 0xc0400164 +#define ixLCAC_CPL_OVR_VAL 0xc0400168 +#define mmROM_SMC_IND_INDEX 0x80 +#define mmROM0_ROM_SMC_IND_INDEX 0x80 +#define mmROM1_ROM_SMC_IND_INDEX 0x82 +#define mmROM2_ROM_SMC_IND_INDEX 0x84 +#define mmROM3_ROM_SMC_IND_INDEX 0x86 +#define mmROM_SMC_IND_DATA 0x81 +#define mmROM0_ROM_SMC_IND_DATA 0x81 +#define mmROM1_ROM_SMC_IND_DATA 0x83 +#define mmROM2_ROM_SMC_IND_DATA 0x85 +#define mmROM3_ROM_SMC_IND_DATA 0x87 +#define ixROM_CNTL 0xc0600000 +#define ixPAGE_MIRROR_CNTL 0xc0600004 +#define ixROM_STATUS 0xc0600008 +#define ixCGTT_ROM_CLK_CTRL0 0xc060000c +#define ixROM_INDEX 0xc0600010 +#define ixROM_DATA 0xc0600014 +#define ixROM_START 0xc0600018 +#define ixROM_SW_CNTL 0xc060001c +#define ixROM_SW_STATUS 0xc0600020 +#define ixROM_SW_COMMAND 0xc0600024 +#define ixROM_SW_DATA_1 0xc0600028 +#define ixROM_SW_DATA_2 0xc060002c +#define ixROM_SW_DATA_3 0xc0600030 +#define ixROM_SW_DATA_4 0xc0600034 +#define ixROM_SW_DATA_5 0xc0600038 +#define ixROM_SW_DATA_6 0xc060003c +#define ixROM_SW_DATA_7 0xc0600040 +#define ixROM_SW_DATA_8 0xc0600044 +#define ixROM_SW_DATA_9 0xc0600048 +#define ixROM_SW_DATA_10 0xc060004c +#define ixROM_SW_DATA_11 0xc0600050 +#define ixROM_SW_DATA_12 0xc0600054 +#define ixROM_SW_DATA_13 0xc0600058 +#define ixROM_SW_DATA_14 0xc060005c +#define ixROM_SW_DATA_15 0xc0600060 +#define ixROM_SW_DATA_16 0xc0600064 +#define ixROM_SW_DATA_17 0xc0600068 +#define ixROM_SW_DATA_18 0xc060006c +#define ixROM_SW_DATA_19 0xc0600070 +#define ixROM_SW_DATA_20 0xc0600074 +#define ixROM_SW_DATA_21 0xc0600078 +#define ixROM_SW_DATA_22 0xc060007c +#define ixROM_SW_DATA_23 0xc0600080 +#define ixROM_SW_DATA_24 0xc0600084 +#define ixROM_SW_DATA_25 0xc0600088 +#define ixROM_SW_DATA_26 0xc060008c +#define ixROM_SW_DATA_27 0xc0600090 +#define ixROM_SW_DATA_28 0xc0600094 +#define ixROM_SW_DATA_29 0xc0600098 +#define ixROM_SW_DATA_30 0xc060009c +#define ixROM_SW_DATA_31 0xc06000a0 +#define ixROM_SW_DATA_32 0xc06000a4 +#define ixROM_SW_DATA_33 0xc06000a8 +#define ixROM_SW_DATA_34 0xc06000ac +#define ixROM_SW_DATA_35 0xc06000b0 +#define ixROM_SW_DATA_36 0xc06000b4 +#define ixROM_SW_DATA_37 0xc06000b8 +#define ixROM_SW_DATA_38 0xc06000bc +#define ixROM_SW_DATA_39 0xc06000c0 +#define ixROM_SW_DATA_40 0xc06000c4 +#define ixROM_SW_DATA_41 0xc06000c8 +#define ixROM_SW_DATA_42 0xc06000cc +#define ixROM_SW_DATA_43 0xc06000d0 +#define ixROM_SW_DATA_44 0xc06000d4 +#define ixROM_SW_DATA_45 0xc06000d8 +#define ixROM_SW_DATA_46 0xc06000dc +#define ixROM_SW_DATA_47 0xc06000e0 +#define ixROM_SW_DATA_48 0xc06000e4 +#define ixROM_SW_DATA_49 0xc06000e8 +#define ixROM_SW_DATA_50 0xc06000ec +#define ixROM_SW_DATA_51 0xc06000f0 +#define ixROM_SW_DATA_52 0xc06000f4 +#define ixROM_SW_DATA_53 0xc06000f8 +#define ixROM_SW_DATA_54 0xc06000fc +#define ixROM_SW_DATA_55 0xc0600100 +#define ixROM_SW_DATA_56 0xc0600104 +#define ixROM_SW_DATA_57 0xc0600108 +#define ixROM_SW_DATA_58 0xc060010c +#define ixROM_SW_DATA_59 0xc0600110 +#define ixROM_SW_DATA_60 0xc0600114 +#define ixROM_SW_DATA_61 0xc0600118 +#define ixROM_SW_DATA_62 0xc060011c +#define ixROM_SW_DATA_63 0xc0600120 +#define ixROM_SW_DATA_64 0xc0600124 + +#endif /* SMU_7_1_1_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h new file mode 100644 index 000000000000..c1a7aba19223 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h @@ -0,0 +1,1205 @@ +/* + * SMU_7_1_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_1_ENUM_H +#define SMU_7_1_1_ENUM_H + +#define CG_SRBM_START_ADDR 0x600 +#define CG_SRBM_END_ADDR 0x8ff +#define RCU_CCF_DWORDS0 0x80 +#define RCU_CCF_BITS0 0x1000 +#define RCU_CCF_DWORDS1 0x0 +#define RCU_CCF_BITS1 0x0 +#define RCU_SAM_BYTES 0x0 +#define RCU_SAM_RTL_BYTES 0x0 +#define RCU_SMU_BYTES 0x0 +#define RCU_SMU_RTL_BYTES 0x0 +#define SFP_CHAIN_ADDR 0x0 +#define SFP_BYTES 0x80 +#define SFP_SADR 0x180 +#define SFP_EADR 0x1ff +#define SAMU_KEY_CHAIN_ADR 0x0 +#define SAMU_KEY_SADR 0x0 +#define SAMU_KEY_EADR 0x0 +#define SMU_KEY_CHAIN_ADR 0x0 +#define SMU_KEY_SADR 0x0 +#define SMU_KEY_EADR 0x0 +#define SMC_MSG_TEST 0x1 +#define SMC_MSG_PHY_LN_OFF 0x2 +#define SMC_MSG_PHY_LN_ON 0x3 +#define SMC_MSG_DDI_PHY_OFF 0x4 +#define SMC_MSG_DDI_PHY_ON 0x5 +#define SMC_MSG_CASCADE_PLL_OFF 0x6 +#define SMC_MSG_CASCADE_PLL_ON 0x7 +#define SMC_MSG_PWR_OFF_x16 0x8 +#define SMC_MSG_CONFIG_LCLK_DPM 0x9 +#define SMC_MSG_FLUSH_DATA_CACHE 0xa +#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb +#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc +#define SMC_MSG_CONFIG_BAPM 0xd +#define SMC_MSG_CONFIG_TDC_LIMIT 0xe +#define SMC_MSG_CONFIG_LPMx 0xf +#define SMC_MSG_CONFIG_HTC_LIMIT 0x10 +#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11 +#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12 +#define SMC_MSG_CONFIG_TDP_CNTL 0x13 +#define SMC_MSG_EN_PM_CNTL 0x14 +#define SMC_MSG_DIS_PM_CNTL 0x15 +#define SMC_MSG_CONFIG_NBDPM 0x16 +#define SMC_MSG_CONFIG_LOADLINE 0x17 +#define SMC_MSG_ADJUST_LOADLINE 0x18 +#define SMC_MSG_RESET 0x20 +#define SMC_MSG_VOLTAGE 0x25 +#define SMC_VERSION_MAJOR 0x7 +#define SMC_VERSION_MINOR 0x0 +#define SMC_HEADER_SIZE 0x40 +#define ROM_SIGNATURE 0xaa55 +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_uvdu_0 = 0x2, + DBG_CLIENT_BLKID_uvdu_1 = 0x3, + DBG_CLIENT_BLKID_uvdu_2 = 0x4, + DBG_CLIENT_BLKID_uvdu_3 = 0x5, + DBG_CLIENT_BLKID_uvdu_4 = 0x6, + DBG_CLIENT_BLKID_uvdu_5 = 0x7, + DBG_CLIENT_BLKID_uvdu_6 = 0x8, + DBG_CLIENT_BLKID_uvdb_0 = 0x9, + DBG_CLIENT_BLKID_uvdc_0 = 0xa, + DBG_CLIENT_BLKID_uvdc_1 = 0xb, + DBG_CLIENT_BLKID_uvdf_0 = 0xc, + DBG_CLIENT_BLKID_uvdf_1 = 0xd, + DBG_CLIENT_BLKID_uvdm_0 = 0xe, + DBG_CLIENT_BLKID_uvdm_1 = 0xf, + DBG_CLIENT_BLKID_uvdm_2 = 0x10, + DBG_CLIENT_BLKID_uvdm_3 = 0x11, + DBG_CLIENT_BLKID_vcea_0 = 0x12, + DBG_CLIENT_BLKID_vcea_1 = 0x13, + DBG_CLIENT_BLKID_vcea_2 = 0x14, + DBG_CLIENT_BLKID_vcea_3 = 0x15, + DBG_CLIENT_BLKID_vceb_0 = 0x16, + DBG_CLIENT_BLKID_vcec_0 = 0x17, + DBG_CLIENT_BLKID_dco = 0x18, + DBG_CLIENT_BLKID_xdma = 0x19, + DBG_CLIENT_BLKID_dci_pg = 0x1a, + DBG_CLIENT_BLKID_smu_0 = 0x1b, + DBG_CLIENT_BLKID_smu_1 = 0x1c, + DBG_CLIENT_BLKID_smu_2 = 0x1d, + DBG_CLIENT_BLKID_gck = 0x1e, + DBG_CLIENT_BLKID_tmonw0 = 0x1f, + DBG_CLIENT_BLKID_tmonw1 = 0x20, + DBG_CLIENT_BLKID_grbm = 0x21, + DBG_CLIENT_BLKID_rlc = 0x22, + DBG_CLIENT_BLKID_ds0 = 0x23, + DBG_CLIENT_BLKID_cpg_0 = 0x24, + DBG_CLIENT_BLKID_cpg_1 = 0x25, + DBG_CLIENT_BLKID_cpc_0 = 0x26, + DBG_CLIENT_BLKID_cpc_1 = 0x27, + DBG_CLIENT_BLKID_cpf_0 = 0x28, + DBG_CLIENT_BLKID_cpf_1 = 0x29, + DBG_CLIENT_BLKID_scf0 = 0x2a, + DBG_CLIENT_BLKID_scf1 = 0x2b, + DBG_CLIENT_BLKID_scf2 = 0x2c, + DBG_CLIENT_BLKID_scf3 = 0x2d, + DBG_CLIENT_BLKID_pc0 = 0x2e, + DBG_CLIENT_BLKID_pc1 = 0x2f, + DBG_CLIENT_BLKID_pc2 = 0x30, + DBG_CLIENT_BLKID_pc3 = 0x31, + DBG_CLIENT_BLKID_vgt0 = 0x32, + DBG_CLIENT_BLKID_vgt1 = 0x33, + DBG_CLIENT_BLKID_vgt2 = 0x34, + DBG_CLIENT_BLKID_vgt3 = 0x35, + DBG_CLIENT_BLKID_sx00 = 0x36, + DBG_CLIENT_BLKID_sx10 = 0x37, + DBG_CLIENT_BLKID_sx20 = 0x38, + DBG_CLIENT_BLKID_sx30 = 0x39, + DBG_CLIENT_BLKID_cb001 = 0x3a, + DBG_CLIENT_BLKID_cb200 = 0x3b, + DBG_CLIENT_BLKID_cb201 = 0x3c, + DBG_CLIENT_BLKID_cbr0 = 0x3d, + DBG_CLIENT_BLKID_cb000 = 0x3e, + DBG_CLIENT_BLKID_cb101 = 0x3f, + DBG_CLIENT_BLKID_cb300 = 0x40, + DBG_CLIENT_BLKID_cb301 = 0x41, + DBG_CLIENT_BLKID_cbr1 = 0x42, + DBG_CLIENT_BLKID_cb100 = 0x43, + DBG_CLIENT_BLKID_ia0 = 0x44, + DBG_CLIENT_BLKID_ia1 = 0x45, + DBG_CLIENT_BLKID_bci0 = 0x46, + DBG_CLIENT_BLKID_bci1 = 0x47, + DBG_CLIENT_BLKID_bci2 = 0x48, + DBG_CLIENT_BLKID_bci3 = 0x49, + DBG_CLIENT_BLKID_pa0 = 0x4a, + DBG_CLIENT_BLKID_pa1 = 0x4b, + DBG_CLIENT_BLKID_spim0 = 0x4c, + DBG_CLIENT_BLKID_spim1 = 0x4d, + DBG_CLIENT_BLKID_spim2 = 0x4e, + DBG_CLIENT_BLKID_spim3 = 0x4f, + DBG_CLIENT_BLKID_sdma = 0x50, + DBG_CLIENT_BLKID_ih = 0x51, + DBG_CLIENT_BLKID_sem = 0x52, + DBG_CLIENT_BLKID_srbm = 0x53, + DBG_CLIENT_BLKID_hdp = 0x54, + DBG_CLIENT_BLKID_acp_0 = 0x55, + DBG_CLIENT_BLKID_acp_1 = 0x56, + DBG_CLIENT_BLKID_sam = 0x57, + DBG_CLIENT_BLKID_mcc0 = 0x58, + DBG_CLIENT_BLKID_mcc1 = 0x59, + DBG_CLIENT_BLKID_mcc2 = 0x5a, + DBG_CLIENT_BLKID_mcc3 = 0x5b, + DBG_CLIENT_BLKID_mcd0 = 0x5c, + DBG_CLIENT_BLKID_mcd1 = 0x5d, + DBG_CLIENT_BLKID_mcd2 = 0x5e, + DBG_CLIENT_BLKID_mcd3 = 0x5f, + DBG_CLIENT_BLKID_mcb = 0x60, + DBG_CLIENT_BLKID_vmc = 0x61, + DBG_CLIENT_BLKID_gmcon = 0x62, + DBG_CLIENT_BLKID_gdc_0 = 0x63, + DBG_CLIENT_BLKID_gdc_1 = 0x64, + DBG_CLIENT_BLKID_gdc_2 = 0x65, + DBG_CLIENT_BLKID_gdc_3 = 0x66, + DBG_CLIENT_BLKID_gdc_4 = 0x67, + DBG_CLIENT_BLKID_gdc_5 = 0x68, + DBG_CLIENT_BLKID_gdc_6 = 0x69, + DBG_CLIENT_BLKID_gdc_7 = 0x6a, + DBG_CLIENT_BLKID_gdc_8 = 0x6b, + DBG_CLIENT_BLKID_gdc_9 = 0x6c, + DBG_CLIENT_BLKID_gdc_10 = 0x6d, + DBG_CLIENT_BLKID_gdc_11 = 0x6e, + DBG_CLIENT_BLKID_gdc_12 = 0x6f, + DBG_CLIENT_BLKID_gdc_13 = 0x70, + DBG_CLIENT_BLKID_gdc_14 = 0x71, + DBG_CLIENT_BLKID_gdc_15 = 0x72, + DBG_CLIENT_BLKID_gdc_16 = 0x73, + DBG_CLIENT_BLKID_gdc_17 = 0x74, + DBG_CLIENT_BLKID_gdc_18 = 0x75, + DBG_CLIENT_BLKID_gdc_19 = 0x76, + DBG_CLIENT_BLKID_gdc_20 = 0x77, + DBG_CLIENT_BLKID_gdc_21 = 0x78, + DBG_CLIENT_BLKID_gdc_22 = 0x79, + DBG_CLIENT_BLKID_gdc_23 = 0x7a, + DBG_CLIENT_BLKID_gdc_24 = 0x7b, + DBG_CLIENT_BLKID_gdc_25 = 0x7c, + DBG_CLIENT_BLKID_gdc_26 = 0x7d, + DBG_CLIENT_BLKID_gdc_27 = 0x7e, + DBG_CLIENT_BLKID_gdc_28 = 0x7f, + DBG_CLIENT_BLKID_wd = 0x80, + DBG_CLIENT_BLKID_sdma_0 = 0x81, + DBG_CLIENT_BLKID_sdma_1 = 0x82, + DBG_CLIENT_BLKID_sammsp = 0x83, + DBG_CLIENT_BLKID_dci_0 = 0x84, + DBG_CLIENT_BLKID_dccg0_0 = 0x85, + DBG_CLIENT_BLKID_dcfe01_0 = 0x86, + DBG_CLIENT_BLKID_dcfe02_0 = 0x87, + DBG_CLIENT_BLKID_dcfe03_0 = 0x88, + DBG_CLIENT_BLKID_dccg0_1 = 0x89, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; + +#endif /* SMU_7_1_1_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h new file mode 100644 index 000000000000..2c997f7b5d13 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h @@ -0,0 +1,4864 @@ +/* + * SMU_7_1_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_1_SH_MASK_H +#define SMU_7_1_1_SH_MASK_H + +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f +#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 +#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f +#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 +#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f +#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 +#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f +#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d +#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 +#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 +#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 +#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 +#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 +#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 +#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1 +#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1 +#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN_MASK 0x200 +#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN__SHIFT 0x9 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa +#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff +#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 +#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 +#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 +#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 +#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa +#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 +#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_0__SMC_RESP_MASK 0xffff +#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_1__SMC_RESP_MASK 0xffff +#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_2__SMC_RESP_MASK 0xffff +#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_3__SMC_RESP_MASK 0xffff +#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_4__SMC_RESP_MASK 0xffff +#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_5__SMC_RESP_MASK 0xffff +#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_6__SMC_RESP_MASK 0xffff +#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_7__SMC_RESP_MASK 0xffff +#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_8__SMC_RESP_MASK 0xffff +#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_9__SMC_RESP_MASK 0xffff +#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_10__SMC_RESP_MASK 0xffff +#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_11__SMC_RESP_MASK 0xffff +#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 +#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 +#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 +#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 +#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 +#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffff +#define SMC_PC_C__smc_pc_c__SHIFT 0x0 +#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff +#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4 +#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff +#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 +#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff +#define GPIOPAD_A__GPIO_A__SHIFT 0x0 +#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff +#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0 +#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff +#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f +#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff +#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000 +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f +#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6 +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0 +#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff +#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 +#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff +#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 +#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff +#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 +#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 +#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3 +#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 +#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 +#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 +#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa +#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 +#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 +#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 +#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 +#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 +#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 +#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 +#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 +#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 +#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 +#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 +#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 +#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 +#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 +#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 +#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 +#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 +#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 +#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 +#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 +#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 +#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 +#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 +#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000 +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000 +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10 +#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000 +#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13 +#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000 +#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16 +#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000 +#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17 +#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000 +#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18 +#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000 +#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19 +#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000 +#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 +#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc +#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 +#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 +#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 +#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 +#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c +#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 +#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d +#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff +#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 +#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 +#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 +#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 +#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 +#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 +#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 +#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e +#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 +#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a +#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 +#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 +#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6 +#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1 +#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10 +#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4 +#define CC_HARVEST_FUSES__ACP_EXISTS_MASK 0x40 +#define CC_HARVEST_FUSES__ACP_EXISTS__SHIFT 0x6 +#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00 +#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8 +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 +#define SMU_STATUS__SMU_DONE_MASK 0x1 +#define SMU_STATUS__SMU_DONE__SHIFT 0x0 +#define SMU_STATUS__SMU_PASS_MASK 0x2 +#define SMU_STATUS__SMU_PASS__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 +#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 +#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 +#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 +#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 +#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 +#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 +#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 +#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 +#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff +#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 +#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 +#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f +#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff +#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18 +#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff +#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00 +#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8 +#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000 +#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000 +#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18 +#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0 +#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff +#define DPM_TABLE_28__SystemFlags__SHIFT 0x0 +#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff +#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0 +#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff +#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0 +#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff +#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0 +#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff +#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0 +#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff +#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0 +#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff +#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0 +#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff +#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff +#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff +#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff +#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff +#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000 +#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10 +#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff +#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0 +#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00 +#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000 +#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10 +#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff +#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0 +#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00 +#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000 +#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10 +#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff +#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0 +#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00 +#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000 +#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10 +#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff +#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0 +#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00 +#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff +#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff +#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff +#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff +#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff +#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00 +#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff +#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00 +#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff +#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00 +#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff +#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0 +#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff +#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00 +#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000 +#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10 +#define DPM_TABLE_68__MasterDeepSleepControl_MASK 0xff +#define DPM_TABLE_68__MasterDeepSleepControl__SHIFT 0x0 +#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00 +#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8 +#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000 +#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10 +#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000 +#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18 +#define DPM_TABLE_69__Reserved_0_MASK 0xffffffff +#define DPM_TABLE_69__Reserved_0__SHIFT 0x0 +#define DPM_TABLE_70__Reserved_1_MASK 0xffffffff +#define DPM_TABLE_70__Reserved_1__SHIFT 0x0 +#define DPM_TABLE_71__Reserved_2_MASK 0xffffffff +#define DPM_TABLE_71__Reserved_2__SHIFT 0x0 +#define DPM_TABLE_72__Reserved_3_MASK 0xffffffff +#define DPM_TABLE_72__Reserved_3__SHIFT 0x0 +#define DPM_TABLE_73__Reserved_4_MASK 0xffffffff +#define DPM_TABLE_73__Reserved_4__SHIFT 0x0 +#define DPM_TABLE_74__GraphicsLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_74__GraphicsLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel_MASK 0xffff +#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_84__GraphicsLevel_0_SclkDid_MASK 0xff000000 +#define DPM_TABLE_84__GraphicsLevel_0_SclkDid__SHIFT 0x18 +#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle_MASK 0xff +#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_85__GraphicsLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_85__GraphicsLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_85__GraphicsLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_85__GraphicsLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_86__GraphicsLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_86__GraphicsLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel_MASK 0xffff +#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_96__GraphicsLevel_1_SclkDid_MASK 0xff000000 +#define DPM_TABLE_96__GraphicsLevel_1_SclkDid__SHIFT 0x18 +#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle_MASK 0xff +#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_97__GraphicsLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_97__GraphicsLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_97__GraphicsLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_97__GraphicsLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_98__GraphicsLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_98__GraphicsLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel_MASK 0xffff +#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_108__GraphicsLevel_2_SclkDid_MASK 0xff000000 +#define DPM_TABLE_108__GraphicsLevel_2_SclkDid__SHIFT 0x18 +#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle_MASK 0xff +#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_109__GraphicsLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_109__GraphicsLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_109__GraphicsLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_109__GraphicsLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_110__GraphicsLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_110__GraphicsLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel_MASK 0xffff +#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_120__GraphicsLevel_3_SclkDid_MASK 0xff000000 +#define DPM_TABLE_120__GraphicsLevel_3_SclkDid__SHIFT 0x18 +#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle_MASK 0xff +#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_121__GraphicsLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_121__GraphicsLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_121__GraphicsLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_121__GraphicsLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_122__GraphicsLevel_4_MinVddc_MASK 0xffffffff +#define DPM_TABLE_122__GraphicsLevel_4_MinVddc__SHIFT 0x0 +#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel_MASK 0xffff +#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_132__GraphicsLevel_4_SclkDid_MASK 0xff000000 +#define DPM_TABLE_132__GraphicsLevel_4_SclkDid__SHIFT 0x18 +#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle_MASK 0xff +#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_133__GraphicsLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_133__GraphicsLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_133__GraphicsLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_133__GraphicsLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_134__GraphicsLevel_5_MinVddc_MASK 0xffffffff +#define DPM_TABLE_134__GraphicsLevel_5_MinVddc__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel_MASK 0xffff +#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_144__GraphicsLevel_5_SclkDid_MASK 0xff000000 +#define DPM_TABLE_144__GraphicsLevel_5_SclkDid__SHIFT 0x18 +#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle_MASK 0xff +#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_145__GraphicsLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_145__GraphicsLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_145__GraphicsLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_145__GraphicsLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_146__GraphicsLevel_6_MinVddc_MASK 0xffffffff +#define DPM_TABLE_146__GraphicsLevel_6_MinVddc__SHIFT 0x0 +#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel_MASK 0xffff +#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_156__GraphicsLevel_6_SclkDid_MASK 0xff000000 +#define DPM_TABLE_156__GraphicsLevel_6_SclkDid__SHIFT 0x18 +#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle_MASK 0xff +#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_157__GraphicsLevel_6_DownHyst_MASK 0xff0000 +#define DPM_TABLE_157__GraphicsLevel_6_DownHyst__SHIFT 0x10 +#define DPM_TABLE_157__GraphicsLevel_6_UpHyst_MASK 0xff000000 +#define DPM_TABLE_157__GraphicsLevel_6_UpHyst__SHIFT 0x18 +#define DPM_TABLE_158__GraphicsLevel_7_MinVddc_MASK 0xffffffff +#define DPM_TABLE_158__GraphicsLevel_7_MinVddc__SHIFT 0x0 +#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel_MASK 0xffff +#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_168__GraphicsLevel_7_SclkDid_MASK 0xff000000 +#define DPM_TABLE_168__GraphicsLevel_7_SclkDid__SHIFT 0x18 +#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle_MASK 0xff +#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_169__GraphicsLevel_7_DownHyst_MASK 0xff0000 +#define DPM_TABLE_169__GraphicsLevel_7_DownHyst__SHIFT 0x10 +#define DPM_TABLE_169__GraphicsLevel_7_UpHyst_MASK 0xff000000 +#define DPM_TABLE_169__GraphicsLevel_7_UpHyst__SHIFT 0x18 +#define DPM_TABLE_170__MemoryACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_170__MemoryACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_172__MemoryACPILevel_MinVddci_MASK 0xffffffff +#define DPM_TABLE_172__MemoryACPILevel_MinVddci__SHIFT 0x0 +#define DPM_TABLE_173__MemoryACPILevel_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_173__MemoryACPILevel_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_175__MemoryACPILevel_StutterEnable_MASK 0xff +#define DPM_TABLE_175__MemoryACPILevel_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_175__MemoryACPILevel_RttEnable_MASK 0xff00 +#define DPM_TABLE_175__MemoryACPILevel_RttEnable__SHIFT 0x8 +#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity_MASK 0xff +#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_177__MemoryACPILevel_padding_MASK 0xff +#define DPM_TABLE_177__MemoryACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_177__MemoryACPILevel_DownHyst_MASK 0xff0000 +#define DPM_TABLE_177__MemoryACPILevel_DownHyst__SHIFT 0x10 +#define DPM_TABLE_177__MemoryACPILevel_UpHyst_MASK 0xff000000 +#define DPM_TABLE_177__MemoryACPILevel_UpHyst__SHIFT 0x18 +#define DPM_TABLE_178__MemoryACPILevel_padding1_MASK 0xff +#define DPM_TABLE_178__MemoryACPILevel_padding1__SHIFT 0x0 +#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_185__MemoryACPILevel_DllCntl_MASK 0xffffffff +#define DPM_TABLE_185__MemoryACPILevel_DllCntl__SHIFT 0x0 +#define DPM_TABLE_186__MemoryACPILevel_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_186__MemoryACPILevel_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_187__MemoryACPILevel_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_187__MemoryACPILevel_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_188__MemoryLevel_0_MinVddc_MASK 0xffffffff +#define DPM_TABLE_188__MemoryLevel_0_MinVddc__SHIFT 0x0 +#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_190__MemoryLevel_0_MinVddci_MASK 0xffffffff +#define DPM_TABLE_190__MemoryLevel_0_MinVddci__SHIFT 0x0 +#define DPM_TABLE_191__MemoryLevel_0_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_191__MemoryLevel_0_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_193__MemoryLevel_0_StutterEnable_MASK 0xff +#define DPM_TABLE_193__MemoryLevel_0_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_193__MemoryLevel_0_RttEnable_MASK 0xff00 +#define DPM_TABLE_193__MemoryLevel_0_RttEnable__SHIFT 0x8 +#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity_MASK 0xff +#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_195__MemoryLevel_0_padding_MASK 0xff +#define DPM_TABLE_195__MemoryLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_195__MemoryLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_195__MemoryLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_195__MemoryLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_195__MemoryLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_196__MemoryLevel_0_padding1_MASK 0xff +#define DPM_TABLE_196__MemoryLevel_0_padding1__SHIFT 0x0 +#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_203__MemoryLevel_0_DllCntl_MASK 0xffffffff +#define DPM_TABLE_203__MemoryLevel_0_DllCntl__SHIFT 0x0 +#define DPM_TABLE_204__MemoryLevel_0_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_204__MemoryLevel_0_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_205__MemoryLevel_0_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_205__MemoryLevel_0_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_206__MemoryLevel_1_MinVddc_MASK 0xffffffff +#define DPM_TABLE_206__MemoryLevel_1_MinVddc__SHIFT 0x0 +#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_208__MemoryLevel_1_MinVddci_MASK 0xffffffff +#define DPM_TABLE_208__MemoryLevel_1_MinVddci__SHIFT 0x0 +#define DPM_TABLE_209__MemoryLevel_1_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_209__MemoryLevel_1_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_211__MemoryLevel_1_StutterEnable_MASK 0xff +#define DPM_TABLE_211__MemoryLevel_1_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_211__MemoryLevel_1_RttEnable_MASK 0xff00 +#define DPM_TABLE_211__MemoryLevel_1_RttEnable__SHIFT 0x8 +#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity_MASK 0xff +#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_213__MemoryLevel_1_padding_MASK 0xff +#define DPM_TABLE_213__MemoryLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_213__MemoryLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_213__MemoryLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_213__MemoryLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_213__MemoryLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_214__MemoryLevel_1_padding1_MASK 0xff +#define DPM_TABLE_214__MemoryLevel_1_padding1__SHIFT 0x0 +#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_221__MemoryLevel_1_DllCntl_MASK 0xffffffff +#define DPM_TABLE_221__MemoryLevel_1_DllCntl__SHIFT 0x0 +#define DPM_TABLE_222__MemoryLevel_1_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_222__MemoryLevel_1_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_223__MemoryLevel_1_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_223__MemoryLevel_1_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_224__MemoryLevel_2_MinVddc_MASK 0xffffffff +#define DPM_TABLE_224__MemoryLevel_2_MinVddc__SHIFT 0x0 +#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_226__MemoryLevel_2_MinVddci_MASK 0xffffffff +#define DPM_TABLE_226__MemoryLevel_2_MinVddci__SHIFT 0x0 +#define DPM_TABLE_227__MemoryLevel_2_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_227__MemoryLevel_2_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_229__MemoryLevel_2_StutterEnable_MASK 0xff +#define DPM_TABLE_229__MemoryLevel_2_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_229__MemoryLevel_2_RttEnable_MASK 0xff00 +#define DPM_TABLE_229__MemoryLevel_2_RttEnable__SHIFT 0x8 +#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity_MASK 0xff +#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_231__MemoryLevel_2_padding_MASK 0xff +#define DPM_TABLE_231__MemoryLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_231__MemoryLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_231__MemoryLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_231__MemoryLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_231__MemoryLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_232__MemoryLevel_2_padding1_MASK 0xff +#define DPM_TABLE_232__MemoryLevel_2_padding1__SHIFT 0x0 +#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_239__MemoryLevel_2_DllCntl_MASK 0xffffffff +#define DPM_TABLE_239__MemoryLevel_2_DllCntl__SHIFT 0x0 +#define DPM_TABLE_240__MemoryLevel_2_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_240__MemoryLevel_2_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_241__MemoryLevel_2_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_241__MemoryLevel_2_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_242__MemoryLevel_3_MinVddc_MASK 0xffffffff +#define DPM_TABLE_242__MemoryLevel_3_MinVddc__SHIFT 0x0 +#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_244__MemoryLevel_3_MinVddci_MASK 0xffffffff +#define DPM_TABLE_244__MemoryLevel_3_MinVddci__SHIFT 0x0 +#define DPM_TABLE_245__MemoryLevel_3_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_245__MemoryLevel_3_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_3_StutterEnable_MASK 0xff +#define DPM_TABLE_247__MemoryLevel_3_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_3_RttEnable_MASK 0xff00 +#define DPM_TABLE_247__MemoryLevel_3_RttEnable__SHIFT 0x8 +#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity_MASK 0xff +#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_249__MemoryLevel_3_padding_MASK 0xff +#define DPM_TABLE_249__MemoryLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_249__MemoryLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_249__MemoryLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_249__MemoryLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_249__MemoryLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_250__MemoryLevel_3_padding1_MASK 0xff +#define DPM_TABLE_250__MemoryLevel_3_padding1__SHIFT 0x0 +#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_257__MemoryLevel_3_DllCntl_MASK 0xffffffff +#define DPM_TABLE_257__MemoryLevel_3_DllCntl__SHIFT 0x0 +#define DPM_TABLE_258__MemoryLevel_3_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_258__MemoryLevel_3_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_259__MemoryLevel_3_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_259__MemoryLevel_3_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_260__LinkLevel_0_SPC_MASK 0xff +#define DPM_TABLE_260__LinkLevel_0_SPC__SHIFT 0x0 +#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_261__LinkLevel_0_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_261__LinkLevel_0_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_262__LinkLevel_0_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_262__LinkLevel_0_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_263__LinkLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_263__LinkLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_264__LinkLevel_1_SPC_MASK 0xff +#define DPM_TABLE_264__LinkLevel_1_SPC__SHIFT 0x0 +#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_265__LinkLevel_1_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_265__LinkLevel_1_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_266__LinkLevel_1_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_266__LinkLevel_1_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_267__LinkLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_267__LinkLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_268__LinkLevel_2_SPC_MASK 0xff +#define DPM_TABLE_268__LinkLevel_2_SPC__SHIFT 0x0 +#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_269__LinkLevel_2_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_269__LinkLevel_2_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_270__LinkLevel_2_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_270__LinkLevel_2_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_271__LinkLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_271__LinkLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_272__LinkLevel_3_SPC_MASK 0xff +#define DPM_TABLE_272__LinkLevel_3_SPC__SHIFT 0x0 +#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_273__LinkLevel_3_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_273__LinkLevel_3_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_274__LinkLevel_3_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_274__LinkLevel_3_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_275__LinkLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_275__LinkLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_276__LinkLevel_4_SPC_MASK 0xff +#define DPM_TABLE_276__LinkLevel_4_SPC__SHIFT 0x0 +#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_277__LinkLevel_4_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_277__LinkLevel_4_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_278__LinkLevel_4_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_278__LinkLevel_4_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_279__LinkLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_279__LinkLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_280__LinkLevel_5_SPC_MASK 0xff +#define DPM_TABLE_280__LinkLevel_5_SPC__SHIFT 0x0 +#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_281__LinkLevel_5_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_281__LinkLevel_5_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_282__LinkLevel_5_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_282__LinkLevel_5_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_283__LinkLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_283__LinkLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_284__LinkLevel_6_SPC_MASK 0xff +#define DPM_TABLE_284__LinkLevel_6_SPC__SHIFT 0x0 +#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_285__LinkLevel_6_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_285__LinkLevel_6_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_286__LinkLevel_6_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_286__LinkLevel_6_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_287__LinkLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_287__LinkLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_288__LinkLevel_7_SPC_MASK 0xff +#define DPM_TABLE_288__LinkLevel_7_SPC__SHIFT 0x0 +#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_289__LinkLevel_7_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_289__LinkLevel_7_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_290__LinkLevel_7_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_290__LinkLevel_7_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_291__LinkLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_291__LinkLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_292__ACPILevel_Flags_MASK 0xffffffff +#define DPM_TABLE_292__ACPILevel_Flags__SHIFT 0x0 +#define DPM_TABLE_293__ACPILevel_MinVddc_MASK 0xffffffff +#define DPM_TABLE_293__ACPILevel_MinVddc__SHIFT 0x0 +#define DPM_TABLE_294__ACPILevel_MinVddcPhases_MASK 0xffffffff +#define DPM_TABLE_294__ACPILevel_MinVddcPhases__SHIFT 0x0 +#define DPM_TABLE_295__ACPILevel_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_295__ACPILevel_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_296__ACPILevel_padding_MASK 0xff +#define DPM_TABLE_296__ACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_296__ACPILevel_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_296__ACPILevel_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_296__ACPILevel_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_296__ACPILevel_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_296__ACPILevel_SclkDid_MASK 0xff000000 +#define DPM_TABLE_296__ACPILevel_SclkDid__SHIFT 0x18 +#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff +#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0 +#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_303__ACPILevel_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_303__ACPILevel_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_305__SclkStepSize_MASK 0xffffffff +#define DPM_TABLE_305__SclkStepSize__SHIFT 0x0 +#define DPM_TABLE_306__Smio_0_MASK 0xffffffff +#define DPM_TABLE_306__Smio_0__SHIFT 0x0 +#define DPM_TABLE_307__Smio_1_MASK 0xffffffff +#define DPM_TABLE_307__Smio_1__SHIFT 0x0 +#define DPM_TABLE_308__Smio_2_MASK 0xffffffff +#define DPM_TABLE_308__Smio_2__SHIFT 0x0 +#define DPM_TABLE_309__Smio_3_MASK 0xffffffff +#define DPM_TABLE_309__Smio_3__SHIFT 0x0 +#define DPM_TABLE_310__Smio_4_MASK 0xffffffff +#define DPM_TABLE_310__Smio_4__SHIFT 0x0 +#define DPM_TABLE_311__Smio_5_MASK 0xffffffff +#define DPM_TABLE_311__Smio_5__SHIFT 0x0 +#define DPM_TABLE_312__Smio_6_MASK 0xffffffff +#define DPM_TABLE_312__Smio_6__SHIFT 0x0 +#define DPM_TABLE_313__Smio_7_MASK 0xffffffff +#define DPM_TABLE_313__Smio_7__SHIFT 0x0 +#define DPM_TABLE_314__Smio_8_MASK 0xffffffff +#define DPM_TABLE_314__Smio_8__SHIFT 0x0 +#define DPM_TABLE_315__Smio_9_MASK 0xffffffff +#define DPM_TABLE_315__Smio_9__SHIFT 0x0 +#define DPM_TABLE_316__Smio_10_MASK 0xffffffff +#define DPM_TABLE_316__Smio_10__SHIFT 0x0 +#define DPM_TABLE_317__Smio_11_MASK 0xffffffff +#define DPM_TABLE_317__Smio_11__SHIFT 0x0 +#define DPM_TABLE_318__Smio_12_MASK 0xffffffff +#define DPM_TABLE_318__Smio_12__SHIFT 0x0 +#define DPM_TABLE_319__Smio_13_MASK 0xffffffff +#define DPM_TABLE_319__Smio_13__SHIFT 0x0 +#define DPM_TABLE_320__Smio_14_MASK 0xffffffff +#define DPM_TABLE_320__Smio_14__SHIFT 0x0 +#define DPM_TABLE_321__Smio_15_MASK 0xffffffff +#define DPM_TABLE_321__Smio_15__SHIFT 0x0 +#define DPM_TABLE_322__Smio_16_MASK 0xffffffff +#define DPM_TABLE_322__Smio_16__SHIFT 0x0 +#define DPM_TABLE_323__Smio_17_MASK 0xffffffff +#define DPM_TABLE_323__Smio_17__SHIFT 0x0 +#define DPM_TABLE_324__Smio_18_MASK 0xffffffff +#define DPM_TABLE_324__Smio_18__SHIFT 0x0 +#define DPM_TABLE_325__Smio_19_MASK 0xffffffff +#define DPM_TABLE_325__Smio_19__SHIFT 0x0 +#define DPM_TABLE_326__Smio_20_MASK 0xffffffff +#define DPM_TABLE_326__Smio_20__SHIFT 0x0 +#define DPM_TABLE_327__Smio_21_MASK 0xffffffff +#define DPM_TABLE_327__Smio_21__SHIFT 0x0 +#define DPM_TABLE_328__Smio_22_MASK 0xffffffff +#define DPM_TABLE_328__Smio_22__SHIFT 0x0 +#define DPM_TABLE_329__Smio_23_MASK 0xffffffff +#define DPM_TABLE_329__Smio_23__SHIFT 0x0 +#define DPM_TABLE_330__Smio_24_MASK 0xffffffff +#define DPM_TABLE_330__Smio_24__SHIFT 0x0 +#define DPM_TABLE_331__Smio_25_MASK 0xffffffff +#define DPM_TABLE_331__Smio_25__SHIFT 0x0 +#define DPM_TABLE_332__Smio_26_MASK 0xffffffff +#define DPM_TABLE_332__Smio_26__SHIFT 0x0 +#define DPM_TABLE_333__Smio_27_MASK 0xffffffff +#define DPM_TABLE_333__Smio_27__SHIFT 0x0 +#define DPM_TABLE_334__Smio_28_MASK 0xffffffff +#define DPM_TABLE_334__Smio_28__SHIFT 0x0 +#define DPM_TABLE_335__Smio_29_MASK 0xffffffff +#define DPM_TABLE_335__Smio_29__SHIFT 0x0 +#define DPM_TABLE_336__Smio_30_MASK 0xffffffff +#define DPM_TABLE_336__Smio_30__SHIFT 0x0 +#define DPM_TABLE_337__Smio_31_MASK 0xffffffff +#define DPM_TABLE_337__Smio_31__SHIFT 0x0 +#define DPM_TABLE_338__GraphicsInterval_MASK 0xff +#define DPM_TABLE_338__GraphicsInterval__SHIFT 0x0 +#define DPM_TABLE_338__GraphicsThermThrottleEnable_MASK 0xff00 +#define DPM_TABLE_338__GraphicsThermThrottleEnable__SHIFT 0x8 +#define DPM_TABLE_338__GraphicsVoltageChangeEnable_MASK 0xff0000 +#define DPM_TABLE_338__GraphicsVoltageChangeEnable__SHIFT 0x10 +#define DPM_TABLE_338__GraphicsBootLevel_MASK 0xff000000 +#define DPM_TABLE_338__GraphicsBootLevel__SHIFT 0x18 +#define DPM_TABLE_339__TemperatureLimitHigh_MASK 0xffff +#define DPM_TABLE_339__TemperatureLimitHigh__SHIFT 0x0 +#define DPM_TABLE_339__ThermalInterval_MASK 0xff0000 +#define DPM_TABLE_339__ThermalInterval__SHIFT 0x10 +#define DPM_TABLE_339__VoltageInterval_MASK 0xff000000 +#define DPM_TABLE_339__VoltageInterval__SHIFT 0x18 +#define DPM_TABLE_340__MemoryVoltageChangeEnable_MASK 0xff +#define DPM_TABLE_340__MemoryVoltageChangeEnable__SHIFT 0x0 +#define DPM_TABLE_340__MemoryBootLevel_MASK 0xff00 +#define DPM_TABLE_340__MemoryBootLevel__SHIFT 0x8 +#define DPM_TABLE_340__TemperatureLimitLow_MASK 0xffff0000 +#define DPM_TABLE_340__TemperatureLimitLow__SHIFT 0x10 +#define DPM_TABLE_341__padding2_MASK 0xff +#define DPM_TABLE_341__padding2__SHIFT 0x0 +#define DPM_TABLE_341__MergedVddci_MASK 0xff00 +#define DPM_TABLE_341__MergedVddci__SHIFT 0x8 +#define DPM_TABLE_341__MemoryThermThrottleEnable_MASK 0xff0000 +#define DPM_TABLE_341__MemoryThermThrottleEnable__SHIFT 0x10 +#define DPM_TABLE_341__MemoryInterval_MASK 0xff000000 +#define DPM_TABLE_341__MemoryInterval__SHIFT 0x18 +#define DPM_TABLE_342__PhaseResponseTime_MASK 0xffff +#define DPM_TABLE_342__PhaseResponseTime__SHIFT 0x0 +#define DPM_TABLE_342__VoltageResponseTime_MASK 0xffff0000 +#define DPM_TABLE_342__VoltageResponseTime__SHIFT 0x10 +#define DPM_TABLE_343__DTEMode_MASK 0xff +#define DPM_TABLE_343__DTEMode__SHIFT 0x0 +#define DPM_TABLE_343__DTEInterval_MASK 0xff00 +#define DPM_TABLE_343__DTEInterval__SHIFT 0x8 +#define DPM_TABLE_343__PCIeGenInterval_MASK 0xff0000 +#define DPM_TABLE_343__PCIeGenInterval__SHIFT 0x10 +#define DPM_TABLE_343__PCIeBootLinkLevel_MASK 0xff000000 +#define DPM_TABLE_343__PCIeBootLinkLevel__SHIFT 0x18 +#define DPM_TABLE_344__ThermGpio_MASK 0xff +#define DPM_TABLE_344__ThermGpio__SHIFT 0x0 +#define DPM_TABLE_344__AcDcGpio_MASK 0xff00 +#define DPM_TABLE_344__AcDcGpio__SHIFT 0x8 +#define DPM_TABLE_344__VRHotGpio_MASK 0xff0000 +#define DPM_TABLE_344__VRHotGpio__SHIFT 0x10 +#define DPM_TABLE_344__SVI2Enable_MASK 0xff000000 +#define DPM_TABLE_344__SVI2Enable__SHIFT 0x18 +#define DPM_TABLE_345__DisplayCac_MASK 0xffffffff +#define DPM_TABLE_345__DisplayCac__SHIFT 0x0 +#define DPM_TABLE_346__NomPwr_MASK 0xffff +#define DPM_TABLE_346__NomPwr__SHIFT 0x0 +#define DPM_TABLE_346__MaxPwr_MASK 0xffff0000 +#define DPM_TABLE_346__MaxPwr__SHIFT 0x10 +#define DPM_TABLE_347__FpsLowThreshold_MASK 0xffff +#define DPM_TABLE_347__FpsLowThreshold__SHIFT 0x0 +#define DPM_TABLE_347__FpsHighThreshold_MASK 0xffff0000 +#define DPM_TABLE_347__FpsHighThreshold__SHIFT 0x10 +#define DPM_TABLE_348__BAPMTI_R_0_1_0_MASK 0xffff +#define DPM_TABLE_348__BAPMTI_R_0_1_0__SHIFT 0x0 +#define DPM_TABLE_348__BAPMTI_R_0_0_0_MASK 0xffff0000 +#define DPM_TABLE_348__BAPMTI_R_0_0_0__SHIFT 0x10 +#define DPM_TABLE_349__BAPMTI_R_1_0_0_MASK 0xffff +#define DPM_TABLE_349__BAPMTI_R_1_0_0__SHIFT 0x0 +#define DPM_TABLE_349__BAPMTI_R_0_2_0_MASK 0xffff0000 +#define DPM_TABLE_349__BAPMTI_R_0_2_0__SHIFT 0x10 +#define DPM_TABLE_350__BAPMTI_R_1_2_0_MASK 0xffff +#define DPM_TABLE_350__BAPMTI_R_1_2_0__SHIFT 0x0 +#define DPM_TABLE_350__BAPMTI_R_1_1_0_MASK 0xffff0000 +#define DPM_TABLE_350__BAPMTI_R_1_1_0__SHIFT 0x10 +#define DPM_TABLE_351__BAPMTI_R_2_1_0_MASK 0xffff +#define DPM_TABLE_351__BAPMTI_R_2_1_0__SHIFT 0x0 +#define DPM_TABLE_351__BAPMTI_R_2_0_0_MASK 0xffff0000 +#define DPM_TABLE_351__BAPMTI_R_2_0_0__SHIFT 0x10 +#define DPM_TABLE_352__BAPMTI_R_3_0_0_MASK 0xffff +#define DPM_TABLE_352__BAPMTI_R_3_0_0__SHIFT 0x0 +#define DPM_TABLE_352__BAPMTI_R_2_2_0_MASK 0xffff0000 +#define DPM_TABLE_352__BAPMTI_R_2_2_0__SHIFT 0x10 +#define DPM_TABLE_353__BAPMTI_R_3_2_0_MASK 0xffff +#define DPM_TABLE_353__BAPMTI_R_3_2_0__SHIFT 0x0 +#define DPM_TABLE_353__BAPMTI_R_3_1_0_MASK 0xffff0000 +#define DPM_TABLE_353__BAPMTI_R_3_1_0__SHIFT 0x10 +#define DPM_TABLE_354__BAPMTI_R_4_1_0_MASK 0xffff +#define DPM_TABLE_354__BAPMTI_R_4_1_0__SHIFT 0x0 +#define DPM_TABLE_354__BAPMTI_R_4_0_0_MASK 0xffff0000 +#define DPM_TABLE_354__BAPMTI_R_4_0_0__SHIFT 0x10 +#define DPM_TABLE_355__BAPMTI_RC_0_0_0_MASK 0xffff +#define DPM_TABLE_355__BAPMTI_RC_0_0_0__SHIFT 0x0 +#define DPM_TABLE_355__BAPMTI_R_4_2_0_MASK 0xffff0000 +#define DPM_TABLE_355__BAPMTI_R_4_2_0__SHIFT 0x10 +#define DPM_TABLE_356__BAPMTI_RC_0_2_0_MASK 0xffff +#define DPM_TABLE_356__BAPMTI_RC_0_2_0__SHIFT 0x0 +#define DPM_TABLE_356__BAPMTI_RC_0_1_0_MASK 0xffff0000 +#define DPM_TABLE_356__BAPMTI_RC_0_1_0__SHIFT 0x10 +#define DPM_TABLE_357__BAPMTI_RC_1_1_0_MASK 0xffff +#define DPM_TABLE_357__BAPMTI_RC_1_1_0__SHIFT 0x0 +#define DPM_TABLE_357__BAPMTI_RC_1_0_0_MASK 0xffff0000 +#define DPM_TABLE_357__BAPMTI_RC_1_0_0__SHIFT 0x10 +#define DPM_TABLE_358__BAPMTI_RC_2_0_0_MASK 0xffff +#define DPM_TABLE_358__BAPMTI_RC_2_0_0__SHIFT 0x0 +#define DPM_TABLE_358__BAPMTI_RC_1_2_0_MASK 0xffff0000 +#define DPM_TABLE_358__BAPMTI_RC_1_2_0__SHIFT 0x10 +#define DPM_TABLE_359__BAPMTI_RC_2_2_0_MASK 0xffff +#define DPM_TABLE_359__BAPMTI_RC_2_2_0__SHIFT 0x0 +#define DPM_TABLE_359__BAPMTI_RC_2_1_0_MASK 0xffff0000 +#define DPM_TABLE_359__BAPMTI_RC_2_1_0__SHIFT 0x10 +#define DPM_TABLE_360__BAPMTI_RC_3_1_0_MASK 0xffff +#define DPM_TABLE_360__BAPMTI_RC_3_1_0__SHIFT 0x0 +#define DPM_TABLE_360__BAPMTI_RC_3_0_0_MASK 0xffff0000 +#define DPM_TABLE_360__BAPMTI_RC_3_0_0__SHIFT 0x10 +#define DPM_TABLE_361__BAPMTI_RC_4_0_0_MASK 0xffff +#define DPM_TABLE_361__BAPMTI_RC_4_0_0__SHIFT 0x0 +#define DPM_TABLE_361__BAPMTI_RC_3_2_0_MASK 0xffff0000 +#define DPM_TABLE_361__BAPMTI_RC_3_2_0__SHIFT 0x10 +#define DPM_TABLE_362__BAPMTI_RC_4_2_0_MASK 0xffff +#define DPM_TABLE_362__BAPMTI_RC_4_2_0__SHIFT 0x0 +#define DPM_TABLE_362__BAPMTI_RC_4_1_0_MASK 0xffff0000 +#define DPM_TABLE_362__BAPMTI_RC_4_1_0__SHIFT 0x10 +#define DPM_TABLE_363__GpuTjHyst_MASK 0xff +#define DPM_TABLE_363__GpuTjHyst__SHIFT 0x0 +#define DPM_TABLE_363__GpuTjMax_MASK 0xff00 +#define DPM_TABLE_363__GpuTjMax__SHIFT 0x8 +#define DPM_TABLE_363__DTETjOffset_MASK 0xff0000 +#define DPM_TABLE_363__DTETjOffset__SHIFT 0x10 +#define DPM_TABLE_363__DTEAmbientTempBase_MASK 0xff000000 +#define DPM_TABLE_363__DTEAmbientTempBase__SHIFT 0x18 +#define DPM_TABLE_364__BootVddci_MASK 0xffff +#define DPM_TABLE_364__BootVddci__SHIFT 0x0 +#define DPM_TABLE_364__BootVddc_MASK 0xffff0000 +#define DPM_TABLE_364__BootVddc__SHIFT 0x10 +#define DPM_TABLE_365__padding_MASK 0xffff +#define DPM_TABLE_365__padding__SHIFT 0x0 +#define DPM_TABLE_365__BootMVdd_MASK 0xffff0000 +#define DPM_TABLE_365__BootMVdd__SHIFT 0x10 +#define DPM_TABLE_366__BAPM_TEMP_GRADIENT_MASK 0xffffffff +#define DPM_TABLE_366__BAPM_TEMP_GRADIENT__SHIFT 0x0 +#define DPM_TABLE_367__LowSclkInterruptThreshold_MASK 0xffffffff +#define DPM_TABLE_367__LowSclkInterruptThreshold__SHIFT 0x0 +#define DPM_TABLE_368__VddGfxReChkWait_MASK 0xffffffff +#define DPM_TABLE_368__VddGfxReChkWait__SHIFT 0x0 +#define DPM_TABLE_369__PPM_TemperatureLimit_MASK 0xffff +#define DPM_TABLE_369__PPM_TemperatureLimit__SHIFT 0x0 +#define DPM_TABLE_369__PPM_PkgPwrLimit_MASK 0xffff0000 +#define DPM_TABLE_369__PPM_PkgPwrLimit__SHIFT 0x10 +#define DPM_TABLE_370__TargetTdp_MASK 0xffff +#define DPM_TABLE_370__TargetTdp__SHIFT 0x0 +#define DPM_TABLE_370__DefaultTdp_MASK 0xffff0000 +#define DPM_TABLE_370__DefaultTdp__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_25__UlvEnterCount_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_25__UlvEnterCount__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_26__UlvTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_26__UlvTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_28__Reserved_0_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_28__Reserved_0__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_29__Reserved_1_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_29__Reserved_1__SHIFT 0x0 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe +#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 +#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 +#define TDC_STATUS__VDD_Boost_MASK 0xff +#define TDC_STATUS__VDD_Boost__SHIFT 0x0 +#define TDC_STATUS__VDD_Throttle_MASK 0xff00 +#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 +#define TDC_STATUS__VDDC_Boost_MASK 0xff0000 +#define TDC_STATUS__VDDC_Boost__SHIFT 0x10 +#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000 +#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18 +#define TDC_MV_AVERAGE__IDD_MASK 0xffff +#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 +#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000 +#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10 +#define TDC_VRM_LIMIT__IDD_MASK 0xffff +#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 +#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000 +#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10 +#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 +#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 +#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 +#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 +#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 +#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 +#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 +#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 +#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 +#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 +#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x20 +#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x5 +#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x40 +#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x6 +#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 +#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 +#define FEATURE_STATUS__BAPM_ON_MASK 0x100 +#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 +#define FEATURE_STATUS__LPMX_ON_MASK 0x200 +#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 +#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 +#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa +#define FEATURE_STATUS__LHTC_ON_MASK 0x800 +#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb +#define FEATURE_STATUS__VPC_ON_MASK 0x1000 +#define FEATURE_STATUS__VPC_ON__SHIFT 0xc +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd +#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 +#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe +#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 +#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf +#define FEATURE_STATUS__AVS_ON_MASK 0x10000 +#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 +#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 +#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 +#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 +#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 +#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 +#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 +#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 +#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 +#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 +#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 +#define FEATURE_STATUS__RESERVED_MASK 0xffc00000 +#define FEATURE_STATUS__RESERVED__SHIFT 0x16 +#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff +#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff +#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0 +#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00 +#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8 +#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000 +#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10 +#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000 +#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18 +#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff +#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0 +#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00 +#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8 +#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000 +#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10 +#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000 +#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18 +#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff +#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0 +#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00 +#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8 +#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000 +#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10 +#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000 +#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18 +#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff +#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0 +#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00 +#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8 +#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000 +#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10 +#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000 +#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18 +#define PM_FUSES_5__VddCVid_3_MASK 0xff +#define PM_FUSES_5__VddCVid_3__SHIFT 0x0 +#define PM_FUSES_5__VddCVid_2_MASK 0xff00 +#define PM_FUSES_5__VddCVid_2__SHIFT 0x8 +#define PM_FUSES_5__VddCVid_1_MASK 0xff0000 +#define PM_FUSES_5__VddCVid_1__SHIFT 0x10 +#define PM_FUSES_5__VddCVid_0_MASK 0xff000000 +#define PM_FUSES_5__VddCVid_0__SHIFT 0x18 +#define PM_FUSES_6__VddCVid_7_MASK 0xff +#define PM_FUSES_6__VddCVid_7__SHIFT 0x0 +#define PM_FUSES_6__VddCVid_6_MASK 0xff00 +#define PM_FUSES_6__VddCVid_6__SHIFT 0x8 +#define PM_FUSES_6__VddCVid_5_MASK 0xff0000 +#define PM_FUSES_6__VddCVid_5__SHIFT 0x10 +#define PM_FUSES_6__VddCVid_4_MASK 0xff000000 +#define PM_FUSES_6__VddCVid_4__SHIFT 0x18 +#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff +#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0 +#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00 +#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8 +#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000 +#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10 +#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000 +#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18 +#define PM_FUSES_8__TDC_MAWt_MASK 0xff +#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00 +#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8 +#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000 +#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10 +#define PM_FUSES_9__Reserved_MASK 0xff +#define PM_FUSES_9__Reserved__SHIFT 0x0 +#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00 +#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8 +#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000 +#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10 +#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000 +#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18 +#define PM_FUSES_10__LPMLTemperatureScaler_3_MASK 0xff +#define PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT 0x0 +#define PM_FUSES_10__LPMLTemperatureScaler_2_MASK 0xff00 +#define PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT 0x8 +#define PM_FUSES_10__LPMLTemperatureScaler_1_MASK 0xff0000 +#define PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT 0x10 +#define PM_FUSES_10__LPMLTemperatureScaler_0_MASK 0xff000000 +#define PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT 0x18 +#define PM_FUSES_11__LPMLTemperatureScaler_7_MASK 0xff +#define PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT 0x0 +#define PM_FUSES_11__LPMLTemperatureScaler_6_MASK 0xff00 +#define PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT 0x8 +#define PM_FUSES_11__LPMLTemperatureScaler_5_MASK 0xff0000 +#define PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT 0x10 +#define PM_FUSES_11__LPMLTemperatureScaler_4_MASK 0xff000000 +#define PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT 0x18 +#define PM_FUSES_12__LPMLTemperatureScaler_11_MASK 0xff +#define PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT 0x0 +#define PM_FUSES_12__LPMLTemperatureScaler_10_MASK 0xff00 +#define PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT 0x8 +#define PM_FUSES_12__LPMLTemperatureScaler_9_MASK 0xff0000 +#define PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT 0x10 +#define PM_FUSES_12__LPMLTemperatureScaler_8_MASK 0xff000000 +#define PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT 0x18 +#define PM_FUSES_13__LPMLTemperatureScaler_15_MASK 0xff +#define PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT 0x0 +#define PM_FUSES_13__LPMLTemperatureScaler_14_MASK 0xff00 +#define PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT 0x8 +#define PM_FUSES_13__LPMLTemperatureScaler_13_MASK 0xff0000 +#define PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT 0x10 +#define PM_FUSES_13__LPMLTemperatureScaler_12_MASK 0xff000000 +#define PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT 0x18 +#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta_MASK 0xffff +#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0 +#define PM_FUSES_14__FuzzyFan_ErrorSetDelta_MASK 0xffff0000 +#define PM_FUSES_14__FuzzyFan_ErrorSetDelta__SHIFT 0x10 +#define PM_FUSES_15__Reserved6_MASK 0xffff +#define PM_FUSES_15__Reserved6__SHIFT 0x0 +#define PM_FUSES_15__FuzzyFan_PwmSetDelta_MASK 0xffff0000 +#define PM_FUSES_15__FuzzyFan_PwmSetDelta__SHIFT 0x10 +#define PM_FUSES_16__GnbLPML_3_MASK 0xff +#define PM_FUSES_16__GnbLPML_3__SHIFT 0x0 +#define PM_FUSES_16__GnbLPML_2_MASK 0xff00 +#define PM_FUSES_16__GnbLPML_2__SHIFT 0x8 +#define PM_FUSES_16__GnbLPML_1_MASK 0xff0000 +#define PM_FUSES_16__GnbLPML_1__SHIFT 0x10 +#define PM_FUSES_16__GnbLPML_0_MASK 0xff000000 +#define PM_FUSES_16__GnbLPML_0__SHIFT 0x18 +#define PM_FUSES_17__GnbLPML_7_MASK 0xff +#define PM_FUSES_17__GnbLPML_7__SHIFT 0x0 +#define PM_FUSES_17__GnbLPML_6_MASK 0xff00 +#define PM_FUSES_17__GnbLPML_6__SHIFT 0x8 +#define PM_FUSES_17__GnbLPML_5_MASK 0xff0000 +#define PM_FUSES_17__GnbLPML_5__SHIFT 0x10 +#define PM_FUSES_17__GnbLPML_4_MASK 0xff000000 +#define PM_FUSES_17__GnbLPML_4__SHIFT 0x18 +#define PM_FUSES_18__GnbLPML_11_MASK 0xff +#define PM_FUSES_18__GnbLPML_11__SHIFT 0x0 +#define PM_FUSES_18__GnbLPML_10_MASK 0xff00 +#define PM_FUSES_18__GnbLPML_10__SHIFT 0x8 +#define PM_FUSES_18__GnbLPML_9_MASK 0xff0000 +#define PM_FUSES_18__GnbLPML_9__SHIFT 0x10 +#define PM_FUSES_18__GnbLPML_8_MASK 0xff000000 +#define PM_FUSES_18__GnbLPML_8__SHIFT 0x18 +#define PM_FUSES_19__GnbLPML_15_MASK 0xff +#define PM_FUSES_19__GnbLPML_15__SHIFT 0x0 +#define PM_FUSES_19__GnbLPML_14_MASK 0xff00 +#define PM_FUSES_19__GnbLPML_14__SHIFT 0x8 +#define PM_FUSES_19__GnbLPML_13_MASK 0xff0000 +#define PM_FUSES_19__GnbLPML_13__SHIFT 0x10 +#define PM_FUSES_19__GnbLPML_12_MASK 0xff000000 +#define PM_FUSES_19__GnbLPML_12__SHIFT 0x18 +#define PM_FUSES_20__Reserved1_1_MASK 0xff +#define PM_FUSES_20__Reserved1_1__SHIFT 0x0 +#define PM_FUSES_20__Reserved1_0_MASK 0xff00 +#define PM_FUSES_20__Reserved1_0__SHIFT 0x8 +#define PM_FUSES_20__GnbLPMLMinVid_MASK 0xff0000 +#define PM_FUSES_20__GnbLPMLMinVid__SHIFT 0x10 +#define PM_FUSES_20__GnbLPMLMaxVid_MASK 0xff000000 +#define PM_FUSES_20__GnbLPMLMaxVid__SHIFT 0x18 +#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd_MASK 0xffff +#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd__SHIFT 0x0 +#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000 +#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd__SHIFT 0x10 +#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_52__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0 +#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8 +#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3 +#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0 +#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4 +#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000 +#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe +#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000 +#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19 +#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000 +#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a +#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff +#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 +#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000 +#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11 +#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000 +#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12 +#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff +#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0 +#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00 +#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8 +#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000 +#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10 +#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000 +#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18 +#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf +#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 +#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0 +#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 +#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000 +#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 +#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff +#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 +#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff +#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 +#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00 +#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL1__M_MASK 0xff0000 +#define CG_FDO_CTRL1__M__SHIFT 0x10 +#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000 +#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 +#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000 +#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e +#define CG_FDO_CTRL2__TMIN_MASK 0xff +#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 +#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800 +#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb +#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000 +#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe +#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000 +#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 +#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7 +#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 +#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8 +#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 +#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff +#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 +#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe +#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1 +#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00 +#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11 +#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000 +#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12 +#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000 +#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18 +#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000 +#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19 +#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000 +#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a +#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000 +#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b +#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000 +#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c +#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000 +#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d +#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000 +#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_INT_DATA__Z_MASK 0x7ff +#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON0_INT_DATA__VALID_MASK 0x800 +#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 +#define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f +#define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0 +#define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20 +#define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1 +#define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0 +#define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff +#define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf +#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 +#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 +#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 +#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 +#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 +#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf +#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 +#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK 0x40000000 +#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT__SHIFT 0x1e +#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff +#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2 +#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1 +#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4 +#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10 +#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000 +#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a +#define ROM_STATUS__ROM_BUSY_MASK 0x1 +#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf +#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define ROM_INDEX__ROM_INDEX_MASK 0xffffff +#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 +#define ROM_DATA__ROM_DATA_MASK 0xffffffff +#define ROM_DATA__ROM_DATA__SHIFT 0x0 +#define ROM_START__ROM_START_MASK 0xffffff +#define ROM_START__ROM_START__SHIFT 0x0 +#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff +#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 +#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000 +#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 +#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1 +#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 +#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 + +#endif /* SMU_7_1_1_SH_MASK_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h new file mode 100644 index 000000000000..933917479985 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h @@ -0,0 +1,1273 @@ +/* + * SMU_7_1_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_2_D_H +#define SMU_7_1_2_D_H + +#define mmGCK_SMC_IND_INDEX 0x80 +#define mmGCK0_GCK_SMC_IND_INDEX 0x80 +#define mmGCK1_GCK_SMC_IND_INDEX 0x82 +#define mmGCK2_GCK_SMC_IND_INDEX 0x84 +#define mmGCK3_GCK_SMC_IND_INDEX 0x86 +#define mmGCK_SMC_IND_DATA 0x81 +#define mmGCK0_GCK_SMC_IND_DATA 0x81 +#define mmGCK1_GCK_SMC_IND_DATA 0x83 +#define mmGCK2_GCK_SMC_IND_DATA 0x85 +#define mmGCK3_GCK_SMC_IND_DATA 0x87 +#define ixCG_DCLK_CNTL 0xc050009c +#define ixCG_DCLK_STATUS 0xc05000a0 +#define ixCG_VCLK_CNTL 0xc05000a4 +#define ixCG_VCLK_STATUS 0xc05000a8 +#define ixCG_ECLK_CNTL 0xc05000ac +#define ixCG_ECLK_STATUS 0xc05000b0 +#define ixCG_ACLK_CNTL 0xc05000dc +#define ixGCK_DFS_BYPASS_CNTL 0xc0500118 +#define ixCG_SPLL_FUNC_CNTL 0xc0500140 +#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 +#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 +#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c +#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 +#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 +#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 +#define ixSPLL_CNTL_MODE 0xc0500160 +#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 +#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 +#define ixMPLL_BYPASSCLK_SEL 0xc050019c +#define ixCG_CLKPIN_CNTL 0xc05001a0 +#define ixCG_CLKPIN_CNTL_2 0xc05001a4 +#define ixCG_CLKPIN_CNTL_DC 0xc0500204 +#define ixTHM_CLK_CNTL 0xc05001a8 +#define ixMISC_CLK_CTRL 0xc05001ac +#define ixGCK_PLL_TEST_CNTL 0xc05001c0 +#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 +#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 +#define mmSMC_IND_INDEX 0x80 +#define mmSMC0_SMC_IND_INDEX 0x80 +#define mmSMC1_SMC_IND_INDEX 0x82 +#define mmSMC2_SMC_IND_INDEX 0x84 +#define mmSMC3_SMC_IND_INDEX 0x86 +#define mmSMC_IND_DATA 0x81 +#define mmSMC0_SMC_IND_DATA 0x81 +#define mmSMC1_SMC_IND_DATA 0x83 +#define mmSMC2_SMC_IND_DATA 0x85 +#define mmSMC3_SMC_IND_DATA 0x87 +#define mmSMC_IND_INDEX_0 0x80 +#define mmSMC_IND_DATA_0 0x81 +#define mmSMC_IND_INDEX_1 0x82 +#define mmSMC_IND_DATA_1 0x83 +#define mmSMC_IND_INDEX_2 0x84 +#define mmSMC_IND_DATA_2 0x85 +#define mmSMC_IND_INDEX_3 0x86 +#define mmSMC_IND_DATA_3 0x87 +#define mmSMC_IND_INDEX_4 0x88 +#define mmSMC_IND_DATA_4 0x89 +#define mmSMC_IND_INDEX_5 0x8a +#define mmSMC_IND_DATA_5 0x8b +#define mmSMC_IND_INDEX_6 0x8c +#define mmSMC_IND_DATA_6 0x8d +#define mmSMC_IND_INDEX_7 0x8e +#define mmSMC_IND_DATA_7 0x8f +#define mmSMC_IND_ACCESS_CNTL 0x92 +#define mmSMC_MESSAGE_0 0x94 +#define mmSMC_RESP_0 0x95 +#define mmSMC_MESSAGE_1 0x96 +#define mmSMC_RESP_1 0x97 +#define mmSMC_MESSAGE_2 0x98 +#define mmSMC_RESP_2 0x99 +#define mmSMC_MESSAGE_3 0x9a +#define mmSMC_RESP_3 0x9b +#define mmSMC_MESSAGE_4 0x9c +#define mmSMC_RESP_4 0x9d +#define mmSMC_MESSAGE_5 0x9e +#define mmSMC_RESP_5 0x9f +#define mmSMC_MESSAGE_6 0xa0 +#define mmSMC_RESP_6 0xa1 +#define mmSMC_MESSAGE_7 0xa2 +#define mmSMC_RESP_7 0xa3 +#define mmSMC_MSG_ARG_0 0xa4 +#define mmSMC_MSG_ARG_1 0xa5 +#define mmSMC_MSG_ARG_2 0xa6 +#define mmSMC_MSG_ARG_3 0xa7 +#define mmSMC_MSG_ARG_4 0xa8 +#define mmSMC_MSG_ARG_5 0xa9 +#define mmSMC_MSG_ARG_6 0xaa +#define mmSMC_MSG_ARG_7 0xab +#define mmSMC_MESSAGE_8 0xb5 +#define mmSMC_RESP_8 0xb6 +#define mmSMC_MESSAGE_9 0xb7 +#define mmSMC_RESP_9 0xb8 +#define mmSMC_MESSAGE_10 0xb9 +#define mmSMC_RESP_10 0xba +#define mmSMC_MESSAGE_11 0xbb +#define mmSMC_RESP_11 0xbc +#define mmSMC_MSG_ARG_8 0xbd +#define mmSMC_MSG_ARG_9 0xbe +#define mmSMC_MSG_ARG_10 0xbf +#define mmSMC_MSG_ARG_11 0x93 +#define ixSMC_SYSCON_RESET_CNTL 0x80000000 +#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 +#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 +#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c +#define ixSMC_SYSCON_MISC_CNTL 0x80000010 +#define ixSMC_SYSCON_MSG_ARG_0 0x80000068 +#define ixSMC_PC_C 0x80000370 +#define ixSMC_SCRATCH9 0x80000424 +#define mmGPIOPAD_SW_INT_STAT 0x180 +#define mmGPIOPAD_STRENGTH 0x181 +#define mmGPIOPAD_MASK 0x182 +#define mmGPIOPAD_A 0x183 +#define mmGPIOPAD_EN 0x184 +#define mmGPIOPAD_Y 0x185 +#define mmGPIOPAD_PINSTRAPS 0x186 +#define mmGPIOPAD_INT_STAT_EN 0x187 +#define mmGPIOPAD_INT_STAT 0x188 +#define mmGPIOPAD_INT_STAT_AK 0x189 +#define mmGPIOPAD_INT_EN 0x18a +#define mmGPIOPAD_INT_TYPE 0x18b +#define mmGPIOPAD_INT_POLARITY 0x18c +#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d +#define mmGPIOPAD_RCVR_SEL 0x191 +#define mmGPIOPAD_PU_EN 0x192 +#define mmGPIOPAD_PD_EN 0x193 +#define mmCG_FPS_CNT 0x1b6 +#define mmSMU_IND_INDEX_0 0x1a6 +#define mmSMU_IND_DATA_0 0x1a7 +#define mmSMU_IND_INDEX_1 0x1a8 +#define mmSMU_IND_DATA_1 0x1a9 +#define mmSMU_IND_INDEX_2 0x1aa +#define mmSMU_IND_DATA_2 0x1ab +#define mmSMU_IND_INDEX_3 0x1ac +#define mmSMU_IND_DATA_3 0x1ad +#define mmSMU_IND_INDEX_4 0x1ae +#define mmSMU_IND_DATA_4 0x1af +#define mmSMU_IND_INDEX_5 0x1b0 +#define mmSMU_IND_DATA_5 0x1b1 +#define mmSMU_IND_INDEX_6 0x1b2 +#define mmSMU_IND_DATA_6 0x1b3 +#define mmSMU_IND_INDEX_7 0x1b4 +#define mmSMU_IND_DATA_7 0x1b5 +#define mmSMU_SMC_IND_INDEX 0x80 +#define mmSMU0_SMU_SMC_IND_INDEX 0x80 +#define mmSMU1_SMU_SMC_IND_INDEX 0x82 +#define mmSMU2_SMU_SMC_IND_INDEX 0x84 +#define mmSMU3_SMU_SMC_IND_INDEX 0x86 +#define mmSMU_SMC_IND_DATA 0x81 +#define mmSMU0_SMU_SMC_IND_DATA 0x81 +#define mmSMU1_SMU_SMC_IND_DATA 0x83 +#define mmSMU2_SMU_SMC_IND_DATA 0x85 +#define mmSMU3_SMU_SMC_IND_DATA 0x87 +#define ixRCU_UC_EVENTS 0xc0000004 +#define ixRCU_MISC_CTRL 0xc0000010 +#define ixRCU_VIRT_RESET_REQ 0xc0000024 +#define ixCC_RCU_FUSES 0xc00c0000 +#define ixCC_SMU_MISC_FUSES 0xc00c0004 +#define ixCC_SCLK_VID_FUSES 0xc00c0008 +#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c +#define ixCC_GIO_IOC_FUSES 0xc00c0010 +#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c +#define ixCC_TST_ID_STRAPS 0xc00c0020 +#define ixCC_FCTRL_FUSES 0xc00c0024 +#define ixCC_HARVEST_FUSES 0xc00c0028 +#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 +#define ixSMU_STATUS 0xe0003088 +#define ixSMU_FIRMWARE 0xe00030a4 +#define ixSMU_INPUT_DATA 0xe00030b8 +#define ixSMU_EFUSE_0 0xc0100000 +#define ixFIRMWARE_FLAGS 0x3f800 +#define ixTDC_STATUS 0x3f804 +#define ixTDC_MV_AVERAGE 0x3f808 +#define ixTDC_VRM_LIMIT 0x3f80c +#define ixFEATURE_STATUS 0x3f810 +#define ixENTITY_TEMPERATURES_1 0x3f814 +#define ixDPM_TABLE_1 0x3f000 +#define ixDPM_TABLE_2 0x3f004 +#define ixDPM_TABLE_3 0x3f008 +#define ixDPM_TABLE_4 0x3f00c +#define ixDPM_TABLE_5 0x3f010 +#define ixDPM_TABLE_6 0x3f014 +#define ixDPM_TABLE_7 0x3f018 +#define ixDPM_TABLE_8 0x3f01c +#define ixDPM_TABLE_9 0x3f020 +#define ixDPM_TABLE_10 0x3f024 +#define ixDPM_TABLE_11 0x3f028 +#define ixDPM_TABLE_12 0x3f02c +#define ixDPM_TABLE_13 0x3f030 +#define ixDPM_TABLE_14 0x3f034 +#define ixDPM_TABLE_15 0x3f038 +#define ixDPM_TABLE_16 0x3f03c +#define ixDPM_TABLE_17 0x3f040 +#define ixDPM_TABLE_18 0x3f044 +#define ixDPM_TABLE_19 0x3f048 +#define ixDPM_TABLE_20 0x3f04c +#define ixDPM_TABLE_21 0x3f050 +#define ixDPM_TABLE_22 0x3f054 +#define ixDPM_TABLE_23 0x3f058 +#define ixDPM_TABLE_24 0x3f05c +#define ixDPM_TABLE_25 0x3f060 +#define ixDPM_TABLE_26 0x3f064 +#define ixDPM_TABLE_27 0x3f068 +#define ixDPM_TABLE_28 0x3f06c +#define ixDPM_TABLE_29 0x3f070 +#define ixDPM_TABLE_30 0x3f074 +#define ixDPM_TABLE_31 0x3f078 +#define ixDPM_TABLE_32 0x3f07c +#define ixDPM_TABLE_33 0x3f080 +#define ixDPM_TABLE_34 0x3f084 +#define ixDPM_TABLE_35 0x3f088 +#define ixDPM_TABLE_36 0x3f08c +#define ixDPM_TABLE_37 0x3f090 +#define ixDPM_TABLE_38 0x3f094 +#define ixDPM_TABLE_39 0x3f098 +#define ixDPM_TABLE_40 0x3f09c +#define ixDPM_TABLE_41 0x3f0a0 +#define ixDPM_TABLE_42 0x3f0a4 +#define ixDPM_TABLE_43 0x3f0a8 +#define ixDPM_TABLE_44 0x3f0ac +#define ixDPM_TABLE_45 0x3f0b0 +#define ixDPM_TABLE_46 0x3f0b4 +#define ixDPM_TABLE_47 0x3f0b8 +#define ixDPM_TABLE_48 0x3f0bc +#define ixDPM_TABLE_49 0x3f0c0 +#define ixDPM_TABLE_50 0x3f0c4 +#define ixDPM_TABLE_51 0x3f0c8 +#define ixDPM_TABLE_52 0x3f0cc +#define ixDPM_TABLE_53 0x3f0d0 +#define ixDPM_TABLE_54 0x3f0d4 +#define ixDPM_TABLE_55 0x3f0d8 +#define ixDPM_TABLE_56 0x3f0dc +#define ixDPM_TABLE_57 0x3f0e0 +#define ixDPM_TABLE_58 0x3f0e4 +#define ixDPM_TABLE_59 0x3f0e8 +#define ixDPM_TABLE_60 0x3f0ec +#define ixDPM_TABLE_61 0x3f0f0 +#define ixDPM_TABLE_62 0x3f0f4 +#define ixDPM_TABLE_63 0x3f0f8 +#define ixDPM_TABLE_64 0x3f0fc +#define ixDPM_TABLE_65 0x3f100 +#define ixDPM_TABLE_66 0x3f104 +#define ixDPM_TABLE_67 0x3f108 +#define ixDPM_TABLE_68 0x3f10c +#define ixDPM_TABLE_69 0x3f110 +#define ixDPM_TABLE_70 0x3f114 +#define ixDPM_TABLE_71 0x3f118 +#define ixDPM_TABLE_72 0x3f11c +#define ixDPM_TABLE_73 0x3f120 +#define ixDPM_TABLE_74 0x3f124 +#define ixDPM_TABLE_75 0x3f128 +#define ixDPM_TABLE_76 0x3f12c +#define ixDPM_TABLE_77 0x3f130 +#define ixDPM_TABLE_78 0x3f134 +#define ixDPM_TABLE_79 0x3f138 +#define ixDPM_TABLE_80 0x3f13c +#define ixDPM_TABLE_81 0x3f140 +#define ixDPM_TABLE_82 0x3f144 +#define ixDPM_TABLE_83 0x3f148 +#define ixDPM_TABLE_84 0x3f14c +#define ixDPM_TABLE_85 0x3f150 +#define ixDPM_TABLE_86 0x3f154 +#define ixDPM_TABLE_87 0x3f158 +#define ixDPM_TABLE_88 0x3f15c +#define ixDPM_TABLE_89 0x3f160 +#define ixDPM_TABLE_90 0x3f164 +#define ixDPM_TABLE_91 0x3f168 +#define ixDPM_TABLE_92 0x3f16c +#define ixDPM_TABLE_93 0x3f170 +#define ixDPM_TABLE_94 0x3f174 +#define ixDPM_TABLE_95 0x3f178 +#define ixDPM_TABLE_96 0x3f17c +#define ixDPM_TABLE_97 0x3f180 +#define ixDPM_TABLE_98 0x3f184 +#define ixDPM_TABLE_99 0x3f188 +#define ixDPM_TABLE_100 0x3f18c +#define ixDPM_TABLE_101 0x3f190 +#define ixDPM_TABLE_102 0x3f194 +#define ixDPM_TABLE_103 0x3f198 +#define ixDPM_TABLE_104 0x3f19c +#define ixDPM_TABLE_105 0x3f1a0 +#define ixDPM_TABLE_106 0x3f1a4 +#define ixDPM_TABLE_107 0x3f1a8 +#define ixDPM_TABLE_108 0x3f1ac +#define ixDPM_TABLE_109 0x3f1b0 +#define ixDPM_TABLE_110 0x3f1b4 +#define ixDPM_TABLE_111 0x3f1b8 +#define ixDPM_TABLE_112 0x3f1bc +#define ixDPM_TABLE_113 0x3f1c0 +#define ixDPM_TABLE_114 0x3f1c4 +#define ixDPM_TABLE_115 0x3f1c8 +#define ixDPM_TABLE_116 0x3f1cc +#define ixDPM_TABLE_117 0x3f1d0 +#define ixDPM_TABLE_118 0x3f1d4 +#define ixDPM_TABLE_119 0x3f1d8 +#define ixDPM_TABLE_120 0x3f1dc +#define ixDPM_TABLE_121 0x3f1e0 +#define ixDPM_TABLE_122 0x3f1e4 +#define ixDPM_TABLE_123 0x3f1e8 +#define ixDPM_TABLE_124 0x3f1ec +#define ixDPM_TABLE_125 0x3f1f0 +#define ixDPM_TABLE_126 0x3f1f4 +#define ixDPM_TABLE_127 0x3f1f8 +#define ixDPM_TABLE_128 0x3f1fc +#define ixDPM_TABLE_129 0x3f200 +#define ixDPM_TABLE_130 0x3f204 +#define ixDPM_TABLE_131 0x3f208 +#define ixDPM_TABLE_132 0x3f20c +#define ixDPM_TABLE_133 0x3f210 +#define ixDPM_TABLE_134 0x3f214 +#define ixDPM_TABLE_135 0x3f218 +#define ixDPM_TABLE_136 0x3f21c +#define ixDPM_TABLE_137 0x3f220 +#define ixDPM_TABLE_138 0x3f224 +#define ixDPM_TABLE_139 0x3f228 +#define ixDPM_TABLE_140 0x3f22c +#define ixDPM_TABLE_141 0x3f230 +#define ixDPM_TABLE_142 0x3f234 +#define ixDPM_TABLE_143 0x3f238 +#define ixDPM_TABLE_144 0x3f23c +#define ixDPM_TABLE_145 0x3f240 +#define ixDPM_TABLE_146 0x3f244 +#define ixDPM_TABLE_147 0x3f248 +#define ixDPM_TABLE_148 0x3f24c +#define ixDPM_TABLE_149 0x3f250 +#define ixDPM_TABLE_150 0x3f254 +#define ixDPM_TABLE_151 0x3f258 +#define ixDPM_TABLE_152 0x3f25c +#define ixDPM_TABLE_153 0x3f260 +#define ixDPM_TABLE_154 0x3f264 +#define ixDPM_TABLE_155 0x3f268 +#define ixDPM_TABLE_156 0x3f26c +#define ixDPM_TABLE_157 0x3f270 +#define ixDPM_TABLE_158 0x3f274 +#define ixDPM_TABLE_159 0x3f278 +#define ixDPM_TABLE_160 0x3f27c +#define ixDPM_TABLE_161 0x3f280 +#define ixDPM_TABLE_162 0x3f284 +#define ixDPM_TABLE_163 0x3f288 +#define ixDPM_TABLE_164 0x3f28c +#define ixDPM_TABLE_165 0x3f290 +#define ixDPM_TABLE_166 0x3f294 +#define ixDPM_TABLE_167 0x3f298 +#define ixDPM_TABLE_168 0x3f29c +#define ixDPM_TABLE_169 0x3f2a0 +#define ixDPM_TABLE_170 0x3f2a4 +#define ixDPM_TABLE_171 0x3f2a8 +#define ixDPM_TABLE_172 0x3f2ac +#define ixDPM_TABLE_173 0x3f2b0 +#define ixDPM_TABLE_174 0x3f2b4 +#define ixDPM_TABLE_175 0x3f2b8 +#define ixDPM_TABLE_176 0x3f2bc +#define ixDPM_TABLE_177 0x3f2c0 +#define ixDPM_TABLE_178 0x3f2c4 +#define ixDPM_TABLE_179 0x3f2c8 +#define ixDPM_TABLE_180 0x3f2cc +#define ixDPM_TABLE_181 0x3f2d0 +#define ixDPM_TABLE_182 0x3f2d4 +#define ixDPM_TABLE_183 0x3f2d8 +#define ixDPM_TABLE_184 0x3f2dc +#define ixDPM_TABLE_185 0x3f2e0 +#define ixDPM_TABLE_186 0x3f2e4 +#define ixDPM_TABLE_187 0x3f2e8 +#define ixDPM_TABLE_188 0x3f2ec +#define ixDPM_TABLE_189 0x3f2f0 +#define ixDPM_TABLE_190 0x3f2f4 +#define ixDPM_TABLE_191 0x3f2f8 +#define ixDPM_TABLE_192 0x3f2fc +#define ixDPM_TABLE_193 0x3f300 +#define ixDPM_TABLE_194 0x3f304 +#define ixDPM_TABLE_195 0x3f308 +#define ixDPM_TABLE_196 0x3f30c +#define ixDPM_TABLE_197 0x3f310 +#define ixDPM_TABLE_198 0x3f314 +#define ixDPM_TABLE_199 0x3f318 +#define ixDPM_TABLE_200 0x3f31c +#define ixDPM_TABLE_201 0x3f320 +#define ixDPM_TABLE_202 0x3f324 +#define ixDPM_TABLE_203 0x3f328 +#define ixDPM_TABLE_204 0x3f32c +#define ixDPM_TABLE_205 0x3f330 +#define ixDPM_TABLE_206 0x3f334 +#define ixDPM_TABLE_207 0x3f338 +#define ixDPM_TABLE_208 0x3f33c +#define ixDPM_TABLE_209 0x3f340 +#define ixDPM_TABLE_210 0x3f344 +#define ixDPM_TABLE_211 0x3f348 +#define ixDPM_TABLE_212 0x3f34c +#define ixDPM_TABLE_213 0x3f350 +#define ixDPM_TABLE_214 0x3f354 +#define ixDPM_TABLE_215 0x3f358 +#define ixDPM_TABLE_216 0x3f35c +#define ixDPM_TABLE_217 0x3f360 +#define ixDPM_TABLE_218 0x3f364 +#define ixDPM_TABLE_219 0x3f368 +#define ixDPM_TABLE_220 0x3f36c +#define ixDPM_TABLE_221 0x3f370 +#define ixDPM_TABLE_222 0x3f374 +#define ixDPM_TABLE_223 0x3f378 +#define ixDPM_TABLE_224 0x3f37c +#define ixDPM_TABLE_225 0x3f380 +#define ixDPM_TABLE_226 0x3f384 +#define ixDPM_TABLE_227 0x3f388 +#define ixDPM_TABLE_228 0x3f38c +#define ixDPM_TABLE_229 0x3f390 +#define ixDPM_TABLE_230 0x3f394 +#define ixDPM_TABLE_231 0x3f398 +#define ixDPM_TABLE_232 0x3f39c +#define ixDPM_TABLE_233 0x3f3a0 +#define ixDPM_TABLE_234 0x3f3a4 +#define ixDPM_TABLE_235 0x3f3a8 +#define ixDPM_TABLE_236 0x3f3ac +#define ixDPM_TABLE_237 0x3f3b0 +#define ixDPM_TABLE_238 0x3f3b4 +#define ixDPM_TABLE_239 0x3f3b8 +#define ixDPM_TABLE_240 0x3f3bc +#define ixDPM_TABLE_241 0x3f3c0 +#define ixDPM_TABLE_242 0x3f3c4 +#define ixDPM_TABLE_243 0x3f3c8 +#define ixDPM_TABLE_244 0x3f3cc +#define ixDPM_TABLE_245 0x3f3d0 +#define ixDPM_TABLE_246 0x3f3d4 +#define ixDPM_TABLE_247 0x3f3d8 +#define ixDPM_TABLE_248 0x3f3dc +#define ixDPM_TABLE_249 0x3f3e0 +#define ixDPM_TABLE_250 0x3f3e4 +#define ixDPM_TABLE_251 0x3f3e8 +#define ixDPM_TABLE_252 0x3f3ec +#define ixDPM_TABLE_253 0x3f3f0 +#define ixDPM_TABLE_254 0x3f3f4 +#define ixDPM_TABLE_255 0x3f3f8 +#define ixDPM_TABLE_256 0x3f3fc +#define ixDPM_TABLE_257 0x3f400 +#define ixDPM_TABLE_258 0x3f404 +#define ixDPM_TABLE_259 0x3f408 +#define ixDPM_TABLE_260 0x3f40c +#define ixDPM_TABLE_261 0x3f410 +#define ixDPM_TABLE_262 0x3f414 +#define ixDPM_TABLE_263 0x3f418 +#define ixDPM_TABLE_264 0x3f41c +#define ixDPM_TABLE_265 0x3f420 +#define ixDPM_TABLE_266 0x3f424 +#define ixDPM_TABLE_267 0x3f428 +#define ixDPM_TABLE_268 0x3f42c +#define ixDPM_TABLE_269 0x3f430 +#define ixDPM_TABLE_270 0x3f434 +#define ixDPM_TABLE_271 0x3f438 +#define ixDPM_TABLE_272 0x3f43c +#define ixDPM_TABLE_273 0x3f440 +#define ixDPM_TABLE_274 0x3f444 +#define ixDPM_TABLE_275 0x3f448 +#define ixDPM_TABLE_276 0x3f44c +#define ixDPM_TABLE_277 0x3f450 +#define ixDPM_TABLE_278 0x3f454 +#define ixDPM_TABLE_279 0x3f458 +#define ixDPM_TABLE_280 0x3f45c +#define ixDPM_TABLE_281 0x3f460 +#define ixDPM_TABLE_282 0x3f464 +#define ixDPM_TABLE_283 0x3f468 +#define ixDPM_TABLE_284 0x3f46c +#define ixDPM_TABLE_285 0x3f470 +#define ixDPM_TABLE_286 0x3f474 +#define ixDPM_TABLE_287 0x3f478 +#define ixDPM_TABLE_288 0x3f47c +#define ixDPM_TABLE_289 0x3f480 +#define ixDPM_TABLE_290 0x3f484 +#define ixDPM_TABLE_291 0x3f488 +#define ixDPM_TABLE_292 0x3f48c +#define ixDPM_TABLE_293 0x3f490 +#define ixDPM_TABLE_294 0x3f494 +#define ixDPM_TABLE_295 0x3f498 +#define ixDPM_TABLE_296 0x3f49c +#define ixDPM_TABLE_297 0x3f4a0 +#define ixDPM_TABLE_298 0x3f4a4 +#define ixDPM_TABLE_299 0x3f4a8 +#define ixDPM_TABLE_300 0x3f4ac +#define ixDPM_TABLE_301 0x3f4b0 +#define ixDPM_TABLE_302 0x3f4b4 +#define ixDPM_TABLE_303 0x3f4b8 +#define ixDPM_TABLE_304 0x3f4bc +#define ixDPM_TABLE_305 0x3f4c0 +#define ixDPM_TABLE_306 0x3f4c4 +#define ixDPM_TABLE_307 0x3f4c8 +#define ixDPM_TABLE_308 0x3f4cc +#define ixDPM_TABLE_309 0x3f4d0 +#define ixDPM_TABLE_310 0x3f4d4 +#define ixDPM_TABLE_311 0x3f4d8 +#define ixDPM_TABLE_312 0x3f4dc +#define ixDPM_TABLE_313 0x3f4e0 +#define ixDPM_TABLE_314 0x3f4e4 +#define ixDPM_TABLE_315 0x3f4e8 +#define ixDPM_TABLE_316 0x3f4ec +#define ixDPM_TABLE_317 0x3f4f0 +#define ixDPM_TABLE_318 0x3f4f4 +#define ixDPM_TABLE_319 0x3f4f8 +#define ixDPM_TABLE_320 0x3f4fc +#define ixDPM_TABLE_321 0x3f500 +#define ixDPM_TABLE_322 0x3f504 +#define ixDPM_TABLE_323 0x3f508 +#define ixDPM_TABLE_324 0x3f50c +#define ixDPM_TABLE_325 0x3f510 +#define ixDPM_TABLE_326 0x3f514 +#define ixDPM_TABLE_327 0x3f518 +#define ixDPM_TABLE_328 0x3f51c +#define ixDPM_TABLE_329 0x3f520 +#define ixDPM_TABLE_330 0x3f524 +#define ixDPM_TABLE_331 0x3f528 +#define ixDPM_TABLE_332 0x3f52c +#define ixDPM_TABLE_333 0x3f530 +#define ixDPM_TABLE_334 0x3f534 +#define ixDPM_TABLE_335 0x3f538 +#define ixDPM_TABLE_336 0x3f53c +#define ixDPM_TABLE_337 0x3f540 +#define ixDPM_TABLE_338 0x3f544 +#define ixDPM_TABLE_339 0x3f548 +#define ixDPM_TABLE_340 0x3f54c +#define ixDPM_TABLE_341 0x3f550 +#define ixDPM_TABLE_342 0x3f554 +#define ixDPM_TABLE_343 0x3f558 +#define ixDPM_TABLE_344 0x3f55c +#define ixDPM_TABLE_345 0x3f560 +#define ixDPM_TABLE_346 0x3f564 +#define ixDPM_TABLE_347 0x3f568 +#define ixDPM_TABLE_348 0x3f56c +#define ixDPM_TABLE_349 0x3f570 +#define ixDPM_TABLE_350 0x3f574 +#define ixDPM_TABLE_351 0x3f578 +#define ixDPM_TABLE_352 0x3f57c +#define ixDPM_TABLE_353 0x3f580 +#define ixDPM_TABLE_354 0x3f584 +#define ixDPM_TABLE_355 0x3f588 +#define ixDPM_TABLE_356 0x3f58c +#define ixDPM_TABLE_357 0x3f590 +#define ixDPM_TABLE_358 0x3f594 +#define ixDPM_TABLE_359 0x3f598 +#define ixDPM_TABLE_360 0x3f59c +#define ixDPM_TABLE_361 0x3f5a0 +#define ixDPM_TABLE_362 0x3f5a4 +#define ixDPM_TABLE_363 0x3f5a8 +#define ixDPM_TABLE_364 0x3f5ac +#define ixDPM_TABLE_365 0x3f5b0 +#define ixDPM_TABLE_366 0x3f5b4 +#define ixDPM_TABLE_367 0x3f5b8 +#define ixDPM_TABLE_368 0x3f5bc +#define ixDPM_TABLE_369 0x3f5c0 +#define ixDPM_TABLE_370 0x3f5c4 +#define ixDPM_TABLE_371 0x3f5c8 +#define ixDPM_TABLE_372 0x3f5cc +#define ixDPM_TABLE_373 0x3f5d0 +#define ixDPM_TABLE_374 0x3f5d4 +#define ixDPM_TABLE_375 0x3f5d8 +#define ixDPM_TABLE_376 0x3f5dc +#define ixDPM_TABLE_377 0x3f5e0 +#define ixDPM_TABLE_378 0x3f5e4 +#define ixDPM_TABLE_379 0x3f5e8 +#define ixDPM_TABLE_380 0x3f5ec +#define ixDPM_TABLE_381 0x3f5f0 +#define ixDPM_TABLE_382 0x3f5f4 +#define ixDPM_TABLE_383 0x3f5f8 +#define ixDPM_TABLE_384 0x3f5fc +#define ixDPM_TABLE_385 0x3f600 +#define ixDPM_TABLE_386 0x3f604 +#define ixDPM_TABLE_387 0x3f608 +#define ixDPM_TABLE_388 0x3f60c +#define ixDPM_TABLE_389 0x3f610 +#define ixDPM_TABLE_390 0x3f614 +#define ixDPM_TABLE_391 0x3f618 +#define ixDPM_TABLE_392 0x3f61c +#define ixDPM_TABLE_393 0x3f620 +#define ixDPM_TABLE_394 0x3f624 +#define ixDPM_TABLE_395 0x3f628 +#define ixDPM_TABLE_396 0x3f62c +#define ixDPM_TABLE_397 0x3f630 +#define ixDPM_TABLE_398 0x3f634 +#define ixDPM_TABLE_399 0x3f638 +#define ixDPM_TABLE_400 0x3f63c +#define ixDPM_TABLE_401 0x3f640 +#define ixDPM_TABLE_402 0x3f644 +#define ixDPM_TABLE_403 0x3f648 +#define ixDPM_TABLE_404 0x3f64c +#define ixDPM_TABLE_405 0x3f650 +#define ixDPM_TABLE_406 0x3f654 +#define ixDPM_TABLE_407 0x3f658 +#define ixDPM_TABLE_408 0x3f65c +#define ixDPM_TABLE_409 0x3f660 +#define ixDPM_TABLE_410 0x3f664 +#define ixDPM_TABLE_411 0x3f668 +#define ixDPM_TABLE_412 0x3f66c +#define ixDPM_TABLE_413 0x3f670 +#define ixDPM_TABLE_414 0x3f674 +#define ixDPM_TABLE_415 0x3f678 +#define ixDPM_TABLE_416 0x3f67c +#define ixDPM_TABLE_417 0x3f680 +#define ixDPM_TABLE_418 0x3f684 +#define ixDPM_TABLE_419 0x3f688 +#define ixDPM_TABLE_420 0x3f68c +#define ixDPM_TABLE_421 0x3f690 +#define ixDPM_TABLE_422 0x3f694 +#define ixDPM_TABLE_423 0x3f698 +#define ixDPM_TABLE_424 0x3f69c +#define ixDPM_TABLE_425 0x3f6a0 +#define ixDPM_TABLE_426 0x3f6a4 +#define ixDPM_TABLE_427 0x3f6a8 +#define ixDPM_TABLE_428 0x3f6ac +#define ixDPM_TABLE_429 0x3f6b0 +#define ixDPM_TABLE_430 0x3f6b4 +#define ixDPM_TABLE_431 0x3f6b8 +#define ixDPM_TABLE_432 0x3f6bc +#define ixDPM_TABLE_433 0x3f6c0 +#define ixDPM_TABLE_434 0x3f6c4 +#define ixDPM_TABLE_435 0x3f6c8 +#define ixDPM_TABLE_436 0x3f6cc +#define ixDPM_TABLE_437 0x3f6d0 +#define ixDPM_TABLE_438 0x3f6d4 +#define ixDPM_TABLE_439 0x3f6d8 +#define ixDPM_TABLE_440 0x3f6dc +#define ixDPM_TABLE_441 0x3f6e0 +#define ixDPM_TABLE_442 0x3f6e4 +#define ixDPM_TABLE_443 0x3f6e8 +#define ixDPM_TABLE_444 0x3f6ec +#define ixDPM_TABLE_445 0x3f6f0 +#define ixDPM_TABLE_446 0x3f6f4 +#define ixDPM_TABLE_447 0x3f6f8 +#define ixDPM_TABLE_448 0x3f6fc +#define ixDPM_TABLE_449 0x3f700 +#define ixDPM_TABLE_450 0x3f704 +#define ixDPM_TABLE_451 0x3f708 +#define ixDPM_TABLE_452 0x3f70c +#define ixDPM_TABLE_453 0x3f710 +#define ixDPM_TABLE_454 0x3f714 +#define ixDPM_TABLE_455 0x3f718 +#define ixDPM_TABLE_456 0x3f71c +#define ixDPM_TABLE_457 0x3f720 +#define ixDPM_TABLE_458 0x3f724 +#define ixDPM_TABLE_459 0x3f728 +#define ixDPM_TABLE_460 0x3f72c +#define ixDPM_TABLE_461 0x3f730 +#define ixDPM_TABLE_462 0x3f734 +#define ixDPM_TABLE_463 0x3f738 +#define ixDPM_TABLE_464 0x3f73c +#define ixDPM_TABLE_465 0x3f740 +#define ixDPM_TABLE_466 0x3f744 +#define ixDPM_TABLE_467 0x3f748 +#define ixDPM_TABLE_468 0x3f74c +#define ixDPM_TABLE_469 0x3f750 +#define ixDPM_TABLE_470 0x3f754 +#define ixDPM_TABLE_471 0x3f758 +#define ixDPM_TABLE_472 0x3f75c +#define ixDPM_TABLE_473 0x3f760 +#define ixDPM_TABLE_474 0x3f764 +#define ixDPM_TABLE_475 0x3f768 +#define ixDPM_TABLE_476 0x3f76c +#define ixDPM_TABLE_477 0x3f770 +#define ixDPM_TABLE_478 0x3f774 +#define ixDPM_TABLE_479 0x3f778 +#define ixDPM_TABLE_480 0x3f77c +#define ixDPM_TABLE_481 0x3f780 +#define ixDPM_TABLE_482 0x3f784 +#define ixDPM_TABLE_483 0x3f788 +#define ixDPM_TABLE_484 0x3f78c +#define ixDPM_TABLE_485 0x3f790 +#define ixDPM_TABLE_486 0x3f794 +#define ixDPM_TABLE_487 0x3f798 +#define ixDPM_TABLE_488 0x3f79c +#define ixDPM_TABLE_489 0x3f7a0 +#define ixDPM_TABLE_490 0x3f7a4 +#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f900 +#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f904 +#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f908 +#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f90c +#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f910 +#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f914 +#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f918 +#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f91c +#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f920 +#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f924 +#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f928 +#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f92c +#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f930 +#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f934 +#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f938 +#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f93c +#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f940 +#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f944 +#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f948 +#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f94c +#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f950 +#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f954 +#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f958 +#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f95c +#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f960 +#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f964 +#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f968 +#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f96c +#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f970 +#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f974 +#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f978 +#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f97c +#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f980 +#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f984 +#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f988 +#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f98c +#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f990 +#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f994 +#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f998 +#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f99c +#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f9a0 +#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f9a4 +#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f9a8 +#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f9ac +#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f9b0 +#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f9b4 +#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f9b8 +#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f9bc +#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f9c0 +#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f9c4 +#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f9c8 +#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f9cc +#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f9d0 +#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f9d4 +#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f9d8 +#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f9dc +#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f9e0 +#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f9e4 +#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f9e8 +#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f9ec +#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f9f0 +#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f9f4 +#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f9f8 +#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f9fc +#define ixMCARB_DRAM_TIMING_TABLE_65 0x3fa00 +#define ixMCARB_DRAM_TIMING_TABLE_66 0x3fa04 +#define ixMCARB_DRAM_TIMING_TABLE_67 0x3fa08 +#define ixMCARB_DRAM_TIMING_TABLE_68 0x3fa0c +#define ixMCARB_DRAM_TIMING_TABLE_69 0x3fa10 +#define ixMCARB_DRAM_TIMING_TABLE_70 0x3fa14 +#define ixMCARB_DRAM_TIMING_TABLE_71 0x3fa18 +#define ixMCARB_DRAM_TIMING_TABLE_72 0x3fa1c +#define ixMCARB_DRAM_TIMING_TABLE_73 0x3fa20 +#define ixMCARB_DRAM_TIMING_TABLE_74 0x3fa24 +#define ixMCARB_DRAM_TIMING_TABLE_75 0x3fa28 +#define ixMCARB_DRAM_TIMING_TABLE_76 0x3fa2c +#define ixMCARB_DRAM_TIMING_TABLE_77 0x3fa30 +#define ixMCARB_DRAM_TIMING_TABLE_78 0x3fa34 +#define ixMCARB_DRAM_TIMING_TABLE_79 0x3fa38 +#define ixMCARB_DRAM_TIMING_TABLE_80 0x3fa3c +#define ixMCARB_DRAM_TIMING_TABLE_81 0x3fa40 +#define ixMCARB_DRAM_TIMING_TABLE_82 0x3fa44 +#define ixMCARB_DRAM_TIMING_TABLE_83 0x3fa48 +#define ixMCARB_DRAM_TIMING_TABLE_84 0x3fa4c +#define ixMCARB_DRAM_TIMING_TABLE_85 0x3fa50 +#define ixMCARB_DRAM_TIMING_TABLE_86 0x3fa54 +#define ixMCARB_DRAM_TIMING_TABLE_87 0x3fa58 +#define ixMCARB_DRAM_TIMING_TABLE_88 0x3fa5c +#define ixMCARB_DRAM_TIMING_TABLE_89 0x3fa60 +#define ixMCARB_DRAM_TIMING_TABLE_90 0x3fa64 +#define ixMCARB_DRAM_TIMING_TABLE_91 0x3fa68 +#define ixMCARB_DRAM_TIMING_TABLE_92 0x3fa6c +#define ixMCARB_DRAM_TIMING_TABLE_93 0x3fa70 +#define ixMCARB_DRAM_TIMING_TABLE_94 0x3fa74 +#define ixMCARB_DRAM_TIMING_TABLE_95 0x3fa78 +#define ixMCARB_DRAM_TIMING_TABLE_96 0x3fa7c +#define ixMC_REGISTERS_TABLE_1 0x3fa80 +#define ixMC_REGISTERS_TABLE_2 0x3fa84 +#define ixMC_REGISTERS_TABLE_3 0x3fa88 +#define ixMC_REGISTERS_TABLE_4 0x3fa8c +#define ixMC_REGISTERS_TABLE_5 0x3fa90 +#define ixMC_REGISTERS_TABLE_6 0x3fa94 +#define ixMC_REGISTERS_TABLE_7 0x3fa98 +#define ixMC_REGISTERS_TABLE_8 0x3fa9c +#define ixMC_REGISTERS_TABLE_9 0x3faa0 +#define ixMC_REGISTERS_TABLE_10 0x3faa4 +#define ixMC_REGISTERS_TABLE_11 0x3faa8 +#define ixMC_REGISTERS_TABLE_12 0x3faac +#define ixMC_REGISTERS_TABLE_13 0x3fab0 +#define ixMC_REGISTERS_TABLE_14 0x3fab4 +#define ixMC_REGISTERS_TABLE_15 0x3fab8 +#define ixMC_REGISTERS_TABLE_16 0x3fabc +#define ixMC_REGISTERS_TABLE_17 0x3fac0 +#define ixMC_REGISTERS_TABLE_18 0x3fac4 +#define ixMC_REGISTERS_TABLE_19 0x3fac8 +#define ixMC_REGISTERS_TABLE_20 0x3facc +#define ixMC_REGISTERS_TABLE_21 0x3fad0 +#define ixMC_REGISTERS_TABLE_22 0x3fad4 +#define ixMC_REGISTERS_TABLE_23 0x3fad8 +#define ixMC_REGISTERS_TABLE_24 0x3fadc +#define ixMC_REGISTERS_TABLE_25 0x3fae0 +#define ixMC_REGISTERS_TABLE_26 0x3fae4 +#define ixMC_REGISTERS_TABLE_27 0x3fae8 +#define ixMC_REGISTERS_TABLE_28 0x3faec +#define ixMC_REGISTERS_TABLE_29 0x3faf0 +#define ixMC_REGISTERS_TABLE_30 0x3faf4 +#define ixMC_REGISTERS_TABLE_31 0x3faf8 +#define ixMC_REGISTERS_TABLE_32 0x3fafc +#define ixMC_REGISTERS_TABLE_33 0x3fb00 +#define ixMC_REGISTERS_TABLE_34 0x3fb04 +#define ixMC_REGISTERS_TABLE_35 0x3fb08 +#define ixMC_REGISTERS_TABLE_36 0x3fb0c +#define ixMC_REGISTERS_TABLE_37 0x3fb10 +#define ixMC_REGISTERS_TABLE_38 0x3fb14 +#define ixMC_REGISTERS_TABLE_39 0x3fb18 +#define ixMC_REGISTERS_TABLE_40 0x3fb1c +#define ixMC_REGISTERS_TABLE_41 0x3fb20 +#define ixMC_REGISTERS_TABLE_42 0x3fb24 +#define ixMC_REGISTERS_TABLE_43 0x3fb28 +#define ixMC_REGISTERS_TABLE_44 0x3fb2c +#define ixMC_REGISTERS_TABLE_45 0x3fb30 +#define ixMC_REGISTERS_TABLE_46 0x3fb34 +#define ixMC_REGISTERS_TABLE_47 0x3fb38 +#define ixMC_REGISTERS_TABLE_48 0x3fb3c +#define ixMC_REGISTERS_TABLE_49 0x3fb40 +#define ixMC_REGISTERS_TABLE_50 0x3fb44 +#define ixMC_REGISTERS_TABLE_51 0x3fb48 +#define ixMC_REGISTERS_TABLE_52 0x3fb4c +#define ixMC_REGISTERS_TABLE_53 0x3fb50 +#define ixMC_REGISTERS_TABLE_54 0x3fb54 +#define ixMC_REGISTERS_TABLE_55 0x3fb58 +#define ixMC_REGISTERS_TABLE_56 0x3fb5c +#define ixMC_REGISTERS_TABLE_57 0x3fb60 +#define ixMC_REGISTERS_TABLE_58 0x3fb64 +#define ixMC_REGISTERS_TABLE_59 0x3fb68 +#define ixMC_REGISTERS_TABLE_60 0x3fb6c +#define ixMC_REGISTERS_TABLE_61 0x3fb70 +#define ixMC_REGISTERS_TABLE_62 0x3fb74 +#define ixMC_REGISTERS_TABLE_63 0x3fb78 +#define ixMC_REGISTERS_TABLE_64 0x3fb7c +#define ixMC_REGISTERS_TABLE_65 0x3fb80 +#define ixMC_REGISTERS_TABLE_66 0x3fb84 +#define ixMC_REGISTERS_TABLE_67 0x3fb88 +#define ixMC_REGISTERS_TABLE_68 0x3fb8c +#define ixMC_REGISTERS_TABLE_69 0x3fb90 +#define ixMC_REGISTERS_TABLE_70 0x3fb94 +#define ixMC_REGISTERS_TABLE_71 0x3fb98 +#define ixMC_REGISTERS_TABLE_72 0x3fb9c +#define ixMC_REGISTERS_TABLE_73 0x3fba0 +#define ixMC_REGISTERS_TABLE_74 0x3fba4 +#define ixMC_REGISTERS_TABLE_75 0x3fba8 +#define ixMC_REGISTERS_TABLE_76 0x3fbac +#define ixMC_REGISTERS_TABLE_77 0x3fbb0 +#define ixMC_REGISTERS_TABLE_78 0x3fbb4 +#define ixMC_REGISTERS_TABLE_79 0x3fbb8 +#define ixMC_REGISTERS_TABLE_80 0x3fbbc +#define ixMC_REGISTERS_TABLE_81 0x3fbc0 +#define ixFAN_TABLE_1 0x3fbc4 +#define ixFAN_TABLE_2 0x3fbc8 +#define ixFAN_TABLE_3 0x3fbcc +#define ixFAN_TABLE_4 0x3fbd0 +#define ixFAN_TABLE_5 0x3fbd4 +#define ixFAN_TABLE_6 0x3fbd8 +#define ixFAN_TABLE_7 0x3fbdc +#define ixFAN_TABLE_8 0x3fbe0 +#define ixFAN_TABLE_9 0x3fbe4 +#define ixSOFT_REGISTERS_TABLE_1 0x3fbe8 +#define ixSOFT_REGISTERS_TABLE_2 0x3fbec +#define ixSOFT_REGISTERS_TABLE_3 0x3fbf0 +#define ixSOFT_REGISTERS_TABLE_4 0x3fbf4 +#define ixSOFT_REGISTERS_TABLE_5 0x3fbf8 +#define ixSOFT_REGISTERS_TABLE_6 0x3fbfc +#define ixSOFT_REGISTERS_TABLE_7 0x3fc00 +#define ixSOFT_REGISTERS_TABLE_8 0x3fc04 +#define ixSOFT_REGISTERS_TABLE_9 0x3fc08 +#define ixSOFT_REGISTERS_TABLE_10 0x3fc0c +#define ixSOFT_REGISTERS_TABLE_11 0x3fc10 +#define ixSOFT_REGISTERS_TABLE_12 0x3fc14 +#define ixSOFT_REGISTERS_TABLE_13 0x3fc18 +#define ixSOFT_REGISTERS_TABLE_14 0x3fc1c +#define ixSOFT_REGISTERS_TABLE_15 0x3fc20 +#define ixSOFT_REGISTERS_TABLE_16 0x3fc24 +#define ixSOFT_REGISTERS_TABLE_17 0x3fc28 +#define ixSOFT_REGISTERS_TABLE_18 0x3fc2c +#define ixSOFT_REGISTERS_TABLE_19 0x3fc30 +#define ixSOFT_REGISTERS_TABLE_20 0x3fc34 +#define ixSOFT_REGISTERS_TABLE_21 0x3fc38 +#define ixSOFT_REGISTERS_TABLE_22 0x3fc3c +#define ixSOFT_REGISTERS_TABLE_23 0x3fc40 +#define ixSOFT_REGISTERS_TABLE_24 0x3fc44 +#define ixSOFT_REGISTERS_TABLE_25 0x3fc48 +#define ixSOFT_REGISTERS_TABLE_26 0x3fc4c +#define ixSOFT_REGISTERS_TABLE_27 0x3fc50 +#define ixSOFT_REGISTERS_TABLE_28 0x3fc54 +#define ixSOFT_REGISTERS_TABLE_29 0x3fc58 +#define ixSOFT_REGISTERS_TABLE_30 0x3fc5c +#define ixPM_FUSES_1 0x3fc60 +#define ixPM_FUSES_2 0x3fc64 +#define ixPM_FUSES_3 0x3fc68 +#define ixPM_FUSES_4 0x3fc6c +#define ixPM_FUSES_5 0x3fc70 +#define ixPM_FUSES_6 0x3fc74 +#define ixPM_FUSES_7 0x3fc78 +#define ixPM_FUSES_8 0x3fc7c +#define ixPM_FUSES_9 0x3fc80 +#define ixPM_FUSES_10 0x3fc84 +#define ixPM_FUSES_11 0x3fc88 +#define ixPM_FUSES_12 0x3fc8c +#define ixPM_FUSES_13 0x3fc90 +#define ixPM_FUSES_14 0x3fc94 +#define ixPM_FUSES_15 0x3fc98 +#define ixSMU_PM_STATUS_0 0x3fe00 +#define ixSMU_PM_STATUS_1 0x3fe04 +#define ixSMU_PM_STATUS_2 0x3fe08 +#define ixSMU_PM_STATUS_3 0x3fe0c +#define ixSMU_PM_STATUS_4 0x3fe10 +#define ixSMU_PM_STATUS_5 0x3fe14 +#define ixSMU_PM_STATUS_6 0x3fe18 +#define ixSMU_PM_STATUS_7 0x3fe1c +#define ixSMU_PM_STATUS_8 0x3fe20 +#define ixSMU_PM_STATUS_9 0x3fe24 +#define ixSMU_PM_STATUS_10 0x3fe28 +#define ixSMU_PM_STATUS_11 0x3fe2c +#define ixSMU_PM_STATUS_12 0x3fe30 +#define ixSMU_PM_STATUS_13 0x3fe34 +#define ixSMU_PM_STATUS_14 0x3fe38 +#define ixSMU_PM_STATUS_15 0x3fe3c +#define ixSMU_PM_STATUS_16 0x3fe40 +#define ixSMU_PM_STATUS_17 0x3fe44 +#define ixSMU_PM_STATUS_18 0x3fe48 +#define ixSMU_PM_STATUS_19 0x3fe4c +#define ixSMU_PM_STATUS_20 0x3fe50 +#define ixSMU_PM_STATUS_21 0x3fe54 +#define ixSMU_PM_STATUS_22 0x3fe58 +#define ixSMU_PM_STATUS_23 0x3fe5c +#define ixSMU_PM_STATUS_24 0x3fe60 +#define ixSMU_PM_STATUS_25 0x3fe64 +#define ixSMU_PM_STATUS_26 0x3fe68 +#define ixSMU_PM_STATUS_27 0x3fe6c +#define ixSMU_PM_STATUS_28 0x3fe70 +#define ixSMU_PM_STATUS_29 0x3fe74 +#define ixSMU_PM_STATUS_30 0x3fe78 +#define ixSMU_PM_STATUS_31 0x3fe7c +#define ixSMU_PM_STATUS_32 0x3fe80 +#define ixSMU_PM_STATUS_33 0x3fe84 +#define ixSMU_PM_STATUS_34 0x3fe88 +#define ixSMU_PM_STATUS_35 0x3fe8c +#define ixSMU_PM_STATUS_36 0x3fe90 +#define ixSMU_PM_STATUS_37 0x3fe94 +#define ixSMU_PM_STATUS_38 0x3fe98 +#define ixSMU_PM_STATUS_39 0x3fe9c +#define ixSMU_PM_STATUS_40 0x3fea0 +#define ixSMU_PM_STATUS_41 0x3fea4 +#define ixSMU_PM_STATUS_42 0x3fea8 +#define ixSMU_PM_STATUS_43 0x3feac +#define ixSMU_PM_STATUS_44 0x3feb0 +#define ixSMU_PM_STATUS_45 0x3feb4 +#define ixSMU_PM_STATUS_46 0x3feb8 +#define ixSMU_PM_STATUS_47 0x3febc +#define ixSMU_PM_STATUS_48 0x3fec0 +#define ixSMU_PM_STATUS_49 0x3fec4 +#define ixSMU_PM_STATUS_50 0x3fec8 +#define ixSMU_PM_STATUS_51 0x3fecc +#define ixSMU_PM_STATUS_52 0x3fed0 +#define ixSMU_PM_STATUS_53 0x3fed4 +#define ixSMU_PM_STATUS_54 0x3fed8 +#define ixSMU_PM_STATUS_55 0x3fedc +#define ixSMU_PM_STATUS_56 0x3fee0 +#define ixSMU_PM_STATUS_57 0x3fee4 +#define ixSMU_PM_STATUS_58 0x3fee8 +#define ixSMU_PM_STATUS_59 0x3feec +#define ixSMU_PM_STATUS_60 0x3fef0 +#define ixSMU_PM_STATUS_61 0x3fef4 +#define ixSMU_PM_STATUS_62 0x3fef8 +#define ixSMU_PM_STATUS_63 0x3fefc +#define ixSMU_PM_STATUS_64 0x3ff00 +#define ixSMU_PM_STATUS_65 0x3ff04 +#define ixSMU_PM_STATUS_66 0x3ff08 +#define ixSMU_PM_STATUS_67 0x3ff0c +#define ixSMU_PM_STATUS_68 0x3ff10 +#define ixSMU_PM_STATUS_69 0x3ff14 +#define ixSMU_PM_STATUS_70 0x3ff18 +#define ixSMU_PM_STATUS_71 0x3ff1c +#define ixSMU_PM_STATUS_72 0x3ff20 +#define ixSMU_PM_STATUS_73 0x3ff24 +#define ixSMU_PM_STATUS_74 0x3ff28 +#define ixSMU_PM_STATUS_75 0x3ff2c +#define ixSMU_PM_STATUS_76 0x3ff30 +#define ixSMU_PM_STATUS_77 0x3ff34 +#define ixSMU_PM_STATUS_78 0x3ff38 +#define ixSMU_PM_STATUS_79 0x3ff3c +#define ixSMU_PM_STATUS_80 0x3ff40 +#define ixSMU_PM_STATUS_81 0x3ff44 +#define ixSMU_PM_STATUS_82 0x3ff48 +#define ixSMU_PM_STATUS_83 0x3ff4c +#define ixSMU_PM_STATUS_84 0x3ff50 +#define ixSMU_PM_STATUS_85 0x3ff54 +#define ixSMU_PM_STATUS_86 0x3ff58 +#define ixSMU_PM_STATUS_87 0x3ff5c +#define ixSMU_PM_STATUS_88 0x3ff60 +#define ixSMU_PM_STATUS_89 0x3ff64 +#define ixSMU_PM_STATUS_90 0x3ff68 +#define ixSMU_PM_STATUS_91 0x3ff6c +#define ixSMU_PM_STATUS_92 0x3ff70 +#define ixSMU_PM_STATUS_93 0x3ff74 +#define ixSMU_PM_STATUS_94 0x3ff78 +#define ixSMU_PM_STATUS_95 0x3ff7c +#define ixSMU_PM_STATUS_96 0x3ff80 +#define ixSMU_PM_STATUS_97 0x3ff84 +#define ixSMU_PM_STATUS_98 0x3ff88 +#define ixSMU_PM_STATUS_99 0x3ff8c +#define ixSMU_PM_STATUS_100 0x3ff90 +#define ixSMU_PM_STATUS_101 0x3ff94 +#define ixSMU_PM_STATUS_102 0x3ff98 +#define ixSMU_PM_STATUS_103 0x3ff9c +#define ixSMU_PM_STATUS_104 0x3ffa0 +#define ixSMU_PM_STATUS_105 0x3ffa4 +#define ixSMU_PM_STATUS_106 0x3ffa8 +#define ixSMU_PM_STATUS_107 0x3ffac +#define ixSMU_PM_STATUS_108 0x3ffb0 +#define ixSMU_PM_STATUS_109 0x3ffb4 +#define ixSMU_PM_STATUS_110 0x3ffb8 +#define ixSMU_PM_STATUS_111 0x3ffbc +#define ixSMU_PM_STATUS_112 0x3ffc0 +#define ixSMU_PM_STATUS_113 0x3ffc4 +#define ixSMU_PM_STATUS_114 0x3ffc8 +#define ixSMU_PM_STATUS_115 0x3ffcc +#define ixSMU_PM_STATUS_116 0x3ffd0 +#define ixSMU_PM_STATUS_117 0x3ffd4 +#define ixSMU_PM_STATUS_118 0x3ffd8 +#define ixSMU_PM_STATUS_119 0x3ffdc +#define ixSMU_PM_STATUS_120 0x3ffe0 +#define ixSMU_PM_STATUS_121 0x3ffe4 +#define ixSMU_PM_STATUS_122 0x3ffe8 +#define ixSMU_PM_STATUS_123 0x3ffec +#define ixSMU_PM_STATUS_124 0x3fff0 +#define ixSMU_PM_STATUS_125 0x3fff4 +#define ixSMU_PM_STATUS_126 0x3fff8 +#define ixSMU_PM_STATUS_127 0x3fffc +#define ixCG_THERMAL_INT_ENA 0xc2100024 +#define ixCG_THERMAL_INT_CTRL 0xc2100028 +#define ixCG_THERMAL_INT_STATUS 0xc210002c +#define ixCG_THERMAL_CTRL 0xc0300004 +#define ixCG_THERMAL_STATUS 0xc0300008 +#define ixCG_THERMAL_INT 0xc030000c +#define ixCG_MULT_THERMAL_CTRL 0xc0300010 +#define ixCG_MULT_THERMAL_STATUS 0xc0300014 +#define ixCG_FDO_CTRL0 0xc0300064 +#define ixCG_FDO_CTRL1 0xc0300068 +#define ixCG_FDO_CTRL2 0xc030006c +#define ixCG_TACH_CTRL 0xc0300070 +#define ixCG_TACH_STATUS 0xc0300074 +#define ixCC_THM_STRAPS0 0xc0300080 +#define ixTHM_TMON0_RDIL0_DATA 0xc0300100 +#define ixTHM_TMON0_RDIL1_DATA 0xc0300104 +#define ixTHM_TMON0_RDIL2_DATA 0xc0300108 +#define ixTHM_TMON0_RDIL3_DATA 0xc030010c +#define ixTHM_TMON0_RDIL4_DATA 0xc0300110 +#define ixTHM_TMON0_RDIL5_DATA 0xc0300114 +#define ixTHM_TMON0_RDIL6_DATA 0xc0300118 +#define ixTHM_TMON0_RDIL7_DATA 0xc030011c +#define ixTHM_TMON0_RDIL8_DATA 0xc0300120 +#define ixTHM_TMON0_RDIL9_DATA 0xc0300124 +#define ixTHM_TMON0_RDIL10_DATA 0xc0300128 +#define ixTHM_TMON0_RDIL11_DATA 0xc030012c +#define ixTHM_TMON0_RDIL12_DATA 0xc0300130 +#define ixTHM_TMON0_RDIL13_DATA 0xc0300134 +#define ixTHM_TMON0_RDIL14_DATA 0xc0300138 +#define ixTHM_TMON0_RDIL15_DATA 0xc030013c +#define ixTHM_TMON0_RDIR0_DATA 0xc0300140 +#define ixTHM_TMON0_RDIR1_DATA 0xc0300144 +#define ixTHM_TMON0_RDIR2_DATA 0xc0300148 +#define ixTHM_TMON0_RDIR3_DATA 0xc030014c +#define ixTHM_TMON0_RDIR4_DATA 0xc0300150 +#define ixTHM_TMON0_RDIR5_DATA 0xc0300154 +#define ixTHM_TMON0_RDIR6_DATA 0xc0300158 +#define ixTHM_TMON0_RDIR7_DATA 0xc030015c +#define ixTHM_TMON0_RDIR8_DATA 0xc0300160 +#define ixTHM_TMON0_RDIR9_DATA 0xc0300164 +#define ixTHM_TMON0_RDIR10_DATA 0xc0300168 +#define ixTHM_TMON0_RDIR11_DATA 0xc030016c +#define ixTHM_TMON0_RDIR12_DATA 0xc0300170 +#define ixTHM_TMON0_RDIR13_DATA 0xc0300174 +#define ixTHM_TMON0_RDIR14_DATA 0xc0300178 +#define ixTHM_TMON0_RDIR15_DATA 0xc030017c +#define ixTHM_TMON1_RDIL0_DATA 0xc0300180 +#define ixTHM_TMON1_RDIL1_DATA 0xc0300184 +#define ixTHM_TMON1_RDIL2_DATA 0xc0300188 +#define ixTHM_TMON1_RDIL3_DATA 0xc030018c +#define ixTHM_TMON1_RDIL4_DATA 0xc0300190 +#define ixTHM_TMON1_RDIL5_DATA 0xc0300194 +#define ixTHM_TMON1_RDIL6_DATA 0xc0300198 +#define ixTHM_TMON1_RDIL7_DATA 0xc030019c +#define ixTHM_TMON1_RDIL8_DATA 0xc03001a0 +#define ixTHM_TMON1_RDIL9_DATA 0xc03001a4 +#define ixTHM_TMON1_RDIL10_DATA 0xc03001a8 +#define ixTHM_TMON1_RDIL11_DATA 0xc03001ac +#define ixTHM_TMON1_RDIL12_DATA 0xc03001b0 +#define ixTHM_TMON1_RDIL13_DATA 0xc03001b4 +#define ixTHM_TMON1_RDIL14_DATA 0xc03001b8 +#define ixTHM_TMON1_RDIL15_DATA 0xc03001bc +#define ixTHM_TMON1_RDIR0_DATA 0xc03001c0 +#define ixTHM_TMON1_RDIR1_DATA 0xc03001c4 +#define ixTHM_TMON1_RDIR2_DATA 0xc03001c8 +#define ixTHM_TMON1_RDIR3_DATA 0xc03001cc +#define ixTHM_TMON1_RDIR4_DATA 0xc03001d0 +#define ixTHM_TMON1_RDIR5_DATA 0xc03001d4 +#define ixTHM_TMON1_RDIR6_DATA 0xc03001d8 +#define ixTHM_TMON1_RDIR7_DATA 0xc03001dc +#define ixTHM_TMON1_RDIR8_DATA 0xc03001e0 +#define ixTHM_TMON1_RDIR9_DATA 0xc03001e4 +#define ixTHM_TMON1_RDIR10_DATA 0xc03001e8 +#define ixTHM_TMON1_RDIR11_DATA 0xc03001ec +#define ixTHM_TMON1_RDIR12_DATA 0xc03001f0 +#define ixTHM_TMON1_RDIR13_DATA 0xc03001f4 +#define ixTHM_TMON1_RDIR14_DATA 0xc03001f8 +#define ixTHM_TMON1_RDIR15_DATA 0xc03001fc +#define ixTHM_TMON0_INT_DATA 0xc0300300 +#define ixTHM_TMON1_INT_DATA 0xc0300304 +#define ixTHM_TMON0_DEBUG 0xc0300310 +#define ixTHM_TMON1_DEBUG 0xc0300314 +#define ixTHM_TMON0_STATUS 0xc0300320 +#define ixTHM_TMON1_STATUS 0xc0300324 +#define ixGENERAL_PWRMGT 0xc0200000 +#define ixCNB_PWRMGT_CNTL 0xc0200004 +#define ixSCLK_PWRMGT_CNTL 0xc0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 +#define ixPWR_PCC_CONTROL 0xc0200018 +#define ixPWR_PCC_GPIO_SELECT 0xc020001c +#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 +#define ixPLL_TEST_CNTL 0xc020003c +#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 +#define ixCG_DISPLAY_GAP_CNTL 0xc0200060 +#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 +#define ixCG_ACPI_CNTL 0xc0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 +#define ixCG_ULV_PARAMETER 0xc020015c +#define ixSCLK_MIN_DIV 0xc02003ac +#define ixPWR_CKS_ENABLE 0xc020034c +#define ixPWR_CKS_CNTL 0xc0200350 +#define ixPWR_DISP_TIMER_CONTROL 0xc02003c0 +#define ixPWR_DISP_TIMER_DEBUG 0xc02003c4 +#define ixPWR_DISP_TIMER2_CONTROL 0xc02003c8 +#define ixPWR_DISP_TIMER2_DEBUG 0xc02003cc +#define ixPWR_DISP_TIMER_CONTROL2 0xc0200378 +#define ixVDDGFX_IDLE_PARAMETER 0xc020036c +#define ixVDDGFX_IDLE_CONTROL 0xc0200370 +#define ixVDDGFX_IDLE_EXIT 0xc0200374 +#define ixLCAC_MC0_CNTL 0xc0400130 +#define ixLCAC_MC0_OVR_SEL 0xc0400134 +#define ixLCAC_MC0_OVR_VAL 0xc0400138 +#define ixLCAC_MC1_CNTL 0xc040013c +#define ixLCAC_MC1_OVR_SEL 0xc0400140 +#define ixLCAC_MC1_OVR_VAL 0xc0400144 +#define ixLCAC_MC2_CNTL 0xc0400148 +#define ixLCAC_MC2_OVR_SEL 0xc040014c +#define ixLCAC_MC2_OVR_VAL 0xc0400150 +#define ixLCAC_MC3_CNTL 0xc0400154 +#define ixLCAC_MC3_OVR_SEL 0xc0400158 +#define ixLCAC_MC3_OVR_VAL 0xc040015c +#define ixLCAC_CPL_CNTL 0xc0400160 +#define ixLCAC_CPL_OVR_SEL 0xc0400164 +#define ixLCAC_CPL_OVR_VAL 0xc0400168 +#define mmROM_SMC_IND_INDEX 0x80 +#define mmROM0_ROM_SMC_IND_INDEX 0x80 +#define mmROM1_ROM_SMC_IND_INDEX 0x82 +#define mmROM2_ROM_SMC_IND_INDEX 0x84 +#define mmROM3_ROM_SMC_IND_INDEX 0x86 +#define mmROM_SMC_IND_DATA 0x81 +#define mmROM0_ROM_SMC_IND_DATA 0x81 +#define mmROM1_ROM_SMC_IND_DATA 0x83 +#define mmROM2_ROM_SMC_IND_DATA 0x85 +#define mmROM3_ROM_SMC_IND_DATA 0x87 +#define ixROM_CNTL 0xc0600000 +#define ixPAGE_MIRROR_CNTL 0xc0600004 +#define ixROM_STATUS 0xc0600008 +#define ixCGTT_ROM_CLK_CTRL0 0xc060000c +#define ixROM_INDEX 0xc0600010 +#define ixROM_DATA 0xc0600014 +#define ixROM_START 0xc0600018 +#define ixROM_SW_CNTL 0xc060001c +#define ixROM_SW_STATUS 0xc0600020 +#define ixROM_SW_COMMAND 0xc0600024 +#define ixROM_SW_DATA_1 0xc0600028 +#define ixROM_SW_DATA_2 0xc060002c +#define ixROM_SW_DATA_3 0xc0600030 +#define ixROM_SW_DATA_4 0xc0600034 +#define ixROM_SW_DATA_5 0xc0600038 +#define ixROM_SW_DATA_6 0xc060003c +#define ixROM_SW_DATA_7 0xc0600040 +#define ixROM_SW_DATA_8 0xc0600044 +#define ixROM_SW_DATA_9 0xc0600048 +#define ixROM_SW_DATA_10 0xc060004c +#define ixROM_SW_DATA_11 0xc0600050 +#define ixROM_SW_DATA_12 0xc0600054 +#define ixROM_SW_DATA_13 0xc0600058 +#define ixROM_SW_DATA_14 0xc060005c +#define ixROM_SW_DATA_15 0xc0600060 +#define ixROM_SW_DATA_16 0xc0600064 +#define ixROM_SW_DATA_17 0xc0600068 +#define ixROM_SW_DATA_18 0xc060006c +#define ixROM_SW_DATA_19 0xc0600070 +#define ixROM_SW_DATA_20 0xc0600074 +#define ixROM_SW_DATA_21 0xc0600078 +#define ixROM_SW_DATA_22 0xc060007c +#define ixROM_SW_DATA_23 0xc0600080 +#define ixROM_SW_DATA_24 0xc0600084 +#define ixROM_SW_DATA_25 0xc0600088 +#define ixROM_SW_DATA_26 0xc060008c +#define ixROM_SW_DATA_27 0xc0600090 +#define ixROM_SW_DATA_28 0xc0600094 +#define ixROM_SW_DATA_29 0xc0600098 +#define ixROM_SW_DATA_30 0xc060009c +#define ixROM_SW_DATA_31 0xc06000a0 +#define ixROM_SW_DATA_32 0xc06000a4 +#define ixROM_SW_DATA_33 0xc06000a8 +#define ixROM_SW_DATA_34 0xc06000ac +#define ixROM_SW_DATA_35 0xc06000b0 +#define ixROM_SW_DATA_36 0xc06000b4 +#define ixROM_SW_DATA_37 0xc06000b8 +#define ixROM_SW_DATA_38 0xc06000bc +#define ixROM_SW_DATA_39 0xc06000c0 +#define ixROM_SW_DATA_40 0xc06000c4 +#define ixROM_SW_DATA_41 0xc06000c8 +#define ixROM_SW_DATA_42 0xc06000cc +#define ixROM_SW_DATA_43 0xc06000d0 +#define ixROM_SW_DATA_44 0xc06000d4 +#define ixROM_SW_DATA_45 0xc06000d8 +#define ixROM_SW_DATA_46 0xc06000dc +#define ixROM_SW_DATA_47 0xc06000e0 +#define ixROM_SW_DATA_48 0xc06000e4 +#define ixROM_SW_DATA_49 0xc06000e8 +#define ixROM_SW_DATA_50 0xc06000ec +#define ixROM_SW_DATA_51 0xc06000f0 +#define ixROM_SW_DATA_52 0xc06000f4 +#define ixROM_SW_DATA_53 0xc06000f8 +#define ixROM_SW_DATA_54 0xc06000fc +#define ixROM_SW_DATA_55 0xc0600100 +#define ixROM_SW_DATA_56 0xc0600104 +#define ixROM_SW_DATA_57 0xc0600108 +#define ixROM_SW_DATA_58 0xc060010c +#define ixROM_SW_DATA_59 0xc0600110 +#define ixROM_SW_DATA_60 0xc0600114 +#define ixROM_SW_DATA_61 0xc0600118 +#define ixROM_SW_DATA_62 0xc060011c +#define ixROM_SW_DATA_63 0xc0600120 +#define ixROM_SW_DATA_64 0xc0600124 + +#endif /* SMU_7_1_2_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h new file mode 100644 index 000000000000..73bbf506b1c9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h @@ -0,0 +1,1246 @@ +/* + * SMU_7_1_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_2_ENUM_H +#define SMU_7_1_2_ENUM_H + +#define CG_SRBM_START_ADDR 0x600 +#define CG_SRBM_END_ADDR 0x8ff +#define RCU_CCF_DWORDS0 0xa0 +#define RCU_CCF_BITS0 0x1400 +#define RCU_CCF_DWORDS1 0x0 +#define RCU_CCF_BITS1 0x0 +#define RCU_SAM_BYTES 0x2c +#define RCU_SAM_RTL_BYTES 0x2c +#define RCU_SMU_BYTES 0x14 +#define RCU_SMU_RTL_BYTES 0x14 +#define SFP_CHAIN_ADDR 0x0 +#define SFP_BYTES 0x140 +#define SFP_SADR 0xc0 +#define SFP_EADR 0x1ff +#define SAMU_KEY_CHAIN_ADR 0x0 +#define SAMU_KEY_SADR 0x2a0 +#define SAMU_KEY_EADR 0x2cb +#define SMU_KEY_CHAIN_ADR 0x0 +#define SMU_KEY_SADR 0x2cc +#define SMU_KEY_EADR 0x2df +#define SMC_MSG_TEST 0x1 +#define SMC_MSG_PHY_LN_OFF 0x2 +#define SMC_MSG_PHY_LN_ON 0x3 +#define SMC_MSG_DDI_PHY_OFF 0x4 +#define SMC_MSG_DDI_PHY_ON 0x5 +#define SMC_MSG_CASCADE_PLL_OFF 0x6 +#define SMC_MSG_CASCADE_PLL_ON 0x7 +#define SMC_MSG_PWR_OFF_x16 0x8 +#define SMC_MSG_CONFIG_LCLK_DPM 0x9 +#define SMC_MSG_FLUSH_DATA_CACHE 0xa +#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb +#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc +#define SMC_MSG_CONFIG_BAPM 0xd +#define SMC_MSG_CONFIG_TDC_LIMIT 0xe +#define SMC_MSG_CONFIG_LPMx 0xf +#define SMC_MSG_CONFIG_HTC_LIMIT 0x10 +#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11 +#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12 +#define SMC_MSG_CONFIG_TDP_CNTL 0x13 +#define SMC_MSG_EN_PM_CNTL 0x14 +#define SMC_MSG_DIS_PM_CNTL 0x15 +#define SMC_MSG_CONFIG_NBDPM 0x16 +#define SMC_MSG_CONFIG_LOADLINE 0x17 +#define SMC_MSG_ADJUST_LOADLINE 0x18 +#define SMC_MSG_RESET 0x20 +#define SMC_MSG_VOLTAGE 0x25 +#define SMC_VERSION_MAJOR 0x7 +#define SMC_VERSION_MINOR 0x0 +#define SMC_HEADER_SIZE 0x40 +#define ROM_SIGNATURE 0xaa55 +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum DebugBlockId { + DBG_CLIENT_BLKID_RESERVED = 0x0, + DBG_CLIENT_BLKID_dbg = 0x1, + DBG_CLIENT_BLKID_scf2 = 0x2, + DBG_CLIENT_BLKID_mcd5 = 0x3, + DBG_CLIENT_BLKID_vmc = 0x4, + DBG_CLIENT_BLKID_sx30 = 0x5, + DBG_CLIENT_BLKID_mcd2 = 0x6, + DBG_CLIENT_BLKID_bci1 = 0x7, + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, + DBG_CLIENT_BLKID_mcc0 = 0x9, + DBG_CLIENT_BLKID_uvdf_0 = 0xa, + DBG_CLIENT_BLKID_uvdf_1 = 0xb, + DBG_CLIENT_BLKID_bci0 = 0xc, + DBG_CLIENT_BLKID_vcec0_0 = 0xd, + DBG_CLIENT_BLKID_cb100 = 0xe, + DBG_CLIENT_BLKID_cb001 = 0xf, + DBG_CLIENT_BLKID_mcd4 = 0x10, + DBG_CLIENT_BLKID_tmonw00 = 0x11, + DBG_CLIENT_BLKID_cb101 = 0x12, + DBG_CLIENT_BLKID_sx10 = 0x13, + DBG_CLIENT_BLKID_cb301 = 0x14, + DBG_CLIENT_BLKID_tmonw01 = 0x15, + DBG_CLIENT_BLKID_vcea0_0 = 0x16, + DBG_CLIENT_BLKID_vcea0_1 = 0x17, + DBG_CLIENT_BLKID_vcea0_2 = 0x18, + DBG_CLIENT_BLKID_vcea0_3 = 0x19, + DBG_CLIENT_BLKID_scf1 = 0x1a, + DBG_CLIENT_BLKID_sx20 = 0x1b, + DBG_CLIENT_BLKID_spim1 = 0x1c, + DBG_CLIENT_BLKID_pa10 = 0x1d, + DBG_CLIENT_BLKID_pa00 = 0x1e, + DBG_CLIENT_BLKID_gmcon = 0x1f, + DBG_CLIENT_BLKID_mcb = 0x20, + DBG_CLIENT_BLKID_vgt0 = 0x21, + DBG_CLIENT_BLKID_pc0 = 0x22, + DBG_CLIENT_BLKID_bci2 = 0x23, + DBG_CLIENT_BLKID_uvdb_0 = 0x24, + DBG_CLIENT_BLKID_spim3 = 0x25, + DBG_CLIENT_BLKID_cpc_0 = 0x26, + DBG_CLIENT_BLKID_cpc_1 = 0x27, + DBG_CLIENT_BLKID_uvdm_0 = 0x28, + DBG_CLIENT_BLKID_uvdm_1 = 0x29, + DBG_CLIENT_BLKID_uvdm_2 = 0x2a, + DBG_CLIENT_BLKID_uvdm_3 = 0x2b, + DBG_CLIENT_BLKID_cb000 = 0x2c, + DBG_CLIENT_BLKID_spim0 = 0x2d, + DBG_CLIENT_BLKID_mcc2 = 0x2e, + DBG_CLIENT_BLKID_ds0 = 0x2f, + DBG_CLIENT_BLKID_srbm = 0x30, + DBG_CLIENT_BLKID_ih = 0x31, + DBG_CLIENT_BLKID_sem = 0x32, + DBG_CLIENT_BLKID_sdma_0 = 0x33, + DBG_CLIENT_BLKID_sdma_1 = 0x34, + DBG_CLIENT_BLKID_hdp = 0x35, + DBG_CLIENT_BLKID_acp_0 = 0x36, + DBG_CLIENT_BLKID_acp_1 = 0x37, + DBG_CLIENT_BLKID_cb200 = 0x38, + DBG_CLIENT_BLKID_scf3 = 0x39, + DBG_CLIENT_BLKID_vceb1_0 = 0x3a, + DBG_CLIENT_BLKID_vcea1_0 = 0x3b, + DBG_CLIENT_BLKID_vcea1_1 = 0x3c, + DBG_CLIENT_BLKID_vcea1_2 = 0x3d, + DBG_CLIENT_BLKID_vcea1_3 = 0x3e, + DBG_CLIENT_BLKID_bci3 = 0x3f, + DBG_CLIENT_BLKID_mcd0 = 0x40, + DBG_CLIENT_BLKID_pa11 = 0x41, + DBG_CLIENT_BLKID_pa01 = 0x42, + DBG_CLIENT_BLKID_cb201 = 0x43, + DBG_CLIENT_BLKID_spim2 = 0x44, + DBG_CLIENT_BLKID_vgt2 = 0x45, + DBG_CLIENT_BLKID_pc2 = 0x46, + DBG_CLIENT_BLKID_smu_0 = 0x47, + DBG_CLIENT_BLKID_smu_1 = 0x48, + DBG_CLIENT_BLKID_smu_2 = 0x49, + DBG_CLIENT_BLKID_cb1 = 0x4a, + DBG_CLIENT_BLKID_ia0 = 0x4b, + DBG_CLIENT_BLKID_wd = 0x4c, + DBG_CLIENT_BLKID_ia1 = 0x4d, + DBG_CLIENT_BLKID_vcec1_0 = 0x4e, + DBG_CLIENT_BLKID_scf0 = 0x4f, + DBG_CLIENT_BLKID_vgt1 = 0x50, + DBG_CLIENT_BLKID_pc1 = 0x51, + DBG_CLIENT_BLKID_cb0 = 0x52, + DBG_CLIENT_BLKID_gdc_one_0 = 0x53, + DBG_CLIENT_BLKID_gdc_one_1 = 0x54, + DBG_CLIENT_BLKID_gdc_one_2 = 0x55, + DBG_CLIENT_BLKID_gdc_one_3 = 0x56, + DBG_CLIENT_BLKID_gdc_one_4 = 0x57, + DBG_CLIENT_BLKID_gdc_one_5 = 0x58, + DBG_CLIENT_BLKID_gdc_one_6 = 0x59, + DBG_CLIENT_BLKID_gdc_one_7 = 0x5a, + DBG_CLIENT_BLKID_gdc_one_8 = 0x5b, + DBG_CLIENT_BLKID_gdc_one_9 = 0x5c, + DBG_CLIENT_BLKID_gdc_one_10 = 0x5d, + DBG_CLIENT_BLKID_gdc_one_11 = 0x5e, + DBG_CLIENT_BLKID_gdc_one_12 = 0x5f, + DBG_CLIENT_BLKID_gdc_one_13 = 0x60, + DBG_CLIENT_BLKID_gdc_one_14 = 0x61, + DBG_CLIENT_BLKID_gdc_one_15 = 0x62, + DBG_CLIENT_BLKID_gdc_one_16 = 0x63, + DBG_CLIENT_BLKID_gdc_one_17 = 0x64, + DBG_CLIENT_BLKID_gdc_one_18 = 0x65, + DBG_CLIENT_BLKID_gdc_one_19 = 0x66, + DBG_CLIENT_BLKID_gdc_one_20 = 0x67, + DBG_CLIENT_BLKID_gdc_one_21 = 0x68, + DBG_CLIENT_BLKID_gdc_one_22 = 0x69, + DBG_CLIENT_BLKID_gdc_one_23 = 0x6a, + DBG_CLIENT_BLKID_gdc_one_24 = 0x6b, + DBG_CLIENT_BLKID_gdc_one_25 = 0x6c, + DBG_CLIENT_BLKID_gdc_one_26 = 0x6d, + DBG_CLIENT_BLKID_gdc_one_27 = 0x6e, + DBG_CLIENT_BLKID_gdc_one_28 = 0x6f, + DBG_CLIENT_BLKID_gdc_one_29 = 0x70, + DBG_CLIENT_BLKID_gdc_one_30 = 0x71, + DBG_CLIENT_BLKID_gdc_one_31 = 0x72, + DBG_CLIENT_BLKID_gdc_one_32 = 0x73, + DBG_CLIENT_BLKID_gdc_one_33 = 0x74, + DBG_CLIENT_BLKID_gdc_one_34 = 0x75, + DBG_CLIENT_BLKID_gdc_one_35 = 0x76, + DBG_CLIENT_BLKID_vceb0_0 = 0x77, + DBG_CLIENT_BLKID_vgt3 = 0x78, + DBG_CLIENT_BLKID_pc3 = 0x79, + DBG_CLIENT_BLKID_mcd3 = 0x7a, + DBG_CLIENT_BLKID_uvdu_0 = 0x7b, + DBG_CLIENT_BLKID_uvdu_1 = 0x7c, + DBG_CLIENT_BLKID_uvdu_2 = 0x7d, + DBG_CLIENT_BLKID_uvdu_3 = 0x7e, + DBG_CLIENT_BLKID_uvdu_4 = 0x7f, + DBG_CLIENT_BLKID_uvdu_5 = 0x80, + DBG_CLIENT_BLKID_uvdu_6 = 0x81, + DBG_CLIENT_BLKID_cb300 = 0x82, + DBG_CLIENT_BLKID_mcd1 = 0x83, + DBG_CLIENT_BLKID_sx00 = 0x84, + DBG_CLIENT_BLKID_uvdc_0 = 0x85, + DBG_CLIENT_BLKID_uvdc_1 = 0x86, + DBG_CLIENT_BLKID_mcc3 = 0x87, + DBG_CLIENT_BLKID_cpg_0 = 0x88, + DBG_CLIENT_BLKID_cpg_1 = 0x89, + DBG_CLIENT_BLKID_gck = 0x8a, + DBG_CLIENT_BLKID_mcc1 = 0x8b, + DBG_CLIENT_BLKID_cpf_0 = 0x8c, + DBG_CLIENT_BLKID_cpf_1 = 0x8d, + DBG_CLIENT_BLKID_rlc = 0x8e, + DBG_CLIENT_BLKID_grbm = 0x8f, + DBG_CLIENT_BLKID_sammsp = 0x90, + DBG_CLIENT_BLKID_dci_pg = 0x91, + DBG_CLIENT_BLKID_dci_0 = 0x92, + DBG_CLIENT_BLKID_dccg0_0 = 0x93, + DBG_CLIENT_BLKID_dccg0_1 = 0x94, + DBG_CLIENT_BLKID_dcfe01_0 = 0x95, + DBG_CLIENT_BLKID_dcfe02_0 = 0x96, + DBG_CLIENT_BLKID_dcfe03_0 = 0x97, + DBG_CLIENT_BLKID_dcfe04_0 = 0x98, + DBG_CLIENT_BLKID_dcfe05_0 = 0x99, + DBG_CLIENT_BLKID_dcfe06_0 = 0x9a, + DBG_CLIENT_BLKID_RESERVED_LAST = 0x9b, +} DebugBlockId; +typedef enum DebugBlockId_OLD { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_AVP = 0xd, + DBG_BLOCK_ID_GMCON = 0xe, + DBG_BLOCK_ID_SMU = 0xf, + DBG_BLOCK_ID_DMA0 = 0x10, + DBG_BLOCK_ID_DMA1 = 0x11, + DBG_BLOCK_ID_SPIM = 0x12, + DBG_BLOCK_ID_GDS = 0x13, + DBG_BLOCK_ID_SPIS = 0x14, + DBG_BLOCK_ID_UNUSED0 = 0x15, + DBG_BLOCK_ID_PA0 = 0x16, + DBG_BLOCK_ID_PA1 = 0x17, + DBG_BLOCK_ID_CP0 = 0x18, + DBG_BLOCK_ID_CP1 = 0x19, + DBG_BLOCK_ID_CP2 = 0x1a, + DBG_BLOCK_ID_UNUSED1 = 0x1b, + DBG_BLOCK_ID_UVDU = 0x1c, + DBG_BLOCK_ID_UVDM = 0x1d, + DBG_BLOCK_ID_VCE = 0x1e, + DBG_BLOCK_ID_UNUSED2 = 0x1f, + DBG_BLOCK_ID_VGT0 = 0x20, + DBG_BLOCK_ID_VGT1 = 0x21, + DBG_BLOCK_ID_IA = 0x22, + DBG_BLOCK_ID_UNUSED3 = 0x23, + DBG_BLOCK_ID_SCT0 = 0x24, + DBG_BLOCK_ID_SCT1 = 0x25, + DBG_BLOCK_ID_SPM0 = 0x26, + DBG_BLOCK_ID_SPM1 = 0x27, + DBG_BLOCK_ID_TCAA = 0x28, + DBG_BLOCK_ID_TCAB = 0x29, + DBG_BLOCK_ID_TCCA = 0x2a, + DBG_BLOCK_ID_TCCB = 0x2b, + DBG_BLOCK_ID_MCC0 = 0x2c, + DBG_BLOCK_ID_MCC1 = 0x2d, + DBG_BLOCK_ID_MCC2 = 0x2e, + DBG_BLOCK_ID_MCC3 = 0x2f, + DBG_BLOCK_ID_SX0 = 0x30, + DBG_BLOCK_ID_SX1 = 0x31, + DBG_BLOCK_ID_SX2 = 0x32, + DBG_BLOCK_ID_SX3 = 0x33, + DBG_BLOCK_ID_UNUSED4 = 0x34, + DBG_BLOCK_ID_UNUSED5 = 0x35, + DBG_BLOCK_ID_UNUSED6 = 0x36, + DBG_BLOCK_ID_UNUSED7 = 0x37, + DBG_BLOCK_ID_PC0 = 0x38, + DBG_BLOCK_ID_PC1 = 0x39, + DBG_BLOCK_ID_UNUSED8 = 0x3a, + DBG_BLOCK_ID_UNUSED9 = 0x3b, + DBG_BLOCK_ID_UNUSED10 = 0x3c, + DBG_BLOCK_ID_UNUSED11 = 0x3d, + DBG_BLOCK_ID_MCB = 0x3e, + DBG_BLOCK_ID_UNUSED12 = 0x3f, + DBG_BLOCK_ID_SCB0 = 0x40, + DBG_BLOCK_ID_SCB1 = 0x41, + DBG_BLOCK_ID_UNUSED13 = 0x42, + DBG_BLOCK_ID_UNUSED14 = 0x43, + DBG_BLOCK_ID_SCF0 = 0x44, + DBG_BLOCK_ID_SCF1 = 0x45, + DBG_BLOCK_ID_UNUSED15 = 0x46, + DBG_BLOCK_ID_UNUSED16 = 0x47, + DBG_BLOCK_ID_BCI0 = 0x48, + DBG_BLOCK_ID_BCI1 = 0x49, + DBG_BLOCK_ID_BCI2 = 0x4a, + DBG_BLOCK_ID_BCI3 = 0x4b, + DBG_BLOCK_ID_UNUSED17 = 0x4c, + DBG_BLOCK_ID_UNUSED18 = 0x4d, + DBG_BLOCK_ID_UNUSED19 = 0x4e, + DBG_BLOCK_ID_UNUSED20 = 0x4f, + DBG_BLOCK_ID_CB00 = 0x50, + DBG_BLOCK_ID_CB01 = 0x51, + DBG_BLOCK_ID_CB02 = 0x52, + DBG_BLOCK_ID_CB03 = 0x53, + DBG_BLOCK_ID_CB04 = 0x54, + DBG_BLOCK_ID_UNUSED21 = 0x55, + DBG_BLOCK_ID_UNUSED22 = 0x56, + DBG_BLOCK_ID_UNUSED23 = 0x57, + DBG_BLOCK_ID_CB10 = 0x58, + DBG_BLOCK_ID_CB11 = 0x59, + DBG_BLOCK_ID_CB12 = 0x5a, + DBG_BLOCK_ID_CB13 = 0x5b, + DBG_BLOCK_ID_CB14 = 0x5c, + DBG_BLOCK_ID_UNUSED24 = 0x5d, + DBG_BLOCK_ID_UNUSED25 = 0x5e, + DBG_BLOCK_ID_UNUSED26 = 0x5f, + DBG_BLOCK_ID_TCP0 = 0x60, + DBG_BLOCK_ID_TCP1 = 0x61, + DBG_BLOCK_ID_TCP2 = 0x62, + DBG_BLOCK_ID_TCP3 = 0x63, + DBG_BLOCK_ID_TCP4 = 0x64, + DBG_BLOCK_ID_TCP5 = 0x65, + DBG_BLOCK_ID_TCP6 = 0x66, + DBG_BLOCK_ID_TCP7 = 0x67, + DBG_BLOCK_ID_TCP8 = 0x68, + DBG_BLOCK_ID_TCP9 = 0x69, + DBG_BLOCK_ID_TCP10 = 0x6a, + DBG_BLOCK_ID_TCP11 = 0x6b, + DBG_BLOCK_ID_TCP12 = 0x6c, + DBG_BLOCK_ID_TCP13 = 0x6d, + DBG_BLOCK_ID_TCP14 = 0x6e, + DBG_BLOCK_ID_TCP15 = 0x6f, + DBG_BLOCK_ID_TCP16 = 0x70, + DBG_BLOCK_ID_TCP17 = 0x71, + DBG_BLOCK_ID_TCP18 = 0x72, + DBG_BLOCK_ID_TCP19 = 0x73, + DBG_BLOCK_ID_TCP20 = 0x74, + DBG_BLOCK_ID_TCP21 = 0x75, + DBG_BLOCK_ID_TCP22 = 0x76, + DBG_BLOCK_ID_TCP23 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, + DBG_BLOCK_ID_DB00 = 0x80, + DBG_BLOCK_ID_DB01 = 0x81, + DBG_BLOCK_ID_DB02 = 0x82, + DBG_BLOCK_ID_DB03 = 0x83, + DBG_BLOCK_ID_DB04 = 0x84, + DBG_BLOCK_ID_UNUSED27 = 0x85, + DBG_BLOCK_ID_UNUSED28 = 0x86, + DBG_BLOCK_ID_UNUSED29 = 0x87, + DBG_BLOCK_ID_DB10 = 0x88, + DBG_BLOCK_ID_DB11 = 0x89, + DBG_BLOCK_ID_DB12 = 0x8a, + DBG_BLOCK_ID_DB13 = 0x8b, + DBG_BLOCK_ID_DB14 = 0x8c, + DBG_BLOCK_ID_UNUSED30 = 0x8d, + DBG_BLOCK_ID_UNUSED31 = 0x8e, + DBG_BLOCK_ID_UNUSED32 = 0x8f, + DBG_BLOCK_ID_TCC0 = 0x90, + DBG_BLOCK_ID_TCC1 = 0x91, + DBG_BLOCK_ID_TCC2 = 0x92, + DBG_BLOCK_ID_TCC3 = 0x93, + DBG_BLOCK_ID_TCC4 = 0x94, + DBG_BLOCK_ID_TCC5 = 0x95, + DBG_BLOCK_ID_TCC6 = 0x96, + DBG_BLOCK_ID_TCC7 = 0x97, + DBG_BLOCK_ID_SPS00 = 0x98, + DBG_BLOCK_ID_SPS01 = 0x99, + DBG_BLOCK_ID_SPS02 = 0x9a, + DBG_BLOCK_ID_SPS10 = 0x9b, + DBG_BLOCK_ID_SPS11 = 0x9c, + DBG_BLOCK_ID_SPS12 = 0x9d, + DBG_BLOCK_ID_UNUSED33 = 0x9e, + DBG_BLOCK_ID_UNUSED34 = 0x9f, + DBG_BLOCK_ID_TA00 = 0xa0, + DBG_BLOCK_ID_TA01 = 0xa1, + DBG_BLOCK_ID_TA02 = 0xa2, + DBG_BLOCK_ID_TA03 = 0xa3, + DBG_BLOCK_ID_TA04 = 0xa4, + DBG_BLOCK_ID_TA05 = 0xa5, + DBG_BLOCK_ID_TA06 = 0xa6, + DBG_BLOCK_ID_TA07 = 0xa7, + DBG_BLOCK_ID_TA08 = 0xa8, + DBG_BLOCK_ID_TA09 = 0xa9, + DBG_BLOCK_ID_TA0A = 0xaa, + DBG_BLOCK_ID_TA0B = 0xab, + DBG_BLOCK_ID_UNUSED35 = 0xac, + DBG_BLOCK_ID_UNUSED36 = 0xad, + DBG_BLOCK_ID_UNUSED37 = 0xae, + DBG_BLOCK_ID_UNUSED38 = 0xaf, + DBG_BLOCK_ID_TA10 = 0xb0, + DBG_BLOCK_ID_TA11 = 0xb1, + DBG_BLOCK_ID_TA12 = 0xb2, + DBG_BLOCK_ID_TA13 = 0xb3, + DBG_BLOCK_ID_TA14 = 0xb4, + DBG_BLOCK_ID_TA15 = 0xb5, + DBG_BLOCK_ID_TA16 = 0xb6, + DBG_BLOCK_ID_TA17 = 0xb7, + DBG_BLOCK_ID_TA18 = 0xb8, + DBG_BLOCK_ID_TA19 = 0xb9, + DBG_BLOCK_ID_TA1A = 0xba, + DBG_BLOCK_ID_TA1B = 0xbb, + DBG_BLOCK_ID_UNUSED39 = 0xbc, + DBG_BLOCK_ID_UNUSED40 = 0xbd, + DBG_BLOCK_ID_UNUSED41 = 0xbe, + DBG_BLOCK_ID_UNUSED42 = 0xbf, + DBG_BLOCK_ID_TD00 = 0xc0, + DBG_BLOCK_ID_TD01 = 0xc1, + DBG_BLOCK_ID_TD02 = 0xc2, + DBG_BLOCK_ID_TD03 = 0xc3, + DBG_BLOCK_ID_TD04 = 0xc4, + DBG_BLOCK_ID_TD05 = 0xc5, + DBG_BLOCK_ID_TD06 = 0xc6, + DBG_BLOCK_ID_TD07 = 0xc7, + DBG_BLOCK_ID_TD08 = 0xc8, + DBG_BLOCK_ID_TD09 = 0xc9, + DBG_BLOCK_ID_TD0A = 0xca, + DBG_BLOCK_ID_TD0B = 0xcb, + DBG_BLOCK_ID_UNUSED43 = 0xcc, + DBG_BLOCK_ID_UNUSED44 = 0xcd, + DBG_BLOCK_ID_UNUSED45 = 0xce, + DBG_BLOCK_ID_UNUSED46 = 0xcf, + DBG_BLOCK_ID_TD10 = 0xd0, + DBG_BLOCK_ID_TD11 = 0xd1, + DBG_BLOCK_ID_TD12 = 0xd2, + DBG_BLOCK_ID_TD13 = 0xd3, + DBG_BLOCK_ID_TD14 = 0xd4, + DBG_BLOCK_ID_TD15 = 0xd5, + DBG_BLOCK_ID_TD16 = 0xd6, + DBG_BLOCK_ID_TD17 = 0xd7, + DBG_BLOCK_ID_TD18 = 0xd8, + DBG_BLOCK_ID_TD19 = 0xd9, + DBG_BLOCK_ID_TD1A = 0xda, + DBG_BLOCK_ID_TD1B = 0xdb, + DBG_BLOCK_ID_UNUSED47 = 0xdc, + DBG_BLOCK_ID_UNUSED48 = 0xdd, + DBG_BLOCK_ID_UNUSED49 = 0xde, + DBG_BLOCK_ID_UNUSED50 = 0xdf, + DBG_BLOCK_ID_MCD0 = 0xe0, + DBG_BLOCK_ID_MCD1 = 0xe1, + DBG_BLOCK_ID_MCD2 = 0xe2, + DBG_BLOCK_ID_MCD3 = 0xe3, + DBG_BLOCK_ID_MCD4 = 0xe4, + DBG_BLOCK_ID_MCD5 = 0xe5, + DBG_BLOCK_ID_UNUSED51 = 0xe6, + DBG_BLOCK_ID_UNUSED52 = 0xe7, +} DebugBlockId_OLD; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_CG_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_GMCON_BY2 = 0x7, + DBG_BLOCK_ID_DMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_SPIS_BY2 = 0xa, + DBG_BLOCK_ID_PA0_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_UVDU_BY2 = 0xe, + DBG_BLOCK_ID_VCE_BY2 = 0xf, + DBG_BLOCK_ID_VGT0_BY2 = 0x10, + DBG_BLOCK_ID_IA_BY2 = 0x11, + DBG_BLOCK_ID_SCT0_BY2 = 0x12, + DBG_BLOCK_ID_SPM0_BY2 = 0x13, + DBG_BLOCK_ID_TCAA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC0_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_SX0_BY2 = 0x18, + DBG_BLOCK_ID_SX2_BY2 = 0x19, + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, + DBG_BLOCK_ID_PC0_BY2 = 0x1c, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, + DBG_BLOCK_ID_MCB_BY2 = 0x1f, + DBG_BLOCK_ID_SCB0_BY2 = 0x20, + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, + DBG_BLOCK_ID_SCF0_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, + DBG_BLOCK_ID_BCI0_BY2 = 0x24, + DBG_BLOCK_ID_BCI2_BY2 = 0x25, + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, + DBG_BLOCK_ID_CB00_BY2 = 0x28, + DBG_BLOCK_ID_CB02_BY2 = 0x29, + DBG_BLOCK_ID_CB04_BY2 = 0x2a, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, + DBG_BLOCK_ID_CB10_BY2 = 0x2c, + DBG_BLOCK_ID_CB12_BY2 = 0x2d, + DBG_BLOCK_ID_CB14_BY2 = 0x2e, + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, + DBG_BLOCK_ID_TCP0_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_DB00_BY2 = 0x40, + DBG_BLOCK_ID_DB02_BY2 = 0x41, + DBG_BLOCK_ID_DB04_BY2 = 0x42, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, + DBG_BLOCK_ID_DB10_BY2 = 0x44, + DBG_BLOCK_ID_DB12_BY2 = 0x45, + DBG_BLOCK_ID_DB14_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, + DBG_BLOCK_ID_TCC0_BY2 = 0x48, + DBG_BLOCK_ID_TCC2_BY2 = 0x49, + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, + DBG_BLOCK_ID_TA00_BY2 = 0x50, + DBG_BLOCK_ID_TA02_BY2 = 0x51, + DBG_BLOCK_ID_TA04_BY2 = 0x52, + DBG_BLOCK_ID_TA06_BY2 = 0x53, + DBG_BLOCK_ID_TA08_BY2 = 0x54, + DBG_BLOCK_ID_TA0A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, + DBG_BLOCK_ID_TA10_BY2 = 0x58, + DBG_BLOCK_ID_TA12_BY2 = 0x59, + DBG_BLOCK_ID_TA14_BY2 = 0x5a, + DBG_BLOCK_ID_TA16_BY2 = 0x5b, + DBG_BLOCK_ID_TA18_BY2 = 0x5c, + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, + DBG_BLOCK_ID_TD00_BY2 = 0x60, + DBG_BLOCK_ID_TD02_BY2 = 0x61, + DBG_BLOCK_ID_TD04_BY2 = 0x62, + DBG_BLOCK_ID_TD06_BY2 = 0x63, + DBG_BLOCK_ID_TD08_BY2 = 0x64, + DBG_BLOCK_ID_TD0A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, + DBG_BLOCK_ID_TD10_BY2 = 0x68, + DBG_BLOCK_ID_TD12_BY2 = 0x69, + DBG_BLOCK_ID_TD14_BY2 = 0x6a, + DBG_BLOCK_ID_TD16_BY2 = 0x6b, + DBG_BLOCK_ID_TD18_BY2 = 0x6c, + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, + DBG_BLOCK_ID_MCD0_BY2 = 0x70, + DBG_BLOCK_ID_MCD2_BY2 = 0x71, + DBG_BLOCK_ID_MCD4_BY2 = 0x72, + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_CG_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_DMA0_BY4 = 0x4, + DBG_BLOCK_ID_SPIS_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UVDU_BY4 = 0x7, + DBG_BLOCK_ID_VGT0_BY4 = 0x8, + DBG_BLOCK_ID_SCT0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC0_BY4 = 0xb, + DBG_BLOCK_ID_SX0_BY4 = 0xc, + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, + DBG_BLOCK_ID_PC0_BY4 = 0xe, + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, + DBG_BLOCK_ID_SCB0_BY4 = 0x10, + DBG_BLOCK_ID_SCF0_BY4 = 0x11, + DBG_BLOCK_ID_BCI0_BY4 = 0x12, + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, + DBG_BLOCK_ID_CB00_BY4 = 0x14, + DBG_BLOCK_ID_CB04_BY4 = 0x15, + DBG_BLOCK_ID_CB10_BY4 = 0x16, + DBG_BLOCK_ID_CB14_BY4 = 0x17, + DBG_BLOCK_ID_TCP0_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_DB_BY4 = 0x20, + DBG_BLOCK_ID_DB04_BY4 = 0x21, + DBG_BLOCK_ID_DB10_BY4 = 0x22, + DBG_BLOCK_ID_DB14_BY4 = 0x23, + DBG_BLOCK_ID_TCC0_BY4 = 0x24, + DBG_BLOCK_ID_TCC4_BY4 = 0x25, + DBG_BLOCK_ID_SPS00_BY4 = 0x26, + DBG_BLOCK_ID_SPS11_BY4 = 0x27, + DBG_BLOCK_ID_TA00_BY4 = 0x28, + DBG_BLOCK_ID_TA04_BY4 = 0x29, + DBG_BLOCK_ID_TA08_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, + DBG_BLOCK_ID_TA10_BY4 = 0x2c, + DBG_BLOCK_ID_TA14_BY4 = 0x2d, + DBG_BLOCK_ID_TA18_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, + DBG_BLOCK_ID_TD00_BY4 = 0x30, + DBG_BLOCK_ID_TD04_BY4 = 0x31, + DBG_BLOCK_ID_TD08_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, + DBG_BLOCK_ID_TD10_BY4 = 0x34, + DBG_BLOCK_ID_TD14_BY4 = 0x35, + DBG_BLOCK_ID_TD18_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, + DBG_BLOCK_ID_MCD0_BY4 = 0x38, + DBG_BLOCK_ID_MCD4_BY4 = 0x39, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_DMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_VGT0_BY8 = 0x4, + DBG_BLOCK_ID_TCAA_BY8 = 0x5, + DBG_BLOCK_ID_SX0_BY8 = 0x6, + DBG_BLOCK_ID_PC0_BY8 = 0x7, + DBG_BLOCK_ID_SCB0_BY8 = 0x8, + DBG_BLOCK_ID_BCI0_BY8 = 0x9, + DBG_BLOCK_ID_CB00_BY8 = 0xa, + DBG_BLOCK_ID_CB10_BY8 = 0xb, + DBG_BLOCK_ID_TCP0_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_DB00_BY8 = 0x10, + DBG_BLOCK_ID_DB10_BY8 = 0x11, + DBG_BLOCK_ID_TCC0_BY8 = 0x12, + DBG_BLOCK_ID_SPS00_BY8 = 0x13, + DBG_BLOCK_ID_TA00_BY8 = 0x14, + DBG_BLOCK_ID_TA08_BY8 = 0x15, + DBG_BLOCK_ID_TA10_BY8 = 0x16, + DBG_BLOCK_ID_TA18_BY8 = 0x17, + DBG_BLOCK_ID_TD00_BY8 = 0x18, + DBG_BLOCK_ID_TD08_BY8 = 0x19, + DBG_BLOCK_ID_TD10_BY8 = 0x1a, + DBG_BLOCK_ID_TD18_BY8 = 0x1b, + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_DMA0_BY16 = 0x1, + DBG_BLOCK_ID_VGT0_BY16 = 0x2, + DBG_BLOCK_ID_SX0_BY16 = 0x3, + DBG_BLOCK_ID_SCB0_BY16 = 0x4, + DBG_BLOCK_ID_CB00_BY16 = 0x5, + DBG_BLOCK_ID_TCP0_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_DB00_BY16 = 0x8, + DBG_BLOCK_ID_TCC0_BY16 = 0x9, + DBG_BLOCK_ID_TA00_BY16 = 0xa, + DBG_BLOCK_ID_TA10_BY16 = 0xb, + DBG_BLOCK_ID_TD00_BY16 = 0xc, + DBG_BLOCK_ID_TD10_BY16 = 0xd, + DBG_BLOCK_ID_MCD0_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* SMU_7_1_2_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h new file mode 100644 index 000000000000..518fd02e9d35 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h @@ -0,0 +1,5834 @@ +/* + * SMU_7_1_2 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_7_1_2_SH_MASK_H +#define SMU_7_1_2_SH_MASK_H + +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f +#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 +#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f +#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 +#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f +#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 +#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 +#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 +#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f +#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 +#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 +#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 +#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 +#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 +#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 +#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 +#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 +#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 +#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 +#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 +#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 +#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000 +#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 +#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 +#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff +#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 +#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 +#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 +#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 +#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 +#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc +#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 +#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 +#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 +#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 +#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 +#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff +#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 +#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 +#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 +#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 +#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 +#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 +#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 +#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 +#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 +#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc +#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 +#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c +#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 +#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d +#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 +#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 +#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff +#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 +#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 +#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 +#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 +#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 +#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 +#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 +#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 +#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 +#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 +#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 +#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 +#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 +#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 +#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 +#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 +#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 +#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 +#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 +#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1 +#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6 +#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 +#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa +#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff +#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 +#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 +#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 +#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff +#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 +#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 +#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 +#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f +#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 +#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 +#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa +#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 +#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 +#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 +#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 +#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 +#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b +#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000 +#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf +#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_0__SMC_RESP_MASK 0xffff +#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_1__SMC_RESP_MASK 0xffff +#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_2__SMC_RESP_MASK 0xffff +#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_3__SMC_RESP_MASK 0xffff +#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_4__SMC_RESP_MASK 0xffff +#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_5__SMC_RESP_MASK 0xffff +#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_6__SMC_RESP_MASK 0xffff +#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_7__SMC_RESP_MASK 0xffff +#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_8__SMC_RESP_MASK 0xffff +#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_9__SMC_RESP_MASK 0xffff +#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_10__SMC_RESP_MASK 0xffff +#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 +#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff +#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 +#define SMC_RESP_11__SMC_RESP_MASK 0xffff +#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 +#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff +#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 +#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 +#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 +#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 +#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 +#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 +#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 +#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 +#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff +#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 +#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding_MASK 0x2 +#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding__SHIFT 0x1 +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff +#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 +#define SMC_PC_C__smc_pc_c_MASK 0xffffffff +#define SMC_PC_C__smc_pc_c__SHIFT 0x0 +#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff +#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1 +#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0 +#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4 +#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff +#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 +#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff +#define GPIOPAD_A__GPIO_A__SHIFT 0x0 +#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff +#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0 +#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff +#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000 +#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000 +#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f +#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff +#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000 +#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000 +#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000 +#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f +#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff +#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000 +#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff +#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000 +#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff +#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000 +#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40 +#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6 +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff +#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0 +#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff +#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 +#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff +#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 +#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff +#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 +#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff +#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 +#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 +#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 +#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 +#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8 +#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3 +#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 +#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 +#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 +#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 +#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 +#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 +#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa +#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 +#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 +#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 +#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 +#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 +#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 +#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 +#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 +#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 +#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 +#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 +#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 +#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 +#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 +#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 +#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 +#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 +#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 +#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 +#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 +#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 +#define RCU_VIRT_RESET_REQ__VF_MASK 0xffff +#define RCU_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define RCU_VIRT_RESET_REQ__PF_MASK 0x80000000 +#define RCU_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 +#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 +#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 +#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 +#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 +#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 +#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 +#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 +#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 +#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 +#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 +#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 +#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 +#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 +#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 +#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000 +#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000 +#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000 +#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10 +#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000 +#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000 +#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000 +#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13 +#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000 +#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000 +#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16 +#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000 +#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17 +#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000 +#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18 +#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000 +#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19 +#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000 +#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 +#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 +#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc +#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 +#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 +#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 +#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 +#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 +#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 +#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 +#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c +#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 +#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d +#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff +#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 +#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 +#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 +#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 +#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 +#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 +#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe +#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 +#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e +#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e +#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 +#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 +#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 +#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 +#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 +#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 +#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 +#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 +#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 +#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 +#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 +#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 +#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a +#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 +#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 +#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 +#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 +#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 +#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 +#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 +#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 +#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6 +#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1 +#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10 +#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4 +#define CC_HARVEST_FUSES__ACP_DISABLE_MASK 0x40 +#define CC_HARVEST_FUSES__ACP_DISABLE__SHIFT 0x6 +#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00 +#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8 +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff +#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 +#define SMU_STATUS__SMU_DONE_MASK 0x1 +#define SMU_STATUS__SMU_DONE__SHIFT 0x0 +#define SMU_STATUS__SMU_PASS_MASK 0x2 +#define SMU_STATUS__SMU_PASS__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 +#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 +#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 +#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 +#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 +#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 +#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 +#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 +#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 +#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 +#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 +#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 +#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff +#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 +#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 +#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f +#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff +#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 +#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe +#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 +#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 +#define TDC_STATUS__VDD_Boost_MASK 0xff +#define TDC_STATUS__VDD_Boost__SHIFT 0x0 +#define TDC_STATUS__VDD_Throttle_MASK 0xff00 +#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 +#define TDC_STATUS__VDDC_Boost_MASK 0xff0000 +#define TDC_STATUS__VDDC_Boost__SHIFT 0x10 +#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000 +#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18 +#define TDC_MV_AVERAGE__IDD_MASK 0xffff +#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 +#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000 +#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10 +#define TDC_VRM_LIMIT__IDD_MASK 0xffff +#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 +#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000 +#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10 +#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 +#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 +#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 +#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 +#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 +#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 +#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 +#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 +#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 +#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 +#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20 +#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5 +#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40 +#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6 +#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 +#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 +#define FEATURE_STATUS__BAPM_ON_MASK 0x100 +#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 +#define FEATURE_STATUS__LPMX_ON_MASK 0x200 +#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 +#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 +#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa +#define FEATURE_STATUS__LHTC_ON_MASK 0x800 +#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb +#define FEATURE_STATUS__VPC_ON_MASK 0x1000 +#define FEATURE_STATUS__VPC_ON__SHIFT 0xc +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 +#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd +#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 +#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe +#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 +#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf +#define FEATURE_STATUS__AVS_ON_MASK 0x10000 +#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 +#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 +#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 +#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 +#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 +#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 +#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 +#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 +#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 +#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 +#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 +#define FEATURE_STATUS__RESERVED_MASK 0xffc00000 +#define FEATURE_STATUS__RESERVED__SHIFT 0x16 +#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff +#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0 +#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff +#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0 +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff +#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0 +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff +#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0 +#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff +#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0 +#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff +#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0 +#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff +#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0 +#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff +#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0 +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff +#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0 +#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff +#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0 +#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff +#define DPM_TABLE_28__SystemFlags__SHIFT 0x0 +#define DPM_TABLE_29__VRConfig_MASK 0xffffffff +#define DPM_TABLE_29__VRConfig__SHIFT 0x0 +#define DPM_TABLE_30__SmioMask1_MASK 0xffffffff +#define DPM_TABLE_30__SmioMask1__SHIFT 0x0 +#define DPM_TABLE_31__SmioMask2_MASK 0xffffffff +#define DPM_TABLE_31__SmioMask2__SHIFT 0x0 +#define DPM_TABLE_32__SmioTable1_Pattern_0_padding_MASK 0xff +#define DPM_TABLE_32__SmioTable1_Pattern_0_padding__SHIFT 0x0 +#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio_MASK 0xff00 +#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio__SHIFT 0x8 +#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_33__SmioTable1_Pattern_1_padding_MASK 0xff +#define DPM_TABLE_33__SmioTable1_Pattern_1_padding__SHIFT 0x0 +#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio_MASK 0xff00 +#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio__SHIFT 0x8 +#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_34__SmioTable1_Pattern_2_padding_MASK 0xff +#define DPM_TABLE_34__SmioTable1_Pattern_2_padding__SHIFT 0x0 +#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio_MASK 0xff00 +#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio__SHIFT 0x8 +#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_35__SmioTable1_Pattern_3_padding_MASK 0xff +#define DPM_TABLE_35__SmioTable1_Pattern_3_padding__SHIFT 0x0 +#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio_MASK 0xff00 +#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio__SHIFT 0x8 +#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_36__SmioTable2_Pattern_0_padding_MASK 0xff +#define DPM_TABLE_36__SmioTable2_Pattern_0_padding__SHIFT 0x0 +#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio_MASK 0xff00 +#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio__SHIFT 0x8 +#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage_MASK 0xffff0000 +#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage__SHIFT 0x10 +#define DPM_TABLE_37__SmioTable2_Pattern_1_padding_MASK 0xff +#define DPM_TABLE_37__SmioTable2_Pattern_1_padding__SHIFT 0x0 +#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio_MASK 0xff00 +#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio__SHIFT 0x8 +#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage_MASK 0xffff0000 +#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage__SHIFT 0x10 +#define DPM_TABLE_38__SmioTable2_Pattern_2_padding_MASK 0xff +#define DPM_TABLE_38__SmioTable2_Pattern_2_padding__SHIFT 0x0 +#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio_MASK 0xff00 +#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio__SHIFT 0x8 +#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage_MASK 0xffff0000 +#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage__SHIFT 0x10 +#define DPM_TABLE_39__SmioTable2_Pattern_3_padding_MASK 0xff +#define DPM_TABLE_39__SmioTable2_Pattern_3_padding__SHIFT 0x0 +#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio_MASK 0xff00 +#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio__SHIFT 0x8 +#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage_MASK 0xffff0000 +#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage__SHIFT 0x10 +#define DPM_TABLE_40__VddcLevelCount_MASK 0xffffffff +#define DPM_TABLE_40__VddcLevelCount__SHIFT 0x0 +#define DPM_TABLE_41__VddciLevelCount_MASK 0xffffffff +#define DPM_TABLE_41__VddciLevelCount__SHIFT 0x0 +#define DPM_TABLE_42__VddGfxLevelCount_MASK 0xffffffff +#define DPM_TABLE_42__VddGfxLevelCount__SHIFT 0x0 +#define DPM_TABLE_43__MvddLevelCount_MASK 0xffffffff +#define DPM_TABLE_43__MvddLevelCount__SHIFT 0x0 +#define DPM_TABLE_44__VddcTable_1_MASK 0xffff +#define DPM_TABLE_44__VddcTable_1__SHIFT 0x0 +#define DPM_TABLE_44__VddcTable_0_MASK 0xffff0000 +#define DPM_TABLE_44__VddcTable_0__SHIFT 0x10 +#define DPM_TABLE_45__VddcTable_3_MASK 0xffff +#define DPM_TABLE_45__VddcTable_3__SHIFT 0x0 +#define DPM_TABLE_45__VddcTable_2_MASK 0xffff0000 +#define DPM_TABLE_45__VddcTable_2__SHIFT 0x10 +#define DPM_TABLE_46__VddcTable_5_MASK 0xffff +#define DPM_TABLE_46__VddcTable_5__SHIFT 0x0 +#define DPM_TABLE_46__VddcTable_4_MASK 0xffff0000 +#define DPM_TABLE_46__VddcTable_4__SHIFT 0x10 +#define DPM_TABLE_47__VddcTable_7_MASK 0xffff +#define DPM_TABLE_47__VddcTable_7__SHIFT 0x0 +#define DPM_TABLE_47__VddcTable_6_MASK 0xffff0000 +#define DPM_TABLE_47__VddcTable_6__SHIFT 0x10 +#define DPM_TABLE_48__VddcTable_9_MASK 0xffff +#define DPM_TABLE_48__VddcTable_9__SHIFT 0x0 +#define DPM_TABLE_48__VddcTable_8_MASK 0xffff0000 +#define DPM_TABLE_48__VddcTable_8__SHIFT 0x10 +#define DPM_TABLE_49__VddcTable_11_MASK 0xffff +#define DPM_TABLE_49__VddcTable_11__SHIFT 0x0 +#define DPM_TABLE_49__VddcTable_10_MASK 0xffff0000 +#define DPM_TABLE_49__VddcTable_10__SHIFT 0x10 +#define DPM_TABLE_50__VddcTable_13_MASK 0xffff +#define DPM_TABLE_50__VddcTable_13__SHIFT 0x0 +#define DPM_TABLE_50__VddcTable_12_MASK 0xffff0000 +#define DPM_TABLE_50__VddcTable_12__SHIFT 0x10 +#define DPM_TABLE_51__VddcTable_15_MASK 0xffff +#define DPM_TABLE_51__VddcTable_15__SHIFT 0x0 +#define DPM_TABLE_51__VddcTable_14_MASK 0xffff0000 +#define DPM_TABLE_51__VddcTable_14__SHIFT 0x10 +#define DPM_TABLE_52__VddGfxTable_1_MASK 0xffff +#define DPM_TABLE_52__VddGfxTable_1__SHIFT 0x0 +#define DPM_TABLE_52__VddGfxTable_0_MASK 0xffff0000 +#define DPM_TABLE_52__VddGfxTable_0__SHIFT 0x10 +#define DPM_TABLE_53__VddGfxTable_3_MASK 0xffff +#define DPM_TABLE_53__VddGfxTable_3__SHIFT 0x0 +#define DPM_TABLE_53__VddGfxTable_2_MASK 0xffff0000 +#define DPM_TABLE_53__VddGfxTable_2__SHIFT 0x10 +#define DPM_TABLE_54__VddGfxTable_5_MASK 0xffff +#define DPM_TABLE_54__VddGfxTable_5__SHIFT 0x0 +#define DPM_TABLE_54__VddGfxTable_4_MASK 0xffff0000 +#define DPM_TABLE_54__VddGfxTable_4__SHIFT 0x10 +#define DPM_TABLE_55__VddGfxTable_7_MASK 0xffff +#define DPM_TABLE_55__VddGfxTable_7__SHIFT 0x0 +#define DPM_TABLE_55__VddGfxTable_6_MASK 0xffff0000 +#define DPM_TABLE_55__VddGfxTable_6__SHIFT 0x10 +#define DPM_TABLE_56__VddGfxTable_9_MASK 0xffff +#define DPM_TABLE_56__VddGfxTable_9__SHIFT 0x0 +#define DPM_TABLE_56__VddGfxTable_8_MASK 0xffff0000 +#define DPM_TABLE_56__VddGfxTable_8__SHIFT 0x10 +#define DPM_TABLE_57__VddGfxTable_11_MASK 0xffff +#define DPM_TABLE_57__VddGfxTable_11__SHIFT 0x0 +#define DPM_TABLE_57__VddGfxTable_10_MASK 0xffff0000 +#define DPM_TABLE_57__VddGfxTable_10__SHIFT 0x10 +#define DPM_TABLE_58__VddGfxTable_13_MASK 0xffff +#define DPM_TABLE_58__VddGfxTable_13__SHIFT 0x0 +#define DPM_TABLE_58__VddGfxTable_12_MASK 0xffff0000 +#define DPM_TABLE_58__VddGfxTable_12__SHIFT 0x10 +#define DPM_TABLE_59__VddGfxTable_15_MASK 0xffff +#define DPM_TABLE_59__VddGfxTable_15__SHIFT 0x0 +#define DPM_TABLE_59__VddGfxTable_14_MASK 0xffff0000 +#define DPM_TABLE_59__VddGfxTable_14__SHIFT 0x10 +#define DPM_TABLE_60__VddciTable_1_MASK 0xffff +#define DPM_TABLE_60__VddciTable_1__SHIFT 0x0 +#define DPM_TABLE_60__VddciTable_0_MASK 0xffff0000 +#define DPM_TABLE_60__VddciTable_0__SHIFT 0x10 +#define DPM_TABLE_61__VddciTable_3_MASK 0xffff +#define DPM_TABLE_61__VddciTable_3__SHIFT 0x0 +#define DPM_TABLE_61__VddciTable_2_MASK 0xffff0000 +#define DPM_TABLE_61__VddciTable_2__SHIFT 0x10 +#define DPM_TABLE_62__VddciTable_5_MASK 0xffff +#define DPM_TABLE_62__VddciTable_5__SHIFT 0x0 +#define DPM_TABLE_62__VddciTable_4_MASK 0xffff0000 +#define DPM_TABLE_62__VddciTable_4__SHIFT 0x10 +#define DPM_TABLE_63__VddciTable_7_MASK 0xffff +#define DPM_TABLE_63__VddciTable_7__SHIFT 0x0 +#define DPM_TABLE_63__VddciTable_6_MASK 0xffff0000 +#define DPM_TABLE_63__VddciTable_6__SHIFT 0x10 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3_MASK 0xff +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3__SHIFT 0x0 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2_MASK 0xff00 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2__SHIFT 0x8 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1_MASK 0xff0000 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1__SHIFT 0x10 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0_MASK 0xff000000 +#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0__SHIFT 0x18 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7_MASK 0xff +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7__SHIFT 0x0 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6_MASK 0xff00 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6__SHIFT 0x8 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5_MASK 0xff0000 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5__SHIFT 0x10 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4_MASK 0xff000000 +#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4__SHIFT 0x18 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11_MASK 0xff +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11__SHIFT 0x0 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10_MASK 0xff00 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10__SHIFT 0x8 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9_MASK 0xff0000 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9__SHIFT 0x10 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8_MASK 0xff000000 +#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8__SHIFT 0x18 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15_MASK 0xff +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15__SHIFT 0x0 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14_MASK 0xff00 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14__SHIFT 0x8 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13_MASK 0xff0000 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13__SHIFT 0x10 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12_MASK 0xff000000 +#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12__SHIFT 0x18 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3_MASK 0xff +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3__SHIFT 0x0 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2_MASK 0xff00 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2__SHIFT 0x8 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1_MASK 0xff0000 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1__SHIFT 0x10 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0_MASK 0xff000000 +#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0__SHIFT 0x18 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7_MASK 0xff +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7__SHIFT 0x0 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6_MASK 0xff00 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6__SHIFT 0x8 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5_MASK 0xff0000 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5__SHIFT 0x10 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4_MASK 0xff000000 +#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4__SHIFT 0x18 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11_MASK 0xff +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11__SHIFT 0x0 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10_MASK 0xff00 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10__SHIFT 0x8 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9_MASK 0xff0000 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9__SHIFT 0x10 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8_MASK 0xff000000 +#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8__SHIFT 0x18 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15_MASK 0xff +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15__SHIFT 0x0 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14_MASK 0xff00 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14__SHIFT 0x8 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13_MASK 0xff0000 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13__SHIFT 0x10 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12_MASK 0xff000000 +#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12__SHIFT 0x18 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3_MASK 0xff +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3__SHIFT 0x0 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2_MASK 0xff00 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2__SHIFT 0x8 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1_MASK 0xff0000 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1__SHIFT 0x10 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0_MASK 0xff000000 +#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0__SHIFT 0x18 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7_MASK 0xff +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7__SHIFT 0x0 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6_MASK 0xff00 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6__SHIFT 0x8 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5_MASK 0xff0000 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5__SHIFT 0x10 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4_MASK 0xff000000 +#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4__SHIFT 0x18 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11_MASK 0xff +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11__SHIFT 0x0 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10_MASK 0xff00 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10__SHIFT 0x8 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9_MASK 0xff0000 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9__SHIFT 0x10 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8_MASK 0xff000000 +#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8__SHIFT 0x18 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15_MASK 0xff +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15__SHIFT 0x0 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14_MASK 0xff00 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14__SHIFT 0x8 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13_MASK 0xff0000 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13__SHIFT 0x10 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12_MASK 0xff000000 +#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12__SHIFT 0x18 +#define DPM_TABLE_76__BapmVddcVidHiSidd_3_MASK 0xff +#define DPM_TABLE_76__BapmVddcVidHiSidd_3__SHIFT 0x0 +#define DPM_TABLE_76__BapmVddcVidHiSidd_2_MASK 0xff00 +#define DPM_TABLE_76__BapmVddcVidHiSidd_2__SHIFT 0x8 +#define DPM_TABLE_76__BapmVddcVidHiSidd_1_MASK 0xff0000 +#define DPM_TABLE_76__BapmVddcVidHiSidd_1__SHIFT 0x10 +#define DPM_TABLE_76__BapmVddcVidHiSidd_0_MASK 0xff000000 +#define DPM_TABLE_76__BapmVddcVidHiSidd_0__SHIFT 0x18 +#define DPM_TABLE_77__BapmVddcVidHiSidd_7_MASK 0xff +#define DPM_TABLE_77__BapmVddcVidHiSidd_7__SHIFT 0x0 +#define DPM_TABLE_77__BapmVddcVidHiSidd_6_MASK 0xff00 +#define DPM_TABLE_77__BapmVddcVidHiSidd_6__SHIFT 0x8 +#define DPM_TABLE_77__BapmVddcVidHiSidd_5_MASK 0xff0000 +#define DPM_TABLE_77__BapmVddcVidHiSidd_5__SHIFT 0x10 +#define DPM_TABLE_77__BapmVddcVidHiSidd_4_MASK 0xff000000 +#define DPM_TABLE_77__BapmVddcVidHiSidd_4__SHIFT 0x18 +#define DPM_TABLE_78__BapmVddcVidHiSidd_11_MASK 0xff +#define DPM_TABLE_78__BapmVddcVidHiSidd_11__SHIFT 0x0 +#define DPM_TABLE_78__BapmVddcVidHiSidd_10_MASK 0xff00 +#define DPM_TABLE_78__BapmVddcVidHiSidd_10__SHIFT 0x8 +#define DPM_TABLE_78__BapmVddcVidHiSidd_9_MASK 0xff0000 +#define DPM_TABLE_78__BapmVddcVidHiSidd_9__SHIFT 0x10 +#define DPM_TABLE_78__BapmVddcVidHiSidd_8_MASK 0xff000000 +#define DPM_TABLE_78__BapmVddcVidHiSidd_8__SHIFT 0x18 +#define DPM_TABLE_79__BapmVddcVidHiSidd_15_MASK 0xff +#define DPM_TABLE_79__BapmVddcVidHiSidd_15__SHIFT 0x0 +#define DPM_TABLE_79__BapmVddcVidHiSidd_14_MASK 0xff00 +#define DPM_TABLE_79__BapmVddcVidHiSidd_14__SHIFT 0x8 +#define DPM_TABLE_79__BapmVddcVidHiSidd_13_MASK 0xff0000 +#define DPM_TABLE_79__BapmVddcVidHiSidd_13__SHIFT 0x10 +#define DPM_TABLE_79__BapmVddcVidHiSidd_12_MASK 0xff000000 +#define DPM_TABLE_79__BapmVddcVidHiSidd_12__SHIFT 0x18 +#define DPM_TABLE_80__BapmVddcVidLoSidd_3_MASK 0xff +#define DPM_TABLE_80__BapmVddcVidLoSidd_3__SHIFT 0x0 +#define DPM_TABLE_80__BapmVddcVidLoSidd_2_MASK 0xff00 +#define DPM_TABLE_80__BapmVddcVidLoSidd_2__SHIFT 0x8 +#define DPM_TABLE_80__BapmVddcVidLoSidd_1_MASK 0xff0000 +#define DPM_TABLE_80__BapmVddcVidLoSidd_1__SHIFT 0x10 +#define DPM_TABLE_80__BapmVddcVidLoSidd_0_MASK 0xff000000 +#define DPM_TABLE_80__BapmVddcVidLoSidd_0__SHIFT 0x18 +#define DPM_TABLE_81__BapmVddcVidLoSidd_7_MASK 0xff +#define DPM_TABLE_81__BapmVddcVidLoSidd_7__SHIFT 0x0 +#define DPM_TABLE_81__BapmVddcVidLoSidd_6_MASK 0xff00 +#define DPM_TABLE_81__BapmVddcVidLoSidd_6__SHIFT 0x8 +#define DPM_TABLE_81__BapmVddcVidLoSidd_5_MASK 0xff0000 +#define DPM_TABLE_81__BapmVddcVidLoSidd_5__SHIFT 0x10 +#define DPM_TABLE_81__BapmVddcVidLoSidd_4_MASK 0xff000000 +#define DPM_TABLE_81__BapmVddcVidLoSidd_4__SHIFT 0x18 +#define DPM_TABLE_82__BapmVddcVidLoSidd_11_MASK 0xff +#define DPM_TABLE_82__BapmVddcVidLoSidd_11__SHIFT 0x0 +#define DPM_TABLE_82__BapmVddcVidLoSidd_10_MASK 0xff00 +#define DPM_TABLE_82__BapmVddcVidLoSidd_10__SHIFT 0x8 +#define DPM_TABLE_82__BapmVddcVidLoSidd_9_MASK 0xff0000 +#define DPM_TABLE_82__BapmVddcVidLoSidd_9__SHIFT 0x10 +#define DPM_TABLE_82__BapmVddcVidLoSidd_8_MASK 0xff000000 +#define DPM_TABLE_82__BapmVddcVidLoSidd_8__SHIFT 0x18 +#define DPM_TABLE_83__BapmVddcVidLoSidd_15_MASK 0xff +#define DPM_TABLE_83__BapmVddcVidLoSidd_15__SHIFT 0x0 +#define DPM_TABLE_83__BapmVddcVidLoSidd_14_MASK 0xff00 +#define DPM_TABLE_83__BapmVddcVidLoSidd_14__SHIFT 0x8 +#define DPM_TABLE_83__BapmVddcVidLoSidd_13_MASK 0xff0000 +#define DPM_TABLE_83__BapmVddcVidLoSidd_13__SHIFT 0x10 +#define DPM_TABLE_83__BapmVddcVidLoSidd_12_MASK 0xff000000 +#define DPM_TABLE_83__BapmVddcVidLoSidd_12__SHIFT 0x18 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_3_MASK 0xff +#define DPM_TABLE_84__BapmVddcVidHiSidd2_3__SHIFT 0x0 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_2_MASK 0xff00 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_2__SHIFT 0x8 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_1_MASK 0xff0000 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_1__SHIFT 0x10 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_0_MASK 0xff000000 +#define DPM_TABLE_84__BapmVddcVidHiSidd2_0__SHIFT 0x18 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_7_MASK 0xff +#define DPM_TABLE_85__BapmVddcVidHiSidd2_7__SHIFT 0x0 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_6_MASK 0xff00 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_6__SHIFT 0x8 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_5_MASK 0xff0000 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_5__SHIFT 0x10 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_4_MASK 0xff000000 +#define DPM_TABLE_85__BapmVddcVidHiSidd2_4__SHIFT 0x18 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_11_MASK 0xff +#define DPM_TABLE_86__BapmVddcVidHiSidd2_11__SHIFT 0x0 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_10_MASK 0xff00 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_10__SHIFT 0x8 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_9_MASK 0xff0000 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_9__SHIFT 0x10 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_8_MASK 0xff000000 +#define DPM_TABLE_86__BapmVddcVidHiSidd2_8__SHIFT 0x18 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_15_MASK 0xff +#define DPM_TABLE_87__BapmVddcVidHiSidd2_15__SHIFT 0x0 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_14_MASK 0xff00 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_14__SHIFT 0x8 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_13_MASK 0xff0000 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_13__SHIFT 0x10 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_12_MASK 0xff000000 +#define DPM_TABLE_87__BapmVddcVidHiSidd2_12__SHIFT 0x18 +#define DPM_TABLE_88__MasterDeepSleepControl_MASK 0xff +#define DPM_TABLE_88__MasterDeepSleepControl__SHIFT 0x0 +#define DPM_TABLE_88__LinkLevelCount_MASK 0xff00 +#define DPM_TABLE_88__LinkLevelCount__SHIFT 0x8 +#define DPM_TABLE_88__MemoryDpmLevelCount_MASK 0xff0000 +#define DPM_TABLE_88__MemoryDpmLevelCount__SHIFT 0x10 +#define DPM_TABLE_88__GraphicsDpmLevelCount_MASK 0xff000000 +#define DPM_TABLE_88__GraphicsDpmLevelCount__SHIFT 0x18 +#define DPM_TABLE_89__SamuLevelCount_MASK 0xff +#define DPM_TABLE_89__SamuLevelCount__SHIFT 0x0 +#define DPM_TABLE_89__AcpLevelCount_MASK 0xff00 +#define DPM_TABLE_89__AcpLevelCount__SHIFT 0x8 +#define DPM_TABLE_89__VceLevelCount_MASK 0xff0000 +#define DPM_TABLE_89__VceLevelCount__SHIFT 0x10 +#define DPM_TABLE_89__UvdLevelCount_MASK 0xff000000 +#define DPM_TABLE_89__UvdLevelCount__SHIFT 0x18 +#define DPM_TABLE_90__Reserved_0_MASK 0xffffffff +#define DPM_TABLE_90__Reserved_0__SHIFT 0x0 +#define DPM_TABLE_91__Reserved_1_MASK 0xffffffff +#define DPM_TABLE_91__Reserved_1__SHIFT 0x0 +#define DPM_TABLE_92__Reserved_2_MASK 0xffffffff +#define DPM_TABLE_92__Reserved_2__SHIFT 0x0 +#define DPM_TABLE_93__Reserved_3_MASK 0xffffffff +#define DPM_TABLE_93__Reserved_3__SHIFT 0x0 +#define DPM_TABLE_94__Reserved_4_MASK 0xffffffff +#define DPM_TABLE_94__Reserved_4__SHIFT 0x0 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel_MASK 0xffff +#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_104__GraphicsLevel_0_SclkDid_MASK 0xff000000 +#define DPM_TABLE_104__GraphicsLevel_0_SclkDid__SHIFT 0x18 +#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle_MASK 0xff +#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_105__GraphicsLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_105__GraphicsLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_105__GraphicsLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_105__GraphicsLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel_MASK 0xffff +#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_115__GraphicsLevel_1_SclkDid_MASK 0xff000000 +#define DPM_TABLE_115__GraphicsLevel_1_SclkDid__SHIFT 0x18 +#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle_MASK 0xff +#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_116__GraphicsLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_116__GraphicsLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_116__GraphicsLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_116__GraphicsLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel_MASK 0xffff +#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_126__GraphicsLevel_2_SclkDid_MASK 0xff000000 +#define DPM_TABLE_126__GraphicsLevel_2_SclkDid__SHIFT 0x18 +#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle_MASK 0xff +#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_127__GraphicsLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_127__GraphicsLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_127__GraphicsLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_127__GraphicsLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel_MASK 0xffff +#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_137__GraphicsLevel_3_SclkDid_MASK 0xff000000 +#define DPM_TABLE_137__GraphicsLevel_3_SclkDid__SHIFT 0x18 +#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle_MASK 0xff +#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_138__GraphicsLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_138__GraphicsLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_138__GraphicsLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_138__GraphicsLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel_MASK 0xffff +#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_148__GraphicsLevel_4_SclkDid_MASK 0xff000000 +#define DPM_TABLE_148__GraphicsLevel_4_SclkDid__SHIFT 0x18 +#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle_MASK 0xff +#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_149__GraphicsLevel_4_DownHyst_MASK 0xff0000 +#define DPM_TABLE_149__GraphicsLevel_4_DownHyst__SHIFT 0x10 +#define DPM_TABLE_149__GraphicsLevel_4_UpHyst_MASK 0xff000000 +#define DPM_TABLE_149__GraphicsLevel_4_UpHyst__SHIFT 0x18 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel_MASK 0xffff +#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_159__GraphicsLevel_5_SclkDid_MASK 0xff000000 +#define DPM_TABLE_159__GraphicsLevel_5_SclkDid__SHIFT 0x18 +#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle_MASK 0xff +#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_160__GraphicsLevel_5_DownHyst_MASK 0xff0000 +#define DPM_TABLE_160__GraphicsLevel_5_DownHyst__SHIFT 0x10 +#define DPM_TABLE_160__GraphicsLevel_5_UpHyst_MASK 0xff000000 +#define DPM_TABLE_160__GraphicsLevel_5_UpHyst__SHIFT 0x18 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff +#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000 +#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18 +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff +#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000 +#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000 +#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel_MASK 0xffff +#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 +#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000 +#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10 +#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000 +#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18 +#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle_MASK 0xff +#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0 +#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_181__GraphicsLevel_7_SclkDid_MASK 0xff000000 +#define DPM_TABLE_181__GraphicsLevel_7_SclkDid__SHIFT 0x18 +#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle_MASK 0xff +#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle__SHIFT 0x0 +#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_182__GraphicsLevel_7_DownHyst_MASK 0xff0000 +#define DPM_TABLE_182__GraphicsLevel_7_DownHyst__SHIFT 0x10 +#define DPM_TABLE_182__GraphicsLevel_7_UpHyst_MASK 0xff000000 +#define DPM_TABLE_182__GraphicsLevel_7_UpHyst__SHIFT 0x18 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_184__MemoryACPILevel_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_184__MemoryACPILevel_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_186__MemoryACPILevel_StutterEnable_MASK 0xff +#define DPM_TABLE_186__MemoryACPILevel_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_186__MemoryACPILevel_RttEnable_MASK 0xff00 +#define DPM_TABLE_186__MemoryACPILevel_RttEnable__SHIFT 0x8 +#define DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_186__MemoryACPILevel_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_186__MemoryACPILevel_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_187__MemoryACPILevel_EnabledForActivity_MASK 0xff +#define DPM_TABLE_187__MemoryACPILevel_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_187__MemoryACPILevel_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_187__MemoryACPILevel_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_187__MemoryACPILevel_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_187__MemoryACPILevel_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_188__MemoryACPILevel_padding_MASK 0xff +#define DPM_TABLE_188__MemoryACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_188__MemoryACPILevel_DownHyst_MASK 0xff0000 +#define DPM_TABLE_188__MemoryACPILevel_DownHyst__SHIFT 0x10 +#define DPM_TABLE_188__MemoryACPILevel_UpHyst_MASK 0xff000000 +#define DPM_TABLE_188__MemoryACPILevel_UpHyst__SHIFT 0x18 +#define DPM_TABLE_189__MemoryACPILevel_padding1_MASK 0xff +#define DPM_TABLE_189__MemoryACPILevel_padding1__SHIFT 0x0 +#define DPM_TABLE_189__MemoryACPILevel_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_189__MemoryACPILevel_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_189__MemoryACPILevel_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_189__MemoryACPILevel_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_196__MemoryACPILevel_DllCntl_MASK 0xffffffff +#define DPM_TABLE_196__MemoryACPILevel_DllCntl__SHIFT 0x0 +#define DPM_TABLE_197__MemoryACPILevel_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_197__MemoryACPILevel_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_198__MemoryACPILevel_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_198__MemoryACPILevel_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_200__MemoryLevel_0_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_200__MemoryLevel_0_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_201__MemoryLevel_0_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_201__MemoryLevel_0_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_202__MemoryLevel_0_StutterEnable_MASK 0xff +#define DPM_TABLE_202__MemoryLevel_0_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_202__MemoryLevel_0_RttEnable_MASK 0xff00 +#define DPM_TABLE_202__MemoryLevel_0_RttEnable__SHIFT 0x8 +#define DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_202__MemoryLevel_0_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_202__MemoryLevel_0_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_203__MemoryLevel_0_EnabledForActivity_MASK 0xff +#define DPM_TABLE_203__MemoryLevel_0_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_203__MemoryLevel_0_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_203__MemoryLevel_0_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_203__MemoryLevel_0_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_203__MemoryLevel_0_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_204__MemoryLevel_0_padding_MASK 0xff +#define DPM_TABLE_204__MemoryLevel_0_padding__SHIFT 0x0 +#define DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_204__MemoryLevel_0_DownHyst_MASK 0xff0000 +#define DPM_TABLE_204__MemoryLevel_0_DownHyst__SHIFT 0x10 +#define DPM_TABLE_204__MemoryLevel_0_UpHyst_MASK 0xff000000 +#define DPM_TABLE_204__MemoryLevel_0_UpHyst__SHIFT 0x18 +#define DPM_TABLE_205__MemoryLevel_0_padding1_MASK 0xff +#define DPM_TABLE_205__MemoryLevel_0_padding1__SHIFT 0x0 +#define DPM_TABLE_205__MemoryLevel_0_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_205__MemoryLevel_0_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_205__MemoryLevel_0_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_205__MemoryLevel_0_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_212__MemoryLevel_0_DllCntl_MASK 0xffffffff +#define DPM_TABLE_212__MemoryLevel_0_DllCntl__SHIFT 0x0 +#define DPM_TABLE_213__MemoryLevel_0_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_213__MemoryLevel_0_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_214__MemoryLevel_0_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_214__MemoryLevel_0_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_216__MemoryLevel_1_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_216__MemoryLevel_1_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_217__MemoryLevel_1_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_217__MemoryLevel_1_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_218__MemoryLevel_1_StutterEnable_MASK 0xff +#define DPM_TABLE_218__MemoryLevel_1_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_218__MemoryLevel_1_RttEnable_MASK 0xff00 +#define DPM_TABLE_218__MemoryLevel_1_RttEnable__SHIFT 0x8 +#define DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_218__MemoryLevel_1_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_218__MemoryLevel_1_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_219__MemoryLevel_1_EnabledForActivity_MASK 0xff +#define DPM_TABLE_219__MemoryLevel_1_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_219__MemoryLevel_1_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_219__MemoryLevel_1_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_219__MemoryLevel_1_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_219__MemoryLevel_1_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_220__MemoryLevel_1_padding_MASK 0xff +#define DPM_TABLE_220__MemoryLevel_1_padding__SHIFT 0x0 +#define DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_220__MemoryLevel_1_DownHyst_MASK 0xff0000 +#define DPM_TABLE_220__MemoryLevel_1_DownHyst__SHIFT 0x10 +#define DPM_TABLE_220__MemoryLevel_1_UpHyst_MASK 0xff000000 +#define DPM_TABLE_220__MemoryLevel_1_UpHyst__SHIFT 0x18 +#define DPM_TABLE_221__MemoryLevel_1_padding1_MASK 0xff +#define DPM_TABLE_221__MemoryLevel_1_padding1__SHIFT 0x0 +#define DPM_TABLE_221__MemoryLevel_1_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_221__MemoryLevel_1_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_221__MemoryLevel_1_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_221__MemoryLevel_1_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_228__MemoryLevel_1_DllCntl_MASK 0xffffffff +#define DPM_TABLE_228__MemoryLevel_1_DllCntl__SHIFT 0x0 +#define DPM_TABLE_229__MemoryLevel_1_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_229__MemoryLevel_1_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_230__MemoryLevel_1_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_230__MemoryLevel_1_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_232__MemoryLevel_2_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_232__MemoryLevel_2_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_233__MemoryLevel_2_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_233__MemoryLevel_2_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_234__MemoryLevel_2_StutterEnable_MASK 0xff +#define DPM_TABLE_234__MemoryLevel_2_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_234__MemoryLevel_2_RttEnable_MASK 0xff00 +#define DPM_TABLE_234__MemoryLevel_2_RttEnable__SHIFT 0x8 +#define DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_234__MemoryLevel_2_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_234__MemoryLevel_2_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_235__MemoryLevel_2_EnabledForActivity_MASK 0xff +#define DPM_TABLE_235__MemoryLevel_2_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_235__MemoryLevel_2_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_235__MemoryLevel_2_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_235__MemoryLevel_2_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_235__MemoryLevel_2_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_236__MemoryLevel_2_padding_MASK 0xff +#define DPM_TABLE_236__MemoryLevel_2_padding__SHIFT 0x0 +#define DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_236__MemoryLevel_2_DownHyst_MASK 0xff0000 +#define DPM_TABLE_236__MemoryLevel_2_DownHyst__SHIFT 0x10 +#define DPM_TABLE_236__MemoryLevel_2_UpHyst_MASK 0xff000000 +#define DPM_TABLE_236__MemoryLevel_2_UpHyst__SHIFT 0x18 +#define DPM_TABLE_237__MemoryLevel_2_padding1_MASK 0xff +#define DPM_TABLE_237__MemoryLevel_2_padding1__SHIFT 0x0 +#define DPM_TABLE_237__MemoryLevel_2_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_237__MemoryLevel_2_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_237__MemoryLevel_2_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_237__MemoryLevel_2_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_244__MemoryLevel_2_DllCntl_MASK 0xffffffff +#define DPM_TABLE_244__MemoryLevel_2_DllCntl__SHIFT 0x0 +#define DPM_TABLE_245__MemoryLevel_2_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_245__MemoryLevel_2_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_246__MemoryLevel_2_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_246__MemoryLevel_2_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_248__MemoryLevel_3_MinMvdd_MASK 0xffffffff +#define DPM_TABLE_248__MemoryLevel_3_MinMvdd__SHIFT 0x0 +#define DPM_TABLE_249__MemoryLevel_3_MclkFrequency_MASK 0xffffffff +#define DPM_TABLE_249__MemoryLevel_3_MclkFrequency__SHIFT 0x0 +#define DPM_TABLE_250__MemoryLevel_3_StutterEnable_MASK 0xff +#define DPM_TABLE_250__MemoryLevel_3_StutterEnable__SHIFT 0x0 +#define DPM_TABLE_250__MemoryLevel_3_RttEnable_MASK 0xff00 +#define DPM_TABLE_250__MemoryLevel_3_RttEnable__SHIFT 0x8 +#define DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000 +#define DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10 +#define DPM_TABLE_250__MemoryLevel_3_EdcReadEnable_MASK 0xff000000 +#define DPM_TABLE_250__MemoryLevel_3_EdcReadEnable__SHIFT 0x18 +#define DPM_TABLE_251__MemoryLevel_3_EnabledForActivity_MASK 0xff +#define DPM_TABLE_251__MemoryLevel_3_EnabledForActivity__SHIFT 0x0 +#define DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle_MASK 0xff00 +#define DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8 +#define DPM_TABLE_251__MemoryLevel_3_StrobeRatio_MASK 0xff0000 +#define DPM_TABLE_251__MemoryLevel_3_StrobeRatio__SHIFT 0x10 +#define DPM_TABLE_251__MemoryLevel_3_StrobeEnable_MASK 0xff000000 +#define DPM_TABLE_251__MemoryLevel_3_StrobeEnable__SHIFT 0x18 +#define DPM_TABLE_252__MemoryLevel_3_padding_MASK 0xff +#define DPM_TABLE_252__MemoryLevel_3_padding__SHIFT 0x0 +#define DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst_MASK 0xff00 +#define DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8 +#define DPM_TABLE_252__MemoryLevel_3_DownHyst_MASK 0xff0000 +#define DPM_TABLE_252__MemoryLevel_3_DownHyst__SHIFT 0x10 +#define DPM_TABLE_252__MemoryLevel_3_UpHyst_MASK 0xff000000 +#define DPM_TABLE_252__MemoryLevel_3_UpHyst__SHIFT 0x18 +#define DPM_TABLE_253__MemoryLevel_3_padding1_MASK 0xff +#define DPM_TABLE_253__MemoryLevel_3_padding1__SHIFT 0x0 +#define DPM_TABLE_253__MemoryLevel_3_DisplayWatermark_MASK 0xff00 +#define DPM_TABLE_253__MemoryLevel_3_DisplayWatermark__SHIFT 0x8 +#define DPM_TABLE_253__MemoryLevel_3_ActivityLevel_MASK 0xffff0000 +#define DPM_TABLE_253__MemoryLevel_3_ActivityLevel__SHIFT 0x10 +#define DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff +#define DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0 +#define DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff +#define DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0 +#define DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff +#define DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0 +#define DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff +#define DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0 +#define DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff +#define DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0 +#define DPM_TABLE_260__MemoryLevel_3_DllCntl_MASK 0xffffffff +#define DPM_TABLE_260__MemoryLevel_3_DllCntl__SHIFT 0x0 +#define DPM_TABLE_261__MemoryLevel_3_MpllSs1_MASK 0xffffffff +#define DPM_TABLE_261__MemoryLevel_3_MpllSs1__SHIFT 0x0 +#define DPM_TABLE_262__MemoryLevel_3_MpllSs2_MASK 0xffffffff +#define DPM_TABLE_262__MemoryLevel_3_MpllSs2__SHIFT 0x0 +#define DPM_TABLE_263__LinkLevel_0_SPC_MASK 0xff +#define DPM_TABLE_263__LinkLevel_0_SPC__SHIFT 0x0 +#define DPM_TABLE_263__LinkLevel_0_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_263__LinkLevel_0_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_263__LinkLevel_0_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_263__LinkLevel_0_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_263__LinkLevel_0_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_263__LinkLevel_0_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_264__LinkLevel_0_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_264__LinkLevel_0_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_265__LinkLevel_0_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_265__LinkLevel_0_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_266__LinkLevel_0_Reserved_MASK 0xffffffff +#define DPM_TABLE_266__LinkLevel_0_Reserved__SHIFT 0x0 +#define DPM_TABLE_267__LinkLevel_1_SPC_MASK 0xff +#define DPM_TABLE_267__LinkLevel_1_SPC__SHIFT 0x0 +#define DPM_TABLE_267__LinkLevel_1_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_267__LinkLevel_1_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_267__LinkLevel_1_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_267__LinkLevel_1_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_267__LinkLevel_1_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_267__LinkLevel_1_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_268__LinkLevel_1_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_268__LinkLevel_1_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_269__LinkLevel_1_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_269__LinkLevel_1_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_270__LinkLevel_1_Reserved_MASK 0xffffffff +#define DPM_TABLE_270__LinkLevel_1_Reserved__SHIFT 0x0 +#define DPM_TABLE_271__LinkLevel_2_SPC_MASK 0xff +#define DPM_TABLE_271__LinkLevel_2_SPC__SHIFT 0x0 +#define DPM_TABLE_271__LinkLevel_2_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_271__LinkLevel_2_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_271__LinkLevel_2_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_271__LinkLevel_2_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_271__LinkLevel_2_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_271__LinkLevel_2_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_272__LinkLevel_2_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_272__LinkLevel_2_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_273__LinkLevel_2_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_273__LinkLevel_2_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_274__LinkLevel_2_Reserved_MASK 0xffffffff +#define DPM_TABLE_274__LinkLevel_2_Reserved__SHIFT 0x0 +#define DPM_TABLE_275__LinkLevel_3_SPC_MASK 0xff +#define DPM_TABLE_275__LinkLevel_3_SPC__SHIFT 0x0 +#define DPM_TABLE_275__LinkLevel_3_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_275__LinkLevel_3_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_275__LinkLevel_3_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_275__LinkLevel_3_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_275__LinkLevel_3_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_275__LinkLevel_3_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_276__LinkLevel_3_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_276__LinkLevel_3_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_277__LinkLevel_3_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_277__LinkLevel_3_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_278__LinkLevel_3_Reserved_MASK 0xffffffff +#define DPM_TABLE_278__LinkLevel_3_Reserved__SHIFT 0x0 +#define DPM_TABLE_279__LinkLevel_4_SPC_MASK 0xff +#define DPM_TABLE_279__LinkLevel_4_SPC__SHIFT 0x0 +#define DPM_TABLE_279__LinkLevel_4_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_279__LinkLevel_4_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_279__LinkLevel_4_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_279__LinkLevel_4_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_279__LinkLevel_4_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_279__LinkLevel_4_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_280__LinkLevel_4_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_280__LinkLevel_4_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_281__LinkLevel_4_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_281__LinkLevel_4_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_282__LinkLevel_4_Reserved_MASK 0xffffffff +#define DPM_TABLE_282__LinkLevel_4_Reserved__SHIFT 0x0 +#define DPM_TABLE_283__LinkLevel_5_SPC_MASK 0xff +#define DPM_TABLE_283__LinkLevel_5_SPC__SHIFT 0x0 +#define DPM_TABLE_283__LinkLevel_5_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_283__LinkLevel_5_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_283__LinkLevel_5_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_283__LinkLevel_5_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_283__LinkLevel_5_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_283__LinkLevel_5_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_284__LinkLevel_5_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_284__LinkLevel_5_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_285__LinkLevel_5_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_285__LinkLevel_5_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_286__LinkLevel_5_Reserved_MASK 0xffffffff +#define DPM_TABLE_286__LinkLevel_5_Reserved__SHIFT 0x0 +#define DPM_TABLE_287__LinkLevel_6_SPC_MASK 0xff +#define DPM_TABLE_287__LinkLevel_6_SPC__SHIFT 0x0 +#define DPM_TABLE_287__LinkLevel_6_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_287__LinkLevel_6_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_287__LinkLevel_6_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_287__LinkLevel_6_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_287__LinkLevel_6_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_287__LinkLevel_6_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_288__LinkLevel_6_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_288__LinkLevel_6_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_289__LinkLevel_6_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_289__LinkLevel_6_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_290__LinkLevel_6_Reserved_MASK 0xffffffff +#define DPM_TABLE_290__LinkLevel_6_Reserved__SHIFT 0x0 +#define DPM_TABLE_291__LinkLevel_7_SPC_MASK 0xff +#define DPM_TABLE_291__LinkLevel_7_SPC__SHIFT 0x0 +#define DPM_TABLE_291__LinkLevel_7_EnabledForActivity_MASK 0xff00 +#define DPM_TABLE_291__LinkLevel_7_EnabledForActivity__SHIFT 0x8 +#define DPM_TABLE_291__LinkLevel_7_PcieLaneCount_MASK 0xff0000 +#define DPM_TABLE_291__LinkLevel_7_PcieLaneCount__SHIFT 0x10 +#define DPM_TABLE_291__LinkLevel_7_PcieGenSpeed_MASK 0xff000000 +#define DPM_TABLE_291__LinkLevel_7_PcieGenSpeed__SHIFT 0x18 +#define DPM_TABLE_292__LinkLevel_7_DownThreshold_MASK 0xffffffff +#define DPM_TABLE_292__LinkLevel_7_DownThreshold__SHIFT 0x0 +#define DPM_TABLE_293__LinkLevel_7_UpThreshold_MASK 0xffffffff +#define DPM_TABLE_293__LinkLevel_7_UpThreshold__SHIFT 0x0 +#define DPM_TABLE_294__LinkLevel_7_Reserved_MASK 0xffffffff +#define DPM_TABLE_294__LinkLevel_7_Reserved__SHIFT 0x0 +#define DPM_TABLE_295__ACPILevel_Flags_MASK 0xffffffff +#define DPM_TABLE_295__ACPILevel_Flags__SHIFT 0x0 +#define DPM_TABLE_296__ACPILevel_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_296__ACPILevel_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_297__ACPILevel_SclkFrequency_MASK 0xffffffff +#define DPM_TABLE_297__ACPILevel_SclkFrequency__SHIFT 0x0 +#define DPM_TABLE_298__ACPILevel_padding_MASK 0xff +#define DPM_TABLE_298__ACPILevel_padding__SHIFT 0x0 +#define DPM_TABLE_298__ACPILevel_DeepSleepDivId_MASK 0xff00 +#define DPM_TABLE_298__ACPILevel_DeepSleepDivId__SHIFT 0x8 +#define DPM_TABLE_298__ACPILevel_DisplayWatermark_MASK 0xff0000 +#define DPM_TABLE_298__ACPILevel_DisplayWatermark__SHIFT 0x10 +#define DPM_TABLE_298__ACPILevel_SclkDid_MASK 0xff000000 +#define DPM_TABLE_298__ACPILevel_SclkDid__SHIFT 0x18 +#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff +#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl__SHIFT 0x0 +#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff +#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0 +#define DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff +#define DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0 +#define DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff +#define DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0 +#define DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff +#define DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0 +#define DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff +#define DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0 +#define DPM_TABLE_305__ACPILevel_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_305__ACPILevel_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_306__ACPILevel_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_306__ACPILevel_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_307__UvdLevel_0_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_307__UvdLevel_0_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_308__UvdLevel_0_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_308__UvdLevel_0_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_310__UvdLevel_0_padding_1_MASK 0xff +#define DPM_TABLE_310__UvdLevel_0_padding_1__SHIFT 0x0 +#define DPM_TABLE_310__UvdLevel_0_padding_0_MASK 0xff00 +#define DPM_TABLE_310__UvdLevel_0_padding_0__SHIFT 0x8 +#define DPM_TABLE_310__UvdLevel_0_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_310__UvdLevel_0_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_310__UvdLevel_0_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_310__UvdLevel_0_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_311__UvdLevel_1_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_311__UvdLevel_1_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_312__UvdLevel_1_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_312__UvdLevel_1_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_314__UvdLevel_1_padding_1_MASK 0xff +#define DPM_TABLE_314__UvdLevel_1_padding_1__SHIFT 0x0 +#define DPM_TABLE_314__UvdLevel_1_padding_0_MASK 0xff00 +#define DPM_TABLE_314__UvdLevel_1_padding_0__SHIFT 0x8 +#define DPM_TABLE_314__UvdLevel_1_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_314__UvdLevel_1_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_314__UvdLevel_1_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_314__UvdLevel_1_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_315__UvdLevel_2_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_315__UvdLevel_2_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_316__UvdLevel_2_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_316__UvdLevel_2_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_318__UvdLevel_2_padding_1_MASK 0xff +#define DPM_TABLE_318__UvdLevel_2_padding_1__SHIFT 0x0 +#define DPM_TABLE_318__UvdLevel_2_padding_0_MASK 0xff00 +#define DPM_TABLE_318__UvdLevel_2_padding_0__SHIFT 0x8 +#define DPM_TABLE_318__UvdLevel_2_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_318__UvdLevel_2_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_318__UvdLevel_2_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_318__UvdLevel_2_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_319__UvdLevel_3_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_319__UvdLevel_3_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_320__UvdLevel_3_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_320__UvdLevel_3_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_322__UvdLevel_3_padding_1_MASK 0xff +#define DPM_TABLE_322__UvdLevel_3_padding_1__SHIFT 0x0 +#define DPM_TABLE_322__UvdLevel_3_padding_0_MASK 0xff00 +#define DPM_TABLE_322__UvdLevel_3_padding_0__SHIFT 0x8 +#define DPM_TABLE_322__UvdLevel_3_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_322__UvdLevel_3_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_322__UvdLevel_3_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_322__UvdLevel_3_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_323__UvdLevel_4_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_323__UvdLevel_4_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_324__UvdLevel_4_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_324__UvdLevel_4_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_326__UvdLevel_4_padding_1_MASK 0xff +#define DPM_TABLE_326__UvdLevel_4_padding_1__SHIFT 0x0 +#define DPM_TABLE_326__UvdLevel_4_padding_0_MASK 0xff00 +#define DPM_TABLE_326__UvdLevel_4_padding_0__SHIFT 0x8 +#define DPM_TABLE_326__UvdLevel_4_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_326__UvdLevel_4_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_326__UvdLevel_4_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_326__UvdLevel_4_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_327__UvdLevel_5_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_327__UvdLevel_5_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_328__UvdLevel_5_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_328__UvdLevel_5_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_330__UvdLevel_5_padding_1_MASK 0xff +#define DPM_TABLE_330__UvdLevel_5_padding_1__SHIFT 0x0 +#define DPM_TABLE_330__UvdLevel_5_padding_0_MASK 0xff00 +#define DPM_TABLE_330__UvdLevel_5_padding_0__SHIFT 0x8 +#define DPM_TABLE_330__UvdLevel_5_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_330__UvdLevel_5_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_330__UvdLevel_5_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_330__UvdLevel_5_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_331__UvdLevel_6_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_331__UvdLevel_6_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_332__UvdLevel_6_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_332__UvdLevel_6_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_334__UvdLevel_6_padding_1_MASK 0xff +#define DPM_TABLE_334__UvdLevel_6_padding_1__SHIFT 0x0 +#define DPM_TABLE_334__UvdLevel_6_padding_0_MASK 0xff00 +#define DPM_TABLE_334__UvdLevel_6_padding_0__SHIFT 0x8 +#define DPM_TABLE_334__UvdLevel_6_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_334__UvdLevel_6_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_334__UvdLevel_6_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_334__UvdLevel_6_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_335__UvdLevel_7_VclkFrequency_MASK 0xffffffff +#define DPM_TABLE_335__UvdLevel_7_VclkFrequency__SHIFT 0x0 +#define DPM_TABLE_336__UvdLevel_7_DclkFrequency_MASK 0xffffffff +#define DPM_TABLE_336__UvdLevel_7_DclkFrequency__SHIFT 0x0 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_338__UvdLevel_7_padding_1_MASK 0xff +#define DPM_TABLE_338__UvdLevel_7_padding_1__SHIFT 0x0 +#define DPM_TABLE_338__UvdLevel_7_padding_0_MASK 0xff00 +#define DPM_TABLE_338__UvdLevel_7_padding_0__SHIFT 0x8 +#define DPM_TABLE_338__UvdLevel_7_DclkDivider_MASK 0xff0000 +#define DPM_TABLE_338__UvdLevel_7_DclkDivider__SHIFT 0x10 +#define DPM_TABLE_338__UvdLevel_7_VclkDivider_MASK 0xff000000 +#define DPM_TABLE_338__UvdLevel_7_VclkDivider__SHIFT 0x18 +#define DPM_TABLE_339__VceLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_339__VceLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_341__VceLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_341__VceLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_341__VceLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_341__VceLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_341__VceLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_341__VceLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_341__VceLevel_0_Divider_MASK 0xff000000 +#define DPM_TABLE_341__VceLevel_0_Divider__SHIFT 0x18 +#define DPM_TABLE_342__VceLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_342__VceLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_344__VceLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_344__VceLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_344__VceLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_344__VceLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_344__VceLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_344__VceLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_344__VceLevel_1_Divider_MASK 0xff000000 +#define DPM_TABLE_344__VceLevel_1_Divider__SHIFT 0x18 +#define DPM_TABLE_345__VceLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_345__VceLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_347__VceLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_347__VceLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_347__VceLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_347__VceLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_347__VceLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_347__VceLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_347__VceLevel_2_Divider_MASK 0xff000000 +#define DPM_TABLE_347__VceLevel_2_Divider__SHIFT 0x18 +#define DPM_TABLE_348__VceLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_348__VceLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_350__VceLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_350__VceLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_350__VceLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_350__VceLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_350__VceLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_350__VceLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_350__VceLevel_3_Divider_MASK 0xff000000 +#define DPM_TABLE_350__VceLevel_3_Divider__SHIFT 0x18 +#define DPM_TABLE_351__VceLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_351__VceLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_353__VceLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_353__VceLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_353__VceLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_353__VceLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_353__VceLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_353__VceLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_353__VceLevel_4_Divider_MASK 0xff000000 +#define DPM_TABLE_353__VceLevel_4_Divider__SHIFT 0x18 +#define DPM_TABLE_354__VceLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_354__VceLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_356__VceLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_356__VceLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_356__VceLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_356__VceLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_356__VceLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_356__VceLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_356__VceLevel_5_Divider_MASK 0xff000000 +#define DPM_TABLE_356__VceLevel_5_Divider__SHIFT 0x18 +#define DPM_TABLE_357__VceLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_357__VceLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_359__VceLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_359__VceLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_359__VceLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_359__VceLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_359__VceLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_359__VceLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_359__VceLevel_6_Divider_MASK 0xff000000 +#define DPM_TABLE_359__VceLevel_6_Divider__SHIFT 0x18 +#define DPM_TABLE_360__VceLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_360__VceLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_362__VceLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_362__VceLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_362__VceLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_362__VceLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_362__VceLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_362__VceLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_362__VceLevel_7_Divider_MASK 0xff000000 +#define DPM_TABLE_362__VceLevel_7_Divider__SHIFT 0x18 +#define DPM_TABLE_363__AcpLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_363__AcpLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_365__AcpLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_365__AcpLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_365__AcpLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_365__AcpLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_365__AcpLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_365__AcpLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_365__AcpLevel_0_Divider_MASK 0xff000000 +#define DPM_TABLE_365__AcpLevel_0_Divider__SHIFT 0x18 +#define DPM_TABLE_366__AcpLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_366__AcpLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_368__AcpLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_368__AcpLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_368__AcpLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_368__AcpLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_368__AcpLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_368__AcpLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_368__AcpLevel_1_Divider_MASK 0xff000000 +#define DPM_TABLE_368__AcpLevel_1_Divider__SHIFT 0x18 +#define DPM_TABLE_369__AcpLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_369__AcpLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_371__AcpLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_371__AcpLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_371__AcpLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_371__AcpLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_371__AcpLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_371__AcpLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_371__AcpLevel_2_Divider_MASK 0xff000000 +#define DPM_TABLE_371__AcpLevel_2_Divider__SHIFT 0x18 +#define DPM_TABLE_372__AcpLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_372__AcpLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_374__AcpLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_374__AcpLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_374__AcpLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_374__AcpLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_374__AcpLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_374__AcpLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_374__AcpLevel_3_Divider_MASK 0xff000000 +#define DPM_TABLE_374__AcpLevel_3_Divider__SHIFT 0x18 +#define DPM_TABLE_375__AcpLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_375__AcpLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_377__AcpLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_377__AcpLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_377__AcpLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_377__AcpLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_377__AcpLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_377__AcpLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_377__AcpLevel_4_Divider_MASK 0xff000000 +#define DPM_TABLE_377__AcpLevel_4_Divider__SHIFT 0x18 +#define DPM_TABLE_378__AcpLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_378__AcpLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_380__AcpLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_380__AcpLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_380__AcpLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_380__AcpLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_380__AcpLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_380__AcpLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_380__AcpLevel_5_Divider_MASK 0xff000000 +#define DPM_TABLE_380__AcpLevel_5_Divider__SHIFT 0x18 +#define DPM_TABLE_381__AcpLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_381__AcpLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_383__AcpLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_383__AcpLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_383__AcpLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_383__AcpLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_383__AcpLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_383__AcpLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_383__AcpLevel_6_Divider_MASK 0xff000000 +#define DPM_TABLE_383__AcpLevel_6_Divider__SHIFT 0x18 +#define DPM_TABLE_384__AcpLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_384__AcpLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_386__AcpLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_386__AcpLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_386__AcpLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_386__AcpLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_386__AcpLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_386__AcpLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_386__AcpLevel_7_Divider_MASK 0xff000000 +#define DPM_TABLE_386__AcpLevel_7_Divider__SHIFT 0x18 +#define DPM_TABLE_387__SamuLevel_0_Frequency_MASK 0xffffffff +#define DPM_TABLE_387__SamuLevel_0_Frequency__SHIFT 0x0 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_389__SamuLevel_0_padding_2_MASK 0xff +#define DPM_TABLE_389__SamuLevel_0_padding_2__SHIFT 0x0 +#define DPM_TABLE_389__SamuLevel_0_padding_1_MASK 0xff00 +#define DPM_TABLE_389__SamuLevel_0_padding_1__SHIFT 0x8 +#define DPM_TABLE_389__SamuLevel_0_padding_0_MASK 0xff0000 +#define DPM_TABLE_389__SamuLevel_0_padding_0__SHIFT 0x10 +#define DPM_TABLE_389__SamuLevel_0_Divider_MASK 0xff000000 +#define DPM_TABLE_389__SamuLevel_0_Divider__SHIFT 0x18 +#define DPM_TABLE_390__SamuLevel_1_Frequency_MASK 0xffffffff +#define DPM_TABLE_390__SamuLevel_1_Frequency__SHIFT 0x0 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_392__SamuLevel_1_padding_2_MASK 0xff +#define DPM_TABLE_392__SamuLevel_1_padding_2__SHIFT 0x0 +#define DPM_TABLE_392__SamuLevel_1_padding_1_MASK 0xff00 +#define DPM_TABLE_392__SamuLevel_1_padding_1__SHIFT 0x8 +#define DPM_TABLE_392__SamuLevel_1_padding_0_MASK 0xff0000 +#define DPM_TABLE_392__SamuLevel_1_padding_0__SHIFT 0x10 +#define DPM_TABLE_392__SamuLevel_1_Divider_MASK 0xff000000 +#define DPM_TABLE_392__SamuLevel_1_Divider__SHIFT 0x18 +#define DPM_TABLE_393__SamuLevel_2_Frequency_MASK 0xffffffff +#define DPM_TABLE_393__SamuLevel_2_Frequency__SHIFT 0x0 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_395__SamuLevel_2_padding_2_MASK 0xff +#define DPM_TABLE_395__SamuLevel_2_padding_2__SHIFT 0x0 +#define DPM_TABLE_395__SamuLevel_2_padding_1_MASK 0xff00 +#define DPM_TABLE_395__SamuLevel_2_padding_1__SHIFT 0x8 +#define DPM_TABLE_395__SamuLevel_2_padding_0_MASK 0xff0000 +#define DPM_TABLE_395__SamuLevel_2_padding_0__SHIFT 0x10 +#define DPM_TABLE_395__SamuLevel_2_Divider_MASK 0xff000000 +#define DPM_TABLE_395__SamuLevel_2_Divider__SHIFT 0x18 +#define DPM_TABLE_396__SamuLevel_3_Frequency_MASK 0xffffffff +#define DPM_TABLE_396__SamuLevel_3_Frequency__SHIFT 0x0 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_398__SamuLevel_3_padding_2_MASK 0xff +#define DPM_TABLE_398__SamuLevel_3_padding_2__SHIFT 0x0 +#define DPM_TABLE_398__SamuLevel_3_padding_1_MASK 0xff00 +#define DPM_TABLE_398__SamuLevel_3_padding_1__SHIFT 0x8 +#define DPM_TABLE_398__SamuLevel_3_padding_0_MASK 0xff0000 +#define DPM_TABLE_398__SamuLevel_3_padding_0__SHIFT 0x10 +#define DPM_TABLE_398__SamuLevel_3_Divider_MASK 0xff000000 +#define DPM_TABLE_398__SamuLevel_3_Divider__SHIFT 0x18 +#define DPM_TABLE_399__SamuLevel_4_Frequency_MASK 0xffffffff +#define DPM_TABLE_399__SamuLevel_4_Frequency__SHIFT 0x0 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_401__SamuLevel_4_padding_2_MASK 0xff +#define DPM_TABLE_401__SamuLevel_4_padding_2__SHIFT 0x0 +#define DPM_TABLE_401__SamuLevel_4_padding_1_MASK 0xff00 +#define DPM_TABLE_401__SamuLevel_4_padding_1__SHIFT 0x8 +#define DPM_TABLE_401__SamuLevel_4_padding_0_MASK 0xff0000 +#define DPM_TABLE_401__SamuLevel_4_padding_0__SHIFT 0x10 +#define DPM_TABLE_401__SamuLevel_4_Divider_MASK 0xff000000 +#define DPM_TABLE_401__SamuLevel_4_Divider__SHIFT 0x18 +#define DPM_TABLE_402__SamuLevel_5_Frequency_MASK 0xffffffff +#define DPM_TABLE_402__SamuLevel_5_Frequency__SHIFT 0x0 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_404__SamuLevel_5_padding_2_MASK 0xff +#define DPM_TABLE_404__SamuLevel_5_padding_2__SHIFT 0x0 +#define DPM_TABLE_404__SamuLevel_5_padding_1_MASK 0xff00 +#define DPM_TABLE_404__SamuLevel_5_padding_1__SHIFT 0x8 +#define DPM_TABLE_404__SamuLevel_5_padding_0_MASK 0xff0000 +#define DPM_TABLE_404__SamuLevel_5_padding_0__SHIFT 0x10 +#define DPM_TABLE_404__SamuLevel_5_Divider_MASK 0xff000000 +#define DPM_TABLE_404__SamuLevel_5_Divider__SHIFT 0x18 +#define DPM_TABLE_405__SamuLevel_6_Frequency_MASK 0xffffffff +#define DPM_TABLE_405__SamuLevel_6_Frequency__SHIFT 0x0 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_407__SamuLevel_6_padding_2_MASK 0xff +#define DPM_TABLE_407__SamuLevel_6_padding_2__SHIFT 0x0 +#define DPM_TABLE_407__SamuLevel_6_padding_1_MASK 0xff00 +#define DPM_TABLE_407__SamuLevel_6_padding_1__SHIFT 0x8 +#define DPM_TABLE_407__SamuLevel_6_padding_0_MASK 0xff0000 +#define DPM_TABLE_407__SamuLevel_6_padding_0__SHIFT 0x10 +#define DPM_TABLE_407__SamuLevel_6_Divider_MASK 0xff000000 +#define DPM_TABLE_407__SamuLevel_6_Divider__SHIFT 0x18 +#define DPM_TABLE_408__SamuLevel_7_Frequency_MASK 0xffffffff +#define DPM_TABLE_408__SamuLevel_7_Frequency__SHIFT 0x0 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases_MASK 0xff +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_410__SamuLevel_7_padding_2_MASK 0xff +#define DPM_TABLE_410__SamuLevel_7_padding_2__SHIFT 0x0 +#define DPM_TABLE_410__SamuLevel_7_padding_1_MASK 0xff00 +#define DPM_TABLE_410__SamuLevel_7_padding_1__SHIFT 0x8 +#define DPM_TABLE_410__SamuLevel_7_padding_0_MASK 0xff0000 +#define DPM_TABLE_410__SamuLevel_7_padding_0__SHIFT 0x10 +#define DPM_TABLE_410__SamuLevel_7_Divider_MASK 0xff000000 +#define DPM_TABLE_410__SamuLevel_7_Divider__SHIFT 0x18 +#define DPM_TABLE_411__Ulv_CcPwrDynRm_MASK 0xffffffff +#define DPM_TABLE_411__Ulv_CcPwrDynRm__SHIFT 0x0 +#define DPM_TABLE_412__Ulv_CcPwrDynRm1_MASK 0xffffffff +#define DPM_TABLE_412__Ulv_CcPwrDynRm1__SHIFT 0x0 +#define DPM_TABLE_413__Ulv_VddcPhase_MASK 0xff +#define DPM_TABLE_413__Ulv_VddcPhase__SHIFT 0x0 +#define DPM_TABLE_413__Ulv_VddcOffsetVid_MASK 0xff00 +#define DPM_TABLE_413__Ulv_VddcOffsetVid__SHIFT 0x8 +#define DPM_TABLE_413__Ulv_VddcOffset_MASK 0xffff0000 +#define DPM_TABLE_413__Ulv_VddcOffset__SHIFT 0x10 +#define DPM_TABLE_414__Ulv_Reserved_MASK 0xffffffff +#define DPM_TABLE_414__Ulv_Reserved__SHIFT 0x0 +#define DPM_TABLE_415__SclkStepSize_MASK 0xffffffff +#define DPM_TABLE_415__SclkStepSize__SHIFT 0x0 +#define DPM_TABLE_416__Smio_0_MASK 0xffffffff +#define DPM_TABLE_416__Smio_0__SHIFT 0x0 +#define DPM_TABLE_417__Smio_1_MASK 0xffffffff +#define DPM_TABLE_417__Smio_1__SHIFT 0x0 +#define DPM_TABLE_418__Smio_2_MASK 0xffffffff +#define DPM_TABLE_418__Smio_2__SHIFT 0x0 +#define DPM_TABLE_419__Smio_3_MASK 0xffffffff +#define DPM_TABLE_419__Smio_3__SHIFT 0x0 +#define DPM_TABLE_420__Smio_4_MASK 0xffffffff +#define DPM_TABLE_420__Smio_4__SHIFT 0x0 +#define DPM_TABLE_421__Smio_5_MASK 0xffffffff +#define DPM_TABLE_421__Smio_5__SHIFT 0x0 +#define DPM_TABLE_422__Smio_6_MASK 0xffffffff +#define DPM_TABLE_422__Smio_6__SHIFT 0x0 +#define DPM_TABLE_423__Smio_7_MASK 0xffffffff +#define DPM_TABLE_423__Smio_7__SHIFT 0x0 +#define DPM_TABLE_424__Smio_8_MASK 0xffffffff +#define DPM_TABLE_424__Smio_8__SHIFT 0x0 +#define DPM_TABLE_425__Smio_9_MASK 0xffffffff +#define DPM_TABLE_425__Smio_9__SHIFT 0x0 +#define DPM_TABLE_426__Smio_10_MASK 0xffffffff +#define DPM_TABLE_426__Smio_10__SHIFT 0x0 +#define DPM_TABLE_427__Smio_11_MASK 0xffffffff +#define DPM_TABLE_427__Smio_11__SHIFT 0x0 +#define DPM_TABLE_428__Smio_12_MASK 0xffffffff +#define DPM_TABLE_428__Smio_12__SHIFT 0x0 +#define DPM_TABLE_429__Smio_13_MASK 0xffffffff +#define DPM_TABLE_429__Smio_13__SHIFT 0x0 +#define DPM_TABLE_430__Smio_14_MASK 0xffffffff +#define DPM_TABLE_430__Smio_14__SHIFT 0x0 +#define DPM_TABLE_431__Smio_15_MASK 0xffffffff +#define DPM_TABLE_431__Smio_15__SHIFT 0x0 +#define DPM_TABLE_432__Smio_16_MASK 0xffffffff +#define DPM_TABLE_432__Smio_16__SHIFT 0x0 +#define DPM_TABLE_433__Smio_17_MASK 0xffffffff +#define DPM_TABLE_433__Smio_17__SHIFT 0x0 +#define DPM_TABLE_434__Smio_18_MASK 0xffffffff +#define DPM_TABLE_434__Smio_18__SHIFT 0x0 +#define DPM_TABLE_435__Smio_19_MASK 0xffffffff +#define DPM_TABLE_435__Smio_19__SHIFT 0x0 +#define DPM_TABLE_436__Smio_20_MASK 0xffffffff +#define DPM_TABLE_436__Smio_20__SHIFT 0x0 +#define DPM_TABLE_437__Smio_21_MASK 0xffffffff +#define DPM_TABLE_437__Smio_21__SHIFT 0x0 +#define DPM_TABLE_438__Smio_22_MASK 0xffffffff +#define DPM_TABLE_438__Smio_22__SHIFT 0x0 +#define DPM_TABLE_439__Smio_23_MASK 0xffffffff +#define DPM_TABLE_439__Smio_23__SHIFT 0x0 +#define DPM_TABLE_440__Smio_24_MASK 0xffffffff +#define DPM_TABLE_440__Smio_24__SHIFT 0x0 +#define DPM_TABLE_441__Smio_25_MASK 0xffffffff +#define DPM_TABLE_441__Smio_25__SHIFT 0x0 +#define DPM_TABLE_442__Smio_26_MASK 0xffffffff +#define DPM_TABLE_442__Smio_26__SHIFT 0x0 +#define DPM_TABLE_443__Smio_27_MASK 0xffffffff +#define DPM_TABLE_443__Smio_27__SHIFT 0x0 +#define DPM_TABLE_444__Smio_28_MASK 0xffffffff +#define DPM_TABLE_444__Smio_28__SHIFT 0x0 +#define DPM_TABLE_445__Smio_29_MASK 0xffffffff +#define DPM_TABLE_445__Smio_29__SHIFT 0x0 +#define DPM_TABLE_446__Smio_30_MASK 0xffffffff +#define DPM_TABLE_446__Smio_30__SHIFT 0x0 +#define DPM_TABLE_447__Smio_31_MASK 0xffffffff +#define DPM_TABLE_447__Smio_31__SHIFT 0x0 +#define DPM_TABLE_448__SamuBootLevel_MASK 0xff +#define DPM_TABLE_448__SamuBootLevel__SHIFT 0x0 +#define DPM_TABLE_448__AcpBootLevel_MASK 0xff00 +#define DPM_TABLE_448__AcpBootLevel__SHIFT 0x8 +#define DPM_TABLE_448__VceBootLevel_MASK 0xff0000 +#define DPM_TABLE_448__VceBootLevel__SHIFT 0x10 +#define DPM_TABLE_448__UvdBootLevel_MASK 0xff000000 +#define DPM_TABLE_448__UvdBootLevel__SHIFT 0x18 +#define DPM_TABLE_449__GraphicsInterval_MASK 0xff +#define DPM_TABLE_449__GraphicsInterval__SHIFT 0x0 +#define DPM_TABLE_449__GraphicsThermThrottleEnable_MASK 0xff00 +#define DPM_TABLE_449__GraphicsThermThrottleEnable__SHIFT 0x8 +#define DPM_TABLE_449__GraphicsVoltageChangeEnable_MASK 0xff0000 +#define DPM_TABLE_449__GraphicsVoltageChangeEnable__SHIFT 0x10 +#define DPM_TABLE_449__GraphicsBootLevel_MASK 0xff000000 +#define DPM_TABLE_449__GraphicsBootLevel__SHIFT 0x18 +#define DPM_TABLE_450__TemperatureLimitHigh_MASK 0xffff +#define DPM_TABLE_450__TemperatureLimitHigh__SHIFT 0x0 +#define DPM_TABLE_450__ThermalInterval_MASK 0xff0000 +#define DPM_TABLE_450__ThermalInterval__SHIFT 0x10 +#define DPM_TABLE_450__VoltageInterval_MASK 0xff000000 +#define DPM_TABLE_450__VoltageInterval__SHIFT 0x18 +#define DPM_TABLE_451__MemoryVoltageChangeEnable_MASK 0xff +#define DPM_TABLE_451__MemoryVoltageChangeEnable__SHIFT 0x0 +#define DPM_TABLE_451__MemoryBootLevel_MASK 0xff00 +#define DPM_TABLE_451__MemoryBootLevel__SHIFT 0x8 +#define DPM_TABLE_451__TemperatureLimitLow_MASK 0xffff0000 +#define DPM_TABLE_451__TemperatureLimitLow__SHIFT 0x10 +#define DPM_TABLE_452__MemoryThermThrottleEnable_MASK 0xff +#define DPM_TABLE_452__MemoryThermThrottleEnable__SHIFT 0x0 +#define DPM_TABLE_452__MemoryInterval_MASK 0xff00 +#define DPM_TABLE_452__MemoryInterval__SHIFT 0x8 +#define DPM_TABLE_452__BootMVdd_MASK 0xffff0000 +#define DPM_TABLE_452__BootMVdd__SHIFT 0x10 +#define DPM_TABLE_453__PhaseResponseTime_MASK 0xffff +#define DPM_TABLE_453__PhaseResponseTime__SHIFT 0x0 +#define DPM_TABLE_453__VoltageResponseTime_MASK 0xffff0000 +#define DPM_TABLE_453__VoltageResponseTime__SHIFT 0x10 +#define DPM_TABLE_454__DTEMode_MASK 0xff +#define DPM_TABLE_454__DTEMode__SHIFT 0x0 +#define DPM_TABLE_454__DTEInterval_MASK 0xff00 +#define DPM_TABLE_454__DTEInterval__SHIFT 0x8 +#define DPM_TABLE_454__PCIeGenInterval_MASK 0xff0000 +#define DPM_TABLE_454__PCIeGenInterval__SHIFT 0x10 +#define DPM_TABLE_454__PCIeBootLinkLevel_MASK 0xff000000 +#define DPM_TABLE_454__PCIeBootLinkLevel__SHIFT 0x18 +#define DPM_TABLE_455__ThermGpio_MASK 0xff +#define DPM_TABLE_455__ThermGpio__SHIFT 0x0 +#define DPM_TABLE_455__AcDcGpio_MASK 0xff00 +#define DPM_TABLE_455__AcDcGpio__SHIFT 0x8 +#define DPM_TABLE_455__VRHotGpio_MASK 0xff0000 +#define DPM_TABLE_455__VRHotGpio__SHIFT 0x10 +#define DPM_TABLE_455__SVI2Enable_MASK 0xff000000 +#define DPM_TABLE_455__SVI2Enable__SHIFT 0x18 +#define DPM_TABLE_456__PPM_TemperatureLimit_MASK 0xffff +#define DPM_TABLE_456__PPM_TemperatureLimit__SHIFT 0x0 +#define DPM_TABLE_456__PPM_PkgPwrLimit_MASK 0xffff0000 +#define DPM_TABLE_456__PPM_PkgPwrLimit__SHIFT 0x10 +#define DPM_TABLE_457__TargetTdp_MASK 0xffff +#define DPM_TABLE_457__TargetTdp__SHIFT 0x0 +#define DPM_TABLE_457__DefaultTdp_MASK 0xffff0000 +#define DPM_TABLE_457__DefaultTdp__SHIFT 0x10 +#define DPM_TABLE_458__FpsLowThreshold_MASK 0xffff +#define DPM_TABLE_458__FpsLowThreshold__SHIFT 0x0 +#define DPM_TABLE_458__FpsHighThreshold_MASK 0xffff0000 +#define DPM_TABLE_458__FpsHighThreshold__SHIFT 0x10 +#define DPM_TABLE_459__BAPMTI_R_0_1_0_MASK 0xffff +#define DPM_TABLE_459__BAPMTI_R_0_1_0__SHIFT 0x0 +#define DPM_TABLE_459__BAPMTI_R_0_0_0_MASK 0xffff0000 +#define DPM_TABLE_459__BAPMTI_R_0_0_0__SHIFT 0x10 +#define DPM_TABLE_460__BAPMTI_R_1_0_0_MASK 0xffff +#define DPM_TABLE_460__BAPMTI_R_1_0_0__SHIFT 0x0 +#define DPM_TABLE_460__BAPMTI_R_0_2_0_MASK 0xffff0000 +#define DPM_TABLE_460__BAPMTI_R_0_2_0__SHIFT 0x10 +#define DPM_TABLE_461__BAPMTI_R_1_2_0_MASK 0xffff +#define DPM_TABLE_461__BAPMTI_R_1_2_0__SHIFT 0x0 +#define DPM_TABLE_461__BAPMTI_R_1_1_0_MASK 0xffff0000 +#define DPM_TABLE_461__BAPMTI_R_1_1_0__SHIFT 0x10 +#define DPM_TABLE_462__BAPMTI_R_2_1_0_MASK 0xffff +#define DPM_TABLE_462__BAPMTI_R_2_1_0__SHIFT 0x0 +#define DPM_TABLE_462__BAPMTI_R_2_0_0_MASK 0xffff0000 +#define DPM_TABLE_462__BAPMTI_R_2_0_0__SHIFT 0x10 +#define DPM_TABLE_463__BAPMTI_R_3_0_0_MASK 0xffff +#define DPM_TABLE_463__BAPMTI_R_3_0_0__SHIFT 0x0 +#define DPM_TABLE_463__BAPMTI_R_2_2_0_MASK 0xffff0000 +#define DPM_TABLE_463__BAPMTI_R_2_2_0__SHIFT 0x10 +#define DPM_TABLE_464__BAPMTI_R_3_2_0_MASK 0xffff +#define DPM_TABLE_464__BAPMTI_R_3_2_0__SHIFT 0x0 +#define DPM_TABLE_464__BAPMTI_R_3_1_0_MASK 0xffff0000 +#define DPM_TABLE_464__BAPMTI_R_3_1_0__SHIFT 0x10 +#define DPM_TABLE_465__BAPMTI_R_4_1_0_MASK 0xffff +#define DPM_TABLE_465__BAPMTI_R_4_1_0__SHIFT 0x0 +#define DPM_TABLE_465__BAPMTI_R_4_0_0_MASK 0xffff0000 +#define DPM_TABLE_465__BAPMTI_R_4_0_0__SHIFT 0x10 +#define DPM_TABLE_466__BAPMTI_RC_0_0_0_MASK 0xffff +#define DPM_TABLE_466__BAPMTI_RC_0_0_0__SHIFT 0x0 +#define DPM_TABLE_466__BAPMTI_R_4_2_0_MASK 0xffff0000 +#define DPM_TABLE_466__BAPMTI_R_4_2_0__SHIFT 0x10 +#define DPM_TABLE_467__BAPMTI_RC_0_2_0_MASK 0xffff +#define DPM_TABLE_467__BAPMTI_RC_0_2_0__SHIFT 0x0 +#define DPM_TABLE_467__BAPMTI_RC_0_1_0_MASK 0xffff0000 +#define DPM_TABLE_467__BAPMTI_RC_0_1_0__SHIFT 0x10 +#define DPM_TABLE_468__BAPMTI_RC_1_1_0_MASK 0xffff +#define DPM_TABLE_468__BAPMTI_RC_1_1_0__SHIFT 0x0 +#define DPM_TABLE_468__BAPMTI_RC_1_0_0_MASK 0xffff0000 +#define DPM_TABLE_468__BAPMTI_RC_1_0_0__SHIFT 0x10 +#define DPM_TABLE_469__BAPMTI_RC_2_0_0_MASK 0xffff +#define DPM_TABLE_469__BAPMTI_RC_2_0_0__SHIFT 0x0 +#define DPM_TABLE_469__BAPMTI_RC_1_2_0_MASK 0xffff0000 +#define DPM_TABLE_469__BAPMTI_RC_1_2_0__SHIFT 0x10 +#define DPM_TABLE_470__BAPMTI_RC_2_2_0_MASK 0xffff +#define DPM_TABLE_470__BAPMTI_RC_2_2_0__SHIFT 0x0 +#define DPM_TABLE_470__BAPMTI_RC_2_1_0_MASK 0xffff0000 +#define DPM_TABLE_470__BAPMTI_RC_2_1_0__SHIFT 0x10 +#define DPM_TABLE_471__BAPMTI_RC_3_1_0_MASK 0xffff +#define DPM_TABLE_471__BAPMTI_RC_3_1_0__SHIFT 0x0 +#define DPM_TABLE_471__BAPMTI_RC_3_0_0_MASK 0xffff0000 +#define DPM_TABLE_471__BAPMTI_RC_3_0_0__SHIFT 0x10 +#define DPM_TABLE_472__BAPMTI_RC_4_0_0_MASK 0xffff +#define DPM_TABLE_472__BAPMTI_RC_4_0_0__SHIFT 0x0 +#define DPM_TABLE_472__BAPMTI_RC_3_2_0_MASK 0xffff0000 +#define DPM_TABLE_472__BAPMTI_RC_3_2_0__SHIFT 0x10 +#define DPM_TABLE_473__BAPMTI_RC_4_2_0_MASK 0xffff +#define DPM_TABLE_473__BAPMTI_RC_4_2_0__SHIFT 0x0 +#define DPM_TABLE_473__BAPMTI_RC_4_1_0_MASK 0xffff0000 +#define DPM_TABLE_473__BAPMTI_RC_4_1_0__SHIFT 0x10 +#define DPM_TABLE_474__GpuTjHyst_MASK 0xff +#define DPM_TABLE_474__GpuTjHyst__SHIFT 0x0 +#define DPM_TABLE_474__GpuTjMax_MASK 0xff00 +#define DPM_TABLE_474__GpuTjMax__SHIFT 0x8 +#define DPM_TABLE_474__DTETjOffset_MASK 0xff0000 +#define DPM_TABLE_474__DTETjOffset__SHIFT 0x10 +#define DPM_TABLE_474__DTEAmbientTempBase_MASK 0xff000000 +#define DPM_TABLE_474__DTEAmbientTempBase__SHIFT 0x18 +#define DPM_TABLE_475__BootVoltage_Phases_MASK 0xff +#define DPM_TABLE_475__BootVoltage_Phases__SHIFT 0x0 +#define DPM_TABLE_475__BootVoltage_VddGfx_MASK 0xff00 +#define DPM_TABLE_475__BootVoltage_VddGfx__SHIFT 0x8 +#define DPM_TABLE_475__BootVoltage_Vddci_MASK 0xff0000 +#define DPM_TABLE_475__BootVoltage_Vddci__SHIFT 0x10 +#define DPM_TABLE_475__BootVoltage_Vddc_MASK 0xff000000 +#define DPM_TABLE_475__BootVoltage_Vddc__SHIFT 0x18 +#define DPM_TABLE_476__BAPM_TEMP_GRADIENT_MASK 0xffffffff +#define DPM_TABLE_476__BAPM_TEMP_GRADIENT__SHIFT 0x0 +#define DPM_TABLE_477__LowSclkInterruptThreshold_MASK 0xffffffff +#define DPM_TABLE_477__LowSclkInterruptThreshold__SHIFT 0x0 +#define DPM_TABLE_478__VddGfxReChkWait_MASK 0xffffffff +#define DPM_TABLE_478__VddGfxReChkWait__SHIFT 0x0 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1_MASK 0xff +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1__SHIFT 0x0 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0_MASK 0xff00 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0__SHIFT 0x8 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID_MASK 0xff0000 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID__SHIFT 0x10 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID_MASK 0xff000000 +#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID__SHIFT 0x18 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3_MASK 0xff +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3__SHIFT 0x0 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2_MASK 0xff00 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2__SHIFT 0x8 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1_MASK 0xff0000 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1__SHIFT 0x10 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0_MASK 0xff000000 +#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0__SHIFT 0x18 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7_MASK 0xff +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7__SHIFT 0x0 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6_MASK 0xff00 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6__SHIFT 0x8 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5_MASK 0xff0000 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5__SHIFT 0x10 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4_MASK 0xff000000 +#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4__SHIFT 0x18 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1_MASK 0xff +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1__SHIFT 0x0 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0_MASK 0xff00 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0__SHIFT 0x8 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID_MASK 0xff0000 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID__SHIFT 0x10 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID_MASK 0xff000000 +#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID__SHIFT 0x18 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3_MASK 0xff +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3__SHIFT 0x0 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2_MASK 0xff00 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2__SHIFT 0x8 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1_MASK 0xff0000 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1__SHIFT 0x10 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0_MASK 0xff000000 +#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0__SHIFT 0x18 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7_MASK 0xff +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7__SHIFT 0x0 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6_MASK 0xff00 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6__SHIFT 0x8 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5_MASK 0xff0000 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5__SHIFT 0x10 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4_MASK 0xff000000 +#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4__SHIFT 0x18 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1_MASK 0xff +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1__SHIFT 0x0 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0_MASK 0xff00 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0__SHIFT 0x8 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID_MASK 0xff0000 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID__SHIFT 0x10 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID_MASK 0xff000000 +#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID__SHIFT 0x18 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3_MASK 0xff +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3__SHIFT 0x0 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2_MASK 0xff00 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2__SHIFT 0x8 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1_MASK 0xff0000 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1__SHIFT 0x10 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0_MASK 0xff000000 +#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0__SHIFT 0x18 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7_MASK 0xff +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7__SHIFT 0x0 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6_MASK 0xff00 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6__SHIFT 0x8 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5_MASK 0xff0000 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5__SHIFT 0x10 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4_MASK 0xff000000 +#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4__SHIFT 0x18 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1_MASK 0xff +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1__SHIFT 0x0 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0_MASK 0xff00 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0__SHIFT 0x8 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID_MASK 0xff0000 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID__SHIFT 0x10 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID_MASK 0xff000000 +#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID__SHIFT 0x18 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3_MASK 0xff +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3__SHIFT 0x0 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2_MASK 0xff00 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2__SHIFT 0x8 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1_MASK 0xff0000 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1__SHIFT 0x10 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0_MASK 0xff000000 +#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0__SHIFT 0x18 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7_MASK 0xff +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7__SHIFT 0x0 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6_MASK 0xff00 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6__SHIFT 0x8 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5_MASK 0xff0000 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5__SHIFT 0x10 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4_MASK 0xff000000 +#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18 +#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff +#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000 +#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18 +#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff +#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00 +#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8 +#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000 +#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000 +#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18 +#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff +#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000 +#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10 +#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0 +#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff +#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0 +#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff +#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0 +#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff +#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0 +#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff +#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0 +#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff +#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0 +#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff +#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0 +#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff +#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0 +#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff +#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0 +#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff +#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0 +#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff +#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0 +#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff +#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0 +#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff +#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0 +#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff +#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0 +#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff +#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0 +#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff +#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0 +#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff +#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0 +#define FAN_TABLE_1__TempMin_MASK 0xffff +#define FAN_TABLE_1__TempMin__SHIFT 0x0 +#define FAN_TABLE_1__FdoMode_MASK 0xffff0000 +#define FAN_TABLE_1__FdoMode__SHIFT 0x10 +#define FAN_TABLE_2__TempMax_MASK 0xffff +#define FAN_TABLE_2__TempMax__SHIFT 0x0 +#define FAN_TABLE_2__TempMed_MASK 0xffff0000 +#define FAN_TABLE_2__TempMed__SHIFT 0x10 +#define FAN_TABLE_3__Slope2_MASK 0xffff +#define FAN_TABLE_3__Slope2__SHIFT 0x0 +#define FAN_TABLE_3__Slope1_MASK 0xffff0000 +#define FAN_TABLE_3__Slope1__SHIFT 0x10 +#define FAN_TABLE_4__HystUp_MASK 0xffff +#define FAN_TABLE_4__HystUp__SHIFT 0x0 +#define FAN_TABLE_4__FdoMin_MASK 0xffff0000 +#define FAN_TABLE_4__FdoMin__SHIFT 0x10 +#define FAN_TABLE_5__HystSlope_MASK 0xffff +#define FAN_TABLE_5__HystSlope__SHIFT 0x0 +#define FAN_TABLE_5__HystDown_MASK 0xffff0000 +#define FAN_TABLE_5__HystDown__SHIFT 0x10 +#define FAN_TABLE_6__TempCurr_MASK 0xffff +#define FAN_TABLE_6__TempCurr__SHIFT 0x0 +#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000 +#define FAN_TABLE_6__TempRespLim__SHIFT 0x10 +#define FAN_TABLE_7__PwmCurr_MASK 0xffff +#define FAN_TABLE_7__PwmCurr__SHIFT 0x0 +#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000 +#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10 +#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff +#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0 +#define FAN_TABLE_9__Padding_MASK 0xff +#define FAN_TABLE_9__Padding__SHIFT 0x0 +#define FAN_TABLE_9__TempSrc_MASK 0xff00 +#define FAN_TABLE_9__TempSrc__SHIFT 0x8 +#define FAN_TABLE_9__FdoMax_MASK 0xffff0000 +#define FAN_TABLE_9__FdoMax__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff +#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff +#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00 +#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000 +#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000 +#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18 +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_29__Reserved_0_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_29__Reserved_0__SHIFT 0x0 +#define SOFT_REGISTERS_TABLE_30__Reserved_1_MASK 0xffffffff +#define SOFT_REGISTERS_TABLE_30__Reserved_1__SHIFT 0x0 +#define PM_FUSES_1__SviLoadLineOffsetVddC_MASK 0xff +#define PM_FUSES_1__SviLoadLineOffsetVddC__SHIFT 0x0 +#define PM_FUSES_1__SviLoadLineTrimVddC_MASK 0xff00 +#define PM_FUSES_1__SviLoadLineTrimVddC__SHIFT 0x8 +#define PM_FUSES_1__SviLoadLineVddC_MASK 0xff0000 +#define PM_FUSES_1__SviLoadLineVddC__SHIFT 0x10 +#define PM_FUSES_1__SviLoadLineEn_MASK 0xff000000 +#define PM_FUSES_1__SviLoadLineEn__SHIFT 0x18 +#define PM_FUSES_2__TDC_MAWt_MASK 0xff +#define PM_FUSES_2__TDC_MAWt__SHIFT 0x0 +#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00 +#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8 +#define PM_FUSES_2__TDC_VDDC_PkgLimit_MASK 0xffff0000 +#define PM_FUSES_2__TDC_VDDC_PkgLimit__SHIFT 0x10 +#define PM_FUSES_3__Reserved_MASK 0xff +#define PM_FUSES_3__Reserved__SHIFT 0x0 +#define PM_FUSES_3__LPMLTemperatureMax_MASK 0xff00 +#define PM_FUSES_3__LPMLTemperatureMax__SHIFT 0x8 +#define PM_FUSES_3__LPMLTemperatureMin_MASK 0xff0000 +#define PM_FUSES_3__LPMLTemperatureMin__SHIFT 0x10 +#define PM_FUSES_3__TdcWaterfallCtl_MASK 0xff000000 +#define PM_FUSES_3__TdcWaterfallCtl__SHIFT 0x18 +#define PM_FUSES_4__LPMLTemperatureScaler_3_MASK 0xff +#define PM_FUSES_4__LPMLTemperatureScaler_3__SHIFT 0x0 +#define PM_FUSES_4__LPMLTemperatureScaler_2_MASK 0xff00 +#define PM_FUSES_4__LPMLTemperatureScaler_2__SHIFT 0x8 +#define PM_FUSES_4__LPMLTemperatureScaler_1_MASK 0xff0000 +#define PM_FUSES_4__LPMLTemperatureScaler_1__SHIFT 0x10 +#define PM_FUSES_4__LPMLTemperatureScaler_0_MASK 0xff000000 +#define PM_FUSES_4__LPMLTemperatureScaler_0__SHIFT 0x18 +#define PM_FUSES_5__LPMLTemperatureScaler_7_MASK 0xff +#define PM_FUSES_5__LPMLTemperatureScaler_7__SHIFT 0x0 +#define PM_FUSES_5__LPMLTemperatureScaler_6_MASK 0xff00 +#define PM_FUSES_5__LPMLTemperatureScaler_6__SHIFT 0x8 +#define PM_FUSES_5__LPMLTemperatureScaler_5_MASK 0xff0000 +#define PM_FUSES_5__LPMLTemperatureScaler_5__SHIFT 0x10 +#define PM_FUSES_5__LPMLTemperatureScaler_4_MASK 0xff000000 +#define PM_FUSES_5__LPMLTemperatureScaler_4__SHIFT 0x18 +#define PM_FUSES_6__LPMLTemperatureScaler_11_MASK 0xff +#define PM_FUSES_6__LPMLTemperatureScaler_11__SHIFT 0x0 +#define PM_FUSES_6__LPMLTemperatureScaler_10_MASK 0xff00 +#define PM_FUSES_6__LPMLTemperatureScaler_10__SHIFT 0x8 +#define PM_FUSES_6__LPMLTemperatureScaler_9_MASK 0xff0000 +#define PM_FUSES_6__LPMLTemperatureScaler_9__SHIFT 0x10 +#define PM_FUSES_6__LPMLTemperatureScaler_8_MASK 0xff000000 +#define PM_FUSES_6__LPMLTemperatureScaler_8__SHIFT 0x18 +#define PM_FUSES_7__LPMLTemperatureScaler_15_MASK 0xff +#define PM_FUSES_7__LPMLTemperatureScaler_15__SHIFT 0x0 +#define PM_FUSES_7__LPMLTemperatureScaler_14_MASK 0xff00 +#define PM_FUSES_7__LPMLTemperatureScaler_14__SHIFT 0x8 +#define PM_FUSES_7__LPMLTemperatureScaler_13_MASK 0xff0000 +#define PM_FUSES_7__LPMLTemperatureScaler_13__SHIFT 0x10 +#define PM_FUSES_7__LPMLTemperatureScaler_12_MASK 0xff000000 +#define PM_FUSES_7__LPMLTemperatureScaler_12__SHIFT 0x18 +#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta_MASK 0xffff +#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0 +#define PM_FUSES_8__FuzzyFan_ErrorSetDelta_MASK 0xffff0000 +#define PM_FUSES_8__FuzzyFan_ErrorSetDelta__SHIFT 0x10 +#define PM_FUSES_9__Reserved6_MASK 0xffff +#define PM_FUSES_9__Reserved6__SHIFT 0x0 +#define PM_FUSES_9__FuzzyFan_PwmSetDelta_MASK 0xffff0000 +#define PM_FUSES_9__FuzzyFan_PwmSetDelta__SHIFT 0x10 +#define PM_FUSES_10__GnbLPML_3_MASK 0xff +#define PM_FUSES_10__GnbLPML_3__SHIFT 0x0 +#define PM_FUSES_10__GnbLPML_2_MASK 0xff00 +#define PM_FUSES_10__GnbLPML_2__SHIFT 0x8 +#define PM_FUSES_10__GnbLPML_1_MASK 0xff0000 +#define PM_FUSES_10__GnbLPML_1__SHIFT 0x10 +#define PM_FUSES_10__GnbLPML_0_MASK 0xff000000 +#define PM_FUSES_10__GnbLPML_0__SHIFT 0x18 +#define PM_FUSES_11__GnbLPML_7_MASK 0xff +#define PM_FUSES_11__GnbLPML_7__SHIFT 0x0 +#define PM_FUSES_11__GnbLPML_6_MASK 0xff00 +#define PM_FUSES_11__GnbLPML_6__SHIFT 0x8 +#define PM_FUSES_11__GnbLPML_5_MASK 0xff0000 +#define PM_FUSES_11__GnbLPML_5__SHIFT 0x10 +#define PM_FUSES_11__GnbLPML_4_MASK 0xff000000 +#define PM_FUSES_11__GnbLPML_4__SHIFT 0x18 +#define PM_FUSES_12__GnbLPML_11_MASK 0xff +#define PM_FUSES_12__GnbLPML_11__SHIFT 0x0 +#define PM_FUSES_12__GnbLPML_10_MASK 0xff00 +#define PM_FUSES_12__GnbLPML_10__SHIFT 0x8 +#define PM_FUSES_12__GnbLPML_9_MASK 0xff0000 +#define PM_FUSES_12__GnbLPML_9__SHIFT 0x10 +#define PM_FUSES_12__GnbLPML_8_MASK 0xff000000 +#define PM_FUSES_12__GnbLPML_8__SHIFT 0x18 +#define PM_FUSES_13__GnbLPML_15_MASK 0xff +#define PM_FUSES_13__GnbLPML_15__SHIFT 0x0 +#define PM_FUSES_13__GnbLPML_14_MASK 0xff00 +#define PM_FUSES_13__GnbLPML_14__SHIFT 0x8 +#define PM_FUSES_13__GnbLPML_13_MASK 0xff0000 +#define PM_FUSES_13__GnbLPML_13__SHIFT 0x10 +#define PM_FUSES_13__GnbLPML_12_MASK 0xff000000 +#define PM_FUSES_13__GnbLPML_12__SHIFT 0x18 +#define PM_FUSES_14__Reserved1_1_MASK 0xff +#define PM_FUSES_14__Reserved1_1__SHIFT 0x0 +#define PM_FUSES_14__Reserved1_0_MASK 0xff00 +#define PM_FUSES_14__Reserved1_0__SHIFT 0x8 +#define PM_FUSES_14__GnbLPMLMinVid_MASK 0xff0000 +#define PM_FUSES_14__GnbLPMLMinVid__SHIFT 0x10 +#define PM_FUSES_14__GnbLPMLMaxVid_MASK 0xff000000 +#define PM_FUSES_14__GnbLPMLMaxVid__SHIFT 0x18 +#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd_MASK 0xffff +#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd__SHIFT 0x0 +#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000 +#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd__SHIFT 0x10 +#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_52__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 +#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff +#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7 +#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0 +#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8 +#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3 +#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0 +#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4 +#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000 +#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe +#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000 +#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000 +#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19 +#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000 +#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a +#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff +#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00 +#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 +#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000 +#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11 +#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000 +#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12 +#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff +#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0 +#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00 +#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8 +#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000 +#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10 +#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000 +#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18 +#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf +#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 +#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x1f0 +#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 +#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000 +#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 +#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff +#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00 +#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000 +#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000 +#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 +#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000 +#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 +#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff +#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 +#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00 +#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 +#define CG_FDO_CTRL1__M_MASK 0xff0000 +#define CG_FDO_CTRL1__M__SHIFT 0x10 +#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000 +#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 +#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000 +#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e +#define CG_FDO_CTRL2__TMIN_MASK 0xff +#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700 +#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 +#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800 +#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb +#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000 +#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe +#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000 +#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000 +#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 +#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7 +#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 +#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8 +#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 +#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff +#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 +#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe +#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1 +#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00 +#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000 +#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11 +#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000 +#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12 +#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000 +#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000 +#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18 +#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000 +#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19 +#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000 +#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a +#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000 +#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b +#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000 +#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c +#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000 +#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d +#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000 +#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f +#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff +#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0 +#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800 +#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb +#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_INT_DATA__Z_MASK 0x7ff +#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON0_INT_DATA__VALID_MASK 0x800 +#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON1_INT_DATA__Z_MASK 0x7ff +#define THM_TMON1_INT_DATA__Z__SHIFT 0x0 +#define THM_TMON1_INT_DATA__VALID_MASK 0x800 +#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb +#define THM_TMON1_INT_DATA__TEMP_MASK 0xfff000 +#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc +#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 +#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x1f +#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0xffe0 +#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5 +#define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f +#define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0 +#define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20 +#define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5 +#define THM_TMON1_STATUS__CURRENT_RDI_MASK 0x1f +#define THM_TMON1_STATUS__CURRENT_RDI__SHIFT 0x0 +#define THM_TMON1_STATUS__MEAS_DONE_MASK 0x20 +#define THM_TMON1_STATUS__MEAS_DONE__SHIFT 0x5 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 +#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 +#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 +#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 +#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 +#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1 +#define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0 +#define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff +#define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 +#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf +#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 +#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 +#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 +#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 +#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 +#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 +#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf +#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 +#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 +#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 +#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff +#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 +#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define PWR_CKS_ENABLE__STRETCH_ENABLE_MASK 0x1 +#define PWR_CKS_ENABLE__STRETCH_ENABLE__SHIFT 0x0 +#define PWR_CKS_ENABLE__masterReset_MASK 0x2 +#define PWR_CKS_ENABLE__masterReset__SHIFT 0x1 +#define PWR_CKS_ENABLE__staticEnable_MASK 0x4 +#define PWR_CKS_ENABLE__staticEnable__SHIFT 0x2 +#define PWR_CKS_CNTL__CKS_BYPASS_MASK 0x1 +#define PWR_CKS_CNTL__CKS_BYPASS__SHIFT 0x0 +#define PWR_CKS_CNTL__CKS_PCCEnable_MASK 0x2 +#define PWR_CKS_CNTL__CKS_PCCEnable__SHIFT 0x1 +#define PWR_CKS_CNTL__CKS_TEMP_COMP_MASK 0x4 +#define PWR_CKS_CNTL__CKS_TEMP_COMP__SHIFT 0x2 +#define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT_MASK 0x78 +#define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT__SHIFT 0x3 +#define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS_MASK 0x80 +#define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS__SHIFT 0x7 +#define PWR_CKS_CNTL__CKS_SAMPLE_SIZE_MASK 0xf00 +#define PWR_CKS_CNTL__CKS_SAMPLE_SIZE__SHIFT 0x8 +#define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES_MASK 0xf000 +#define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES__SHIFT 0xc +#define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ_MASK 0x10000 +#define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ__SHIFT 0x10 +#define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP_MASK 0x20000 +#define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP__SHIFT 0x11 +#define PWR_CKS_CNTL__CKS_LDO_REFSEL_MASK 0x3c0000 +#define PWR_CKS_CNTL__CKS_LDO_REFSEL__SHIFT 0x12 +#define PWR_CKS_CNTL__DDT_DEBUS_SEL_MASK 0x400000 +#define PWR_CKS_CNTL__DDT_DEBUS_SEL__SHIFT 0x16 +#define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL_MASK 0x7f800000 +#define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL__SHIFT 0x17 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x4 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x4 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 +#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff +#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2 +#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1 +#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4 +#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000 +#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10 +#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000 +#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000 +#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a +#define ROM_STATUS__ROM_BUSY_MASK 0x1 +#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf +#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define ROM_INDEX__ROM_INDEX_MASK 0xffffff +#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 +#define ROM_DATA__ROM_DATA_MASK 0xffffffff +#define ROM_DATA__ROM_DATA__SHIFT 0x0 +#define ROM_START__ROM_START_MASK 0xffffff +#define ROM_START__ROM_START__SHIFT 0x0 +#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff +#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 +#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000 +#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 +#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1 +#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 +#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff +#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 + +#endif /* SMU_7_1_2_SH_MASK_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h new file mode 100644 index 000000000000..b404815ab2c4 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h @@ -0,0 +1,671 @@ +/* + * SMU_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_8_0_D_H +#define SMU_8_0_D_H + +#define ixTHM_TCON_CSR_CONFIG 0xd82014a4 +#define ixTHM_TCON_CSR_DATA 0xd82014a8 +#define ixTHM_TCON_HTC 0xd8200c64 +#define ixTHM_TCON_CUR_TMP 0xd8200ca4 +#define ixTHM_TCON_THERM_TRIP 0xd8200ce4 +#define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00 +#define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04 +#define ixTHM_THERMAL_INT_ENA 0xd8200d10 +#define ixTHM_THERMAL_INT_CTRL 0xd8200d14 +#define ixTHM_THERMAL_INT_STATUS 0xd8200d18 +#define ixTMON0_RDIL0_DATA 0xd8202000 +#define ixTMON0_RDIL1_DATA 0xd8202004 +#define ixTMON0_RDIL2_DATA 0xd8202008 +#define ixTMON0_RDIL3_DATA 0xd820200c +#define ixTMON0_RDIL4_DATA 0xd8202010 +#define ixTMON0_RDIL5_DATA 0xd8202014 +#define ixTMON0_RDIL6_DATA 0xd8202018 +#define ixTMON0_RDIL7_DATA 0xd820201c +#define ixTMON0_RDIL8_DATA 0xd8202020 +#define ixTMON0_RDIL9_DATA 0xd8202024 +#define ixTMON0_RDIL10_DATA 0xd8202028 +#define ixTMON0_RDIL11_DATA 0xd820202c +#define ixTMON0_RDIL12_DATA 0xd8202030 +#define ixTMON0_RDIL13_DATA 0xd8202034 +#define ixTMON0_RDIL14_DATA 0xd8202038 +#define ixTMON0_RDIL15_DATA 0xd820203c +#define ixTMON0_RDIR0_DATA 0xd8202040 +#define ixTMON0_RDIR1_DATA 0xd8202044 +#define ixTMON0_RDIR2_DATA 0xd8202048 +#define ixTMON0_RDIR3_DATA 0xd820204c +#define ixTMON0_RDIR4_DATA 0xd8202050 +#define ixTMON0_RDIR5_DATA 0xd8202054 +#define ixTMON0_RDIR6_DATA 0xd8202058 +#define ixTMON0_RDIR7_DATA 0xd820205c +#define ixTMON0_RDIR8_DATA 0xd8202060 +#define ixTMON0_RDIR9_DATA 0xd8202064 +#define ixTMON0_RDIR10_DATA 0xd8202068 +#define ixTMON0_RDIR11_DATA 0xd820206c +#define ixTMON0_RDIR12_DATA 0xd8202070 +#define ixTMON0_RDIR13_DATA 0xd8202074 +#define ixTMON0_RDIR14_DATA 0xd8202078 +#define ixTMON0_RDIR15_DATA 0xd820207c +#define ixTMON0_INT_DATA 0xd8202080 +#define ixTMON0_RDIL_PRESENT0 0xd8202084 +#define ixTMON0_RDIL_PRESENT1 0xd8202088 +#define ixTMON0_RDIR_PRESENT0 0xd820208c +#define ixTMON0_RDIR_PRESENT1 0xd8202090 +#define ixTMON0_CONFIG 0xd8202098 +#define ixTMON0_TEMP_CALC_COEFF0 0xd82020a0 +#define ixTMON0_TEMP_CALC_COEFF1 0xd82020a4 +#define ixTMON0_TEMP_CALC_COEFF2 0xd82020a8 +#define ixTMON0_TEMP_CALC_COEFF3 0xd82020ac +#define ixTMON0_TEMP_CALC_COEFF4 0xd82020b0 +#define ixTMON0_DEBUG0 0xd82020b4 +#define ixTMON0_DEBUG1 0xd82020b8 +#define ixTMON1_RDIL0_DATA 0xd8202100 +#define ixTMON1_RDIL1_DATA 0xd8202104 +#define ixTMON1_RDIL2_DATA 0xd8202108 +#define ixTMON1_RDIL3_DATA 0xd820210c +#define ixTMON1_RDIL4_DATA 0xd8202110 +#define ixTMON1_RDIL5_DATA 0xd8202114 +#define ixTMON1_RDIL6_DATA 0xd8202118 +#define ixTMON1_RDIL7_DATA 0xd820211c +#define ixTMON1_RDIL8_DATA 0xd8202120 +#define ixTMON1_RDIL9_DATA 0xd8202124 +#define ixTMON1_RDIL10_DATA 0xd8202128 +#define ixTMON1_RDIL11_DATA 0xd820212c +#define ixTMON1_RDIL12_DATA 0xd8202130 +#define ixTMON1_RDIL13_DATA 0xd8202134 +#define ixTMON1_RDIL14_DATA 0xd8202138 +#define ixTMON1_RDIL15_DATA 0xd820213c +#define ixTMON1_RDIR0_DATA 0xd8202140 +#define ixTMON1_RDIR1_DATA 0xd8202144 +#define ixTMON1_RDIR2_DATA 0xd8202148 +#define ixTMON1_RDIR3_DATA 0xd820214c +#define ixTMON1_RDIR4_DATA 0xd8202150 +#define ixTMON1_RDIR5_DATA 0xd8202154 +#define ixTMON1_RDIR6_DATA 0xd8202158 +#define ixTMON1_RDIR7_DATA 0xd820215c +#define ixTMON1_RDIR8_DATA 0xd8202160 +#define ixTMON1_RDIR9_DATA 0xd8202164 +#define ixTMON1_RDIR10_DATA 0xd8202168 +#define ixTMON1_RDIR11_DATA 0xd820216c +#define ixTMON1_RDIR12_DATA 0xd8202170 +#define ixTMON1_RDIR13_DATA 0xd8202174 +#define ixTMON1_RDIR14_DATA 0xd8202178 +#define ixTMON1_RDIR15_DATA 0xd820217c +#define ixTMON1_INT_DATA 0xd8202180 +#define ixTMON1_RDIL_PRESENT0 0xd8202184 +#define ixTMON1_RDIL_PRESENT1 0xd8202188 +#define ixTMON1_RDIR_PRESENT0 0xd820218c +#define ixTMON1_RDIR_PRESENT1 0xd8202190 +#define ixTMON1_CONFIG 0xd8202198 +#define ixTMON1_TEMP_CALC_COEFF0 0xd82021a0 +#define ixTMON1_TEMP_CALC_COEFF1 0xd82021a4 +#define ixTMON1_TEMP_CALC_COEFF2 0xd82021a8 +#define ixTMON1_TEMP_CALC_COEFF3 0xd82021ac +#define ixTMON1_TEMP_CALC_COEFF4 0xd82021b0 +#define ixTMON1_DEBUG0 0xd82021b4 +#define ixTMON1_DEBUG1 0xd82021b8 +#define ixTHM_TMON0_REMOTE_START 0xd8202800 +#define ixTHM_TMON0_REMOTE_END 0xd82028fc +#define ixTHM_TMON1_REMOTE_START 0xd8202900 +#define ixTHM_TMON1_REMOTE_END 0xd82029fc +#define ixTHM_TCON_LOCAL0 0xd8202e00 +#define ixTHM_TCON_LOCAL1 0xd8202e04 +#define ixTHM_TCON_LOCAL2 0xd8202e08 +#define ixTHM_TCON_LOCAL3 0xd8202e0c +#define ixTHM_TCON_LOCAL4 0xd8202e10 +#define ixTHM_TCON_LOCAL5 0xd8202e14 +#define ixTHM_TCON_LOCAL6 0xd8202e18 +#define ixTHM_TCON_LOCAL7 0xd8202e1c +#define ixTHM_TCON_LOCAL8 0xd8202e20 +#define ixTHM_TCON_LOCAL9 0xd8202e24 +#define ixTHM_TCON_LOCAL10 0xd8202e28 +#define ixTHM_TCON_LOCAL11 0xd8202e2c +#define ixTHM_TCON_LOCAL12 0xd8202e30 +#define ixTHM_TCON_LOCAL13 0xd8202ef8 +#define ixTHM_TCON_LOCAL14 0xd8202efc +#define ixTHM_FUSE0 0xd8210000 +#define ixTHM_FUSE1 0xd8210004 +#define ixTHM_FUSE2 0xd8210008 +#define ixTHM_FUSE3 0xd821000c +#define ixTHM_FUSE4 0xd8210010 +#define ixTHM_FUSE5 0xd8210014 +#define ixTHM_FUSE6 0xd8210018 +#define ixTHM_FUSE7 0xd821001c +#define ixTHM_FUSE8 0xd8210020 +#define ixTHM_FUSE9 0xd8210024 +#define ixTHM_FUSE10 0xd8210028 +#define ixTHM_FUSE11 0xd821002c +#define ixTHM_FUSE12 0xd8210030 +#define mmMP0PUB_IND_INDEX 0x180 +#define mmMP_SMUIF0_MP0PUB_IND_INDEX 0x180 +#define mmMP_SMUIF1_MP0PUB_IND_INDEX 0x182 +#define mmMP_SMUIF2_MP0PUB_IND_INDEX 0x184 +#define mmMP_SMUIF3_MP0PUB_IND_INDEX 0x186 +#define mmMP_SMUIF4_MP0PUB_IND_INDEX 0x188 +#define mmMP_SMUIF5_MP0PUB_IND_INDEX 0x18a +#define mmMP_SMUIF6_MP0PUB_IND_INDEX 0x18c +#define mmMP_SMUIF7_MP0PUB_IND_INDEX 0x18e +#define mmMP_SMUIF8_MP0PUB_IND_INDEX 0x190 +#define mmMP_SMUIF9_MP0PUB_IND_INDEX 0x192 +#define mmMP_SMUIF10_MP0PUB_IND_INDEX 0x194 +#define mmMP_SMUIF11_MP0PUB_IND_INDEX 0x196 +#define mmMP_SMUIF12_MP0PUB_IND_INDEX 0x198 +#define mmMP_SMUIF13_MP0PUB_IND_INDEX 0x19a +#define mmMP_SMUIF14_MP0PUB_IND_INDEX 0x19c +#define mmMP_SMUIF15_MP0PUB_IND_INDEX 0x19e +#define mmMP0PUB_IND_DATA 0x181 +#define mmMP_SMUIF0_MP0PUB_IND_DATA 0x181 +#define mmMP_SMUIF1_MP0PUB_IND_DATA 0x183 +#define mmMP_SMUIF2_MP0PUB_IND_DATA 0x185 +#define mmMP_SMUIF3_MP0PUB_IND_DATA 0x187 +#define mmMP_SMUIF4_MP0PUB_IND_DATA 0x189 +#define mmMP_SMUIF5_MP0PUB_IND_DATA 0x18b +#define mmMP_SMUIF6_MP0PUB_IND_DATA 0x18d +#define mmMP_SMUIF7_MP0PUB_IND_DATA 0x18f +#define mmMP_SMUIF8_MP0PUB_IND_DATA 0x191 +#define mmMP_SMUIF9_MP0PUB_IND_DATA 0x193 +#define mmMP_SMUIF10_MP0PUB_IND_DATA 0x195 +#define mmMP_SMUIF11_MP0PUB_IND_DATA 0x197 +#define mmMP_SMUIF12_MP0PUB_IND_DATA 0x199 +#define mmMP_SMUIF13_MP0PUB_IND_DATA 0x19b +#define mmMP_SMUIF14_MP0PUB_IND_DATA 0x19d +#define mmMP_SMUIF15_MP0PUB_IND_DATA 0x19f +#define mmMP0PUB_IND_INDEX_0 0x180 +#define mmMP0PUB_IND_DATA_0 0x181 +#define mmMP0PUB_IND_INDEX_1 0x182 +#define mmMP0PUB_IND_DATA_1 0x183 +#define mmMP0PUB_IND_INDEX_2 0x184 +#define mmMP0PUB_IND_DATA_2 0x185 +#define mmMP0PUB_IND_INDEX_3 0x186 +#define mmMP0PUB_IND_DATA_3 0x187 +#define mmMP0PUB_IND_INDEX_4 0x188 +#define mmMP0PUB_IND_DATA_4 0x189 +#define mmMP0PUB_IND_INDEX_5 0x18a +#define mmMP0PUB_IND_DATA_5 0x18b +#define mmMP0PUB_IND_INDEX_6 0x18c +#define mmMP0PUB_IND_DATA_6 0x18d +#define mmMP0PUB_IND_INDEX_7 0x18e +#define mmMP0PUB_IND_DATA_7 0x18f +#define mmMP0PUB_IND_INDEX_8 0x190 +#define mmMP0PUB_IND_DATA_8 0x191 +#define mmMP0PUB_IND_INDEX_9 0x192 +#define mmMP0PUB_IND_DATA_9 0x193 +#define mmMP0PUB_IND_INDEX_10 0x194 +#define mmMP0PUB_IND_DATA_10 0x195 +#define mmMP0PUB_IND_INDEX_11 0x196 +#define mmMP0PUB_IND_DATA_11 0x197 +#define mmMP0PUB_IND_INDEX_12 0x198 +#define mmMP0PUB_IND_DATA_12 0x199 +#define mmMP0PUB_IND_INDEX_13 0x19a +#define mmMP0PUB_IND_DATA_13 0x19b +#define mmMP0PUB_IND_INDEX_14 0x19c +#define mmMP0PUB_IND_DATA_14 0x19d +#define mmMP0PUB_IND_INDEX_15 0x19e +#define mmMP0PUB_IND_DATA_15 0x19f +#define mmMP0_IND_ACCESS_CNTL 0x1a0 +#define mmMP0_MSP_MESSAGE_0 0x1a1 +#define mmMP0_MSP_MESSAGE_1 0x1a2 +#define mmMP0_MSP_MESSAGE_2 0x1a3 +#define mmMP0_MSP_MESSAGE_3 0x1a4 +#define mmMP0_MSP_MESSAGE_4 0x1a5 +#define mmMP0_MSP_MESSAGE_5 0x1a6 +#define mmMP0_MSP_MESSAGE_6 0x1a7 +#define mmMP0_MSP_MESSAGE_7 0x1a8 +#define mmSAM_IH_EXT_ERR_INTR 0x1a9 +#define mmSAM_IH_EXT_ERR_INTR_STATUS 0x1aa +#define mmMP0_DISP_TIMER0_CTRL0 0x1ab +#define mmMP0_DISP_TIMER0_CTRL1 0x1ac +#define mmMP0_DISP_TIMER0_CMP_AUTOINC 0x1ad +#define mmMP0_DISP_TIMER0_INTEN 0x1ae +#define mmMP0_DISP_TIMER0_OCMP_0_0 0x1af +#define mmMP0_DISP_TIMER0_OCMP_0_1 0x1b0 +#define mmMP0_DISP_TIMER0_CNT 0x1b1 +#define mmMP0_DISP_TIMER1_CTRL0 0x1b2 +#define mmMP0_DISP_TIMER1_CTRL1 0x1b3 +#define mmMP0_DISP_TIMER1_CMP_AUTOINC 0x1b4 +#define mmMP0_DISP_TIMER1_INTEN 0x1b5 +#define mmMP0_DISP_TIMER1_OCMP_0_0 0x1b6 +#define mmMP0_DISP_TIMER1_OCMP_0_1 0x1b7 +#define mmMP0_DISP_TIMER1_CNT 0x1b8 +#define mmSMU_MP1_SRBM2P_MSG_0 0x1c0 +#define mmSMU_MP1_SRBM2P_MSG_1 0x1c1 +#define mmSMU_MP1_SRBM2P_MSG_2 0x1c2 +#define mmSMU_MP1_SRBM2P_MSG_3 0x1c3 +#define mmSMU_MP1_SRBM2P_MSG_4 0x1c4 +#define mmSMU_MP1_SRBM2P_MSG_5 0x1c5 +#define mmSMU_MP1_SRBM2P_MSG_6 0x1c6 +#define mmSMU_MP1_SRBM2P_MSG_7 0x1c7 +#define mmSMU_MP1_SRBM2P_MSG_8 0x1c8 +#define mmSMU_MP1_SRBM2P_MSG_9 0x1c9 +#define mmSMU_MP1_SRBM2P_MSG_10 0x1ca +#define mmSMU_MP1_SRBM2P_MSG_11 0x1cb +#define mmSMU_MP1_SRBM2P_MSG_12 0x1cc +#define mmSMU_MP1_SRBM2P_MSG_13 0x1cd +#define mmSMU_MP1_SRBM2P_MSG_14 0x1ce +#define mmSMU_MP1_SRBM2P_MSG_15 0x1cf +#define mmSMU_MP1_SRBM2P_RESP_0 0x1d0 +#define mmSMU_MP1_SRBM2P_RESP_1 0x1d1 +#define mmSMU_MP1_SRBM2P_RESP_2 0x1d2 +#define mmSMU_MP1_SRBM2P_RESP_3 0x1d3 +#define mmSMU_MP1_SRBM2P_RESP_4 0x1d4 +#define mmSMU_MP1_SRBM2P_RESP_5 0x1d5 +#define mmSMU_MP1_SRBM2P_RESP_6 0x1d6 +#define mmSMU_MP1_SRBM2P_RESP_7 0x1d7 +#define mmSMU_MP1_SRBM2P_RESP_8 0x1d8 +#define mmSMU_MP1_SRBM2P_RESP_9 0x1d9 +#define mmSMU_MP1_SRBM2P_RESP_10 0x1da +#define mmSMU_MP1_SRBM2P_RESP_11 0x1db +#define mmSMU_MP1_SRBM2P_RESP_12 0x1dc +#define mmSMU_MP1_SRBM2P_RESP_13 0x1dd +#define mmSMU_MP1_SRBM2P_RESP_14 0x1de +#define mmSMU_MP1_SRBM2P_RESP_15 0x1df +#define mmSMU_MP1_SRBM2P_ARG_0 0x1e0 +#define mmSMU_MP1_SRBM2P_ARG_1 0x1e1 +#define mmSMU_MP1_SRBM2P_ARG_2 0x1e2 +#define mmSMU_MP1_SRBM2P_ARG_3 0x1e3 +#define mmSMU_MP1_SRBM2P_ARG_4 0x1e4 +#define mmSMU_MP1_SRBM2P_ARG_5 0x1e5 +#define mmSMU_MP1_SRBM2P_ARG_6 0x1e6 +#define mmSMU_MP1_SRBM2P_ARG_7 0x1e7 +#define mmSMU_MP1_SRBM2P_ARG_8 0x1e8 +#define mmSMU_MP1_SRBM2P_ARG_9 0x1e9 +#define mmSMU_MP1_SRBM2P_ARG_10 0x1ea +#define mmSMU_MP1_SRBM2P_ARG_11 0x1eb +#define mmSMU_MP1_SRBM2P_ARG_12 0x1ec +#define mmSMU_MP1_SRBM2P_ARG_13 0x1ed +#define mmSMU_MP1_SRBM2P_ARG_14 0x1ee +#define mmSMU_MP1_SRBM2P_ARG_15 0x1ef +#define mmSMU_MP1_ACP2MP_RESP 0x1f0 +#define mmSMU_MP1_DC2MP_RESP 0x1f1 +#define mmSMU_MP1_UVD2MP_RESP 0x1f2 +#define mmSMU_MP1_VCE2MP_RESP 0x1f3 +#define mmSMU_MP1_RLC2MP_RESP 0x1f4 +#define mmMP_FPS_CNT 0x1f5 +#define mmSMU_DISP0_TIMER_INT_CONTROL 0x1f6 +#define mmSMU_DISP1_TIMER_INT_CONTROL 0x1f7 +#define mmSMU_SRBM_CONFIG 0x1f8 +#define ixMP_FPS_CNT_XBAR 0xcf200800 +#define ixMP_SRBM_CONFIG_XBAR 0xcf200804 +#define ixMP_SRBM_CONTROL 0xcf200c00 +#define ixMP_SRBM_ACCVIO_LOG 0xcf200c04 +#define ixMP_SRBM_ACCVIO_ADDR 0xcf200c08 +#define ixMP_CRBBM_CONTROL 0xcf200c0c +#define ixMP_CRBBM_ACCVIO_LOG 0xcf200c10 +#define ixMP_CRBBM_ACCVIO_ADDR 0xcf200c14 +#define ixMP_DRAM_CNTL_WRREQ_CNTL 0xcf200000 +#define ixMP_DRAM_CNTL_WRREQ_CNTL_1 0xcf200004 +#define ixMP_DRAM_CNTL_WRREQ_LOW_ADDR 0xcf200008 +#define ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR 0xcf20000c +#define ixMP_DRAM_CNTL_WRREQ_MASK 0xcf200010 +#define ixMP_DRAM_CNTL_WRREQ_DATA_0 0xcf200014 +#define ixMP_DRAM_CNTL_WRREQ_DATA_1 0xcf200018 +#define ixMP_DRAM_CNTL_WRREQ_DATA_2 0xcf20001c +#define ixMP_DRAM_CNTL_WRREQ_DATA_3 0xcf200020 +#define ixMP_DRAM_CNTL_WRREQ_DATA_4 0xcf200024 +#define ixMP_DRAM_CNTL_WRREQ_DATA_5 0xcf200028 +#define ixMP_DRAM_CNTL_WRREQ_DATA_6 0xcf20002c +#define ixMP_DRAM_CNTL_WRREQ_DATA_7 0xcf200030 +#define ixMP_DRAM_CNTL_WRREQ_STATUS 0xcf200038 +#define ixMP_DRAM_CNTL_WRRET_STATUS_0 0xcf20003c +#define ixMP_DRAM_CNTL_RDREQ_ADDR 0xcf200040 +#define ixMP_DRAM_CNTL_RDREQ_CNTL 0xcf200044 +#define ixMP_DRAM_CNTL_RDREQ_CNTL_1 0xcf200048 +#define ixMP_DRAM_CNTL_RDRET_VALID 0xcf20004c +#define ixMP_DRAM_CNTL_RDRET_NACK 0xcf200050 +#define ixMP_DRAM_CNTL_RDRET_DATA_0 0xcf200054 +#define ixMP_DRAM_CNTL_RDRET_DATA_1 0xcf200058 +#define ixMP_DRAM_CNTL_RDRET_DATA_2 0xcf20005c +#define ixMP_DRAM_CNTL_RDRET_DATA_3 0xcf200060 +#define ixMP_DRAM_CNTL_RDRET_DATA_4 0xcf200064 +#define ixMP_DRAM_CNTL_RDRET_DATA_5 0xcf200068 +#define ixMP_DRAM_CNTL_RDRET_DATA_6 0xcf20006c +#define ixMP_DRAM_CNTL_RDRET_DATA_7 0xcf200070 +#define ixMP_DRAM_CNTL_RDRET_DATA_8 0xcf200074 +#define ixMP_DRAM_CNTL_RDRET_DATA_9 0xcf200078 +#define ixMP_DRAM_CNTL_RDRET_DATA_10 0xcf20007c +#define ixMP_DRAM_CNTL_RDRET_DATA_11 0xcf200080 +#define ixMP_DRAM_CNTL_RDRET_DATA_12 0xcf200084 +#define ixMP_DRAM_CNTL_RDRET_DATA_13 0xcf200088 +#define ixMP_DRAM_CNTL_RDRET_DATA_14 0xcf20008c +#define ixMP_DRAM_CNTL_RDRET_DATA_15 0xcf200090 +#define ixMP_DRAM_CNTL_RDRET_DATA_16 0xcf200094 +#define ixMP_DRAM_CNTL_RDRET_DATA_17 0xcf200098 +#define ixMP_DRAM_CNTL_RDRET_DATA_18 0xcf20009c +#define ixMP_DRAM_CNTL_RDRET_DATA_19 0xcf2000a0 +#define ixMP_DRAM_CNTL_RDRET_DATA_20 0xcf2000a4 +#define ixMP_DRAM_CNTL_RDRET_DATA_21 0xcf2000a8 +#define ixMP_DRAM_CNTL_RDRET_DATA_22 0xcf2000ac +#define ixMP_DRAM_CNTL_RDRET_DATA_23 0xcf2000b0 +#define ixMP_DRAM_CNTL_RDRET_DATA_24 0xcf2000b4 +#define ixMP_DRAM_CNTL_RDRET_DATA_25 0xcf2000b8 +#define ixMP_DRAM_CNTL_RDRET_DATA_26 0xcf2000bc +#define ixMP_DRAM_CNTL_RDRET_DATA_27 0xcf2000c0 +#define ixMP_DRAM_CNTL_RDRET_DATA_28 0xcf2000c4 +#define ixMP_DRAM_CNTL_RDRET_DATA_29 0xcf2000c8 +#define ixMP_DRAM_CNTL_RDRET_DATA_30 0xcf2000cc +#define ixMP_DRAM_CNTL_RDRET_DATA_31 0xcf2000d0 +#define ixMP_DRAM_CNTL_RDRET_DATA_32 0xcf2000d4 +#define ixMP_DRAM_CNTL_RDRET_DATA_33 0xcf2000d8 +#define ixMP_DRAM_CNTL_RDRET_DATA_34 0xcf2000dc +#define ixMP_DRAM_CNTL_RDRET_DATA_35 0xcf2000e0 +#define ixMP_DRAM_CNTL_RDRET_DATA_36 0xcf2000e4 +#define ixMP_DRAM_CNTL_RDRET_DATA_37 0xcf2000e8 +#define ixMP_DRAM_CNTL_RDRET_DATA_38 0xcf2000ec +#define ixMP_DRAM_CNTL_RDRET_DATA_39 0xcf2000f0 +#define ixMP_DRAM_CNTL_RDRET_DATA_40 0xcf2000f4 +#define ixMP_DRAM_CNTL_RDRET_DATA_41 0xcf2000f8 +#define ixMP_DRAM_CNTL_RDRET_DATA_42 0xcf2000fc +#define ixMP_DRAM_CNTL_RDRET_DATA_43 0xcf200100 +#define ixMP_DRAM_CNTL_RDRET_DATA_44 0xcf200104 +#define ixMP_DRAM_CNTL_RDRET_DATA_45 0xcf200108 +#define ixMP_DRAM_CNTL_RDRET_DATA_46 0xcf20010c +#define ixMP_DRAM_CNTL_RDRET_DATA_47 0xcf200110 +#define ixMP_DRAM_CNTL_RDRET_DATA_48 0xcf200114 +#define ixMP_DRAM_CNTL_RDRET_DATA_49 0xcf200118 +#define ixMP_DRAM_CNTL_RDRET_DATA_50 0xcf20011c +#define ixMP_DRAM_CNTL_RDRET_DATA_51 0xcf200120 +#define ixMP_DRAM_CNTL_RDRET_DATA_52 0xcf200124 +#define ixMP_DRAM_CNTL_RDRET_DATA_53 0xcf200128 +#define ixMP_DRAM_CNTL_RDRET_DATA_54 0xcf20012c +#define ixMP_DRAM_CNTL_RDRET_DATA_55 0xcf200130 +#define ixMP_DRAM_CNTL_RDRET_DATA_56 0xcf200134 +#define ixMP_DRAM_CNTL_RDRET_DATA_57 0xcf200138 +#define ixMP_DRAM_CNTL_RDRET_DATA_58 0xcf20013c +#define ixMP_DRAM_CNTL_RDRET_DATA_59 0xcf200140 +#define ixMP_DRAM_CNTL_RDRET_DATA_60 0xcf200144 +#define ixMP_DRAM_CNTL_RDRET_DATA_61 0xcf200148 +#define ixMP_DRAM_CNTL_RDRET_DATA_62 0xcf20014c +#define ixMP_DRAM_CNTL_RDRET_DATA_63 0xcf200150 +#define ixMP_IOC_CTRL 0xcf100000 +#define ixMP_IOC_RDDATA 0xcf100004 +#define ixMP_IOC_PHASE1 0xcf100008 +#define ixMP_IOC_PHASE2 0xcf10000c +#define ixMP_IOC_PHASE3 0xcf100010 +#define ixMP_IOC_READ_0 0xcf100024 +#define ixMP_IOC_READ_1 0xcf100028 +#define ixMP_IOC_READ_2 0xcf10002c +#define ixMP_IOC_READ_3 0xcf100030 +#define ixMP_IOC_READ_4 0xcf100034 +#define ixMP_IOC_READ_5 0xcf100038 +#define ixMP_IOC_READ_6 0xcf10003c +#define ixMP_IOC_READ_7 0xcf100040 +#define ixMP_IOC_READ_8 0xcf100044 +#define ixMP_IOC_READ_9 0xcf100048 +#define ixMP_IOC_READ_10 0xcf10004c +#define ixMP_IOC_READ_11 0xcf100050 +#define ixMP_IOC_READ_12 0xcf100054 +#define ixMP_IOC_READ_13 0xcf100058 +#define ixMP_IOC_READ_14 0xcf10005c +#define ixMP_IOC_READ_15 0xcf100060 +#define ixMP_IOC_WRITE_0 0xcf100064 +#define ixMP_IOC_WRITE_1 0xcf100068 +#define ixMP_IOC_WRITE_2 0xcf10006c +#define ixMP_IOC_WRITE_3 0xcf100070 +#define ixMP_IOC_WRITE_4 0xcf100074 +#define ixMP_IOC_WRITE_5 0xcf100078 +#define ixMP_IOC_WRITE_6 0xcf10007c +#define ixMP_IOC_WRITE_7 0xcf100080 +#define ixMP_IOC_WRITE_8 0xcf100084 +#define ixMP_IOC_WRITE_9 0xcf100088 +#define ixMP_IOC_WRITE_10 0xcf10008c +#define ixMP_IOC_WRITE_11 0xcf100090 +#define ixMP_IOC_WRITE_12 0xcf100094 +#define ixMP_IOC_WRITE_13 0xcf100098 +#define ixMP_IOC_WRITE_14 0xcf10009c +#define ixMP_IOC_WRITE_15 0xcf1000a0 +#define ixMP_INTERRUPT_CONTROL 0xcf200400 +#define ixMP0_SW_INT 0xcf200404 +#define ixMP0_SW_INT_CTXID 0xcf200408 +#define ixMP1_SW_INT 0xcf20040c +#define ixMP1_SW_INT_CTXID 0xcf200410 +#define ixDISP_TIMER_ID 0xcf200414 +#define mmPWRHW_SMC_IND_INDEX 0x180 +#define mmPWRHW0_PWRHW_SMC_IND_INDEX 0x180 +#define mmPWRHW1_PWRHW_SMC_IND_INDEX 0x182 +#define mmPWRHW2_PWRHW_SMC_IND_INDEX 0x184 +#define mmPWRHW3_PWRHW_SMC_IND_INDEX 0x186 +#define mmPWRHW_SMC_IND_DATA 0x181 +#define mmPWRHW0_PWRHW_SMC_IND_DATA 0x181 +#define mmPWRHW1_PWRHW_SMC_IND_DATA 0x183 +#define mmPWRHW2_PWRHW_SMC_IND_DATA 0x185 +#define mmPWRHW3_PWRHW_SMC_IND_DATA 0x187 +#define ixCURRENT_STATE_CPU0 0xd0210000 +#define ixCURRENT_STATE_CPU1 0xd0210010 +#define ixCPU_REDUN_DONE0 0xd0210004 +#define ixCPU_REDUN_DONE1 0xd0210014 +#define ixCURRENT_VID_CPU0 0xd0210008 +#define ixCURRENT_VID_CPU1 0xd0210018 +#define ixUNBPM_PWRMGT_ACK 0xd0211000 +#define ixCURRENT_FREQ_STATE_NB 0xd0211004 +#define ixCURRENT_PSTATE_NB 0xd0211008 +#define ixUNBPM_MSG_INT_CONFIG 0xd021100c +#define ixUNBPM_NBPWRMGT_CMD 0xd0211010 +#define ixUNBPM_NBPWRMGT_FSM_CFG 0xd0211014 +#define ixDDR0_FUSE_SSB_XFER 0xd0211018 +#define ixDDR0_FUSE_SSB_XFER_CFG 0xd021101c +#define ixDDR1_FUSE_SSB_XFER 0xd0211020 +#define ixDDR1_FUSE_SSB_XFER_CFG 0xd0211024 +#define ixUNBPM_FUSES_VAL_PWROK 0xd0211028 +#define ixSYNFIFO_CLK_RATIO 0xd021102c +#define ixMISC_SMU_PWRMGT_CFG0 0xd0211030 +#define ixMISC_GNB_PWRMGT_CFG1 0xd0211034 +#define ixMISC_SMU_PWRMGT_CFG1 0xd0211038 +#define ixMISC_GNB_PWRMGT_DATA 0xd021103c +#define ixGN_GNB_SLOW 0xd0211040 +#define ixGN_FORCE_NBPS1 0xd0211044 +#define ixMISC_SMU_PWRMGT_DATA 0xd0211048 +#define ixNB_COF 0xd021104c +#define ixUNBPM_CK_IRESET 0xd0211050 +#define ixCURRENT_VID_NB 0xd0211054 +#define ixSPR_FUSE_PSTATEPWR1 0xd0211058 +#define ixSPR_FUSE_PSTATEPWR2 0xd021105c +#define ixSPR_FUSE_PSTATEPWR3 0xd0211060 +#define ixSPR_FUSE_THERMAL_SCRATCH 0xd0211064 +#define ixSPR_PRODUCT_INFO0 0xd0211068 +#define ixSPR_SERIALNUM_REG1 0xd021106c +#define ixSPR_SERIALNUM_REG2 0xd0211070 +#define ixSPR_PRODUCT_INFO1 0xd0211074 +#define ixSPR_EXT_PRODUCT_INFO 0xd021107c +#define ixSPR_MSIDFUSE 0xd0211080 +#define ixSPR_LINK_PRODUCT_INFO 0xd0211084 +#define ixSPR_BRAND_NAME_ADDR 0xd0211088 +#define ixSPR_BRAND_NAME_DATA 0xd021108c +#define ixSPR_COMBO_PHY_PRODUCT_INFO 0xd0211090 +#define ixMISC_GNB_PWRMGT_CFG0 0xd0211094 +#define ixUNBPM_EXIT_TO_PSTATE 0xd0211098 +#define ixUNBPM_WARM_RESET_HS_STATUS 0xd021109c +#define ixUNBPM_VOLTAGE_CNTL 0xd02110a0 +#define ixUNBPM_VOLTAGE_STATUS 0xd02110a4 +#define ixNUM_BOOST_STATES 0xd02110a8 +#define ixWARM_RESET_NB_CONTROL 0xd02110ac +#define ixONION_NO_STREAMS_PEND 0xd02110b0 +#define ixSPR_PROGRAMMABLE_CTRL 0xd02110b4 +#define ixPHN_FUSERX_MISC_FUSES 0xd02110b8 +#define ixUNBPM_PWRCTRL_MISC 0xd02110bc +#define ixCSTATE_ACTIVE_SAMPLER 0xd02110c0 +#define ixUNBPM_DEBUG_CONFIG_STATUS 0xd02110c4 +#define ixUNBPM_AXIMST_LAST_CMD 0xd02110c8 +#define ixUNB_IF_INTRGEN_LAST_SENT 0xd02110cc +#define ixUNBPM_DEBUG_BUS_CNTL 0xd02110d0 +#define ixUNBPM_PWRMGT_REQ_DBG_STATUS 0xd02110d4 +#define ixUNBPM_VIDCHG_REQ_DBG_STATUS 0xd02110d8 +#define ixUNBPM_SCRATCH_0 0xd021e000 +#define ixUNBPM_SCRATCH_1 0xd021e004 +#define ixPOWERON_CPU_0 0xd0220000 +#define ixPOWERREADY_CPU_0 0xd0220004 +#define ixPGRUNFEEDBACK_CPU_0 0xd0220008 +#define ixRCC3ON_CPU_0 0xd022000c +#define ixRCC3EXITDONE_CPU_0 0xd0220010 +#define ixCORE_FUNC_LATE_SSB_XFER_0 0xd0220014 +#define ixCORE_FUNC_LATE_SSB_XFER_CFG_0 0xd0220018 +#define ixCORE_REDUN_SSB_XFER_0 0xd022001c +#define ixCORE_REDUN_SSB_XFER_CFG_0 0xd0220020 +#define ixCORE_APM_SSB_XFER_0 0xd0220024 +#define ixCORE_APM_SSB_XFER_CFG_0 0xd0220028 +#define ixCOREPM_PWRCTRL_MISC_0 0xd022002c +#define ixLDOIVRON_CPU_0 0xd0220030 +#define ixLDOIVREXITDONE_CPU_0 0xd0220034 +#define ixRCC3_TARGETPSMREF_CPU_0 0xd0220038 +#define ixIVR_TARGETPSMREF_CPU_0 0xd022003c +#define ixCK_JTCOOLRESET_LATCHED_CPU_0 0xd0220044 +#define ixCK_DISABLECORE_CPU_0 0xd0220048 +#define ixCOREPM_ID_0 0xd022004c +#define ixCOREPM_SCRATCH_0 0xd0220050 +#define ixRCC3_WAKEMIN_CPU_0 0xd0220054 +#define ixSPMI_CONFIG0_0 0xd0221000 +#define ixSPMI_CONFIG1_0 0xd0221004 +#define ixSPMI_FSM_READ_TRIGGER_0 0xd0221008 +#define ixSPMI_FSM_WRITE_TRIGGER_0 0xd022100c +#define ixSPMI_FSM_RESET_TRIGGER_0 0xd0221010 +#define ixSPMI_FSM_BUSY_0 0xd0221014 +#define ixSPMI_PATH_0 0xd0221018 +#define ixSPMI_C6_STATE_0 0xd022101c +#define ixSPMI_JTAG_OVER_0 0xd0221020 +#define ixSPMI_SRAM_ADDRESS_0 0xd0221024 +#define ixSPMI_SRAM_DATA_0 0xd0221028 +#define ixSPMI_RESET_0 0xd022102c +#define ixSPMI_FORCE_CLOCK_GATERS_0 0xd0221030 +#define ixSPMI_SPARE_0 0xd0221034 +#define ixSPMI_SPARE_EX_0 0xd0221038 +#define ixSPMI_SRAM_CLK_GATER_0 0xd022103c +#define ixPOWERON_CPU_1 0xd0230000 +#define ixPOWERREADY_CPU_1 0xd0230004 +#define ixPGRUNFEEDBACK_CPU_1 0xd0230008 +#define ixRCC3ON_CPU_1 0xd023000c +#define ixRCC3EXITDONE_CPU_1 0xd0230010 +#define ixCORE_FUNC_LATE_SSB_XFER_1 0xd0230014 +#define ixCORE_FUNC_LATE_SSB_XFER_CFG_1 0xd0230018 +#define ixCORE_REDUN_SSB_XFER_1 0xd023001c +#define ixCORE_REDUN_SSB_XFER_CFG_1 0xd0230020 +#define ixCORE_APM_SSB_XFER_1 0xd0230024 +#define ixCORE_APM_SSB_XFER_CFG_1 0xd0230028 +#define ixCOREPM_PWRCTRL_MISC_1 0xd023002c +#define ixLDOIVRON_CPU_1 0xd0230030 +#define ixLDOIVREXITDONE_CPU_1 0xd0230034 +#define ixRCC3_TARGETPSMREF_CPU_1 0xd0230038 +#define ixIVR_TARGETPSMREF_CPU_1 0xd023003c +#define ixCK_JTCOOLRESET_LATCHED_CPU_1 0xd0230044 +#define ixCK_DISABLECORE_CPU_1 0xd0230048 +#define ixCOREPM_ID_1 0xd023004c +#define ixCOREPM_SCRATCH_1 0xd0230050 +#define ixRCC3_WAKEMIN_CPU_1 0xd0230054 +#define ixSPMI_CONFIG0_1 0xd0231000 +#define ixSPMI_CONFIG1_1 0xd0231004 +#define ixSPMI_FSM_READ_TRIGGER_1 0xd0231008 +#define ixSPMI_FSM_WRITE_TRIGGER_1 0xd023100c +#define ixSPMI_FSM_RESET_TRIGGER_1 0xd0231010 +#define ixSPMI_FSM_BUSY_1 0xd0231014 +#define ixSPMI_PATH_1 0xd0231018 +#define ixSPMI_C6_STATE_1 0xd023101c +#define ixSPMI_JTAG_OVER_1 0xd0231020 +#define ixSPMI_SRAM_ADDRESS_1 0xd0231024 +#define ixSPMI_SRAM_DATA_1 0xd0231028 +#define ixSPMI_RESET_1 0xd023102c +#define ixSPMI_FORCE_CLOCK_GATERS_1 0xd0231030 +#define ixSPMI_SPARE_1 0xd0231034 +#define ixSPMI_SPARE_EX_1 0xd0231038 +#define ixSPMI_SRAM_CLK_GATER_1 0xd023103c +#define ixGENERAL_PWRMGT 0xd0200000 +#define ixCNB_PWRMGT_CNTL 0xd0200004 +#define ixSCLK_PWRMGT_CNTL 0xd0200008 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xd0200014 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xd02000f0 +#define ixTARGET_AND_CURRENT_PROFILE_INDEX_2 0xd02000f4 +#define ixCG_FREQ_TRAN_VOTING_0 0xd02001a8 +#define ixCG_FREQ_TRAN_VOTING_1 0xd02001ac +#define ixCG_FREQ_TRAN_VOTING_2 0xd02001b0 +#define ixCG_FREQ_TRAN_VOTING_3 0xd02001b4 +#define ixCG_FREQ_TRAN_VOTING_4 0xd02001b8 +#define ixCG_FREQ_TRAN_VOTING_5 0xd02001bc +#define ixCG_FREQ_TRAN_VOTING_6 0xd02001c0 +#define ixCG_FREQ_TRAN_VOTING_7 0xd02001c4 +#define ixCG_STATIC_SCREEN_PARAMETER 0xd0200044 +#define ixCG_ACPI_CNTL 0xd0200064 +#define ixSCLK_DEEP_SLEEP_CNTL 0xd0200080 +#define ixSCLK_DEEP_SLEEP_CNTL2 0xd0200084 +#define ixSCLK_DEEP_SLEEP_CNTL3 0xd020009c +#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xd0200088 +#define ixLCLK_DEEP_SLEEP_CNTL 0xd020008c +#define ixLCLK_DEEP_SLEEP_CNTL2 0xd0200310 +#define ixSMU_VOLTAGE_STATUS 0xd0200094 +#define ixCG_ULV_PARAMETER 0xd020015c +#define ixPWR_DC_RESP 0xd0200300 +#define ixPWR_VCE_RESP 0xd0200304 +#define ixPWR_UVD_RESP 0xd0200308 +#define ixPWR_ACP_RESP 0xd020030c +#define ixPWR_DC_REQ 0xd020031c +#define ixSCLK_MIN_DIV 0xd02003ac +#define ixPCIE_PGFSM_CONFIG 0xd02002d0 +#define ixPCIE_PGFSM_WRITE 0xd02002d4 +#define ixSERDES_BUSY 0xd02002d8 +#define ixPCIE_PGFSM2_CONFIG 0xd02002dc +#define ixPCIE_PGFSM2_WRITE 0xd02002e0 +#define ixSERDES2_BUSY 0xd02002e4 +#define ixPCIE_PGFSM_0_READ 0xd02002e8 +#define ixPCIE_PGFSM_1_READ 0xd02002ec +#define ixPWR_ACPI_INTERRUPT 0xd0200318 +#define ixVDDGFX_IDLE_PARAMETER 0xd020036c +#define ixVDDGFX_IDLE_CONTROL 0xd0200370 +#define ixVDDGFX_IDLE_EXIT 0xd0200374 +#define ixREG_SCLK_DEEP_SLEEP_EXIT 0xd0200378 +#define ixCAC_WEIGHT_LKG_DC_3 0xd020803c +#define ixLCAC_MC0_CNTL 0xd0208130 +#define ixLCAC_MC0_OVR_SEL 0xd0208134 +#define ixLCAC_MC0_OVR_VAL 0xd0208138 +#define ixLCAC_MC1_CNTL 0xd020813c +#define ixLCAC_MC1_OVR_SEL 0xd0208140 +#define ixLCAC_MC1_OVR_VAL 0xd0208144 +#define ixLCAC_MC2_CNTL 0xd0208148 +#define ixLCAC_MC2_OVR_SEL 0xd020814c +#define ixLCAC_MC2_OVR_VAL 0xd0208150 +#define ixLCAC_MC3_CNTL 0xd0208154 +#define ixLCAC_MC3_OVR_SEL 0xd0208158 +#define ixLCAC_MC3_OVR_VAL 0xd020815c +#define ixLCAC_CPL_CNTL 0xd0208160 +#define ixLCAC_CPL_OVR_SEL 0xd0208164 +#define ixLCAC_CPL_OVR_VAL 0xd0208168 +#define ixMISC_UNB_PWRMGT_CFG0 0xd020c000 +#define ixMISC_UNB_PWRMGT_CFG1 0xd020c004 +#define ixMISC_UNB_PWRMGT_DATA 0xd020c00c +#define ixGNBPM_SMU_PWRMGT_DATA 0xd020c010 +#define ixDMA_ACTIVE_SAMPLER_CFG 0xd020c014 +#define ixSOUTHBRIDGE_TYPE 0xd020c01c +#define ixGNBPM_SMU_PWRMGT_STATUS 0xd020c020 +#define ixALLOW_SR_INTR_CTRL 0xd020c024 +#define mmGC_CAC_LKG_AGGR_LOWER 0x3294 +#define mmGC_CAC_LKG_AGGR_UPPER 0x3295 +#define ixGC_CAC_WEIGHT_CU_0 0x32 +#define ixGC_CAC_WEIGHT_CU_1 0x33 +#define ixGC_CAC_WEIGHT_CU_2 0x34 +#define ixGC_CAC_WEIGHT_CU_3 0x35 +#define ixGC_CAC_ACC_CU0 0xba +#define ixGC_CAC_ACC_CU1 0xbb +#define ixGC_CAC_ACC_CU2 0xbc +#define ixGC_CAC_ACC_CU3 0xbd +#define ixGC_CAC_ACC_CU4 0xbe +#define ixGC_CAC_ACC_CU5 0xbf +#define ixGC_CAC_ACC_CU6 0xc0 +#define ixGC_CAC_ACC_CU7 0xc1 +#define ixGC_CAC_OVRD_CU 0xe7 + +#endif /* SMU_8_0_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h new file mode 100644 index 000000000000..e1540c181bf8 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h @@ -0,0 +1,1072 @@ +/* + * SMU_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_8_0_ENUM_H +#define SMU_8_0_ENUM_H + +typedef enum DebugBlockId { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_UVDU = 0xd, + DBG_BLOCK_ID_SQA = 0xe, + DBG_BLOCK_ID_SDMA0 = 0xf, + DBG_BLOCK_ID_SDMA1 = 0x10, + DBG_BLOCK_ID_SPIM = 0x11, + DBG_BLOCK_ID_GDS = 0x12, + DBG_BLOCK_ID_VC0 = 0x13, + DBG_BLOCK_ID_VC1 = 0x14, + DBG_BLOCK_ID_PA0 = 0x15, + DBG_BLOCK_ID_PA1 = 0x16, + DBG_BLOCK_ID_CP0 = 0x17, + DBG_BLOCK_ID_CP1 = 0x18, + DBG_BLOCK_ID_CP2 = 0x19, + DBG_BLOCK_ID_XBR = 0x1a, + DBG_BLOCK_ID_UVDM = 0x1b, + DBG_BLOCK_ID_VGT0 = 0x1c, + DBG_BLOCK_ID_VGT1 = 0x1d, + DBG_BLOCK_ID_IA = 0x1e, + DBG_BLOCK_ID_SXM0 = 0x1f, + DBG_BLOCK_ID_SXM1 = 0x20, + DBG_BLOCK_ID_SCT0 = 0x21, + DBG_BLOCK_ID_SCT1 = 0x22, + DBG_BLOCK_ID_SPM0 = 0x23, + DBG_BLOCK_ID_SPM1 = 0x24, + DBG_BLOCK_ID_UNUSED0 = 0x25, + DBG_BLOCK_ID_UNUSED1 = 0x26, + DBG_BLOCK_ID_TCAA = 0x27, + DBG_BLOCK_ID_TCAB = 0x28, + DBG_BLOCK_ID_TCCA = 0x29, + DBG_BLOCK_ID_TCCB = 0x2a, + DBG_BLOCK_ID_MCC0 = 0x2b, + DBG_BLOCK_ID_MCC1 = 0x2c, + DBG_BLOCK_ID_MCC2 = 0x2d, + DBG_BLOCK_ID_MCC3 = 0x2e, + DBG_BLOCK_ID_SXS0 = 0x2f, + DBG_BLOCK_ID_SXS1 = 0x30, + DBG_BLOCK_ID_SXS2 = 0x31, + DBG_BLOCK_ID_SXS3 = 0x32, + DBG_BLOCK_ID_SXS4 = 0x33, + DBG_BLOCK_ID_SXS5 = 0x34, + DBG_BLOCK_ID_SXS6 = 0x35, + DBG_BLOCK_ID_SXS7 = 0x36, + DBG_BLOCK_ID_SXS8 = 0x37, + DBG_BLOCK_ID_SXS9 = 0x38, + DBG_BLOCK_ID_BCI0 = 0x39, + DBG_BLOCK_ID_BCI1 = 0x3a, + DBG_BLOCK_ID_BCI2 = 0x3b, + DBG_BLOCK_ID_BCI3 = 0x3c, + DBG_BLOCK_ID_MCB = 0x3d, + DBG_BLOCK_ID_UNUSED6 = 0x3e, + DBG_BLOCK_ID_SQA00 = 0x3f, + DBG_BLOCK_ID_SQA01 = 0x40, + DBG_BLOCK_ID_SQA02 = 0x41, + DBG_BLOCK_ID_SQA10 = 0x42, + DBG_BLOCK_ID_SQA11 = 0x43, + DBG_BLOCK_ID_SQA12 = 0x44, + DBG_BLOCK_ID_UNUSED7 = 0x45, + DBG_BLOCK_ID_UNUSED8 = 0x46, + DBG_BLOCK_ID_SQB00 = 0x47, + DBG_BLOCK_ID_SQB01 = 0x48, + DBG_BLOCK_ID_SQB10 = 0x49, + DBG_BLOCK_ID_SQB11 = 0x4a, + DBG_BLOCK_ID_SQ00 = 0x4b, + DBG_BLOCK_ID_SQ01 = 0x4c, + DBG_BLOCK_ID_SQ10 = 0x4d, + DBG_BLOCK_ID_SQ11 = 0x4e, + DBG_BLOCK_ID_CB00 = 0x4f, + DBG_BLOCK_ID_CB01 = 0x50, + DBG_BLOCK_ID_CB02 = 0x51, + DBG_BLOCK_ID_CB03 = 0x52, + DBG_BLOCK_ID_CB04 = 0x53, + DBG_BLOCK_ID_UNUSED9 = 0x54, + DBG_BLOCK_ID_UNUSED10 = 0x55, + DBG_BLOCK_ID_UNUSED11 = 0x56, + DBG_BLOCK_ID_CB10 = 0x57, + DBG_BLOCK_ID_CB11 = 0x58, + DBG_BLOCK_ID_CB12 = 0x59, + DBG_BLOCK_ID_CB13 = 0x5a, + DBG_BLOCK_ID_CB14 = 0x5b, + DBG_BLOCK_ID_UNUSED12 = 0x5c, + DBG_BLOCK_ID_UNUSED13 = 0x5d, + DBG_BLOCK_ID_UNUSED14 = 0x5e, + DBG_BLOCK_ID_TCP0 = 0x5f, + DBG_BLOCK_ID_TCP1 = 0x60, + DBG_BLOCK_ID_TCP2 = 0x61, + DBG_BLOCK_ID_TCP3 = 0x62, + DBG_BLOCK_ID_TCP4 = 0x63, + DBG_BLOCK_ID_TCP5 = 0x64, + DBG_BLOCK_ID_TCP6 = 0x65, + DBG_BLOCK_ID_TCP7 = 0x66, + DBG_BLOCK_ID_TCP8 = 0x67, + DBG_BLOCK_ID_TCP9 = 0x68, + DBG_BLOCK_ID_TCP10 = 0x69, + DBG_BLOCK_ID_TCP11 = 0x6a, + DBG_BLOCK_ID_TCP12 = 0x6b, + DBG_BLOCK_ID_TCP13 = 0x6c, + DBG_BLOCK_ID_TCP14 = 0x6d, + DBG_BLOCK_ID_TCP15 = 0x6e, + DBG_BLOCK_ID_TCP16 = 0x6f, + DBG_BLOCK_ID_TCP17 = 0x70, + DBG_BLOCK_ID_TCP18 = 0x71, + DBG_BLOCK_ID_TCP19 = 0x72, + DBG_BLOCK_ID_TCP20 = 0x73, + DBG_BLOCK_ID_TCP21 = 0x74, + DBG_BLOCK_ID_TCP22 = 0x75, + DBG_BLOCK_ID_TCP23 = 0x76, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, + DBG_BLOCK_ID_DB00 = 0x7f, + DBG_BLOCK_ID_DB01 = 0x80, + DBG_BLOCK_ID_DB02 = 0x81, + DBG_BLOCK_ID_DB03 = 0x82, + DBG_BLOCK_ID_DB04 = 0x83, + DBG_BLOCK_ID_UNUSED15 = 0x84, + DBG_BLOCK_ID_UNUSED16 = 0x85, + DBG_BLOCK_ID_UNUSED17 = 0x86, + DBG_BLOCK_ID_DB10 = 0x87, + DBG_BLOCK_ID_DB11 = 0x88, + DBG_BLOCK_ID_DB12 = 0x89, + DBG_BLOCK_ID_DB13 = 0x8a, + DBG_BLOCK_ID_DB14 = 0x8b, + DBG_BLOCK_ID_UNUSED18 = 0x8c, + DBG_BLOCK_ID_UNUSED19 = 0x8d, + DBG_BLOCK_ID_UNUSED20 = 0x8e, + DBG_BLOCK_ID_TCC0 = 0x8f, + DBG_BLOCK_ID_TCC1 = 0x90, + DBG_BLOCK_ID_TCC2 = 0x91, + DBG_BLOCK_ID_TCC3 = 0x92, + DBG_BLOCK_ID_TCC4 = 0x93, + DBG_BLOCK_ID_TCC5 = 0x94, + DBG_BLOCK_ID_TCC6 = 0x95, + DBG_BLOCK_ID_TCC7 = 0x96, + DBG_BLOCK_ID_SPS00 = 0x97, + DBG_BLOCK_ID_SPS01 = 0x98, + DBG_BLOCK_ID_SPS02 = 0x99, + DBG_BLOCK_ID_SPS10 = 0x9a, + DBG_BLOCK_ID_SPS11 = 0x9b, + DBG_BLOCK_ID_SPS12 = 0x9c, + DBG_BLOCK_ID_UNUSED21 = 0x9d, + DBG_BLOCK_ID_UNUSED22 = 0x9e, + DBG_BLOCK_ID_TA00 = 0x9f, + DBG_BLOCK_ID_TA01 = 0xa0, + DBG_BLOCK_ID_TA02 = 0xa1, + DBG_BLOCK_ID_TA03 = 0xa2, + DBG_BLOCK_ID_TA04 = 0xa3, + DBG_BLOCK_ID_TA05 = 0xa4, + DBG_BLOCK_ID_TA06 = 0xa5, + DBG_BLOCK_ID_TA07 = 0xa6, + DBG_BLOCK_ID_TA08 = 0xa7, + DBG_BLOCK_ID_TA09 = 0xa8, + DBG_BLOCK_ID_TA0A = 0xa9, + DBG_BLOCK_ID_TA0B = 0xaa, + DBG_BLOCK_ID_UNUSED23 = 0xab, + DBG_BLOCK_ID_UNUSED24 = 0xac, + DBG_BLOCK_ID_UNUSED25 = 0xad, + DBG_BLOCK_ID_UNUSED26 = 0xae, + DBG_BLOCK_ID_TA10 = 0xaf, + DBG_BLOCK_ID_TA11 = 0xb0, + DBG_BLOCK_ID_TA12 = 0xb1, + DBG_BLOCK_ID_TA13 = 0xb2, + DBG_BLOCK_ID_TA14 = 0xb3, + DBG_BLOCK_ID_TA15 = 0xb4, + DBG_BLOCK_ID_TA16 = 0xb5, + DBG_BLOCK_ID_TA17 = 0xb6, + DBG_BLOCK_ID_TA18 = 0xb7, + DBG_BLOCK_ID_TA19 = 0xb8, + DBG_BLOCK_ID_TA1A = 0xb9, + DBG_BLOCK_ID_TA1B = 0xba, + DBG_BLOCK_ID_UNUSED27 = 0xbb, + DBG_BLOCK_ID_UNUSED28 = 0xbc, + DBG_BLOCK_ID_UNUSED29 = 0xbd, + DBG_BLOCK_ID_UNUSED30 = 0xbe, + DBG_BLOCK_ID_TD00 = 0xbf, + DBG_BLOCK_ID_TD01 = 0xc0, + DBG_BLOCK_ID_TD02 = 0xc1, + DBG_BLOCK_ID_TD03 = 0xc2, + DBG_BLOCK_ID_TD04 = 0xc3, + DBG_BLOCK_ID_TD05 = 0xc4, + DBG_BLOCK_ID_TD06 = 0xc5, + DBG_BLOCK_ID_TD07 = 0xc6, + DBG_BLOCK_ID_TD08 = 0xc7, + DBG_BLOCK_ID_TD09 = 0xc8, + DBG_BLOCK_ID_TD0A = 0xc9, + DBG_BLOCK_ID_TD0B = 0xca, + DBG_BLOCK_ID_UNUSED31 = 0xcb, + DBG_BLOCK_ID_UNUSED32 = 0xcc, + DBG_BLOCK_ID_UNUSED33 = 0xcd, + DBG_BLOCK_ID_UNUSED34 = 0xce, + DBG_BLOCK_ID_TD10 = 0xcf, + DBG_BLOCK_ID_TD11 = 0xd0, + DBG_BLOCK_ID_TD12 = 0xd1, + DBG_BLOCK_ID_TD13 = 0xd2, + DBG_BLOCK_ID_TD14 = 0xd3, + DBG_BLOCK_ID_TD15 = 0xd4, + DBG_BLOCK_ID_TD16 = 0xd5, + DBG_BLOCK_ID_TD17 = 0xd6, + DBG_BLOCK_ID_TD18 = 0xd7, + DBG_BLOCK_ID_TD19 = 0xd8, + DBG_BLOCK_ID_TD1A = 0xd9, + DBG_BLOCK_ID_TD1B = 0xda, + DBG_BLOCK_ID_UNUSED35 = 0xdb, + DBG_BLOCK_ID_UNUSED36 = 0xdc, + DBG_BLOCK_ID_UNUSED37 = 0xdd, + DBG_BLOCK_ID_UNUSED38 = 0xde, + DBG_BLOCK_ID_LDS00 = 0xdf, + DBG_BLOCK_ID_LDS01 = 0xe0, + DBG_BLOCK_ID_LDS02 = 0xe1, + DBG_BLOCK_ID_LDS03 = 0xe2, + DBG_BLOCK_ID_LDS04 = 0xe3, + DBG_BLOCK_ID_LDS05 = 0xe4, + DBG_BLOCK_ID_LDS06 = 0xe5, + DBG_BLOCK_ID_LDS07 = 0xe6, + DBG_BLOCK_ID_LDS08 = 0xe7, + DBG_BLOCK_ID_LDS09 = 0xe8, + DBG_BLOCK_ID_LDS0A = 0xe9, + DBG_BLOCK_ID_LDS0B = 0xea, + DBG_BLOCK_ID_UNUSED39 = 0xeb, + DBG_BLOCK_ID_UNUSED40 = 0xec, + DBG_BLOCK_ID_UNUSED41 = 0xed, + DBG_BLOCK_ID_UNUSED42 = 0xee, + DBG_BLOCK_ID_LDS10 = 0xef, + DBG_BLOCK_ID_LDS11 = 0xf0, + DBG_BLOCK_ID_LDS12 = 0xf1, + DBG_BLOCK_ID_LDS13 = 0xf2, + DBG_BLOCK_ID_LDS14 = 0xf3, + DBG_BLOCK_ID_LDS15 = 0xf4, + DBG_BLOCK_ID_LDS16 = 0xf5, + DBG_BLOCK_ID_LDS17 = 0xf6, + DBG_BLOCK_ID_LDS18 = 0xf7, + DBG_BLOCK_ID_LDS19 = 0xf8, + DBG_BLOCK_ID_LDS1A = 0xf9, + DBG_BLOCK_ID_LDS1B = 0xfa, + DBG_BLOCK_ID_UNUSED43 = 0xfb, + DBG_BLOCK_ID_UNUSED44 = 0xfc, + DBG_BLOCK_ID_UNUSED45 = 0xfd, + DBG_BLOCK_ID_UNUSED46 = 0xfe, +} DebugBlockId; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_UVD_BY2 = 0x7, + DBG_BLOCK_ID_SDMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_VC0_BY2 = 0xa, + DBG_BLOCK_ID_PA_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_PC0_BY2 = 0xe, + DBG_BLOCK_ID_BCI0_BY2 = 0xf, + DBG_BLOCK_ID_SXM0_BY2 = 0x10, + DBG_BLOCK_ID_SCT0_BY2 = 0x11, + DBG_BLOCK_ID_SPM0_BY2 = 0x12, + DBG_BLOCK_ID_BCI2_BY2 = 0x13, + DBG_BLOCK_ID_TCA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_MCD_BY2 = 0x18, + DBG_BLOCK_ID_MCD2_BY2 = 0x19, + DBG_BLOCK_ID_MCD4_BY2 = 0x1a, + DBG_BLOCK_ID_MCB_BY2 = 0x1b, + DBG_BLOCK_ID_SQA_BY2 = 0x1c, + DBG_BLOCK_ID_SQA02_BY2 = 0x1d, + DBG_BLOCK_ID_SQA11_BY2 = 0x1e, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, + DBG_BLOCK_ID_SQB_BY2 = 0x20, + DBG_BLOCK_ID_SQB10_BY2 = 0x21, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, + DBG_BLOCK_ID_CB_BY2 = 0x24, + DBG_BLOCK_ID_CB02_BY2 = 0x25, + DBG_BLOCK_ID_CB10_BY2 = 0x26, + DBG_BLOCK_ID_CB12_BY2 = 0x27, + DBG_BLOCK_ID_SXS_BY2 = 0x28, + DBG_BLOCK_ID_SXS2_BY2 = 0x29, + DBG_BLOCK_ID_SXS4_BY2 = 0x2a, + DBG_BLOCK_ID_SXS6_BY2 = 0x2b, + DBG_BLOCK_ID_DB_BY2 = 0x2c, + DBG_BLOCK_ID_DB02_BY2 = 0x2d, + DBG_BLOCK_ID_DB10_BY2 = 0x2e, + DBG_BLOCK_ID_DB12_BY2 = 0x2f, + DBG_BLOCK_ID_TCP_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_TCC_BY2 = 0x40, + DBG_BLOCK_ID_TCC2_BY2 = 0x41, + DBG_BLOCK_ID_TCC4_BY2 = 0x42, + DBG_BLOCK_ID_TCC6_BY2 = 0x43, + DBG_BLOCK_ID_SPS_BY2 = 0x44, + DBG_BLOCK_ID_SPS02_BY2 = 0x45, + DBG_BLOCK_ID_SPS11_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, + DBG_BLOCK_ID_TA_BY2 = 0x48, + DBG_BLOCK_ID_TA02_BY2 = 0x49, + DBG_BLOCK_ID_TA04_BY2 = 0x4a, + DBG_BLOCK_ID_TA06_BY2 = 0x4b, + DBG_BLOCK_ID_TA08_BY2 = 0x4c, + DBG_BLOCK_ID_TA0A_BY2 = 0x4d, + DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, + DBG_BLOCK_ID_TA10_BY2 = 0x50, + DBG_BLOCK_ID_TA12_BY2 = 0x51, + DBG_BLOCK_ID_TA14_BY2 = 0x52, + DBG_BLOCK_ID_TA16_BY2 = 0x53, + DBG_BLOCK_ID_TA18_BY2 = 0x54, + DBG_BLOCK_ID_TA1A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, + DBG_BLOCK_ID_TD_BY2 = 0x58, + DBG_BLOCK_ID_TD02_BY2 = 0x59, + DBG_BLOCK_ID_TD04_BY2 = 0x5a, + DBG_BLOCK_ID_TD06_BY2 = 0x5b, + DBG_BLOCK_ID_TD08_BY2 = 0x5c, + DBG_BLOCK_ID_TD0A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, + DBG_BLOCK_ID_TD10_BY2 = 0x60, + DBG_BLOCK_ID_TD12_BY2 = 0x61, + DBG_BLOCK_ID_TD14_BY2 = 0x62, + DBG_BLOCK_ID_TD16_BY2 = 0x63, + DBG_BLOCK_ID_TD18_BY2 = 0x64, + DBG_BLOCK_ID_TD1A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, + DBG_BLOCK_ID_LDS_BY2 = 0x68, + DBG_BLOCK_ID_LDS02_BY2 = 0x69, + DBG_BLOCK_ID_LDS04_BY2 = 0x6a, + DBG_BLOCK_ID_LDS06_BY2 = 0x6b, + DBG_BLOCK_ID_LDS08_BY2 = 0x6c, + DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, + DBG_BLOCK_ID_LDS10_BY2 = 0x70, + DBG_BLOCK_ID_LDS12_BY2 = 0x71, + DBG_BLOCK_ID_LDS14_BY2 = 0x72, + DBG_BLOCK_ID_LDS16_BY2 = 0x73, + DBG_BLOCK_ID_LDS18_BY2 = 0x74, + DBG_BLOCK_ID_LDS1A_BY2 = 0x75, + DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, + DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_SDMA0_BY4 = 0x4, + DBG_BLOCK_ID_VC0_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, + DBG_BLOCK_ID_SXM0_BY4 = 0x8, + DBG_BLOCK_ID_SPM0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC_BY4 = 0xb, + DBG_BLOCK_ID_MCD_BY4 = 0xc, + DBG_BLOCK_ID_MCD4_BY4 = 0xd, + DBG_BLOCK_ID_SQA_BY4 = 0xe, + DBG_BLOCK_ID_SQA11_BY4 = 0xf, + DBG_BLOCK_ID_SQB_BY4 = 0x10, + DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, + DBG_BLOCK_ID_CB_BY4 = 0x12, + DBG_BLOCK_ID_CB10_BY4 = 0x13, + DBG_BLOCK_ID_SXS_BY4 = 0x14, + DBG_BLOCK_ID_SXS4_BY4 = 0x15, + DBG_BLOCK_ID_DB_BY4 = 0x16, + DBG_BLOCK_ID_DB10_BY4 = 0x17, + DBG_BLOCK_ID_TCP_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_TCC_BY4 = 0x20, + DBG_BLOCK_ID_TCC4_BY4 = 0x21, + DBG_BLOCK_ID_SPS_BY4 = 0x22, + DBG_BLOCK_ID_SPS11_BY4 = 0x23, + DBG_BLOCK_ID_TA_BY4 = 0x24, + DBG_BLOCK_ID_TA04_BY4 = 0x25, + DBG_BLOCK_ID_TA08_BY4 = 0x26, + DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, + DBG_BLOCK_ID_TA10_BY4 = 0x28, + DBG_BLOCK_ID_TA14_BY4 = 0x29, + DBG_BLOCK_ID_TA18_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, + DBG_BLOCK_ID_TD_BY4 = 0x2c, + DBG_BLOCK_ID_TD04_BY4 = 0x2d, + DBG_BLOCK_ID_TD08_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, + DBG_BLOCK_ID_TD10_BY4 = 0x30, + DBG_BLOCK_ID_TD14_BY4 = 0x31, + DBG_BLOCK_ID_TD18_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, + DBG_BLOCK_ID_LDS_BY4 = 0x34, + DBG_BLOCK_ID_LDS04_BY4 = 0x35, + DBG_BLOCK_ID_LDS08_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, + DBG_BLOCK_ID_LDS10_BY4 = 0x38, + DBG_BLOCK_ID_LDS14_BY4 = 0x39, + DBG_BLOCK_ID_LDS18_BY4 = 0x3a, + DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_SDMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_SXM0_BY8 = 0x4, + DBG_BLOCK_ID_TCA_BY8 = 0x5, + DBG_BLOCK_ID_MCD_BY8 = 0x6, + DBG_BLOCK_ID_SQA_BY8 = 0x7, + DBG_BLOCK_ID_SQB_BY8 = 0x8, + DBG_BLOCK_ID_CB_BY8 = 0x9, + DBG_BLOCK_ID_SXS_BY8 = 0xa, + DBG_BLOCK_ID_DB_BY8 = 0xb, + DBG_BLOCK_ID_TCP_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_TCC_BY8 = 0x10, + DBG_BLOCK_ID_SPS_BY8 = 0x11, + DBG_BLOCK_ID_TA_BY8 = 0x12, + DBG_BLOCK_ID_TA08_BY8 = 0x13, + DBG_BLOCK_ID_TA10_BY8 = 0x14, + DBG_BLOCK_ID_TA18_BY8 = 0x15, + DBG_BLOCK_ID_TD_BY8 = 0x16, + DBG_BLOCK_ID_TD08_BY8 = 0x17, + DBG_BLOCK_ID_TD10_BY8 = 0x18, + DBG_BLOCK_ID_TD18_BY8 = 0x19, + DBG_BLOCK_ID_LDS_BY8 = 0x1a, + DBG_BLOCK_ID_LDS08_BY8 = 0x1b, + DBG_BLOCK_ID_LDS10_BY8 = 0x1c, + DBG_BLOCK_ID_LDS18_BY8 = 0x1d, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_SDMA0_BY16 = 0x1, + DBG_BLOCK_ID_SXM_BY16 = 0x2, + DBG_BLOCK_ID_MCD_BY16 = 0x3, + DBG_BLOCK_ID_SQB_BY16 = 0x4, + DBG_BLOCK_ID_SXS_BY16 = 0x5, + DBG_BLOCK_ID_TCP_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_TCC_BY16 = 0x8, + DBG_BLOCK_ID_TA_BY16 = 0x9, + DBG_BLOCK_ID_TA10_BY16 = 0xa, + DBG_BLOCK_ID_TD_BY16 = 0xb, + DBG_BLOCK_ID_TD10_BY16 = 0xc, + DBG_BLOCK_ID_LDS_BY16 = 0xd, + DBG_BLOCK_ID_LDS10_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_RESERVED_15 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_RESERVED_23 = 0x17, + IMG_DATA_FORMAT_RESERVED_24 = 0x18, + IMG_DATA_FORMAT_RESERVED_25 = 0x19, + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_32_AS_8 = 0x3d, + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; +#define CG_SRBM_START_ADDR 0x600 +#define CG_SRBM_END_ADDR 0x8ff +#define CG_SRBM_DEC0_START_ADDR 0x200 +#define CG_SRBM_DEC0_END_ADDR 0x2ff + +#endif /* SMU_8_0_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h new file mode 100644 index 000000000000..3dbe24df7e02 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h @@ -0,0 +1,2964 @@ +/* + * SMU_8_0 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef SMU_8_0_SH_MASK_H +#define SMU_8_0_SH_MASK_H + +#define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff +#define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0 +#define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400 +#define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa +#define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff +#define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0 +#define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000 +#define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc +#define THM_TCON_HTC__HTC_EN_MASK 0x1 +#define THM_TCON_HTC__HTC_EN__SHIFT 0x0 +#define THM_TCON_HTC__RSVD0_MASK 0x2 +#define THM_TCON_HTC__RSVD0__SHIFT 0x1 +#define THM_TCON_HTC__HTC_P_STATE_EN_MASK 0x4 +#define THM_TCON_HTC__HTC_P_STATE_EN__SHIFT 0x2 +#define THM_TCON_HTC__RSVD1_MASK 0x8 +#define THM_TCON_HTC__RSVD1__SHIFT 0x3 +#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x10 +#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 +#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x20 +#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 +#define THM_TCON_HTC__HTC_APIC_HI_EN_MASK 0x40 +#define THM_TCON_HTC__HTC_APIC_HI_EN__SHIFT 0x6 +#define THM_TCON_HTC__HTC_APIC_LO_EN_MASK 0x80 +#define THM_TCON_HTC__HTC_APIC_LO_EN__SHIFT 0x7 +#define THM_TCON_HTC__HTC_DIAG_MASK 0x100 +#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 +#define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x200 +#define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9 +#define THM_TCON_HTC__HTC_TO_GNB_EN_MASK 0x400 +#define THM_TCON_HTC__HTC_TO_GNB_EN__SHIFT 0xa +#define THM_TCON_HTC__PROCHOT_TO_GNB_EN_MASK 0x800 +#define THM_TCON_HTC__PROCHOT_TO_GNB_EN__SHIFT 0xb +#define THM_TCON_HTC__RSVD2_MASK 0xf000 +#define THM_TCON_HTC__RSVD2__SHIFT 0xc +#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x7f0000 +#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 +#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x800000 +#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x17 +#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0xf000000 +#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x18 +#define THM_TCON_HTC__HTC_PSTATE_LIMIT_MASK 0x70000000 +#define THM_TCON_HTC__HTC_PSTATE_LIMIT__SHIFT 0x1c +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x1f +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x60 +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x80 +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x1f00 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x30000 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x40000 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x80000 +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 +#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xffe00000 +#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 +#define THM_TCON_THERM_TRIP__RSVD0_MASK 0x1 +#define THM_TCON_THERM_TRIP__RSVD0__SHIFT 0x0 +#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x2 +#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 +#define THM_TCON_THERM_TRIP__RSVD1_MASK 0x4 +#define THM_TCON_THERM_TRIP__RSVD1__SHIFT 0x2 +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x8 +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 +#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x10 +#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 +#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x20 +#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 +#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7fffffc0 +#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0x6 +#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000 +#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f +#define THM_GPIO_PROCHOT_CTRL__TX12_EN_MASK 0x1 +#define THM_GPIO_PROCHOT_CTRL__TX12_EN__SHIFT 0x0 +#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x2 +#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x4 +#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x8 +#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_PROCHOT_CTRL__SN_MASK 0x10 +#define THM_GPIO_PROCHOT_CTRL__SN__SHIFT 0x4 +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x100 +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x8 +#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x200 +#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x9 +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x400 +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0xa +#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x800 +#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0xb +#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x1000 +#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0xc +#define THM_GPIO_THERMTRIP_CTRL__TX12_EN_MASK 0x1 +#define THM_GPIO_THERMTRIP_CTRL__TX12_EN__SHIFT 0x0 +#define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x2 +#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x4 +#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x8 +#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_THERMTRIP_CTRL__SN_MASK 0x10 +#define THM_GPIO_THERMTRIP_CTRL__SN__SHIFT 0x4 +#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x100 +#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x8 +#define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x200 +#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x9 +#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x400 +#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0xa +#define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x800 +#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0xb +#define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x1000 +#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0xc +#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 +#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 +#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 +#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 +#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 +#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 +#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 +#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 +#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 +#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 +#define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 +#define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 +#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 +#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 +#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 +#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 +#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b +#define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 +#define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c +#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 +#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 +#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 +#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 +#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 +#define TMON0_RDIL0_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL0_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL1_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL1_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL2_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL2_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL3_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL3_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL4_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL4_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL5_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL5_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL6_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL6_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL7_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL7_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL8_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL8_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL9_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL9_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL10_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL10_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL11_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL11_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL12_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL12_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL13_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL13_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL14_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL14_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL15_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIL15_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR0_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR0_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR1_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR1_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR2_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR2_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR3_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR3_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR4_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR4_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR5_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR5_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR6_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR6_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR7_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR7_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR8_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR8_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR9_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR9_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR10_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR10_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR11_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR11_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR12_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR12_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR13_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR13_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR14_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR14_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIR15_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_RDIR15_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_INT_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON0_INT_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK 0xff +#define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT 0x0 +#define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK 0xff +#define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT 0x0 +#define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK 0xff +#define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT 0x0 +#define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK 0xff +#define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT 0x0 +#define TMON0_CONFIG__NUM_ACQ_MASK 0x7 +#define TMON0_CONFIG__NUM_ACQ__SHIFT 0x0 +#define TMON0_CONFIG__FORCE_MAX_ACQ_MASK 0x8 +#define TMON0_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3 +#define TMON0_CONFIG__RDI_INTERLEAVE_MASK 0x10 +#define TMON0_CONFIG__RDI_INTERLEAVE__SHIFT 0x4 +#define TMON0_CONFIG__RE_CALIB_EN_MASK 0x40 +#define TMON0_CONFIG__RE_CALIB_EN__SHIFT 0x6 +#define TMON0_TEMP_CALC_COEFF0__Z_MASK 0x7ff +#define TMON0_TEMP_CALC_COEFF0__Z__SHIFT 0x0 +#define TMON0_TEMP_CALC_COEFF1__A_MASK 0xfff +#define TMON0_TEMP_CALC_COEFF1__A__SHIFT 0x0 +#define TMON0_TEMP_CALC_COEFF2__B_MASK 0x3f +#define TMON0_TEMP_CALC_COEFF2__B__SHIFT 0x0 +#define TMON0_TEMP_CALC_COEFF3__C_MASK 0x7ff +#define TMON0_TEMP_CALC_COEFF3__C__SHIFT 0x0 +#define TMON0_TEMP_CALC_COEFF4__K_MASK 0x1 +#define TMON0_TEMP_CALC_COEFF4__K__SHIFT 0x0 +#define TMON0_DEBUG0__DEBUG_Z_MASK 0x7ff +#define TMON0_DEBUG0__DEBUG_Z__SHIFT 0x0 +#define TMON0_DEBUG0__DEBUG_Z_EN_MASK 0x800 +#define TMON0_DEBUG0__DEBUG_Z_EN__SHIFT 0xb +#define TMON0_DEBUG1__DEBUG_RDI_MASK 0x1f +#define TMON0_DEBUG1__DEBUG_RDI__SHIFT 0x0 +#define TMON1_RDIL0_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL0_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL1_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL1_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL2_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL2_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL3_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL3_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL4_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL4_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL5_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL5_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL6_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL6_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL7_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL7_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL8_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL8_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL9_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL9_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL10_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL10_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL11_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL11_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL12_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL12_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL13_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL13_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL14_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL14_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL15_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIL15_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR0_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR0_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR1_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR1_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR2_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR2_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR3_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR3_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR4_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR4_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR5_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR5_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR6_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR6_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR7_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR7_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR8_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR8_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR9_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR9_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR10_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR10_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR11_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR11_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR12_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR12_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR13_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR13_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR14_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR14_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIR15_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_RDIR15_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_INT_DATA__TEMP_Z_DATA_MASK 0xfff +#define TMON1_INT_DATA__TEMP_Z_DATA__SHIFT 0x0 +#define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK 0xff +#define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT 0x0 +#define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK 0xff +#define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT 0x0 +#define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK 0xff +#define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT 0x0 +#define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK 0xff +#define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT 0x0 +#define TMON1_CONFIG__NUM_ACQ_MASK 0x7 +#define TMON1_CONFIG__NUM_ACQ__SHIFT 0x0 +#define TMON1_CONFIG__FORCE_MAX_ACQ_MASK 0x8 +#define TMON1_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3 +#define TMON1_CONFIG__RDI_INTERLEAVE_MASK 0x10 +#define TMON1_CONFIG__RDI_INTERLEAVE__SHIFT 0x4 +#define TMON1_CONFIG__RE_CALIB_EN_MASK 0x40 +#define TMON1_CONFIG__RE_CALIB_EN__SHIFT 0x6 +#define TMON1_TEMP_CALC_COEFF0__Z_MASK 0x7ff +#define TMON1_TEMP_CALC_COEFF0__Z__SHIFT 0x0 +#define TMON1_TEMP_CALC_COEFF1__A_MASK 0xfff +#define TMON1_TEMP_CALC_COEFF1__A__SHIFT 0x0 +#define TMON1_TEMP_CALC_COEFF2__B_MASK 0x3f +#define TMON1_TEMP_CALC_COEFF2__B__SHIFT 0x0 +#define TMON1_TEMP_CALC_COEFF3__C_MASK 0x7ff +#define TMON1_TEMP_CALC_COEFF3__C__SHIFT 0x0 +#define TMON1_TEMP_CALC_COEFF4__K_MASK 0x1 +#define TMON1_TEMP_CALC_COEFF4__K__SHIFT 0x0 +#define TMON1_DEBUG0__DEBUG_Z_MASK 0x7ff +#define TMON1_DEBUG0__DEBUG_Z__SHIFT 0x0 +#define TMON1_DEBUG0__DEBUG_Z_EN_MASK 0x800 +#define TMON1_DEBUG0__DEBUG_Z_EN__SHIFT 0xb +#define TMON1_DEBUG1__DEBUG_RDI_MASK 0x1f +#define TMON1_DEBUG1__DEBUG_RDI__SHIFT 0x0 +#define THM_TMON0_REMOTE_START__DATA_MASK 0xffffffff +#define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0 +#define THM_TMON0_REMOTE_END__DATA_MASK 0xffffffff +#define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0 +#define THM_TMON1_REMOTE_START__DATA_MASK 0xffffffff +#define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0 +#define THM_TMON1_REMOTE_END__DATA_MASK 0xffffffff +#define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0 +#define THM_TCON_LOCAL0__HaltPolling_MASK 0x1 +#define THM_TCON_LOCAL0__HaltPolling__SHIFT 0x0 +#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x2 +#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1 +#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x4 +#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2 +#define THM_TCON_LOCAL1__PwrDn_Limit_Temp_MASK 0x7 +#define THM_TCON_LOCAL1__PwrDn_Limit_Temp__SHIFT 0x0 +#define THM_TCON_LOCAL1__PwrDn_DelaySlope_MASK 0x38 +#define THM_TCON_LOCAL1__PwrDn_DelaySlope__SHIFT 0x3 +#define THM_TCON_LOCAL1__PwrDn_MinDelay_MASK 0x1c0 +#define THM_TCON_LOCAL1__PwrDn_MinDelay__SHIFT 0x6 +#define THM_TCON_LOCAL2__PwrDn_MaxDlyMult_MASK 0x3 +#define THM_TCON_LOCAL2__PwrDn_MaxDlyMult__SHIFT 0x0 +#define THM_TCON_LOCAL2__PwrDn_NumSensors_MASK 0xc +#define THM_TCON_LOCAL2__PwrDn_NumSensors__SHIFT 0x2 +#define THM_TCON_LOCAL2__start_mission_polling_MASK 0x10 +#define THM_TCON_LOCAL2__start_mission_polling__SHIFT 0x4 +#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x20 +#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 +#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x40 +#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 +#define THM_TCON_LOCAL2__csrslave_use_corrected_MASK 0x80 +#define THM_TCON_LOCAL2__csrslave_use_corrected__SHIFT 0x7 +#define THM_TCON_LOCAL2__smu_use_corrected_MASK 0x100 +#define THM_TCON_LOCAL2__smu_use_corrected__SHIFT 0x8 +#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x800 +#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb +#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x7ff +#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 +#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0xff +#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 +#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x7ff +#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 +#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0xff +#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 +#define THM_TCON_LOCAL7__THERMID_MASK 0xff +#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 +#define THM_TCON_LOCAL8__THERMMAX_MASK 0x7ff +#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 +#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x7ff +#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0 +#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0xf +#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x7ff +#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0 +#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0xf +#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL13__PowerDownTmon0_MASK 0x1 +#define THM_TCON_LOCAL13__PowerDownTmon0__SHIFT 0x0 +#define THM_TCON_LOCAL13__PowerDownTmon1_MASK 0x2 +#define THM_TCON_LOCAL13__PowerDownTmon1__SHIFT 0x1 +#define THM_TCON_LOCAL14__boot_done_MASK 0x1 +#define THM_TCON_LOCAL14__boot_done__SHIFT 0x0 +#define THM_FUSE0__FUSE_TmonRsInterleave_MASK 0x1 +#define THM_FUSE0__FUSE_TmonRsInterleave__SHIFT 0x0 +#define THM_FUSE0__FUSE_TmonNumAcq_MASK 0xe +#define THM_FUSE0__FUSE_TmonNumAcq__SHIFT 0x1 +#define THM_FUSE0__FUSE_TmonForceMaxAcq_MASK 0x10 +#define THM_FUSE0__FUSE_TmonForceMaxAcq__SHIFT 0x4 +#define THM_FUSE0__FUSE_TmonClkDiv_MASK 0x60 +#define THM_FUSE0__FUSE_TmonClkDiv__SHIFT 0x5 +#define THM_FUSE0__FUSE_TmonBGAdj1_MASK 0x7f80 +#define THM_FUSE0__FUSE_TmonBGAdj1__SHIFT 0x7 +#define THM_FUSE0__FUSE_TmonBGAdj0_MASK 0x7f8000 +#define THM_FUSE0__FUSE_TmonBGAdj0__SHIFT 0xf +#define THM_FUSE0__FUSE_TconZtValue_MASK 0xff800000 +#define THM_FUSE0__FUSE_TconZtValue__SHIFT 0x17 +#define THM_FUSE1__FUSE_TconZtValue_MASK 0x3 +#define THM_FUSE1__FUSE_TconZtValue__SHIFT 0x0 +#define THM_FUSE1__FUSE_TconUseSecondary_MASK 0xc +#define THM_FUSE1__FUSE_TconUseSecondary__SHIFT 0x2 +#define THM_FUSE1__FUSE_TconTmpAdjLoRes_MASK 0x10 +#define THM_FUSE1__FUSE_TconTmpAdjLoRes__SHIFT 0x4 +#define THM_FUSE1__FUSE_TconPwrUpStaggerTime_MASK 0x60 +#define THM_FUSE1__FUSE_TconPwrUpStaggerTime__SHIFT 0x5 +#define THM_FUSE1__FUSE_TconPwrDnTmpLmt_MASK 0x380 +#define THM_FUSE1__FUSE_TconPwrDnTmpLmt__SHIFT 0x7 +#define THM_FUSE1__FUSE_TconPwrDnNumSensors_MASK 0xc00 +#define THM_FUSE1__FUSE_TconPwrDnNumSensors__SHIFT 0xa +#define THM_FUSE1__FUSE_TconPwrDnMinDelay_MASK 0x7000 +#define THM_FUSE1__FUSE_TconPwrDnMinDelay__SHIFT 0xc +#define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult_MASK 0x18000 +#define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult__SHIFT 0xf +#define THM_FUSE1__FUSE_TconPwrDnDelaySlope_MASK 0xe0000 +#define THM_FUSE1__FUSE_TconPwrDnDelaySlope__SHIFT 0x11 +#define THM_FUSE1__FUSE_TconKValue_MASK 0x100000 +#define THM_FUSE1__FUSE_TconKValue__SHIFT 0x14 +#define THM_FUSE1__FUSE_TconDtValue31_MASK 0x7e00000 +#define THM_FUSE1__FUSE_TconDtValue31__SHIFT 0x15 +#define THM_FUSE1__FUSE_TconDtValue30_MASK 0xf8000000 +#define THM_FUSE1__FUSE_TconDtValue30__SHIFT 0x1b +#define THM_FUSE2__FUSE_TconDtValue30_MASK 0x1 +#define THM_FUSE2__FUSE_TconDtValue30__SHIFT 0x0 +#define THM_FUSE2__FUSE_TconDtValue29_MASK 0x7e +#define THM_FUSE2__FUSE_TconDtValue29__SHIFT 0x1 +#define THM_FUSE2__FUSE_TconDtValue28_MASK 0x1f80 +#define THM_FUSE2__FUSE_TconDtValue28__SHIFT 0x7 +#define THM_FUSE2__FUSE_TconDtValue27_MASK 0x7e000 +#define THM_FUSE2__FUSE_TconDtValue27__SHIFT 0xd +#define THM_FUSE2__FUSE_TconDtValue26_MASK 0x1f80000 +#define THM_FUSE2__FUSE_TconDtValue26__SHIFT 0x13 +#define THM_FUSE2__FUSE_TconDtValue25_MASK 0x7e000000 +#define THM_FUSE2__FUSE_TconDtValue25__SHIFT 0x19 +#define THM_FUSE2__FUSE_TconDtValue24_MASK 0x80000000 +#define THM_FUSE2__FUSE_TconDtValue24__SHIFT 0x1f +#define THM_FUSE3__FUSE_TconDtValue24_MASK 0x1f +#define THM_FUSE3__FUSE_TconDtValue24__SHIFT 0x0 +#define THM_FUSE3__FUSE_TconDtValue23_MASK 0x7e0 +#define THM_FUSE3__FUSE_TconDtValue23__SHIFT 0x5 +#define THM_FUSE3__FUSE_TconDtValue22_MASK 0x1f800 +#define THM_FUSE3__FUSE_TconDtValue22__SHIFT 0xb +#define THM_FUSE3__FUSE_TconDtValue21_MASK 0x7e0000 +#define THM_FUSE3__FUSE_TconDtValue21__SHIFT 0x11 +#define THM_FUSE3__FUSE_TconDtValue20_MASK 0x1f800000 +#define THM_FUSE3__FUSE_TconDtValue20__SHIFT 0x17 +#define THM_FUSE3__FUSE_TconDtValue19_MASK 0xe0000000 +#define THM_FUSE3__FUSE_TconDtValue19__SHIFT 0x1d +#define THM_FUSE4__FUSE_TconDtValue19_MASK 0x7 +#define THM_FUSE4__FUSE_TconDtValue19__SHIFT 0x0 +#define THM_FUSE4__FUSE_TconDtValue18_MASK 0x1f8 +#define THM_FUSE4__FUSE_TconDtValue18__SHIFT 0x3 +#define THM_FUSE4__FUSE_TconDtValue17_MASK 0x7e00 +#define THM_FUSE4__FUSE_TconDtValue17__SHIFT 0x9 +#define THM_FUSE4__FUSE_TconDtValue16_MASK 0x1f8000 +#define THM_FUSE4__FUSE_TconDtValue16__SHIFT 0xf +#define THM_FUSE4__FUSE_TconDtValue15_MASK 0x7e00000 +#define THM_FUSE4__FUSE_TconDtValue15__SHIFT 0x15 +#define THM_FUSE4__FUSE_TconDtValue14_MASK 0xf8000000 +#define THM_FUSE4__FUSE_TconDtValue14__SHIFT 0x1b +#define THM_FUSE5__FUSE_TconDtValue14_MASK 0x1 +#define THM_FUSE5__FUSE_TconDtValue14__SHIFT 0x0 +#define THM_FUSE5__FUSE_TconDtValue13_MASK 0x7e +#define THM_FUSE5__FUSE_TconDtValue13__SHIFT 0x1 +#define THM_FUSE5__FUSE_TconDtValue12_MASK 0x1f80 +#define THM_FUSE5__FUSE_TconDtValue12__SHIFT 0x7 +#define THM_FUSE5__FUSE_TconDtValue11_MASK 0x7e000 +#define THM_FUSE5__FUSE_TconDtValue11__SHIFT 0xd +#define THM_FUSE5__FUSE_TconDtValue10_MASK 0x1f80000 +#define THM_FUSE5__FUSE_TconDtValue10__SHIFT 0x13 +#define THM_FUSE5__FUSE_TconDtValue9_MASK 0x7e000000 +#define THM_FUSE5__FUSE_TconDtValue9__SHIFT 0x19 +#define THM_FUSE5__FUSE_TconDtValue8_MASK 0x80000000 +#define THM_FUSE5__FUSE_TconDtValue8__SHIFT 0x1f +#define THM_FUSE6__FUSE_TconDtValue8_MASK 0x1f +#define THM_FUSE6__FUSE_TconDtValue8__SHIFT 0x0 +#define THM_FUSE6__FUSE_TconDtValue7_MASK 0x7e0 +#define THM_FUSE6__FUSE_TconDtValue7__SHIFT 0x5 +#define THM_FUSE6__FUSE_TconDtValue6_MASK 0x1f800 +#define THM_FUSE6__FUSE_TconDtValue6__SHIFT 0xb +#define THM_FUSE6__FUSE_TconDtValue5_MASK 0x7e0000 +#define THM_FUSE6__FUSE_TconDtValue5__SHIFT 0x11 +#define THM_FUSE6__FUSE_TconDtValue4_MASK 0x1f800000 +#define THM_FUSE6__FUSE_TconDtValue4__SHIFT 0x17 +#define THM_FUSE6__FUSE_TconDtValue3_MASK 0xe0000000 +#define THM_FUSE6__FUSE_TconDtValue3__SHIFT 0x1d +#define THM_FUSE7__FUSE_TconDtValue3_MASK 0x7 +#define THM_FUSE7__FUSE_TconDtValue3__SHIFT 0x0 +#define THM_FUSE7__FUSE_TconDtValue2_MASK 0x1f8 +#define THM_FUSE7__FUSE_TconDtValue2__SHIFT 0x3 +#define THM_FUSE7__FUSE_TconDtValue1_MASK 0x7e00 +#define THM_FUSE7__FUSE_TconDtValue1__SHIFT 0x9 +#define THM_FUSE7__FUSE_TconDtValue0_MASK 0x1f8000 +#define THM_FUSE7__FUSE_TconDtValue0__SHIFT 0xf +#define THM_FUSE7__FUSE_TconCtValue1_MASK 0xffe00000 +#define THM_FUSE7__FUSE_TconCtValue1__SHIFT 0x15 +#define THM_FUSE8__FUSE_TconCtValue0_MASK 0x7ff +#define THM_FUSE8__FUSE_TconCtValue0__SHIFT 0x0 +#define THM_FUSE8__FUSE_TconBtValue_MASK 0x1f800 +#define THM_FUSE8__FUSE_TconBtValue__SHIFT 0xb +#define THM_FUSE8__FUSE_TconBootDelay_MASK 0x60000 +#define THM_FUSE8__FUSE_TconBootDelay__SHIFT 0x11 +#define THM_FUSE8__FUSE_TconAtValue1_MASK 0x7ff80000 +#define THM_FUSE8__FUSE_TconAtValue1__SHIFT 0x13 +#define THM_FUSE8__FUSE_TconAtValue0_MASK 0x80000000 +#define THM_FUSE8__FUSE_TconAtValue0__SHIFT 0x1f +#define THM_FUSE9__FUSE_TconAtValue0_MASK 0x7ff +#define THM_FUSE9__FUSE_TconAtValue0__SHIFT 0x0 +#define THM_FUSE9__FUSE_ThermTripLimit_MASK 0x7f800 +#define THM_FUSE9__FUSE_ThermTripLimit__SHIFT 0xb +#define THM_FUSE9__FUSE_ThermTripEn_MASK 0x80000 +#define THM_FUSE9__FUSE_ThermTripEn__SHIFT 0x13 +#define THM_FUSE9__FUSE_HtcTmpLmt_MASK 0x7f00000 +#define THM_FUSE9__FUSE_HtcTmpLmt__SHIFT 0x14 +#define THM_FUSE9__FUSE_HtcMsrLock_MASK 0x8000000 +#define THM_FUSE9__FUSE_HtcMsrLock__SHIFT 0x1b +#define THM_FUSE9__FUSE_HtcHystLmt_MASK 0xf0000000 +#define THM_FUSE9__FUSE_HtcHystLmt__SHIFT 0x1c +#define THM_FUSE10__FUSE_HtcDis_MASK 0x1 +#define THM_FUSE10__FUSE_HtcDis__SHIFT 0x0 +#define THM_FUSE10__FUSE_HtcClkInact_MASK 0xe +#define THM_FUSE10__FUSE_HtcClkInact__SHIFT 0x1 +#define THM_FUSE10__FUSE_HtcClkAct_MASK 0x70 +#define THM_FUSE10__FUSE_HtcClkAct__SHIFT 0x4 +#define THM_FUSE10__FUSE_UnusedBits_MASK 0xffffff80 +#define THM_FUSE10__FUSE_UnusedBits__SHIFT 0x7 +#define THM_FUSE11__PA_SPARE_MASK 0xff +#define THM_FUSE11__PA_SPARE__SHIFT 0x0 +#define THM_FUSE12__FusesValid_MASK 0x1 +#define THM_FUSE12__FusesValid__SHIFT 0x0 +#define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR_MASK 0xffffffff +#define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR__SHIFT 0x0 +#define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA_MASK 0xffffffff +#define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA__SHIFT 0x0 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000 +#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf +#define MP0_MSP_MESSAGE_0__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_0__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_1__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_1__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_2__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_2__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_3__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_3__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_4__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_4__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_5__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_5__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_6__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_6__MP0_MSP_MSG__SHIFT 0x0 +#define MP0_MSP_MESSAGE_7__MP0_MSP_MSG_MASK 0xffffffff +#define MP0_MSP_MESSAGE_7__MP0_MSP_MSG__SHIFT 0x0 +#define SAM_IH_EXT_ERR_INTR__UVD_MASK 0x1 +#define SAM_IH_EXT_ERR_INTR__UVD__SHIFT 0x0 +#define SAM_IH_EXT_ERR_INTR__VCE_MASK 0x2 +#define SAM_IH_EXT_ERR_INTR__VCE__SHIFT 0x1 +#define SAM_IH_EXT_ERR_INTR__ISP_MASK 0x4 +#define SAM_IH_EXT_ERR_INTR__ISP__SHIFT 0x2 +#define SAM_IH_EXT_ERR_INTR__RESERVED_MASK 0xfffffff8 +#define SAM_IH_EXT_ERR_INTR__RESERVED__SHIFT 0x3 +#define SAM_IH_EXT_ERR_INTR_STATUS__UVD_MASK 0x1 +#define SAM_IH_EXT_ERR_INTR_STATUS__UVD__SHIFT 0x0 +#define SAM_IH_EXT_ERR_INTR_STATUS__VCE_MASK 0x2 +#define SAM_IH_EXT_ERR_INTR_STATUS__VCE__SHIFT 0x1 +#define SAM_IH_EXT_ERR_INTR_STATUS__ISP_MASK 0x4 +#define SAM_IH_EXT_ERR_INTR_STATUS__ISP__SHIFT 0x2 +#define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED_MASK 0xfffffff8 +#define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED__SHIFT 0x3 +#define MP0_DISP_TIMER0_CTRL0__START_MASK 0x1 +#define MP0_DISP_TIMER0_CTRL0__START__SHIFT 0x0 +#define MP0_DISP_TIMER0_CTRL0__CLEAR_MASK 0x100 +#define MP0_DISP_TIMER0_CTRL0__CLEAR__SHIFT 0x8 +#define MP0_DISP_TIMER0_CTRL0__DEC_MASK 0x10000 +#define MP0_DISP_TIMER0_CTRL0__DEC__SHIFT 0x10 +#define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE_MASK 0x1000000 +#define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE__SHIFT 0x18 +#define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN_MASK 0x1 +#define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN__SHIFT 0x0 +#define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN_MASK 0x100 +#define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x8 +#define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN_MASK 0x10000 +#define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN__SHIFT 0x10 +#define MP0_DISP_TIMER0_CTRL1__RESERVED_MASK 0xff000000 +#define MP0_DISP_TIMER0_CTRL1__RESERVED__SHIFT 0x18 +#define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC_MASK 0xf +#define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC__SHIFT 0x0 +#define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED_MASK 0xfffffff0 +#define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED__SHIFT 0x4 +#define MP0_DISP_TIMER0_INTEN__INTEN_MASK 0xf +#define MP0_DISP_TIMER0_INTEN__INTEN__SHIFT 0x0 +#define MP0_DISP_TIMER0_INTEN__RESERVED_MASK 0xfffffff0 +#define MP0_DISP_TIMER0_INTEN__RESERVED__SHIFT 0x4 +#define MP0_DISP_TIMER0_OCMP_0_0__OCMP_MASK 0xffffffff +#define MP0_DISP_TIMER0_OCMP_0_0__OCMP__SHIFT 0x0 +#define MP0_DISP_TIMER0_OCMP_0_1__OCMP_MASK 0xffffffff +#define MP0_DISP_TIMER0_OCMP_0_1__OCMP__SHIFT 0x0 +#define MP0_DISP_TIMER0_CNT__COUNT_MASK 0xffffffff +#define MP0_DISP_TIMER0_CNT__COUNT__SHIFT 0x0 +#define MP0_DISP_TIMER1_CTRL0__START_MASK 0x1 +#define MP0_DISP_TIMER1_CTRL0__START__SHIFT 0x0 +#define MP0_DISP_TIMER1_CTRL0__CLEAR_MASK 0x100 +#define MP0_DISP_TIMER1_CTRL0__CLEAR__SHIFT 0x8 +#define MP0_DISP_TIMER1_CTRL0__DEC_MASK 0x10000 +#define MP0_DISP_TIMER1_CTRL0__DEC__SHIFT 0x10 +#define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE_MASK 0x1000000 +#define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE__SHIFT 0x18 +#define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN_MASK 0x1 +#define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN__SHIFT 0x0 +#define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN_MASK 0x100 +#define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x8 +#define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN_MASK 0x10000 +#define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN__SHIFT 0x10 +#define MP0_DISP_TIMER1_CTRL1__RESERVED_MASK 0xff000000 +#define MP0_DISP_TIMER1_CTRL1__RESERVED__SHIFT 0x18 +#define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC_MASK 0xf +#define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC__SHIFT 0x0 +#define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED_MASK 0xfffffff0 +#define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED__SHIFT 0x4 +#define MP0_DISP_TIMER1_INTEN__INTEN_MASK 0xf +#define MP0_DISP_TIMER1_INTEN__INTEN__SHIFT 0x0 +#define MP0_DISP_TIMER1_INTEN__RESERVED_MASK 0xfffffff0 +#define MP0_DISP_TIMER1_INTEN__RESERVED__SHIFT 0x4 +#define MP0_DISP_TIMER1_OCMP_0_0__OCMP_MASK 0xffffffff +#define MP0_DISP_TIMER1_OCMP_0_0__OCMP__SHIFT 0x0 +#define MP0_DISP_TIMER1_OCMP_0_1__OCMP_MASK 0xffffffff +#define MP0_DISP_TIMER1_OCMP_0_1__OCMP__SHIFT 0x0 +#define MP0_DISP_TIMER1_CNT__COUNT_MASK 0xffffffff +#define MP0_DISP_TIMER1_CNT__COUNT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_0__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_0__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_1__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_1__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_2__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_2__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_3__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_3__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_4__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_4__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_5__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_5__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_6__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_6__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_7__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_7__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_8__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_8__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_9__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_9__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_10__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_10__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_11__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_11__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_12__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_12__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_13__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_13__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_14__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_14__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_MSG_15__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_MSG_15__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_0__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_0__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_1__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_1__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_2__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_2__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_3__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_3__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_4__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_4__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_5__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_5__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_6__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_6__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_7__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_7__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_8__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_8__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_9__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_9__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_10__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_10__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_11__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_11__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_12__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_12__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_13__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_13__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_14__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_14__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_RESP_15__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_RESP_15__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_0__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_0__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_1__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_1__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_2__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_2__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_3__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_3__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_4__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_4__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_5__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_5__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_6__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_6__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_7__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_7__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_8__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_8__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_9__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_9__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_10__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_10__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_11__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_11__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_12__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_12__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_13__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_13__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_14__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_14__CONTENT__SHIFT 0x0 +#define SMU_MP1_SRBM2P_ARG_15__CONTENT_MASK 0xffffffff +#define SMU_MP1_SRBM2P_ARG_15__CONTENT__SHIFT 0x0 +#define SMU_MP1_ACP2MP_RESP__CONTENT_MASK 0xffffffff +#define SMU_MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0 +#define SMU_MP1_DC2MP_RESP__CONTENT_MASK 0xffffffff +#define SMU_MP1_DC2MP_RESP__CONTENT__SHIFT 0x0 +#define SMU_MP1_UVD2MP_RESP__CONTENT_MASK 0xffffffff +#define SMU_MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0 +#define SMU_MP1_VCE2MP_RESP__CONTENT_MASK 0xffffffff +#define SMU_MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0 +#define SMU_MP1_RLC2MP_RESP__CONTENT_MASK 0xffffffff +#define SMU_MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0 +#define MP_FPS_CNT__FPS_CNT_MASK 0xffffffff +#define MP_FPS_CNT__FPS_CNT__SHIFT 0x0 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT_MASK 0x1 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT__SHIFT 0x0 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK__SHIFT 0x1 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE_MASK 0x4 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK_MASK 0x8 +#define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK__SHIFT 0x3 +#define SMU_DISP0_TIMER_INT_CONTROL__MASK_MASK 0x10 +#define SMU_DISP0_TIMER_INT_CONTROL__MASK__SHIFT 0x4 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT_MASK 0x1 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT__SHIFT 0x0 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK__SHIFT 0x1 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE_MASK 0x4 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK_MASK 0x8 +#define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK__SHIFT 0x3 +#define SMU_DISP1_TIMER_INT_CONTROL__MASK_MASK 0x10 +#define SMU_DISP1_TIMER_INT_CONTROL__MASK__SHIFT 0x4 +#define SMU_SRBM_CONFIG__MSTR_CREDITS_MASK 0x1f +#define SMU_SRBM_CONFIG__MSTR_CREDITS__SHIFT 0x0 +#define MP_FPS_CNT_XBAR__FPS_CNT_MASK 0xffffffff +#define MP_FPS_CNT_XBAR__FPS_CNT__SHIFT 0x0 +#define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS_MASK 0x1f +#define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS__SHIFT 0x0 +#define MP_SRBM_CONTROL__ACC_VIO_EN_MASK 0x1 +#define MP_SRBM_CONTROL__ACC_VIO_EN__SHIFT 0x0 +#define MP_SRBM_CONTROL__ALLOW_NS_ACC_MASK 0x2 +#define MP_SRBM_CONTROL__ALLOW_NS_ACC__SHIFT 0x1 +#define MP_SRBM_CONTROL__SOFT_RST_MASK_MASK 0x4 +#define MP_SRBM_CONTROL__SOFT_RST_MASK__SHIFT 0x2 +#define MP_SRBM_CONTROL__SOFT_RST_STS_MASK 0x8 +#define MP_SRBM_CONTROL__SOFT_RST_STS__SHIFT 0x3 +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP_MASK 0x1 +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT 0x0 +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID_MASK 0xe +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID__SHIFT 0x1 +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID_MASK 0x80000000 +#define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT 0x1f +#define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK 0xffffffff +#define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT 0x0 +#define MP_CRBBM_CONTROL__ACC_VIO_EN_MASK 0x1 +#define MP_CRBBM_CONTROL__ACC_VIO_EN__SHIFT 0x0 +#define MP_CRBBM_CONTROL__MP0_ACCESS_MASK 0x2 +#define MP_CRBBM_CONTROL__MP0_ACCESS__SHIFT 0x1 +#define MP_CRBBM_CONTROL__ALLOW_NS_ACC_MASK 0x4 +#define MP_CRBBM_CONTROL__ALLOW_NS_ACC__SHIFT 0x2 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP_MASK 0x1 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT 0x0 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF_MASK 0x2 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF__SHIFT 0x1 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID_MASK 0x80000000 +#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT 0x1f +#define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK 0xffffffff +#define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_CNTL__tag_MASK 0x1ffff +#define MP_DRAM_CNTL_WRREQ_CNTL__tag__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_CNTL__urg_MASK 0x1e0000 +#define MP_DRAM_CNTL_WRREQ_CNTL__urg__SHIFT 0x11 +#define MP_DRAM_CNTL_WRREQ_CNTL__stall_MASK 0x200000 +#define MP_DRAM_CNTL_WRREQ_CNTL__stall__SHIFT 0x15 +#define MP_DRAM_CNTL_WRREQ_CNTL__priv_MASK 0x400000 +#define MP_DRAM_CNTL_WRREQ_CNTL__priv__SHIFT 0x16 +#define MP_DRAM_CNTL_WRREQ_CNTL__cid_MASK 0xff800000 +#define MP_DRAM_CNTL_WRREQ_CNTL__cid__SHIFT 0x17 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vf_MASK 0x1 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vf__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid_MASK 0xfe +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid__SHIFT 0x1 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__physical_MASK 0x100 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__physical__SHIFT 0x8 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop_MASK 0x200 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop__SHIFT 0x9 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__inval_MASK 0x400 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__inval__SHIFT 0xa +#define MP_DRAM_CNTL_WRREQ_CNTL_1__op_MASK 0x3f800 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__op__SHIFT 0xb +#define MP_DRAM_CNTL_WRREQ_CNTL_1__swap_MASK 0x300000 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__swap__SHIFT 0x14 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid_MASK 0x3c00000 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid__SHIFT 0x16 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__atc_MASK 0x4000000 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__atc__SHIFT 0x1a +#define MP_DRAM_CNTL_WRREQ_CNTL_1__fed_MASK 0x8000000 +#define MP_DRAM_CNTL_WRREQ_CNTL_1__fed__SHIFT 0x1b +#define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37_MASK 0x7ff +#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved_MASK 0xfffff800 +#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved__SHIFT 0xb +#define MP_DRAM_CNTL_WRREQ_MASK__mask_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_MASK__mask__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_0__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_0__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_1__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_1__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_2__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_2__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_3__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_3__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_4__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_4__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_5__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_5__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_6__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_6__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_DATA_7__data_MASK 0xffffffff +#define MP_DRAM_CNTL_WRREQ_DATA_7__data__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter_MASK 0x1f +#define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter__SHIFT 0x0 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved0_MASK 0xe0 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved0__SHIFT 0x5 +#define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty_MASK 0x100 +#define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty__SHIFT 0x8 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved1_MASK 0xfe00 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved1__SHIFT 0x9 +#define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer_MASK 0xf0000 +#define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer__SHIFT 0x10 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved2_MASK 0xfff00000 +#define MP_DRAM_CNTL_WRREQ_STATUS__reserved2__SHIFT 0x14 +#define MP_DRAM_CNTL_WRRET_STATUS_0__valid_MASK 0x1 +#define MP_DRAM_CNTL_WRRET_STATUS_0__valid__SHIFT 0x0 +#define MP_DRAM_CNTL_WRRET_STATUS_0__nack_MASK 0x6 +#define MP_DRAM_CNTL_WRRET_STATUS_0__nack__SHIFT 0x1 +#define MP_DRAM_CNTL_WRRET_STATUS_0__reserved_MASK 0xfff8 +#define MP_DRAM_CNTL_WRRET_STATUS_0__reserved__SHIFT 0x3 +#define MP_DRAM_CNTL_WRRET_STATUS_0__tag_MASK 0xffff0000 +#define MP_DRAM_CNTL_WRRET_STATUS_0__tag__SHIFT 0x10 +#define MP_DRAM_CNTL_RDREQ_ADDR__addr_MASK 0xffffffff +#define MP_DRAM_CNTL_RDREQ_ADDR__addr__SHIFT 0x0 +#define MP_DRAM_CNTL_RDREQ_CNTL__tag_MASK 0xffff +#define MP_DRAM_CNTL_RDREQ_CNTL__tag__SHIFT 0x0 +#define MP_DRAM_CNTL_RDREQ_CNTL__mask_MASK 0xff0000 +#define MP_DRAM_CNTL_RDREQ_CNTL__mask__SHIFT 0x10 +#define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40_MASK 0xff000000 +#define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40__SHIFT 0x18 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__urg_MASK 0xf +#define MP_DRAM_CNTL_RDREQ_CNTL_1__urg__SHIFT 0x0 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__stall_MASK 0x10 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__stall__SHIFT 0x4 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__priv_MASK 0x20 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__priv__SHIFT 0x5 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__swap_MASK 0xc0 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__swap__SHIFT 0x6 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__cid_MASK 0x1ff00 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__cid__SHIFT 0x8 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid_MASK 0x1e0000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid__SHIFT 0x11 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__atc_MASK 0x200000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__atc__SHIFT 0x15 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__physical_MASK 0x400000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__physical__SHIFT 0x16 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__exe_MASK 0x800000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__exe__SHIFT 0x17 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop_MASK 0x1000000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop__SHIFT 0x18 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__shared_MASK 0x2000000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__shared__SHIFT 0x19 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vf_MASK 0x4000000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vf__SHIFT 0x1a +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid_MASK 0xf8000000 +#define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid__SHIFT 0x1b +#define MP_DRAM_CNTL_RDRET_VALID__vld_0_MASK 0x1 +#define MP_DRAM_CNTL_RDRET_VALID__vld_0__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_VALID__vld_1_MASK 0x2 +#define MP_DRAM_CNTL_RDRET_VALID__vld_1__SHIFT 0x1 +#define MP_DRAM_CNTL_RDRET_VALID__vld_2_MASK 0x4 +#define MP_DRAM_CNTL_RDRET_VALID__vld_2__SHIFT 0x2 +#define MP_DRAM_CNTL_RDRET_VALID__vld_3_MASK 0x8 +#define MP_DRAM_CNTL_RDRET_VALID__vld_3__SHIFT 0x3 +#define MP_DRAM_CNTL_RDRET_VALID__vld_4_MASK 0x10 +#define MP_DRAM_CNTL_RDRET_VALID__vld_4__SHIFT 0x4 +#define MP_DRAM_CNTL_RDRET_VALID__vld_5_MASK 0x20 +#define MP_DRAM_CNTL_RDRET_VALID__vld_5__SHIFT 0x5 +#define MP_DRAM_CNTL_RDRET_VALID__vld_6_MASK 0x40 +#define MP_DRAM_CNTL_RDRET_VALID__vld_6__SHIFT 0x6 +#define MP_DRAM_CNTL_RDRET_VALID__vld_7_MASK 0x80 +#define MP_DRAM_CNTL_RDRET_VALID__vld_7__SHIFT 0x7 +#define MP_DRAM_CNTL_RDRET_VALID__reserved_MASK 0xffff00 +#define MP_DRAM_CNTL_RDRET_VALID__reserved__SHIFT 0x8 +#define MP_DRAM_CNTL_RDRET_VALID__atomic_MASK 0xff000000 +#define MP_DRAM_CNTL_RDRET_VALID__atomic__SHIFT 0x18 +#define MP_DRAM_CNTL_RDRET_NACK__nack_0_MASK 0x3 +#define MP_DRAM_CNTL_RDRET_NACK__nack_0__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_NACK__nack_1_MASK 0xc +#define MP_DRAM_CNTL_RDRET_NACK__nack_1__SHIFT 0x2 +#define MP_DRAM_CNTL_RDRET_NACK__nack_2_MASK 0x30 +#define MP_DRAM_CNTL_RDRET_NACK__nack_2__SHIFT 0x4 +#define MP_DRAM_CNTL_RDRET_NACK__nack_3_MASK 0xc0 +#define MP_DRAM_CNTL_RDRET_NACK__nack_3__SHIFT 0x6 +#define MP_DRAM_CNTL_RDRET_NACK__nack_4_MASK 0x300 +#define MP_DRAM_CNTL_RDRET_NACK__nack_4__SHIFT 0x8 +#define MP_DRAM_CNTL_RDRET_NACK__nack_5_MASK 0xc00 +#define MP_DRAM_CNTL_RDRET_NACK__nack_5__SHIFT 0xa +#define MP_DRAM_CNTL_RDRET_NACK__nack_6_MASK 0x3000 +#define MP_DRAM_CNTL_RDRET_NACK__nack_6__SHIFT 0xc +#define MP_DRAM_CNTL_RDRET_NACK__nack_7_MASK 0xc000 +#define MP_DRAM_CNTL_RDRET_NACK__nack_7__SHIFT 0xe +#define MP_DRAM_CNTL_RDRET_NACK__reserved_MASK 0xffff0000 +#define MP_DRAM_CNTL_RDRET_NACK__reserved__SHIFT 0x10 +#define MP_DRAM_CNTL_RDRET_DATA_0__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_0__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_1__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_1__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_2__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_2__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_3__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_3__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_4__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_4__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_5__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_5__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_6__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_6__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_7__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_7__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_8__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_8__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_9__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_9__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_10__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_10__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_11__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_11__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_12__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_12__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_13__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_13__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_14__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_14__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_15__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_15__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_16__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_16__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_17__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_17__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_18__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_18__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_19__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_19__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_20__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_20__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_21__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_21__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_22__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_22__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_23__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_23__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_24__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_24__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_25__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_25__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_26__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_26__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_27__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_27__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_28__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_28__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_29__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_29__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_30__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_30__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_31__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_31__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_32__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_32__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_33__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_33__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_34__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_34__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_35__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_35__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_36__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_36__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_37__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_37__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_38__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_38__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_39__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_39__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_40__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_40__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_41__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_41__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_42__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_42__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_43__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_43__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_44__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_44__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_45__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_45__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_46__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_46__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_47__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_47__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_48__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_48__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_49__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_49__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_50__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_50__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_51__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_51__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_52__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_52__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_53__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_53__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_54__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_54__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_55__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_55__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_56__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_56__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_57__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_57__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_58__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_58__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_59__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_59__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_60__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_60__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_61__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_61__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_62__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_62__DATA__SHIFT 0x0 +#define MP_DRAM_CNTL_RDRET_DATA_63__DATA_MASK 0xffffffff +#define MP_DRAM_CNTL_RDRET_DATA_63__DATA__SHIFT 0x0 +#define MP_IOC_CTRL__IOC_mst_send_MASK 0x1 +#define MP_IOC_CTRL__IOC_mst_send__SHIFT 0x0 +#define MP_IOC_CTRL__IOC_mst_stop_MASK 0x2 +#define MP_IOC_CTRL__IOC_mst_stop__SHIFT 0x1 +#define MP_IOC_CTRL__IOC_mst_force_active_MASK 0x4 +#define MP_IOC_CTRL__IOC_mst_force_active__SHIFT 0x2 +#define MP_IOC_CTRL__IOC_mst_rdValid_MASK 0x8 +#define MP_IOC_CTRL__IOC_mst_rdValid__SHIFT 0x3 +#define MP_IOC_CTRL__IOC_mst_busy_MASK 0x10 +#define MP_IOC_CTRL__IOC_mst_busy__SHIFT 0x4 +#define MP_IOC_CTRL__IOC_mst_disabled_MASK 0x20 +#define MP_IOC_CTRL__IOC_mst_disabled__SHIFT 0x5 +#define MP_IOC_CTRL__IOC_mst_debug_rst_MASK 0x40 +#define MP_IOC_CTRL__IOC_mst_debug_rst__SHIFT 0x6 +#define MP_IOC_CTRL__IOC_mst_stop_ack_MASK 0x80 +#define MP_IOC_CTRL__IOC_mst_stop_ack__SHIFT 0x7 +#define MP_IOC_CTRL__IOC_mst_rderr_MASK 0x300 +#define MP_IOC_CTRL__IOC_mst_rderr__SHIFT 0x8 +#define MP_IOC_RDDATA__IOC_mst_rdData_MASK 0xffffffff +#define MP_IOC_RDDATA__IOC_mst_rdData__SHIFT 0x0 +#define MP_IOC_PHASE1__BiuCqfC_AwqReqCommit_MASK 0x2 +#define MP_IOC_PHASE1__BiuCqfC_AwqReqCommit__SHIFT 0x1 +#define MP_IOC_PHASE1__BiuCqfC_AltReqRdCmd_MASK 0x4 +#define MP_IOC_PHASE1__BiuCqfC_AltReqRdCmd__SHIFT 0x2 +#define MP_IOC_PHASE1__BiuCqfC_AltReqAddrLo_MASK 0xfffffff8 +#define MP_IOC_PHASE1__BiuCqfC_AltReqAddrLo__SHIFT 0x3 +#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrMid_MASK 0xff +#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrMid__SHIFT 0x0 +#define MP_IOC_PHASE2__BiuCqfC_AltReqMask_MASK 0xff00 +#define MP_IOC_PHASE2__BiuCqfC_AltReqMask__SHIFT 0x8 +#define MP_IOC_PHASE2__BiuCqfC_AltReqSize_MASK 0x30000 +#define MP_IOC_PHASE2__BiuCqfC_AltReqSize__SHIFT 0x10 +#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrHi_MASK 0xff000000 +#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrHi__SHIFT 0x18 +#define MP_IOC_PHASE3__BiuDbfC_C2aDataOut_MASK 0xffffffff +#define MP_IOC_PHASE3__BiuDbfC_C2aDataOut__SHIFT 0x0 +#define MP_IOC_READ_0__data_MASK 0xffffffff +#define MP_IOC_READ_0__data__SHIFT 0x0 +#define MP_IOC_READ_1__data_MASK 0xffffffff +#define MP_IOC_READ_1__data__SHIFT 0x0 +#define MP_IOC_READ_2__data_MASK 0xffffffff +#define MP_IOC_READ_2__data__SHIFT 0x0 +#define MP_IOC_READ_3__data_MASK 0xffffffff +#define MP_IOC_READ_3__data__SHIFT 0x0 +#define MP_IOC_READ_4__data_MASK 0xffffffff +#define MP_IOC_READ_4__data__SHIFT 0x0 +#define MP_IOC_READ_5__data_MASK 0xffffffff +#define MP_IOC_READ_5__data__SHIFT 0x0 +#define MP_IOC_READ_6__data_MASK 0xffffffff +#define MP_IOC_READ_6__data__SHIFT 0x0 +#define MP_IOC_READ_7__data_MASK 0xffffffff +#define MP_IOC_READ_7__data__SHIFT 0x0 +#define MP_IOC_READ_8__data_MASK 0xffffffff +#define MP_IOC_READ_8__data__SHIFT 0x0 +#define MP_IOC_READ_9__data_MASK 0xffffffff +#define MP_IOC_READ_9__data__SHIFT 0x0 +#define MP_IOC_READ_10__data_MASK 0xffffffff +#define MP_IOC_READ_10__data__SHIFT 0x0 +#define MP_IOC_READ_11__data_MASK 0xffffffff +#define MP_IOC_READ_11__data__SHIFT 0x0 +#define MP_IOC_READ_12__data_MASK 0xffffffff +#define MP_IOC_READ_12__data__SHIFT 0x0 +#define MP_IOC_READ_13__data_MASK 0xffffffff +#define MP_IOC_READ_13__data__SHIFT 0x0 +#define MP_IOC_READ_14__data_MASK 0xffffffff +#define MP_IOC_READ_14__data__SHIFT 0x0 +#define MP_IOC_READ_15__data_MASK 0xffffffff +#define MP_IOC_READ_15__data__SHIFT 0x0 +#define MP_IOC_WRITE_0__data_MASK 0xffffffff +#define MP_IOC_WRITE_0__data__SHIFT 0x0 +#define MP_IOC_WRITE_1__data_MASK 0xffffffff +#define MP_IOC_WRITE_1__data__SHIFT 0x0 +#define MP_IOC_WRITE_2__data_MASK 0xffffffff +#define MP_IOC_WRITE_2__data__SHIFT 0x0 +#define MP_IOC_WRITE_3__data_MASK 0xffffffff +#define MP_IOC_WRITE_3__data__SHIFT 0x0 +#define MP_IOC_WRITE_4__data_MASK 0xffffffff +#define MP_IOC_WRITE_4__data__SHIFT 0x0 +#define MP_IOC_WRITE_5__data_MASK 0xffffffff +#define MP_IOC_WRITE_5__data__SHIFT 0x0 +#define MP_IOC_WRITE_6__data_MASK 0xffffffff +#define MP_IOC_WRITE_6__data__SHIFT 0x0 +#define MP_IOC_WRITE_7__data_MASK 0xffffffff +#define MP_IOC_WRITE_7__data__SHIFT 0x0 +#define MP_IOC_WRITE_8__data_MASK 0xffffffff +#define MP_IOC_WRITE_8__data__SHIFT 0x0 +#define MP_IOC_WRITE_9__data_MASK 0xffffffff +#define MP_IOC_WRITE_9__data__SHIFT 0x0 +#define MP_IOC_WRITE_10__data_MASK 0xffffffff +#define MP_IOC_WRITE_10__data__SHIFT 0x0 +#define MP_IOC_WRITE_11__data_MASK 0xffffffff +#define MP_IOC_WRITE_11__data__SHIFT 0x0 +#define MP_IOC_WRITE_12__data_MASK 0xffffffff +#define MP_IOC_WRITE_12__data__SHIFT 0x0 +#define MP_IOC_WRITE_13__data_MASK 0xffffffff +#define MP_IOC_WRITE_13__data__SHIFT 0x0 +#define MP_IOC_WRITE_14__data_MASK 0xffffffff +#define MP_IOC_WRITE_14__data__SHIFT 0x0 +#define MP_IOC_WRITE_15__data_MASK 0xffffffff +#define MP_IOC_WRITE_15__data__SHIFT 0x0 +#define MP_INTERRUPT_CONTROL__MAX_CREDIT_VALUE_MASK 0x1f +#define MP_INTERRUPT_CONTROL__MAX_CREDIT_VALUE__SHIFT 0x0 +#define MP_INTERRUPT_CONTROL__MP0_SW_TRIG_MASK_MASK 0x20 +#define MP_INTERRUPT_CONTROL__MP0_SW_TRIG_MASK__SHIFT 0x5 +#define MP_INTERRUPT_CONTROL__MP0_SW_INT_ACK_MASK 0x40 +#define MP_INTERRUPT_CONTROL__MP0_SW_INT_ACK__SHIFT 0x6 +#define MP_INTERRUPT_CONTROL__MP1_SW_TRIG_MASK_MASK 0x80 +#define MP_INTERRUPT_CONTROL__MP1_SW_TRIG_MASK__SHIFT 0x7 +#define MP_INTERRUPT_CONTROL__MP1_SW_INT_ACK_MASK 0x100 +#define MP_INTERRUPT_CONTROL__MP1_SW_INT_ACK__SHIFT 0x8 +#define MP0_SW_INT__VALID_MASK 0x1 +#define MP0_SW_INT__VALID__SHIFT 0x0 +#define MP0_SW_INT__INT_ID_MASK 0x1fe +#define MP0_SW_INT__INT_ID__SHIFT 0x1 +#define MP0_SW_INT_CTXID__CTXID_MASK 0xfffffff +#define MP0_SW_INT_CTXID__CTXID__SHIFT 0x0 +#define MP1_SW_INT__VALID_MASK 0x1 +#define MP1_SW_INT__VALID__SHIFT 0x0 +#define MP1_SW_INT__INT_ID_MASK 0x1fe +#define MP1_SW_INT__INT_ID__SHIFT 0x1 +#define MP1_SW_INT_CTXID__CTXID_MASK 0xfffffff +#define MP1_SW_INT_CTXID__CTXID__SHIFT 0x0 +#define DISP_TIMER_ID__DISP_T0_INT_ID_MASK 0xff +#define DISP_TIMER_ID__DISP_T0_INT_ID__SHIFT 0x0 +#define DISP_TIMER_ID__DISP_T1_INT_ID_MASK 0xff00 +#define DISP_TIMER_ID__DISP_T1_INT_ID__SHIFT 0x8 +#define PWRHW_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff +#define PWRHW_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 +#define PWRHW_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff +#define PWRHW_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 +#define CURRENT_STATE_CPU0__CURRENT_PSTATE_ID_MASK 0x7 +#define CURRENT_STATE_CPU0__CURRENT_PSTATE_ID__SHIFT 0x0 +#define CURRENT_STATE_CPU0__CURRENT_DID_MASK 0x38 +#define CURRENT_STATE_CPU0__CURRENT_DID__SHIFT 0x3 +#define CURRENT_STATE_CPU0__CURRENT_FID_MASK 0xfc0 +#define CURRENT_STATE_CPU0__CURRENT_FID__SHIFT 0x6 +#define CURRENT_STATE_CPU0__CPU_COF_MASK 0xfff000 +#define CURRENT_STATE_CPU0__CPU_COF__SHIFT 0xc +#define CURRENT_STATE_CPU0__CPU_COF_IND_PROG_MASK 0x7f000000 +#define CURRENT_STATE_CPU0__CPU_COF_IND_PROG__SHIFT 0x18 +#define CURRENT_STATE_CPU1__CURRENT_PSTATE_ID_MASK 0x7 +#define CURRENT_STATE_CPU1__CURRENT_PSTATE_ID__SHIFT 0x0 +#define CURRENT_STATE_CPU1__CURRENT_DID_MASK 0x38 +#define CURRENT_STATE_CPU1__CURRENT_DID__SHIFT 0x3 +#define CURRENT_STATE_CPU1__CURRENT_FID_MASK 0xfc0 +#define CURRENT_STATE_CPU1__CURRENT_FID__SHIFT 0x6 +#define CURRENT_STATE_CPU1__CPU_COF_MASK 0xfff000 +#define CURRENT_STATE_CPU1__CPU_COF__SHIFT 0xc +#define CURRENT_STATE_CPU1__CPU_COF_IND_PROG_MASK 0x7f000000 +#define CURRENT_STATE_CPU1__CPU_COF_IND_PROG__SHIFT 0x18 +#define CPU_REDUN_DONE0__CPU_REDUN_DONE_MASK 0x1 +#define CPU_REDUN_DONE0__CPU_REDUN_DONE__SHIFT 0x0 +#define CPU_REDUN_DONE1__CPU_REDUN_DONE_MASK 0x1 +#define CPU_REDUN_DONE1__CPU_REDUN_DONE__SHIFT 0x0 +#define CURRENT_VID_CPU0__CURRENT_VID_MASK 0xff +#define CURRENT_VID_CPU0__CURRENT_VID__SHIFT 0x0 +#define CURRENT_VID_CPU1__CURRENT_VID_MASK 0xff +#define CURRENT_VID_CPU1__CURRENT_VID__SHIFT 0x0 +#define UNBPM_PWRMGT_ACK__REQUESTOR_CODE_MASK 0x1f +#define UNBPM_PWRMGT_ACK__REQUESTOR_CODE__SHIFT 0x0 +#define UNBPM_PWRMGT_ACK__REQUEST_ACK_MASK 0x100 +#define UNBPM_PWRMGT_ACK__REQUEST_ACK__SHIFT 0x8 +#define UNBPM_PWRMGT_ACK__REQUEST_NACK_MASK 0x10000 +#define UNBPM_PWRMGT_ACK__REQUEST_NACK__SHIFT 0x10 +#define UNBPM_PWRMGT_ACK__ERROR_CODE_MASK 0xff000000 +#define UNBPM_PWRMGT_ACK__ERROR_CODE__SHIFT 0x18 +#define CURRENT_FREQ_STATE_NB__CURRENT_FID_MASK 0xff +#define CURRENT_FREQ_STATE_NB__CURRENT_FID__SHIFT 0x0 +#define CURRENT_FREQ_STATE_NB__CURRENT_DID_MASK 0xff00 +#define CURRENT_FREQ_STATE_NB__CURRENT_DID__SHIFT 0x8 +#define CURRENT_FREQ_STATE_NB__NB_LOW_POWER_MASK 0xff0000 +#define CURRENT_FREQ_STATE_NB__NB_LOW_POWER__SHIFT 0x10 +#define CURRENT_FREQ_STATE_NB__NB_STUTTER_MODE_MASK 0xff000000 +#define CURRENT_FREQ_STATE_NB__NB_STUTTER_MODE__SHIFT 0x18 +#define CURRENT_PSTATE_NB__CURRENT_PSTATE_ID_MASK 0xff +#define CURRENT_PSTATE_NB__CURRENT_PSTATE_ID__SHIFT 0x0 +#define CURRENT_PSTATE_NB__CURRENT_PSTATE_LO_MASK 0x100 +#define CURRENT_PSTATE_NB__CURRENT_PSTATE_LO__SHIFT 0x8 +#define CURRENT_PSTATE_NB__CURRENT_MEM_PSTATE_ID_MASK 0x200 +#define CURRENT_PSTATE_NB__CURRENT_MEM_PSTATE_ID__SHIFT 0x9 +#define UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR_MASK 0xffffffff +#define UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR__SHIFT 0x0 +#define UNBPM_NBPWRMGT_CMD__TARGET_BLOCK_MASK 0x3 +#define UNBPM_NBPWRMGT_CMD__TARGET_BLOCK__SHIFT 0x0 +#define UNBPM_NBPWRMGT_CMD__TARGET_CMD_MASK 0x100 +#define UNBPM_NBPWRMGT_CMD__TARGET_CMD__SHIFT 0x8 +#define UNBPM_NBPWRMGT_CMD__DCT_SR_MAP_MASK 0xff0000 +#define UNBPM_NBPWRMGT_CMD__DCT_SR_MAP__SHIFT 0x10 +#define UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK_MASK 0x1000000 +#define UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK__SHIFT 0x18 +#define UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS_MASK 0x2000000 +#define UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS__SHIFT 0x19 +#define UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER_MASK 0x4000000 +#define UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER__SHIFT 0x1a +#define UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE_MASK 0x8000000 +#define UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE__SHIFT 0x1b +#define UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT_MASK 0x2 +#define UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT__SHIFT 0x1 +#define DDR0_FUSE_SSB_XFER__START_STATUS_XFER_MASK 0x1 +#define DDR0_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT 0x0 +#define DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR_MASK 0x7ff +#define DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR__SHIFT 0x0 +#define DDR1_FUSE_SSB_XFER__START_STATUS_XFER_MASK 0x1 +#define DDR1_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT 0x0 +#define DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR_MASK 0x7ff +#define DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR__SHIFT 0x0 +#define UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK_MASK 0x1 +#define UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK__SHIFT 0x0 +#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER0_MASK 0x1 +#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER0__SHIFT 0x0 +#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER1_MASK 0x2 +#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER1__SHIFT 0x1 +#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER0_MASK 0x4 +#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER0__SHIFT 0x2 +#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER1_MASK 0x8 +#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER1__SHIFT 0x3 +#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN0_MASK 0x10 +#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN0__SHIFT 0x4 +#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN1_MASK 0x20 +#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN1__SHIFT 0x5 +#define MISC_SMU_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff +#define MISC_SMU_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0 +#define MISC_GNB_PWRMGT_CFG1__TIMER_EN_MASK 0x1 +#define MISC_GNB_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0 +#define MISC_GNB_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe +#define MISC_GNB_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1 +#define MISC_GNB_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000 +#define MISC_GNB_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11 +#define MISC_SMU_PWRMGT_CFG1__TIMER_EN_MASK 0x1 +#define MISC_SMU_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0 +#define MISC_SMU_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe +#define MISC_SMU_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1 +#define MISC_SMU_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000 +#define MISC_SMU_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11 +#define MISC_GNB_PWRMGT_DATA__GN_ON_INB_WAKE_MASK 0x1 +#define MISC_GNB_PWRMGT_DATA__GN_ON_INB_WAKE__SHIFT 0x0 +#define MISC_GNB_PWRMGT_DATA__GN_ALLOW_NB_PSTATES_MASK 0x2 +#define MISC_GNB_PWRMGT_DATA__GN_ALLOW_NB_PSTATES__SHIFT 0x1 +#define MISC_GNB_PWRMGT_DATA__GN_FLUSH_REQ_TOGGLE_MASK 0x4 +#define MISC_GNB_PWRMGT_DATA__GN_FLUSH_REQ_TOGGLE__SHIFT 0x2 +#define MISC_GNB_PWRMGT_DATA__GN_CROSS_TRIGGER_MASK 0x78 +#define MISC_GNB_PWRMGT_DATA__GN_CROSS_TRIGGER__SHIFT 0x3 +#define MISC_GNB_PWRMGT_DATA__GN_STOP_CLOCKS_MASK 0x80 +#define MISC_GNB_PWRMGT_DATA__GN_STOP_CLOCKS__SHIFT 0x7 +#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH0LINK_WAKE_MASK 0x100 +#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH0LINK_WAKE__SHIFT 0x8 +#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH1LINK_WAKE_MASK 0x200 +#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH1LINK_WAKE__SHIFT 0x9 +#define GN_GNB_SLOW__GN_GNB_SLOW_DATA_MASK 0x1 +#define GN_GNB_SLOW__GN_GNB_SLOW_DATA__SHIFT 0x0 +#define GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA_MASK 0x1 +#define GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA__SHIFT 0x0 +#define MISC_SMU_PWRMGT_DATA__NB_NBPS_MASK 0x1 +#define MISC_SMU_PWRMGT_DATA__NB_NBPS__SHIFT 0x0 +#define MISC_SMU_PWRMGT_DATA__NB_MEMPS_MASK 0x2 +#define MISC_SMU_PWRMGT_DATA__NB_MEMPS__SHIFT 0x1 +#define NB_COF__NB_COF_MASK 0xffff +#define NB_COF__NB_COF__SHIFT 0x0 +#define UNBPM_CK_IRESET__CK_IRESET_LOCAL_MASK 0x1 +#define UNBPM_CK_IRESET__CK_IRESET_LOCAL__SHIFT 0x0 +#define CURRENT_VID_NB__CURRENT_VID_MASK 0xff +#define CURRENT_VID_NB__CURRENT_VID__SHIFT 0x0 +#define SPR_FUSE_PSTATEPWR1__PwrValue0_MASK 0xff +#define SPR_FUSE_PSTATEPWR1__PwrValue0__SHIFT 0x0 +#define SPR_FUSE_PSTATEPWR1__PwrValue1_MASK 0xff00 +#define SPR_FUSE_PSTATEPWR1__PwrValue1__SHIFT 0x8 +#define SPR_FUSE_PSTATEPWR1__PwrValue2_MASK 0xff0000 +#define SPR_FUSE_PSTATEPWR1__PwrValue2__SHIFT 0x10 +#define SPR_FUSE_PSTATEPWR1__PwrValue3_MASK 0xff000000 +#define SPR_FUSE_PSTATEPWR1__PwrValue3__SHIFT 0x18 +#define SPR_FUSE_PSTATEPWR2__PwrValue4_MASK 0xff +#define SPR_FUSE_PSTATEPWR2__PwrValue4__SHIFT 0x0 +#define SPR_FUSE_PSTATEPWR2__PwrDiv0_MASK 0x300 +#define SPR_FUSE_PSTATEPWR2__PwrDiv0__SHIFT 0x8 +#define SPR_FUSE_PSTATEPWR2__PwrDiv1_MASK 0xc00 +#define SPR_FUSE_PSTATEPWR2__PwrDiv1__SHIFT 0xa +#define SPR_FUSE_PSTATEPWR2__PwrDiv2_MASK 0x3000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv2__SHIFT 0xc +#define SPR_FUSE_PSTATEPWR2__PwrDiv3_MASK 0xc000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv3__SHIFT 0xe +#define SPR_FUSE_PSTATEPWR2__PwrDiv4_MASK 0x30000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv4__SHIFT 0x10 +#define SPR_FUSE_PSTATEPWR2__PwrDiv5_MASK 0xc0000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv5__SHIFT 0x12 +#define SPR_FUSE_PSTATEPWR2__PwrDiv6_MASK 0x300000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv6__SHIFT 0x14 +#define SPR_FUSE_PSTATEPWR2__PwrDiv7_MASK 0xc00000 +#define SPR_FUSE_PSTATEPWR2__PwrDiv7__SHIFT 0x16 +#define SPR_FUSE_PSTATEPWR2__Reserved_MASK 0xff000000 +#define SPR_FUSE_PSTATEPWR2__Reserved__SHIFT 0x18 +#define SPR_FUSE_PSTATEPWR3__PwrValue5_MASK 0xff +#define SPR_FUSE_PSTATEPWR3__PwrValue5__SHIFT 0x0 +#define SPR_FUSE_PSTATEPWR3__PwrValue6_MASK 0xff00 +#define SPR_FUSE_PSTATEPWR3__PwrValue6__SHIFT 0x8 +#define SPR_FUSE_PSTATEPWR3__PwrValue7_MASK 0xff0000 +#define SPR_FUSE_PSTATEPWR3__PwrValue7__SHIFT 0x10 +#define SPR_FUSE_PSTATEPWR3__Reserved_MASK 0xff000000 +#define SPR_FUSE_PSTATEPWR3__Reserved__SHIFT 0x18 +#define SPR_FUSE_THERMAL_SCRATCH__ThermalScratch_MASK 0xffffffff +#define SPR_FUSE_THERMAL_SCRATCH__ThermalScratch__SHIFT 0x0 +#define SPR_PRODUCT_INFO0__BrandId_MASK 0xffff +#define SPR_PRODUCT_INFO0__BrandId__SHIFT 0x0 +#define SPR_PRODUCT_INFO0__Reserved0_MASK 0x70000 +#define SPR_PRODUCT_INFO0__Reserved0__SHIFT 0x10 +#define SPR_PRODUCT_INFO0__SerialNumRdDis_MASK 0x80000 +#define SPR_PRODUCT_INFO0__SerialNumRdDis__SHIFT 0x13 +#define SPR_PRODUCT_INFO0__Reserved1_MASK 0xfff00000 +#define SPR_PRODUCT_INFO0__Reserved1__SHIFT 0x14 +#define SPR_SERIALNUM_REG1__SPR_SERIALNUM_REG1_MASK 0xffffffff +#define SPR_SERIALNUM_REG1__SPR_SERIALNUM_REG1__SHIFT 0x0 +#define SPR_SERIALNUM_REG2__SPR_SERIALNUM_REG2_MASK 0xffffffff +#define SPR_SERIALNUM_REG2__SPR_SERIALNUM_REG2__SHIFT 0x0 +#define SPR_PRODUCT_INFO1__DiDtMode_MASK 0x1 +#define SPR_PRODUCT_INFO1__DiDtMode__SHIFT 0x0 +#define SPR_PRODUCT_INFO1__DiDtCfg0_MASK 0x3e +#define SPR_PRODUCT_INFO1__DiDtCfg0__SHIFT 0x1 +#define SPR_PRODUCT_INFO1__DiDtCfg1_MASK 0x3fc0 +#define SPR_PRODUCT_INFO1__DiDtCfg1__SHIFT 0x6 +#define SPR_PRODUCT_INFO1__DiDtCfg2_MASK 0xc000 +#define SPR_PRODUCT_INFO1__DiDtCfg2__SHIFT 0xe +#define SPR_PRODUCT_INFO1__DiDtCfg3_MASK 0x10000 +#define SPR_PRODUCT_INFO1__DiDtCfg3__SHIFT 0x10 +#define SPR_PRODUCT_INFO1__DiDtCfg4_MASK 0x1e0000 +#define SPR_PRODUCT_INFO1__DiDtCfg4__SHIFT 0x11 +#define SPR_PRODUCT_INFO1__Reserved_MASK 0xffe00000 +#define SPR_PRODUCT_INFO1__Reserved__SHIFT 0x15 +#define SPR_EXT_PRODUCT_INFO__Reserved_MASK 0xffffffff +#define SPR_EXT_PRODUCT_INFO__Reserved__SHIFT 0x0 +#define SPR_MSIDFUSE__MSID_MASK 0xffffff +#define SPR_MSIDFUSE__MSID__SHIFT 0x0 +#define SPR_MSIDFUSE__Reserved_MASK 0xff000000 +#define SPR_MSIDFUSE__Reserved__SHIFT 0x18 +#define SPR_LINK_PRODUCT_INFO__Reserved_MASK 0xffffffff +#define SPR_LINK_PRODUCT_INFO__Reserved__SHIFT 0x0 +#define SPR_BRAND_NAME_ADDR__Index_MASK 0xf +#define SPR_BRAND_NAME_ADDR__Index__SHIFT 0x0 +#define SPR_BRAND_NAME_ADDR__Reserved_MASK 0xfffffff0 +#define SPR_BRAND_NAME_ADDR__Reserved__SHIFT 0x4 +#define SPR_BRAND_NAME_DATA__DATA_MASK 0xffffffff +#define SPR_BRAND_NAME_DATA__DATA__SHIFT 0x0 +#define SPR_COMBO_PHY_PRODUCT_INFO__SPR_COMBO_PHY_PRODUCT_INFO_MASK 0xffffffff +#define SPR_COMBO_PHY_PRODUCT_INFO__SPR_COMBO_PHY_PRODUCT_INFO__SHIFT 0x0 +#define MISC_GNB_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff +#define MISC_GNB_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0 +#define UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE_MASK 0x1 +#define UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE__SHIFT 0x0 +#define UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE_MASK 0x1 +#define UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE__SHIFT 0x0 +#define UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE_MASK 0x2 +#define UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE__SHIFT 0x1 +#define UNBPM_VOLTAGE_CNTL__VOLTAGE_EN_MASK 0x1 +#define UNBPM_VOLTAGE_CNTL__VOLTAGE_EN__SHIFT 0x0 +#define UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL_MASK 0x1fe +#define UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL__SHIFT 0x1 +#define UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS_MASK 0x1 +#define UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS__SHIFT 0x0 +#define UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL_MASK 0x1fe +#define UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL__SHIFT 0x1 +#define NUM_BOOST_STATES__NUM_BOOST_STATES_MASK 0x7 +#define NUM_BOOST_STATES__NUM_BOOST_STATES__SHIFT 0x0 +#define WARM_RESET_NB_CONTROL__WARM_RESET_CPU_VID_MASK 0xff +#define WARM_RESET_NB_CONTROL__WARM_RESET_CPU_VID__SHIFT 0x0 +#define WARM_RESET_NB_CONTROL__NB_DISABLE_CORE_MASK 0xff00 +#define WARM_RESET_NB_CONTROL__NB_DISABLE_CORE__SHIFT 0x8 +#define ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND_MASK 0x1 +#define ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND__SHIFT 0x0 +#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0_MASK 0x2 +#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0__SHIFT 0x1 +#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1_MASK 0x4 +#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1__SHIFT 0x2 +#define SPR_PROGRAMMABLE_CTRL__PllRegUpTime_MASK 0x3 +#define SPR_PROGRAMMABLE_CTRL__PllRegUpTime__SHIFT 0x0 +#define SPR_PROGRAMMABLE_CTRL__PllVddOutUpTime_MASK 0xc +#define SPR_PROGRAMMABLE_CTRL__PllVddOutUpTime__SHIFT 0x2 +#define SPR_PROGRAMMABLE_CTRL__ResonanceTime_MASK 0x30 +#define SPR_PROGRAMMABLE_CTRL__ResonanceTime__SHIFT 0x4 +#define SPR_PROGRAMMABLE_CTRL__C6PLLPwrDnReg_MASK 0x40 +#define SPR_PROGRAMMABLE_CTRL__C6PLLPwrDnReg__SHIFT 0x6 +#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnVCO_MASK 0x80 +#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnVCO__SHIFT 0x7 +#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnReg_MASK 0x100 +#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnReg__SHIFT 0x8 +#define SPR_PROGRAMMABLE_CTRL__NbPLLPwrDnReg_MASK 0x200 +#define SPR_PROGRAMMABLE_CTRL__NbPLLPwrDnReg__SHIFT 0x9 +#define SPR_PROGRAMMABLE_CTRL__SOIWait_MASK 0x3c00 +#define SPR_PROGRAMMABLE_CTRL__SOIWait__SHIFT 0xa +#define PHN_FUSERX_MISC_FUSES__Spare_MASK 0xff +#define PHN_FUSERX_MISC_FUSES__Spare__SHIFT 0x0 +#define PHN_FUSERX_MISC_FUSES__OverClockRefClkDis_MASK 0x100 +#define PHN_FUSERX_MISC_FUSES__OverClockRefClkDis__SHIFT 0x8 +#define PHN_FUSERX_MISC_FUSES__MemPstate_MASK 0x1e00 +#define PHN_FUSERX_MISC_FUSES__MemPstate__SHIFT 0x9 +#define PHN_FUSERX_MISC_FUSES__NbPstateHi_MASK 0x6000 +#define PHN_FUSERX_MISC_FUSES__NbPstateHi__SHIFT 0xd +#define PHN_FUSERX_MISC_FUSES__NbPstateLo_MASK 0x18000 +#define PHN_FUSERX_MISC_FUSES__NbPstateLo__SHIFT 0xf +#define PHN_FUSERX_MISC_FUSES__ScanCLK400MHz_MASK 0x20000 +#define PHN_FUSERX_MISC_FUSES__ScanCLK400MHz__SHIFT 0x11 +#define PHN_FUSERX_MISC_FUSES__CoreDis_MASK 0x3c0000 +#define PHN_FUSERX_MISC_FUSES__CoreDis__SHIFT 0x12 +#define PHN_FUSERX_MISC_FUSES__PHN_FusesValid_MASK 0x80000000 +#define PHN_FUSERX_MISC_FUSES__PHN_FusesValid__SHIFT 0x1f +#define UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS_MASK 0x1 +#define UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS__SHIFT 0x0 +#define CSTATE_ACTIVE_SAMPLER__SAMPLE_TIME_MASK 0x1f +#define CSTATE_ACTIVE_SAMPLER__SAMPLE_TIME__SHIFT 0x0 +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS_MASK 0xf +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS__SHIFT 0x0 +#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH_MASK 0x10 +#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH__SHIFT 0x4 +#define UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN_MASK 0x20 +#define UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN__SHIFT 0x5 +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE_MASK 0x100 +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE__SHIFT 0x8 +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY_MASK 0x200 +#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY__SHIFT 0x9 +#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT_MASK 0x3c00 +#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT__SHIFT 0xa +#define UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS_MASK 0xff0000 +#define UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS__SHIFT 0x10 +#define UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD_MASK 0xffffffff +#define UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD__SHIFT 0x0 +#define UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT_MASK 0xffff +#define UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT__SHIFT 0x0 +#define UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT_MASK 0xffff0000 +#define UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT__SHIFT 0x10 +#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN_MASK 0x1 +#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN__SHIFT 0x0 +#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM_MASK 0x1fe +#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM__SHIFT 0x1 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb_MASK 0x1 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb__SHIFT 0x0 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct_MASK 0x6 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct__SHIFT 0x1 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu_MASK 0x38 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu__SHIFT 0x3 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog_MASK 0x40 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog__SHIFT 0x6 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo_MASK 0x80 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo__SHIFT 0x7 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate_MASK 0x100 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate__SHIFT 0x8 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid_MASK 0x7e00 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid__SHIFT 0x9 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid_MASK 0x38000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid__SHIFT 0xf +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate_MASK 0x40000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate__SHIFT 0x12 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId_MASK 0x380000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId__SHIFT 0x13 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn_MASK 0x400000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn__SHIFT 0x16 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn_MASK 0x800000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn__SHIFT 0x17 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding_MASK 0x7000000 +#define UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding__SHIFT 0x18 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid_MASK 0x1 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid__SHIFT 0x0 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane_MASK 0x6 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane__SHIFT 0x1 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp_MASK 0x8 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp__SHIFT 0x3 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid_MASK 0xff0 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid__SHIFT 0x4 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime_MASK 0x7000 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime__SHIFT 0xc +#define UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy_MASK 0x10000 +#define UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy__SHIFT 0x10 +#define UNBPM_SCRATCH_0__DATA_MASK 0xffffffff +#define UNBPM_SCRATCH_0__DATA__SHIFT 0x0 +#define UNBPM_SCRATCH_1__DATA_MASK 0xffffffff +#define UNBPM_SCRATCH_1__DATA__SHIFT 0x0 +#define POWERON_CPU_0__POWERON_MASK 0x1 +#define POWERON_CPU_0__POWERON__SHIFT 0x0 +#define POWERREADY_CPU_0__POWERREADY_MASK 0x1 +#define POWERREADY_CPU_0__POWERREADY__SHIFT 0x0 +#define PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK_MASK 0x1 +#define PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK__SHIFT 0x0 +#define RCC3ON_CPU_0__CK_RCC3ON_MASK 0x1 +#define RCC3ON_CPU_0__CK_RCC3ON__SHIFT 0x0 +#define RCC3ON_CPU_0__RCC3_PSM_EN_MASK 0x2 +#define RCC3ON_CPU_0__RCC3_PSM_EN__SHIFT 0x1 +#define RCC3ON_CPU_0__RCC3_PSM_CLK_DIV_MASK 0xc +#define RCC3ON_CPU_0__RCC3_PSM_CLK_DIV__SHIFT 0x2 +#define RCC3ON_CPU_0__RCC3_AVG_EN_MASK 0x10 +#define RCC3ON_CPU_0__RCC3_AVG_EN__SHIFT 0x4 +#define RCC3ON_CPU_0__RCC3_AVG_DIV_MASK 0x7e0 +#define RCC3ON_CPU_0__RCC3_AVG_DIV__SHIFT 0x5 +#define RCC3ON_CPU_0__RCC3_DIDT_TIMER_MASK 0x1f800 +#define RCC3ON_CPU_0__RCC3_DIDT_TIMER__SHIFT 0xb +#define RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0_MASK 0xfffe0000 +#define RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0__SHIFT 0x11 +#define RCC3EXITDONE_CPU_0__RCC3EXITDONE_MASK 0x1 +#define RCC3EXITDONE_CPU_0__RCC3EXITDONE__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_0__START_STATUS_XFER_MASK 0x1 +#define CORE_FUNC_LATE_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_FUNC_LAST_ADDR_MASK 0x7ff +#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_FUNC_LAST_ADDR__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_LATE_LAST_ADDR_MASK 0x7ff0000 +#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_LATE_LAST_ADDR__SHIFT 0x10 +#define CORE_REDUN_SSB_XFER_0__START_STATUS_XFER_MASK 0x1 +#define CORE_REDUN_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0 +#define CORE_REDUN_SSB_XFER_CFG_0__FUSE_REDUN_LAST_ADDR_MASK 0x7ff +#define CORE_REDUN_SSB_XFER_CFG_0__FUSE_REDUN_LAST_ADDR__SHIFT 0x0 +#define CORE_APM_SSB_XFER_0__START_STATUS_XFER_MASK 0x1 +#define CORE_APM_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0 +#define CORE_APM_SSB_XFER_CFG_0__FUSE_APM_LAST_ADDR_MASK 0x7ff +#define CORE_APM_SSB_XFER_CFG_0__FUSE_APM_LAST_ADDR__SHIFT 0x0 +#define COREPM_PWRCTRL_MISC_0__PWRGATEMASTERDIS_MASK 0x1 +#define COREPM_PWRCTRL_MISC_0__PWRGATEMASTERDIS__SHIFT 0x0 +#define LDOIVRON_CPU_0__CK_LDOIVRON_MASK 0x1 +#define LDOIVRON_CPU_0__CK_LDOIVRON__SHIFT 0x0 +#define LDOIVREXITDONE_CPU_0__LDOIVREXITDONE_MASK 0x1 +#define LDOIVREXITDONE_CPU_0__LDOIVREXITDONE__SHIFT 0x0 +#define RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF_MASK 0x3fff +#define RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF__SHIFT 0x0 +#define IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF_MASK 0x3fff +#define IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF__SHIFT 0x0 +#define CK_JTCOOLRESET_LATCHED_CPU_0__CK_JTCOOLRESET_LATCHED_MASK 0x1 +#define CK_JTCOOLRESET_LATCHED_CPU_0__CK_JTCOOLRESET_LATCHED__SHIFT 0x0 +#define CK_DISABLECORE_CPU_0__CK_DISABLECORE_MASK 0x1 +#define CK_DISABLECORE_CPU_0__CK_DISABLECORE__SHIFT 0x0 +#define COREPM_ID_0__COREPM_INDEX_MASK 0x1 +#define COREPM_ID_0__COREPM_INDEX__SHIFT 0x0 +#define COREPM_SCRATCH_0__SCRATCH_DATA_MASK 0xffffffff +#define COREPM_SCRATCH_0__SCRATCH_DATA__SHIFT 0x0 +#define RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15_MASK 0xffffffff +#define RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15__SHIFT 0x0 +#define SPMI_CONFIG0_0__SPMI_ENABLE_MASK 0x1 +#define SPMI_CONFIG0_0__SPMI_ENABLE__SHIFT 0x0 +#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS_MASK 0x7c +#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2 +#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES_MASK 0xf80 +#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES__SHIFT 0x7 +#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES_MASK 0x1f000 +#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES__SHIFT 0xc +#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK 0x3e0000 +#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT 0x11 +#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK 0x7c00000 +#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT 0x16 +#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK 0x1f +#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT 0x0 +#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE_MASK 0xffe0 +#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE__SHIFT 0x5 +#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER_MASK 0x1 +#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER_MASK 0x1 +#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER_MASK 0x1 +#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_BUSY_0__FSM_BUSY_MASK 0x1 +#define SPMI_FSM_BUSY_0__FSM_BUSY__SHIFT 0x0 +#define SPMI_PATH_0__PATH_ENABLE_REQ_MASK 0x1 +#define SPMI_PATH_0__PATH_ENABLE_REQ__SHIFT 0x0 +#define SPMI_PATH_0__PATH_ENABLE_ACK_MASK 0x2 +#define SPMI_PATH_0__PATH_ENABLE_ACK__SHIFT 0x1 +#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear_MASK 0x10 +#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear__SHIFT 0x4 +#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_MASK 0x1 +#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED__SHIFT 0x0 +#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2 +#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT 0x1 +#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6_MASK 0xfffc +#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2 +#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED_MASK 0x1 +#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT 0x0 +#define SPMI_SRAM_ADDRESS_0__SRAM_ADDRESS_MASK 0xffffffff +#define SPMI_SRAM_ADDRESS_0__SRAM_ADDRESS__SHIFT 0x0 +#define SPMI_SRAM_DATA_0__SRAM_DATA_MASK 0xffffffff +#define SPMI_SRAM_DATA_0__SRAM_DATA__SHIFT 0x0 +#define SPMI_RESET_0__ASYNC_RESET_0_MASK 0x1 +#define SPMI_RESET_0__ASYNC_RESET_0__SHIFT 0x0 +#define SPMI_RESET_0__SYNC_RESET_MASK 0x80000000 +#define SPMI_RESET_0__SYNC_RESET__SHIFT 0x1f +#define SPMI_FORCE_CLOCK_GATERS_0__CLOCK_GATER_0_FORCE_MASK 0x1 +#define SPMI_FORCE_CLOCK_GATERS_0__CLOCK_GATER_0_FORCE__SHIFT 0x0 +#define SPMI_FORCE_CLOCK_GATERS_0__SRAM_CLOCK_GATER_FORCE_MASK 0x100 +#define SPMI_FORCE_CLOCK_GATERS_0__SRAM_CLOCK_GATER_FORCE__SHIFT 0x8 +#define SPMI_SPARE_0__SPARE_DATA_MASK 0xffffffff +#define SPMI_SPARE_0__SPARE_DATA__SHIFT 0x0 +#define SPMI_SPARE_EX_0__SPARE_DATA_EX_MASK 0xffffffff +#define SPMI_SPARE_EX_0__SPARE_DATA_EX__SHIFT 0x0 +#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_EN_MASK 0x1 +#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_EN__SHIFT 0x0 +#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_TIMER_MASK 0x7fe +#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_TIMER__SHIFT 0x1 +#define POWERON_CPU_1__POWERON_MASK 0x1 +#define POWERON_CPU_1__POWERON__SHIFT 0x0 +#define POWERREADY_CPU_1__POWERREADY_MASK 0x1 +#define POWERREADY_CPU_1__POWERREADY__SHIFT 0x0 +#define PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK_MASK 0x1 +#define PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK__SHIFT 0x0 +#define RCC3ON_CPU_1__CK_RCC3ON_MASK 0x1 +#define RCC3ON_CPU_1__CK_RCC3ON__SHIFT 0x0 +#define RCC3ON_CPU_1__RCC3_PSM_EN_MASK 0x2 +#define RCC3ON_CPU_1__RCC3_PSM_EN__SHIFT 0x1 +#define RCC3ON_CPU_1__RCC3_PSM_CLK_DIV_MASK 0xc +#define RCC3ON_CPU_1__RCC3_PSM_CLK_DIV__SHIFT 0x2 +#define RCC3ON_CPU_1__RCC3_AVG_EN_MASK 0x10 +#define RCC3ON_CPU_1__RCC3_AVG_EN__SHIFT 0x4 +#define RCC3ON_CPU_1__RCC3_AVG_DIV_MASK 0x7e0 +#define RCC3ON_CPU_1__RCC3_AVG_DIV__SHIFT 0x5 +#define RCC3ON_CPU_1__RCC3_DIDT_TIMER_MASK 0x1f800 +#define RCC3ON_CPU_1__RCC3_DIDT_TIMER__SHIFT 0xb +#define RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0_MASK 0xfffe0000 +#define RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0__SHIFT 0x11 +#define RCC3EXITDONE_CPU_1__RCC3EXITDONE_MASK 0x1 +#define RCC3EXITDONE_CPU_1__RCC3EXITDONE__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_1__START_STATUS_XFER_MASK 0x1 +#define CORE_FUNC_LATE_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_FUNC_LAST_ADDR_MASK 0x7ff +#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_FUNC_LAST_ADDR__SHIFT 0x0 +#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_LATE_LAST_ADDR_MASK 0x7ff0000 +#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_LATE_LAST_ADDR__SHIFT 0x10 +#define CORE_REDUN_SSB_XFER_1__START_STATUS_XFER_MASK 0x1 +#define CORE_REDUN_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0 +#define CORE_REDUN_SSB_XFER_CFG_1__FUSE_REDUN_LAST_ADDR_MASK 0x7ff +#define CORE_REDUN_SSB_XFER_CFG_1__FUSE_REDUN_LAST_ADDR__SHIFT 0x0 +#define CORE_APM_SSB_XFER_1__START_STATUS_XFER_MASK 0x1 +#define CORE_APM_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0 +#define CORE_APM_SSB_XFER_CFG_1__FUSE_APM_LAST_ADDR_MASK 0x7ff +#define CORE_APM_SSB_XFER_CFG_1__FUSE_APM_LAST_ADDR__SHIFT 0x0 +#define COREPM_PWRCTRL_MISC_1__PWRGATEMASTERDIS_MASK 0x1 +#define COREPM_PWRCTRL_MISC_1__PWRGATEMASTERDIS__SHIFT 0x0 +#define LDOIVRON_CPU_1__CK_LDOIVRON_MASK 0x1 +#define LDOIVRON_CPU_1__CK_LDOIVRON__SHIFT 0x0 +#define LDOIVREXITDONE_CPU_1__LDOIVREXITDONE_MASK 0x1 +#define LDOIVREXITDONE_CPU_1__LDOIVREXITDONE__SHIFT 0x0 +#define RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF_MASK 0x3fff +#define RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF__SHIFT 0x0 +#define IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF_MASK 0x3fff +#define IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF__SHIFT 0x0 +#define CK_JTCOOLRESET_LATCHED_CPU_1__CK_JTCOOLRESET_LATCHED_MASK 0x1 +#define CK_JTCOOLRESET_LATCHED_CPU_1__CK_JTCOOLRESET_LATCHED__SHIFT 0x0 +#define CK_DISABLECORE_CPU_1__CK_DISABLECORE_MASK 0x1 +#define CK_DISABLECORE_CPU_1__CK_DISABLECORE__SHIFT 0x0 +#define COREPM_ID_1__COREPM_INDEX_MASK 0x1 +#define COREPM_ID_1__COREPM_INDEX__SHIFT 0x0 +#define COREPM_SCRATCH_1__SCRATCH_DATA_MASK 0xffffffff +#define COREPM_SCRATCH_1__SCRATCH_DATA__SHIFT 0x0 +#define RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15_MASK 0xffffffff +#define RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15__SHIFT 0x0 +#define SPMI_CONFIG0_1__SPMI_ENABLE_MASK 0x1 +#define SPMI_CONFIG0_1__SPMI_ENABLE__SHIFT 0x0 +#define SPMI_CONFIG0_1__SPMI_PATH_NUM_TIMING_FLOPS_MASK 0x7c +#define SPMI_CONFIG0_1__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2 +#define SPMI_CONFIG0_1__SPMI_SIGNALING_DELAY_CYCLES_MASK 0xf80 +#define SPMI_CONFIG0_1__SPMI_SIGNALING_DELAY_CYCLES__SHIFT 0x7 +#define SPMI_CONFIG0_1__SPMI_SIGNALING_HOLD_CYCLES_MASK 0x1f000 +#define SPMI_CONFIG0_1__SPMI_SIGNALING_HOLD_CYCLES__SHIFT 0xc +#define SPMI_CONFIG0_1__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK 0x3e0000 +#define SPMI_CONFIG0_1__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT 0x11 +#define SPMI_CONFIG0_1__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK 0x7c00000 +#define SPMI_CONFIG0_1__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT 0x16 +#define SPMI_CONFIG1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK 0x1f +#define SPMI_CONFIG1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT 0x0 +#define SPMI_CONFIG1_1__SPMI_CHAIN_SIZE_MASK 0xffe0 +#define SPMI_CONFIG1_1__SPMI_CHAIN_SIZE__SHIFT 0x5 +#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER_MASK 0x1 +#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER_MASK 0x1 +#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER_MASK 0x1 +#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER__SHIFT 0x0 +#define SPMI_FSM_BUSY_1__FSM_BUSY_MASK 0x1 +#define SPMI_FSM_BUSY_1__FSM_BUSY__SHIFT 0x0 +#define SPMI_PATH_1__PATH_ENABLE_REQ_MASK 0x1 +#define SPMI_PATH_1__PATH_ENABLE_REQ__SHIFT 0x0 +#define SPMI_PATH_1__PATH_ENABLE_ACK_MASK 0x2 +#define SPMI_PATH_1__PATH_ENABLE_ACK__SHIFT 0x1 +#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear_MASK 0x10 +#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear__SHIFT 0x4 +#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_MASK 0x1 +#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED__SHIFT 0x0 +#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2 +#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT 0x1 +#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6_MASK 0xfffc +#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2 +#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED_MASK 0x1 +#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT 0x0 +#define SPMI_SRAM_ADDRESS_1__SRAM_ADDRESS_MASK 0xffffffff +#define SPMI_SRAM_ADDRESS_1__SRAM_ADDRESS__SHIFT 0x0 +#define SPMI_SRAM_DATA_1__SRAM_DATA_MASK 0xffffffff +#define SPMI_SRAM_DATA_1__SRAM_DATA__SHIFT 0x0 +#define SPMI_RESET_1__ASYNC_RESET_0_MASK 0x1 +#define SPMI_RESET_1__ASYNC_RESET_0__SHIFT 0x0 +#define SPMI_RESET_1__SYNC_RESET_MASK 0x80000000 +#define SPMI_RESET_1__SYNC_RESET__SHIFT 0x1f +#define SPMI_FORCE_CLOCK_GATERS_1__CLOCK_GATER_0_FORCE_MASK 0x1 +#define SPMI_FORCE_CLOCK_GATERS_1__CLOCK_GATER_0_FORCE__SHIFT 0x0 +#define SPMI_FORCE_CLOCK_GATERS_1__SRAM_CLOCK_GATER_FORCE_MASK 0x100 +#define SPMI_FORCE_CLOCK_GATERS_1__SRAM_CLOCK_GATER_FORCE__SHIFT 0x8 +#define SPMI_SPARE_1__SPARE_DATA_MASK 0xffffffff +#define SPMI_SPARE_1__SPARE_DATA__SHIFT 0x0 +#define SPMI_SPARE_EX_1__SPARE_DATA_EX_MASK 0xffffffff +#define SPMI_SPARE_EX_1__SPARE_DATA_EX__SHIFT 0x0 +#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_EN_MASK 0x1 +#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_EN__SHIFT 0x0 +#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_TIMER_MASK 0x7fe +#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_TIMER__SHIFT 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 +#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 +#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 +#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 +#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 +#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 +#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 +#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 +#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 +#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa +#define GENERAL_PWRMGT__SPARE11_MASK 0x800 +#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 +#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe +#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 +#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf +#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 +#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 +#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 +#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 +#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 +#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 +#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 +#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 +#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 +#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b +#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 +#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 +#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 +#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 +#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 +#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 +#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 +#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 +#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 +#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 +#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 +#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40 +#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6 +#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000 +#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX_MASK 0xf +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX__SHIFT 0x0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX_MASK 0xf0 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX__SHIFT 0x4 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX_MASK 0xf00 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX__SHIFT 0x8 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX_MASK 0xf000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX__SHIFT 0xc +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX_MASK 0xf0000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX__SHIFT 0x10 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX_MASK 0xf00000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX__SHIFT 0x14 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX_MASK 0xf000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX__SHIFT 0x18 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX_MASK 0xf0000000 +#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_0__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_0__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_0__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_0__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_1__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_1__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_1__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_1__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_2__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_2__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_2__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_2__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_3__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_3__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_3__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_3__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_4__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_4__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_4__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_4__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_5__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_5__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_5__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_5__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_6__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_6__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_6__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_6__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 +#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 +#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 +#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 +#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 +#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 +#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 +#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 +#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 +#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 +#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 +#define CG_FREQ_TRAN_VOTING_7__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400 +#define CG_FREQ_TRAN_VOTING_7__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 +#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 +#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 +#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 +#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e +#define CG_FREQ_TRAN_VOTING_7__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000 +#define CG_FREQ_TRAN_VOTING_7__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 +#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f +#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 +#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 +#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 +#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 +#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 +#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 +#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 +#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 +#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 +#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c +#define SCLK_DEEP_SLEEP_CNTL__VCE_0_BUSY_MASK_MASK 0x20000000 +#define SCLK_DEEP_SLEEP_CNTL__VCE_0_BUSY_MASK__SHIFT 0x1d +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 +#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL2__VCE_0_CG_MC_STAT_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_0_CG_MC_STAT_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_BUSY_MASK_MASK 0x200000 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_BUSY_MASK__SHIFT 0x15 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_CG_MC_STAT_BUSY_MASK_MASK 0x400000 +#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_CG_MC_STAT_BUSY_MASK__SHIFT 0x16 +#define SCLK_DEEP_SLEEP_CNTL2__REG_SCLK_DEEP_SLEEP_MASK_MASK 0x800000 +#define SCLK_DEEP_SLEEP_CNTL2__REG_SCLK_DEEP_SLEEP_MASK__SHIFT 0x17 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 +#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 +#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf +#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_SLAVE_SCLK_BUSY_MASK_MASK 0x10000 +#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_SLAVE_SCLK_BUSY_MASK__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_MASTER_SCLK_BUSY_MASK_MASK 0x20000 +#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_MASTER_SCLK_BUSY_MASK__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 +#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 +#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 +#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 +#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 +#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 +#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 +#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 +#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 +#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 +#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 +#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 +#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE0_IDLE_MASK_MASK 0x200000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE0_IDLE_MASK__SHIFT 0x15 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE1_IDLE_MASK_MASK 0x400000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE1_IDLE_MASK__SHIFT 0x16 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUIOAGR_IDLE_MASK_MASK 0x800000 +#define LCLK_DEEP_SLEEP_CNTL2__L1IMUIOAGR_IDLE_MASK__SHIFT 0x17 +#define LCLK_DEEP_SLEEP_CNTL2__SPG_SMU_IDLE_MASK_MASK 0x1000000 +#define LCLK_DEEP_SLEEP_CNTL2__SPG_SMU_IDLE_MASK__SHIFT 0x18 +#define LCLK_DEEP_SLEEP_CNTL2__APG_SMU_IDLE_MASK_MASK 0x2000000 +#define LCLK_DEEP_SLEEP_CNTL2__APG_SMU_IDLE_MASK__SHIFT 0x19 +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE0_MASK_MASK 0x4000000 +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE0_MASK__SHIFT 0x1a +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE1_MASK_MASK 0x8000000 +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE1_MASK__SHIFT 0x1b +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE2_MASK_MASK 0x10000000 +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE2_MASK__SHIFT 0x1c +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE3_MASK_MASK 0x20000000 +#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE3_MASK__SHIFT 0x1d +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xc0000000 +#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x1e +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS_MASK 0x1 +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS__SHIFT 0x0 +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK 0x1fe +#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT 0x1 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff +#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 +#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 +#define PWR_DC_RESP__RESPONSE_MASK 0x1 +#define PWR_DC_RESP__RESPONSE__SHIFT 0x0 +#define PWR_VCE_RESP__RESPONSE_MASK 0xffffffff +#define PWR_VCE_RESP__RESPONSE__SHIFT 0x0 +#define PWR_UVD_RESP__RESPONSE_MASK 0xffffffff +#define PWR_UVD_RESP__RESPONSE__SHIFT 0x0 +#define PWR_ACP_RESP__RESPONSE_MASK 0xffffffff +#define PWR_ACP_RESP__RESPONSE__SHIFT 0x0 +#define PWR_DC_REQ__REQUEST_MASK 0x1 +#define PWR_DC_REQ__REQUEST__SHIFT 0x0 +#define SCLK_MIN_DIV__FRACV_MASK 0xfff +#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 +#define SCLK_MIN_DIV__INTV_MASK 0x7f000 +#define SCLK_MIN_DIV__INTV__SHIFT 0xc +#define PCIE_PGFSM_CONFIG__FSM_ADDR_MASK 0xff +#define PCIE_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define PCIE_PGFSM_CONFIG__Power_Down_MASK 0x100 +#define PCIE_PGFSM_CONFIG__Power_Down__SHIFT 0x8 +#define PCIE_PGFSM_CONFIG__Power_Up_MASK 0x200 +#define PCIE_PGFSM_CONFIG__Power_Up__SHIFT 0x9 +#define PCIE_PGFSM_CONFIG__P1_Select_MASK 0x400 +#define PCIE_PGFSM_CONFIG__P1_Select__SHIFT 0xa +#define PCIE_PGFSM_CONFIG__P2_Select_MASK 0x800 +#define PCIE_PGFSM_CONFIG__P2_Select__SHIFT 0xb +#define PCIE_PGFSM_CONFIG__Write_Op_MASK 0x1000 +#define PCIE_PGFSM_CONFIG__Write_Op__SHIFT 0xc +#define PCIE_PGFSM_CONFIG__Read_Op_MASK 0x2000 +#define PCIE_PGFSM_CONFIG__Read_Op__SHIFT 0xd +#define PCIE_PGFSM_CONFIG__Reserved_MASK 0xfffc000 +#define PCIE_PGFSM_CONFIG__Reserved__SHIFT 0xe +#define PCIE_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 +#define PCIE_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define PCIE_PGFSM_WRITE__Write_value_MASK 0xffffffff +#define PCIE_PGFSM_WRITE__Write_value__SHIFT 0x0 +#define SERDES_BUSY__PCIE_SERDES_BUSY_MASK 0x1 +#define SERDES_BUSY__PCIE_SERDES_BUSY__SHIFT 0x0 +#define PCIE_PGFSM2_CONFIG__FSM_ADDR_MASK 0xff +#define PCIE_PGFSM2_CONFIG__FSM_ADDR__SHIFT 0x0 +#define PCIE_PGFSM2_CONFIG__Power_Down_MASK 0x100 +#define PCIE_PGFSM2_CONFIG__Power_Down__SHIFT 0x8 +#define PCIE_PGFSM2_CONFIG__Power_Up_MASK 0x200 +#define PCIE_PGFSM2_CONFIG__Power_Up__SHIFT 0x9 +#define PCIE_PGFSM2_CONFIG__P1_Select_MASK 0x400 +#define PCIE_PGFSM2_CONFIG__P1_Select__SHIFT 0xa +#define PCIE_PGFSM2_CONFIG__P2_Select_MASK 0x800 +#define PCIE_PGFSM2_CONFIG__P2_Select__SHIFT 0xb +#define PCIE_PGFSM2_CONFIG__Write_Op_MASK 0x1000 +#define PCIE_PGFSM2_CONFIG__Write_Op__SHIFT 0xc +#define PCIE_PGFSM2_CONFIG__Read_Op_MASK 0x2000 +#define PCIE_PGFSM2_CONFIG__Read_Op__SHIFT 0xd +#define PCIE_PGFSM2_CONFIG__Reserved_MASK 0xfffc000 +#define PCIE_PGFSM2_CONFIG__Reserved__SHIFT 0xe +#define PCIE_PGFSM2_CONFIG__REG_ADDR_MASK 0xf0000000 +#define PCIE_PGFSM2_CONFIG__REG_ADDR__SHIFT 0x1c +#define PCIE_PGFSM2_WRITE__Write_value_MASK 0xffffffff +#define PCIE_PGFSM2_WRITE__Write_value__SHIFT 0x0 +#define SERDES2_BUSY__PCIE_SERDES_BUSY_MASK 0x1 +#define SERDES2_BUSY__PCIE_SERDES_BUSY__SHIFT 0x0 +#define PCIE_PGFSM_0_READ__Read_value_MASK 0xffffff +#define PCIE_PGFSM_0_READ__Read_value__SHIFT 0x0 +#define PCIE_PGFSM_0_READ__Read_valid_MASK 0x1000000 +#define PCIE_PGFSM_0_READ__Read_valid__SHIFT 0x18 +#define PCIE_PGFSM_1_READ__Read_value_MASK 0xffffff +#define PCIE_PGFSM_1_READ__Read_value__SHIFT 0x0 +#define PCIE_PGFSM_1_READ__Read_valid_MASK 0x1000000 +#define PCIE_PGFSM_1_READ__Read_valid__SHIFT 0x18 +#define PWR_ACPI_INTERRUPT__BIF_CG_req_MASK 0x1 +#define PWR_ACPI_INTERRUPT__BIF_CG_req__SHIFT 0x0 +#define PWR_ACPI_INTERRUPT__AZ_CG_req_MASK 0x2 +#define PWR_ACPI_INTERRUPT__AZ_CG_req__SHIFT 0x1 +#define PWR_ACPI_INTERRUPT__AZ_CG_resp_MASK 0x4 +#define PWR_ACPI_INTERRUPT__AZ_CG_resp__SHIFT 0x2 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000 +#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2 +#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4 +#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8 +#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1 +#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0 +#define REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit_MASK 0x1 +#define REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit__SHIFT 0x0 +#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG4_MASK 0xffff +#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG4__SHIFT 0x0 +#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG5_MASK 0xffff0000 +#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG5__SHIFT 0x10 +#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 +#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 +#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe +#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff +#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff +#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 +#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 +#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe +#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff +#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff +#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 +#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 +#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe +#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff +#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff +#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 +#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 +#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe +#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 +#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff +#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff +#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 +#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 +#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe +#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 +#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 +#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff +#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff +#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 +#define MISC_UNB_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff +#define MISC_UNB_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0 +#define MISC_UNB_PWRMGT_CFG1__TIMER_EN_MASK 0x1 +#define MISC_UNB_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0 +#define MISC_UNB_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe +#define MISC_UNB_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1 +#define MISC_UNB_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000 +#define MISC_UNB_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11 +#define MISC_UNB_PWRMGT_DATA__NB_CROSS_TRIGGER_MASK 0xf +#define MISC_UNB_PWRMGT_DATA__NB_CROSS_TRIGGER__SHIFT 0x0 +#define MISC_UNB_PWRMGT_DATA__NB_PRE_SELF_REFRESH_MASK 0x10 +#define MISC_UNB_PWRMGT_DATA__NB_PRE_SELF_REFRESH__SHIFT 0x4 +#define MISC_UNB_PWRMGT_DATA__NB_REQ_NB_PSTATE_MASK 0x20 +#define MISC_UNB_PWRMGT_DATA__NB_REQ_NB_PSTATE__SHIFT 0x5 +#define MISC_UNB_PWRMGT_DATA__NB_FLUSH_ACK_TOGGLE_MASK 0x40 +#define MISC_UNB_PWRMGT_DATA__NB_FLUSH_ACK_TOGGLE__SHIFT 0x6 +#define MISC_UNB_PWRMGT_DATA__NB_ON_INB_WAKE_ACK_MASK 0x80 +#define MISC_UNB_PWRMGT_DATA__NB_ON_INB_WAKE_ACK__SHIFT 0x7 +#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH0LINK_WAKE_ACK_MASK 0x100 +#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH0LINK_WAKE_ACK__SHIFT 0x8 +#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH1LINK_WAKE_ACK_MASK 0x200 +#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH1LINK_WAKE_ACK__SHIFT 0x9 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6_MASK 0x1 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6__SHIFT 0x0 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive_MASK 0x2 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive__SHIFT 0x1 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt_MASK 0x4 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt__SHIFT 0x2 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE_MASK 0xf8 +#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE__SHIFT 0x3 +#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN_MASK 0x1 +#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN__SHIFT 0x0 +#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD_MASK 0x1fffe +#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD__SHIFT 0x1 +#define DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT_MASK 0x60000 +#define DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT__SHIFT 0x11 +#define SOUTHBRIDGE_TYPE__DISCRETE_SB_MASK 0x1 +#define SOUTHBRIDGE_TYPE__DISCRETE_SB__SHIFT 0x0 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6_MASK 0x1 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6__SHIFT 0x0 +#define GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive_MASK 0x2 +#define GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive__SHIFT 0x1 +#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt_MASK 0x4 +#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt__SHIFT 0x2 +#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit_MASK 0x8 +#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit__SHIFT 0x3 +#define GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh_MASK 0x10 +#define GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh__SHIFT 0x4 +#define GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate_MASK 0x20 +#define GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate__SHIFT 0x5 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate_MASK 0x40 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate__SHIFT 0x6 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh_MASK 0x80 +#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh__SHIFT 0x7 +#define GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake_MASK 0x100 +#define GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake__SHIFT 0x8 +#define GNBPM_SMU_PWRMGT_STATUS__SPARE_MASK 0xfe00 +#define GNBPM_SMU_PWRMGT_STATUS__SPARE__SHIFT 0x9 +#define ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL_MASK 0x3 +#define ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL__SHIFT 0x0 +#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xffffffff +#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0 +#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xffffffff +#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0xffff +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xffff0000 +#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0xffff +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xffff0000 +#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0xffff +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xffff0000 +#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0xffff +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xffff0000 +#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10 +#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xffffffff +#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0 +#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0xffff +#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 +#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0xffff0000 +#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10 + +#endif /* SMU_8_0_SH_MASK_H */ |