diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/discovery.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/discovery.h | 140 |
1 files changed, 134 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h index f150404ffc68..710e328fad48 100644 --- a/drivers/gpu/drm/amd/include/discovery.h +++ b/drivers/gpu/drm/amd/include/discovery.h @@ -30,16 +30,16 @@ #define GC_TABLE_ID 0x4347 #define HARVEST_TABLE_SIGNATURE 0x56524148 #define VCN_INFO_TABLE_ID 0x004E4356 -#define MALL_INFO_TABLE_ID 0x4D414C4C +#define MALL_INFO_TABLE_ID 0x4C4C414D +#define NPS_INFO_TABLE_ID 0x0053504E -typedef enum -{ +typedef enum { IP_DISCOVERY = 0, GC, HARVEST_INFO, VCN_INFO, MALL_INFO, - RESERVED_1, + NPS_INFO, TOTAL_TABLES = 6 } table; @@ -79,7 +79,14 @@ typedef struct ip_discovery_header uint32_t id; /* Table ID */ uint16_t num_dies; /* Number of Dies */ die_info die_info[16]; /* list die information for up to 16 dies */ - uint16_t padding[1]; /* padding */ + union { + uint16_t padding[1]; /* version <= 3 */ + struct { /* version == 4 */ + uint8_t base_addr_64_bit : 1; /* ip structures are using 64 bit base address */ + uint8_t reserved : 7; + uint8_t reserved2; + }; + }; } ip_discovery_header; typedef struct ip @@ -115,9 +122,29 @@ typedef struct ip_v3 uint8_t sub_revision : 4; /* HCID Sub-Revision */ uint8_t variant : 4; /* HW variant */ #endif - uint32_t base_address[1]; /* Base Address list. Corresponds to the num_base_address field*/ + uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/ } ip_v3; +typedef struct ip_v4 { + uint16_t hw_id; /* Hardware ID */ + uint8_t instance_number; /* Instance number for the IP */ + uint8_t num_base_address; /* Number of base addresses*/ + uint8_t major; /* Hardware ID.major version */ + uint8_t minor; /* Hardware ID.minor version */ + uint8_t revision; /* Hardware ID.revision version */ +#if defined(LITTLEENDIAN_CPU) + uint8_t sub_revision : 4; /* HCID Sub-Revision */ + uint8_t variant : 4; /* HW variant */ +#elif defined(BIGENDIAN_CPU) + uint8_t variant : 4; /* HW variant */ + uint8_t sub_revision : 4; /* HCID Sub-Revision */ +#endif + union { + DECLARE_FLEX_ARRAY(uint32_t, base_address); /* 32-bit Base Address list. Corresponds to the num_base_address field*/ + DECLARE_FLEX_ARRAY(uint64_t, base_address_64); /* 64-bit Base Address list. Corresponds to the num_base_address field*/ + } __packed; +} ip_v4; + typedef struct die_header { uint16_t die_id; @@ -134,6 +161,7 @@ typedef struct ip_structure { ip *ip_list; ip_v3 *ip_v3_list; + ip_v4 *ip_v4_list; }; /* IP list. Variable size*/ } die; } ip_structure; @@ -230,6 +258,48 @@ struct gc_info_v1_2 { uint32_t gc_gl2c_per_gpu; }; +struct gc_info_v1_3 { + struct gpu_info_header header; + uint32_t gc_num_se; + uint32_t gc_num_wgp0_per_sa; + uint32_t gc_num_wgp1_per_sa; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_gl2c; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_sa_per_se; + uint32_t gc_num_packer_per_sc; + uint32_t gc_num_gl2a; + uint32_t gc_num_tcp_per_sa; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_tcps; + uint32_t gc_num_tcp_per_wpg; + uint32_t gc_tcp_l1_size; + uint32_t gc_num_sqc_per_wgp; + uint32_t gc_l1_instruction_cache_size_per_sqc; + uint32_t gc_l1_data_cache_size_per_sqc; + uint32_t gc_gl1c_per_sa; + uint32_t gc_gl1c_size_per_instance; + uint32_t gc_gl2c_per_gpu; + uint32_t gc_tcp_size_per_cu; + uint32_t gc_tcp_cache_line_size; + uint32_t gc_instruction_cache_size_per_sqc; + uint32_t gc_instruction_cache_line_size; + uint32_t gc_scalar_data_cache_size_per_sqc; + uint32_t gc_scalar_data_cache_line_size; + uint32_t gc_tcc_size; + uint32_t gc_tcc_cache_line_size; +}; + struct gc_info_v2_0 { struct gpu_info_header header; @@ -252,6 +322,36 @@ struct gc_info_v2_0 { uint32_t gc_num_packer_per_sc; }; +struct gc_info_v2_1 { + struct gpu_info_header header; + + uint32_t gc_num_se; + uint32_t gc_num_cu_per_sh; + uint32_t gc_num_sh_per_se; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_tccs; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_packer_per_sc; + /* new for v2_1 */ + uint32_t gc_num_tcp_per_sh; + uint32_t gc_tcp_size_per_cu; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_cu_per_sqc; + uint32_t gc_instruction_cache_size_per_sqc; + uint32_t gc_scalar_data_cache_size_per_sqc; + uint32_t gc_tcc_size; +}; + typedef struct harvest_info_header { uint32_t signature; /* Table Signature */ uint32_t version; /* Table Version */ @@ -284,6 +384,12 @@ struct mall_info_v1_0 { uint32_t reserved[5]; }; +struct mall_info_v2_0 { + struct mall_info_header header; + uint32_t mall_size_per_umc; + uint32_t reserved[8]; +}; + #define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4 struct vcn_info_header { @@ -316,6 +422,28 @@ struct vcn_info_v1_0 { uint32_t reserved[4]; }; +#define NPS_INFO_TABLE_MAX_NUM_INSTANCES 12 + +struct nps_info_header { + uint32_t table_id; /* table ID */ + uint16_t version_major; /* table version */ + uint16_t version_minor; /* table version */ + uint32_t size_bytes; /* size of the entire header+data in bytes = 0x000000D4 (212) */ +}; + +struct nps_instance_info_v1_0 { + uint64_t base_address; + uint64_t limit_address; +}; + +struct nps_info_v1_0 { + struct nps_info_header header; + uint32_t nps_type; + uint32_t count; + struct nps_instance_info_v1_0 + instance_info[NPS_INFO_TABLE_MAX_NUM_INSTANCES]; +}; + #pragma pack() #endif |