diff options
Diffstat (limited to 'drivers/gpu/drm/amd/pm/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 79 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h | 43 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h | 203 |
4 files changed, 111 insertions, 220 deletions
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index cb5b9df78b4d..aa3f427819a0 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -50,8 +50,12 @@ enum amdgpu_runpm_mode { AMDGPU_RUNPM_PX, AMDGPU_RUNPM_BOCO, AMDGPU_RUNPM_BACO, + AMDGPU_RUNPM_BAMACO, }; +#define BACO_SUPPORT (1<<0) +#define MACO_SUPPORT (1<<1) + struct amdgpu_ps { u32 caps; /* vbios flags */ u32 class; /* vbios flags */ @@ -89,6 +93,8 @@ struct amdgpu_dpm_thermal { int max_mem_crit_temp; /* memory max emergency(shutdown) temp */ int max_mem_emergency_temp; + /* SWCTF threshold */ + int sw_ctf_threshold; /* was last interrupt low to high or high to low */ bool high_to_low; /* interrupt source */ @@ -257,10 +263,6 @@ struct amdgpu_dpm { u32 voltage_response_time; u32 backbias_response_time; void *priv; - u32 new_active_crtcs; - int new_active_crtc_count; - u32 current_active_crtcs; - int current_active_crtc_count; struct amdgpu_dpm_dynamic_state dyn_state; struct amdgpu_dpm_fan fan; u32 tdp_limit; @@ -289,7 +291,8 @@ enum ip_power_state { }; /* Used to mask smu debug modes */ -#define SMU_DEBUG_HALT_ON_ERROR 0x1 +#define SMU_DEBUG_HALT_ON_ERROR BIT(0) +#define SMU_DEBUG_POOL_USE_VRAM BIT(1) #define MAX_SMU_I2C_BUSES 2 @@ -312,6 +315,21 @@ struct config_table_setting uint16_t fclk_average_tau; }; +#define OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE BIT(0) +#define OD_OPS_SUPPORT_FAN_CURVE_SET BIT(1) +#define OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE BIT(2) +#define OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET BIT(3) +#define OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE BIT(4) +#define OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET BIT(5) +#define OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE BIT(6) +#define OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET BIT(7) +#define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE BIT(8) +#define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET BIT(9) +#define OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE BIT(10) +#define OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET BIT(11) +#define OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE BIT(12) +#define OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET BIT(13) + struct amdgpu_pm { struct mutex mutex; u32 current_sclk; @@ -364,13 +382,19 @@ struct amdgpu_pm { struct config_table_setting config_table; /* runtime mode */ enum amdgpu_runpm_mode rpm_mode; + + struct list_head od_kobj_list; + uint32_t od_feature_mask; }; int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, void *data, uint32_t *size); +int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit); +int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit); + int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, - uint32_t block_type, bool gate); + uint32_t block_type, bool gate, int inst); extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low); @@ -382,14 +406,19 @@ int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, enum PP_SMC_POWER_PROFILE type, bool en); +int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, + bool pause); int amdgpu_dpm_baco_reset(struct amdgpu_device *adev); int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev); +int amdgpu_dpm_link_reset(struct amdgpu_device *adev); +int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev); -bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev); +int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev); bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev); +bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev); int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, @@ -404,8 +433,6 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev); int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, uint32_t cstate); -int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en); - int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev); int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, @@ -418,12 +445,15 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev); void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable); +void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst); void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable); void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable); +void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable); int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version); int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable); int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size); int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size); +int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev); int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t *min, @@ -488,6 +518,22 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, long *input, uint32_t size); int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table); +ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, + void *table); +ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, + enum smu_temp_metric_type type, void *table); + +/** + * @get_pm_metrics: Get one snapshot of power management metrics from PMFW. The + * sample is copied to pm_metrics buffer. It's expected to be allocated by the + * caller and size of the allocated buffer is passed. Max size expected for a + * metrics sample is 4096 bytes. + * + * Return: Actual size of the metrics sample + */ +ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, + size_t size); + int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, uint32_t *fan_mode); int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, @@ -505,7 +551,7 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, enum pp_power_limit_level pp_limit_level, enum pp_power_type power_type); int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, - uint32_t limit); + uint32_t limit_type, uint32_t limit); int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev); int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, struct seq_file *m); @@ -513,6 +559,7 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, void **addr, size_t *size); int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev); +int amdgpu_dpm_is_overdrive_enabled(struct amdgpu_device *adev); int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, const char *buf, size_t size); @@ -555,4 +602,16 @@ enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, unsigned int *num_states); int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, struct dpm_clocks *clock_table); +int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, + int policy_level); +ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, + enum pp_pm_policy p_type, char *buf); +int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask); +bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev); +int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask); +bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev); +bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, + enum smu_temp_metric_type type); +const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev); + #endif diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h index 5c2a89f0d5d5..cc6d7ba040e9 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h @@ -23,10 +23,6 @@ #ifndef __AMDGPU_DPM_INTERNAL_H__ #define __AMDGPU_DPM_INTERNAL_H__ -void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev); - -u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev); - -u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev); +void amdgpu_dpm_get_display_cfg(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h index 52045ad59bed..c12ced32f780 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h @@ -24,8 +24,7 @@ #ifndef __AMDGPU_PM_H__ #define __AMDGPU_PM_H__ -struct cg_flag_name -{ +struct cg_flag_name { u64 flag; const char *name; }; @@ -44,8 +43,47 @@ enum amdgpu_device_attr_states { ATTR_STATE_SUPPORTED, }; +enum amdgpu_device_attr_id { + device_attr_id__unknown = -1, + device_attr_id__power_dpm_state = 0, + device_attr_id__power_dpm_force_performance_level, + device_attr_id__pp_num_states, + device_attr_id__pp_cur_state, + device_attr_id__pp_force_state, + device_attr_id__pp_table, + device_attr_id__pp_dpm_sclk, + device_attr_id__pp_dpm_mclk, + device_attr_id__pp_dpm_socclk, + device_attr_id__pp_dpm_fclk, + device_attr_id__pp_dpm_vclk, + device_attr_id__pp_dpm_vclk1, + device_attr_id__pp_dpm_dclk, + device_attr_id__pp_dpm_dclk1, + device_attr_id__pp_dpm_dcefclk, + device_attr_id__pp_dpm_pcie, + device_attr_id__pp_sclk_od, + device_attr_id__pp_mclk_od, + device_attr_id__pp_power_profile_mode, + device_attr_id__pp_od_clk_voltage, + device_attr_id__gpu_busy_percent, + device_attr_id__mem_busy_percent, + device_attr_id__vcn_busy_percent, + device_attr_id__pcie_bw, + device_attr_id__pp_features, + device_attr_id__unique_id, + device_attr_id__thermal_throttling_logging, + device_attr_id__apu_thermal_cap, + device_attr_id__gpu_metrics, + device_attr_id__smartshift_apu_power, + device_attr_id__smartshift_dgpu_power, + device_attr_id__smartshift_bias, + device_attr_id__pm_metrics, + device_attr_id__count, +}; + struct amdgpu_device_attr { struct device_attribute dev_attr; + enum amdgpu_device_attr_id attr_id; enum amdgpu_device_attr_flags flags; int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, uint32_t mask, enum amdgpu_device_attr_states *states); @@ -62,6 +100,7 @@ struct amdgpu_device_attr_entry { #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \ { .dev_attr = __ATTR(_name, _mode, _show, _store), \ + .attr_id = device_attr_id__##_name, \ .flags = _flags, \ ##__VA_ARGS__, } diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h deleted file mode 100644 index 566a0da59e53..000000000000 --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2021 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef SMU_13_0_0_PPTABLE_H -#define SMU_13_0_0_PPTABLE_H - -#pragma pack(push, 1) - -#define SMU_13_0_0_TABLE_FORMAT_REVISION 15 - -//// POWERPLAYTABLE::ulPlatformCaps -#define SMU_13_0_0_PP_PLATFORM_CAP_POWERPLAY 0x1 // This cap indicates whether CCC need to show Powerplay page. -#define SMU_13_0_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 // This cap indicates whether power source notificaiton is done by SBIOS instead of OS. -#define SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC 0x4 // This cap indicates whether DC mode notificaiton is done by GPIO pin directly. -#define SMU_13_0_0_PP_PLATFORM_CAP_BACO 0x8 // This cap indicates whether board supports the BACO circuitry. -#define SMU_13_0_0_PP_PLATFORM_CAP_MACO 0x10 // This cap indicates whether board supports the MACO circuitry. -#define SMU_13_0_0_PP_PLATFORM_CAP_SHADOWPSTATE 0x20 // This cap indicates whether board supports the Shadow Pstate. - -// SMU_13_0_0_PP_THERMALCONTROLLER - Thermal Controller Type -#define SMU_13_0_0_PP_THERMALCONTROLLER_NONE 0 -#define SMU_13_0_0_PP_THERMALCONTROLLER_NAVI21 28 - -#define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x81 // OverDrive 8 Table Version 0.2 -#define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock Table Version 1.00 - -enum SMU_13_0_0_ODFEATURE_CAP -{ - SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0, - SMU_13_0_0_ODCAP_GFXCLK_CURVE, - SMU_13_0_0_ODCAP_UCLK_LIMITS, - SMU_13_0_0_ODCAP_POWER_LIMIT, - SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT, - SMU_13_0_0_ODCAP_FAN_SPEED_MIN, - SMU_13_0_0_ODCAP_TEMPERATURE_FAN, - SMU_13_0_0_ODCAP_TEMPERATURE_SYSTEM, - SMU_13_0_0_ODCAP_MEMORY_TIMING_TUNE, - SMU_13_0_0_ODCAP_FAN_ZERO_RPM_CONTROL, - SMU_13_0_0_ODCAP_AUTO_UV_ENGINE, - SMU_13_0_0_ODCAP_AUTO_OC_ENGINE, - SMU_13_0_0_ODCAP_AUTO_OC_MEMORY, - SMU_13_0_0_ODCAP_FAN_CURVE, - SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, - SMU_13_0_0_ODCAP_POWER_MODE, - SMU_13_0_0_ODCAP_COUNT, -}; - -enum SMU_13_0_0_ODFEATURE_ID -{ - SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS = 1 << SMU_13_0_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature - SMU_13_0_0_ODFEATURE_GFXCLK_CURVE = 1 << SMU_13_0_0_ODCAP_GFXCLK_CURVE, //GFXCLK Curve feature - SMU_13_0_0_ODFEATURE_UCLK_LIMITS = 1 << SMU_13_0_0_ODCAP_UCLK_LIMITS, //UCLK Limit feature - SMU_13_0_0_ODFEATURE_POWER_LIMIT = 1 << SMU_13_0_0_ODCAP_POWER_LIMIT, //Power Limit feature - SMU_13_0_0_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature - SMU_13_0_0_ODFEATURE_FAN_SPEED_MIN = 1 << SMU_13_0_0_ODCAP_FAN_SPEED_MIN, //Minimum Fan Speed feature - SMU_13_0_0_ODFEATURE_TEMPERATURE_FAN = 1 << SMU_13_0_0_ODCAP_TEMPERATURE_FAN, //Fan Target Temperature Limit feature - SMU_13_0_0_ODFEATURE_TEMPERATURE_SYSTEM = 1 << SMU_13_0_0_ODCAP_TEMPERATURE_SYSTEM, //Operating Temperature Limit feature - SMU_13_0_0_ODFEATURE_MEMORY_TIMING_TUNE = 1 << SMU_13_0_0_ODCAP_MEMORY_TIMING_TUNE, //AC Timing Tuning feature - SMU_13_0_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_13_0_0_ODCAP_FAN_ZERO_RPM_CONTROL, //Zero RPM feature - SMU_13_0_0_ODFEATURE_AUTO_UV_ENGINE = 1 << SMU_13_0_0_ODCAP_AUTO_UV_ENGINE, //Auto Under Volt GFXCLK feature - SMU_13_0_0_ODFEATURE_AUTO_OC_ENGINE = 1 << SMU_13_0_0_ODCAP_AUTO_OC_ENGINE, //Auto Over Clock GFXCLK feature - SMU_13_0_0_ODFEATURE_AUTO_OC_MEMORY = 1 << SMU_13_0_0_ODCAP_AUTO_OC_MEMORY, //Auto Over Clock MCLK feature - SMU_13_0_0_ODFEATURE_FAN_CURVE = 1 << SMU_13_0_0_ODCAP_FAN_CURVE, //Fan Curve feature - SMU_13_0_0_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, //Auto Fan Acoustic RPM feature - SMU_13_0_0_ODFEATURE_POWER_MODE = 1 << SMU_13_0_0_ODCAP_POWER_MODE, //Optimized GPU Power Mode feature - SMU_13_0_0_ODFEATURE_COUNT = 16, -}; - -#define SMU_13_0_0_MAX_ODFEATURE 32 //Maximum Number of OD Features - -enum SMU_13_0_0_ODSETTING_ID -{ - SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0, - SMU_13_0_0_ODSETTING_GFXCLKFMIN, - SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_A, - SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_B, - SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_C, - SMU_13_0_0_ODSETTING_CUSTOM_CURVE_VFT_FMIN, - SMU_13_0_0_ODSETTING_UCLKFMIN, - SMU_13_0_0_ODSETTING_UCLKFMAX, - SMU_13_0_0_ODSETTING_POWERPERCENTAGE, - SMU_13_0_0_ODSETTING_FANRPMMIN, - SMU_13_0_0_ODSETTING_FANRPMACOUSTICLIMIT, - SMU_13_0_0_ODSETTING_FANTARGETTEMPERATURE, - SMU_13_0_0_ODSETTING_OPERATINGTEMPMAX, - SMU_13_0_0_ODSETTING_ACTIMING, - SMU_13_0_0_ODSETTING_FAN_ZERO_RPM_CONTROL, - SMU_13_0_0_ODSETTING_AUTOUVENGINE, - SMU_13_0_0_ODSETTING_AUTOOCENGINE, - SMU_13_0_0_ODSETTING_AUTOOCMEMORY, - SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_1, - SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_1, - SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_2, - SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_2, - SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_3, - SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_3, - SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_4, - SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_4, - SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_5, - SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_5, - SMU_13_0_0_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT, - SMU_13_0_0_ODSETTING_POWER_MODE, - SMU_13_0_0_ODSETTING_COUNT, -}; -#define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings - -enum SMU_13_0_0_PWRMODE_SETTING -{ - SMU_13_0_0_PMSETTING_POWER_LIMIT_QUIET = 0, - SMU_13_0_0_PMSETTING_POWER_LIMIT_BALANCE, - SMU_13_0_0_PMSETTING_POWER_LIMIT_TURBO, - SMU_13_0_0_PMSETTING_POWER_LIMIT_RAGE, - SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_QUIET, - SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_BALANCE, - SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_TURBO, - SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_RAGE, - SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_QUIET, - SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_BALANCE, - SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_TURBO, - SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_RAGE, - SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_QUIET, - SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_BALANCE, - SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_TURBO, - SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_RAGE, -}; -#define SMU_13_0_0_MAX_PMSETTING 32 //Maximum Number of PowerMode Settings - -struct smu_13_0_0_overdrive_table -{ - uint8_t revision; //Revision = SMU_13_0_0_PP_OVERDRIVE_VERSION - uint8_t reserve[3]; //Zero filled field reserved for future use - uint32_t feature_count; //Total number of supported features - uint32_t setting_count; //Total number of supported settings - uint8_t cap[SMU_13_0_0_MAX_ODFEATURE]; //OD feature support flags - uint32_t max[SMU_13_0_0_MAX_ODSETTING]; //default maximum settings - uint32_t min[SMU_13_0_0_MAX_ODSETTING]; //default minimum settings - int16_t pm_setting[SMU_13_0_0_MAX_PMSETTING]; //Optimized power mode feature settings -}; - -enum SMU_13_0_0_PPCLOCK_ID -{ - SMU_13_0_0_PPCLOCK_GFXCLK = 0, - SMU_13_0_0_PPCLOCK_SOCCLK, - SMU_13_0_0_PPCLOCK_UCLK, - SMU_13_0_0_PPCLOCK_FCLK, - SMU_13_0_0_PPCLOCK_DCLK_0, - SMU_13_0_0_PPCLOCK_VCLK_0, - SMU_13_0_0_PPCLOCK_DCLK_1, - SMU_13_0_0_PPCLOCK_VCLK_1, - SMU_13_0_0_PPCLOCK_DCEFCLK, - SMU_13_0_0_PPCLOCK_DISPCLK, - SMU_13_0_0_PPCLOCK_PIXCLK, - SMU_13_0_0_PPCLOCK_PHYCLK, - SMU_13_0_0_PPCLOCK_DTBCLK, - SMU_13_0_0_PPCLOCK_COUNT, -}; -#define SMU_13_0_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks - -struct smu_13_0_0_powerplay_table -{ - struct atom_common_table_header header; //For SMU13, header.format_revision = 15, header.content_revision = 0 - uint8_t table_revision; //For SMU13, table_revision = 2 - uint8_t padding; - uint16_t table_size; //Driver portion table size. The offset to smc_pptable including header size - uint32_t golden_pp_id; //PPGen use only: PP Table ID on the Golden Data Base - uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base - uint16_t format_id; //PPGen use only: PPTable for different ASICs. For SMU13 this should be 0x80 - uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps - - uint8_t thermal_controller_type; //one of SMU_13_0_0_PP_THERMALCONTROLLER - - uint16_t small_power_limit1; - uint16_t small_power_limit2; - uint16_t boost_power_limit; //For Gemini Board, when the slave adapter is in BACO mode, the master adapter will use this boost power limit instead of the default power limit to boost the power limit. - uint16_t software_shutdown_temp; - - uint32_t reserve[45]; - - struct smu_13_0_0_overdrive_table overdrive_table; - uint8_t padding1; - PPTable_t smc_pptable; //PPTable_t in driver_if.h -}; - -#pragma pack(pop) - -#endif |