summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h')
-rw-r--r--drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h41
1 files changed, 33 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 0917dec8efe3..3f94c33df7b7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -362,6 +362,27 @@ struct smu_table_context {
void *gpu_metrics_table;
};
+struct smu_context;
+struct smu_dpm_policy;
+
+struct smu_dpm_policy_desc {
+ const char *name;
+ char *(*get_desc)(struct smu_dpm_policy *dpm_policy, int level);
+};
+
+struct smu_dpm_policy {
+ struct smu_dpm_policy_desc *desc;
+ enum pp_pm_policy policy_type;
+ unsigned long level_mask;
+ int current_level;
+ int (*set_policy)(struct smu_context *ctxt, int level);
+};
+
+struct smu_dpm_policy_ctxt {
+ struct smu_dpm_policy policies[PP_PM_POLICY_NUM];
+ unsigned long policy_mask;
+};
+
struct smu_dpm_context {
uint32_t dpm_context_size;
void *dpm_context;
@@ -372,6 +393,7 @@ struct smu_dpm_context {
struct smu_power_state *dpm_request_power_state;
struct smu_power_state *dpm_current_power_state;
struct mclock_latency_table *mclk_latency_table;
+ struct smu_dpm_policy_ctxt *dpm_policies;
};
struct smu_power_gate {
@@ -580,8 +602,6 @@ struct smu_context {
struct delayed_work swctf_delayed_work;
- enum pp_xgmi_plpd_mode plpd_mode;
-
/* data structures for wbrf feature support */
bool wbrf_supported;
struct notifier_block wbrf_notifier;
@@ -857,12 +877,6 @@ struct pptable_funcs {
int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
/**
- * @select_xgmi_plpd_policy: Select xgmi per-link power down policy.
- */
- int (*select_xgmi_plpd_policy)(struct smu_context *smu,
- enum pp_xgmi_plpd_mode mode);
-
- /**
* @update_pcie_parameters: Update and upload the system's PCIe
* capabilites to the SMU.
* &pcie_gen_cap: Maximum allowed PCIe generation.
@@ -1551,6 +1565,12 @@ typedef struct {
uint32_t MmHubPadding[8];
} WifiBandEntryTable_t;
+#define STR_SOC_PSTATE_POLICY "soc_pstate"
+#define STR_XGMI_PLPD_POLICY "xgmi_plpd"
+
+struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu,
+ enum pp_pm_policy p_type);
+
#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
int smu_get_power_limit(void *handle,
uint32_t *limit,
@@ -1598,5 +1618,10 @@ void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev);
int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size);
int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size);
int smu_send_rma_reason(struct smu_context *smu);
+int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type,
+ int level);
+ssize_t smu_get_pm_policy_info(struct smu_context *smu,
+ enum pp_pm_policy p_type, char *sysbuf);
+
#endif
#endif