diff options
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 240 |
1 files changed, 48 insertions, 192 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index a78b2e295895..6109815a0401 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -26,6 +26,7 @@ #include "kgd_pp_interface.h" #include "dm_pp_interface.h" #include "dm_pp_smu.h" +#include "smu_types.h" #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 @@ -150,124 +151,6 @@ struct smu_power_state { struct smu_hw_power_state hardware; }; -enum smu_message_type -{ - SMU_MSG_TestMessage = 0, - SMU_MSG_GetSmuVersion, - SMU_MSG_GetDriverIfVersion, - SMU_MSG_SetAllowedFeaturesMaskLow, - SMU_MSG_SetAllowedFeaturesMaskHigh, - SMU_MSG_EnableAllSmuFeatures, - SMU_MSG_DisableAllSmuFeatures, - SMU_MSG_EnableSmuFeaturesLow, - SMU_MSG_EnableSmuFeaturesHigh, - SMU_MSG_DisableSmuFeaturesLow, - SMU_MSG_DisableSmuFeaturesHigh, - SMU_MSG_GetEnabledSmuFeaturesLow, - SMU_MSG_GetEnabledSmuFeaturesHigh, - SMU_MSG_SetWorkloadMask, - SMU_MSG_SetPptLimit, - SMU_MSG_SetDriverDramAddrHigh, - SMU_MSG_SetDriverDramAddrLow, - SMU_MSG_SetToolsDramAddrHigh, - SMU_MSG_SetToolsDramAddrLow, - SMU_MSG_TransferTableSmu2Dram, - SMU_MSG_TransferTableDram2Smu, - SMU_MSG_UseDefaultPPTable, - SMU_MSG_UseBackupPPTable, - SMU_MSG_RunBtc, - SMU_MSG_RequestI2CBus, - SMU_MSG_ReleaseI2CBus, - SMU_MSG_SetFloorSocVoltage, - SMU_MSG_SoftReset, - SMU_MSG_StartBacoMonitor, - SMU_MSG_CancelBacoMonitor, - SMU_MSG_EnterBaco, - SMU_MSG_SetSoftMinByFreq, - SMU_MSG_SetSoftMaxByFreq, - SMU_MSG_SetHardMinByFreq, - SMU_MSG_SetHardMaxByFreq, - SMU_MSG_GetMinDpmFreq, - SMU_MSG_GetMaxDpmFreq, - SMU_MSG_GetDpmFreqByIndex, - SMU_MSG_GetDpmClockFreq, - SMU_MSG_GetSsVoltageByDpm, - SMU_MSG_SetMemoryChannelConfig, - SMU_MSG_SetGeminiMode, - SMU_MSG_SetGeminiApertureHigh, - SMU_MSG_SetGeminiApertureLow, - SMU_MSG_SetMinLinkDpmByIndex, - SMU_MSG_OverridePcieParameters, - SMU_MSG_OverDriveSetPercentage, - SMU_MSG_SetMinDeepSleepDcefclk, - SMU_MSG_ReenableAcDcInterrupt, - SMU_MSG_NotifyPowerSource, - SMU_MSG_SetUclkFastSwitch, - SMU_MSG_SetUclkDownHyst, - SMU_MSG_GfxDeviceDriverReset, - SMU_MSG_GetCurrentRpm, - SMU_MSG_SetVideoFps, - SMU_MSG_SetTjMax, - SMU_MSG_SetFanTemperatureTarget, - SMU_MSG_PrepareMp1ForUnload, - SMU_MSG_DramLogSetDramAddrHigh, - SMU_MSG_DramLogSetDramAddrLow, - SMU_MSG_DramLogSetDramSize, - SMU_MSG_SetFanMaxRpm, - SMU_MSG_SetFanMinPwm, - SMU_MSG_ConfigureGfxDidt, - SMU_MSG_NumOfDisplays, - SMU_MSG_RemoveMargins, - SMU_MSG_ReadSerialNumTop32, - SMU_MSG_ReadSerialNumBottom32, - SMU_MSG_SetSystemVirtualDramAddrHigh, - SMU_MSG_SetSystemVirtualDramAddrLow, - SMU_MSG_WaflTest, - SMU_MSG_SetFclkGfxClkRatio, - SMU_MSG_AllowGfxOff, - SMU_MSG_DisallowGfxOff, - SMU_MSG_GetPptLimit, - SMU_MSG_GetDcModeMaxDpmFreq, - SMU_MSG_GetDebugData, - SMU_MSG_SetXgmiMode, - SMU_MSG_RunAfllBtc, - SMU_MSG_ExitBaco, - SMU_MSG_PrepareMp1ForReset, - SMU_MSG_PrepareMp1ForShutdown, - SMU_MSG_SetMGpuFanBoostLimitRpm, - SMU_MSG_GetAVFSVoltageByDpm, - SMU_MSG_PowerUpVcn, - SMU_MSG_PowerDownVcn, - SMU_MSG_PowerUpJpeg, - SMU_MSG_PowerDownJpeg, - SMU_MSG_BacoAudioD3PME, - SMU_MSG_ArmD3, - SMU_MSG_MAX_COUNT, -}; - -enum smu_clk_type -{ - SMU_GFXCLK, - SMU_VCLK, - SMU_DCLK, - SMU_ECLK, - SMU_SOCCLK, - SMU_UCLK, - SMU_DCEFCLK, - SMU_DISPCLK, - SMU_PIXCLK, - SMU_PHYCLK, - SMU_FCLK, - SMU_SCLK, - SMU_MCLK, - SMU_PCIE, - SMU_OD_SCLK, - SMU_OD_MCLK, - SMU_OD_VDDC_CURVE, - SMU_OD_RANGE, - SMU_CLK_COUNT, -}; - enum smu_power_src_type { SMU_POWER_SOURCE_AC, @@ -275,63 +158,6 @@ enum smu_power_src_type SMU_POWER_SOURCE_COUNT, }; -enum smu_feature_mask -{ - SMU_FEATURE_DPM_PREFETCHER_BIT, - SMU_FEATURE_DPM_GFXCLK_BIT, - SMU_FEATURE_DPM_UCLK_BIT, - SMU_FEATURE_DPM_SOCCLK_BIT, - SMU_FEATURE_DPM_UVD_BIT, - SMU_FEATURE_DPM_VCE_BIT, - SMU_FEATURE_ULV_BIT, - SMU_FEATURE_DPM_MP0CLK_BIT, - SMU_FEATURE_DPM_LINK_BIT, - SMU_FEATURE_DPM_DCEFCLK_BIT, - SMU_FEATURE_DS_GFXCLK_BIT, - SMU_FEATURE_DS_SOCCLK_BIT, - SMU_FEATURE_DS_LCLK_BIT, - SMU_FEATURE_PPT_BIT, - SMU_FEATURE_TDC_BIT, - SMU_FEATURE_THERMAL_BIT, - SMU_FEATURE_GFX_PER_CU_CG_BIT, - SMU_FEATURE_RM_BIT, - SMU_FEATURE_DS_DCEFCLK_BIT, - SMU_FEATURE_ACDC_BIT, - SMU_FEATURE_VR0HOT_BIT, - SMU_FEATURE_VR1HOT_BIT, - SMU_FEATURE_FW_CTF_BIT, - SMU_FEATURE_LED_DISPLAY_BIT, - SMU_FEATURE_FAN_CONTROL_BIT, - SMU_FEATURE_GFX_EDC_BIT, - SMU_FEATURE_GFXOFF_BIT, - SMU_FEATURE_CG_BIT, - SMU_FEATURE_DPM_FCLK_BIT, - SMU_FEATURE_DS_FCLK_BIT, - SMU_FEATURE_DS_MP1CLK_BIT, - SMU_FEATURE_DS_MP0CLK_BIT, - SMU_FEATURE_XGMI_BIT, - SMU_FEATURE_DPM_GFX_PACE_BIT, - SMU_FEATURE_MEM_VDDCI_SCALING_BIT, - SMU_FEATURE_MEM_MVDD_SCALING_BIT, - SMU_FEATURE_DS_UCLK_BIT, - SMU_FEATURE_GFX_ULV_BIT, - SMU_FEATURE_FW_DSTATE_BIT, - SMU_FEATURE_BACO_BIT, - SMU_FEATURE_VCN_PG_BIT, - SMU_FEATURE_JPEG_PG_BIT, - SMU_FEATURE_USB_PG_BIT, - SMU_FEATURE_RSMU_SMN_CG_BIT, - SMU_FEATURE_APCC_PLUS_BIT, - SMU_FEATURE_GTHR_BIT, - SMU_FEATURE_GFX_DCS_BIT, - SMU_FEATURE_GFX_SS_BIT, - SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT, - SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT, - SMU_FEATURE_MMHUB_PG_BIT, - SMU_FEATURE_ATHUB_PG_BIT, - SMU_FEATURE_COUNT, -}; - enum smu_memory_pool_size { SMU_MEMORY_POOL_SIZE_ZERO = 0, @@ -396,12 +222,17 @@ struct smu_bios_boot_up_values uint16_t vdd_gfx; uint8_t cooling_id; uint32_t pp_table_id; + uint32_t format_revision; + uint32_t content_revision; + uint32_t fclk; }; enum smu_table_id { SMU_TABLE_PPTABLE = 0, SMU_TABLE_WATERMARKS, + SMU_TABLE_CUSTOM_DPM, + SMU_TABLE_DPMCLOCKS, SMU_TABLE_AVFS, SMU_TABLE_AVFS_PSM_DEBUG, SMU_TABLE_AVFS_FUSE_OVERRIDE, @@ -422,6 +253,7 @@ struct smu_table_context void *hardcode_pptable; unsigned long metrics_time; void *metrics_table; + void *clocks_table; void *max_sustainable_clocks; struct smu_bios_boot_up_values boot_values; @@ -540,6 +372,8 @@ struct smu_context #define WATERMARKS_EXIST (1 << 0) #define WATERMARKS_LOADED (1 << 1) uint32_t watermarks_bitmap; + uint32_t hard_min_uclk_req_from_dal; + bool disable_uclk_switch; uint32_t workload_mask; uint32_t workload_prority[WORKLOAD_POLICY_MAX]; @@ -607,8 +441,6 @@ struct pptable_funcs { uint32_t *mclk_mask, uint32_t *soc_mask); int (*set_cpu_power_state)(struct smu_context *smu); - int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures); - int (*get_ppfeature_status)(struct smu_context *smu, char *buf); bool (*is_dpm_running)(struct smu_context *smu); int (*tables_init)(struct smu_context *smu, struct smu_table *tables); int (*set_thermal_fan_table)(struct smu_context *smu); @@ -623,6 +455,10 @@ struct pptable_funcs { int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); int (*set_default_od_settings)(struct smu_context *smu, bool initialize); int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); + int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); + void (*dump_pptable)(struct smu_context *smu); + int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default); + int (*get_dpm_uclk_limited)(struct smu_context *smu, uint32_t *clock, bool max); }; struct smu_funcs @@ -639,8 +475,11 @@ struct smu_funcs int (*get_clk_info_from_vbios)(struct smu_context *smu); int (*check_pptable)(struct smu_context *smu); int (*parse_pptable)(struct smu_context *smu); - int (*populate_smc_pptable)(struct smu_context *smu); + int (*populate_smc_tables)(struct smu_context *smu); int (*check_fw_version)(struct smu_context *smu); + int (*powergate_sdma)(struct smu_context *smu, bool gate); + int (*powergate_vcn)(struct smu_context *smu, bool gate); + int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); int (*write_pptable)(struct smu_context *smu); int (*set_min_dcef_deep_sleep)(struct smu_context *smu); int (*set_tool_table_location)(struct smu_context *smu); @@ -654,9 +493,7 @@ struct smu_funcs int (*init_display_count)(struct smu_context *smu, uint32_t count); int (*set_allowed_mask)(struct smu_context *smu); int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); - int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled); int (*notify_display_change)(struct smu_context *smu); - int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def); int (*set_power_limit)(struct smu_context *smu, uint32_t n); int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value); int (*init_max_sustainable_clocks)(struct smu_context *smu); @@ -700,7 +537,7 @@ struct smu_funcs enum smu_baco_state (*baco_get_state)(struct smu_context *smu); int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); int (*baco_reset)(struct smu_context *smu); - + int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); }; #define smu_init_microcode(smu) \ @@ -719,6 +556,12 @@ struct smu_funcs ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0) #define smu_setup_pptable(smu) \ ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0) +#define smu_powergate_sdma(smu, gate) \ + ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0) +#define smu_powergate_vcn(smu, gate) \ + ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0) +#define smu_set_gfx_cgpg(smu, enabled) \ + ((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0) #define smu_get_vbios_bootup_values(smu) \ ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0) #define smu_get_clk_info_from_vbios(smu) \ @@ -727,8 +570,8 @@ struct smu_funcs ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0) #define smu_parse_pptable(smu) \ ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0) -#define smu_populate_smc_pptable(smu) \ - ((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0) +#define smu_populate_smc_tables(smu) \ + ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0) #define smu_check_fw_version(smu) \ ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0) #define smu_write_pptable(smu) \ @@ -770,8 +613,6 @@ struct smu_funcs ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0) #define smu_is_dpm_running(smu) \ ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0) -#define smu_feature_update_enable_state(smu, feature_id, enabled) \ - ((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0) #define smu_notify_display_change(smu) \ ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0) #define smu_store_powerplay_table(smu) \ @@ -787,7 +628,7 @@ struct smu_funcs #define smu_set_default_od8_settings(smu) \ ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0) #define smu_get_power_limit(smu, limit, def) \ - ((smu)->funcs->get_power_limit ? (smu)->funcs->get_power_limit((smu), (limit), (def)) : 0) + ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0) #define smu_set_power_limit(smu, limit) \ ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0) #define smu_get_current_clk_freq(smu, clk_id, value) \ @@ -809,9 +650,9 @@ struct smu_funcs #define smu_start_thermal_control(smu) \ ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0) #define smu_read_sensor(smu, sensor, data, size) \ - ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : 0) -#define smu_asic_read_sensor(smu, sensor, data, size) \ ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0) +#define smu_smc_read_sensor(smu, sensor, data, size) \ + ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL) #define smu_get_power_profile_mode(smu, buf) \ ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0) #define smu_set_power_profile_mode(smu, param, param_size) \ @@ -875,6 +716,8 @@ struct smu_funcs ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0) #define smu_display_clock_voltage_request(smu, clock_req) \ ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0) +#define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \ + ((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL) #define smu_get_dal_power_level(smu, clocks) \ ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0) #define smu_get_perf_level(smu, designation, level) \ @@ -891,10 +734,6 @@ struct smu_funcs ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0) #define smu_set_xgmi_pstate(smu, pstate) \ ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0) -#define smu_set_ppfeature_status(smu, ppfeatures) \ - ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL) -#define smu_get_ppfeature_status(smu, buf) \ - ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL) #define smu_set_watermarks_table(smu, tab, clock_ranges) \ ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0) #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \ @@ -907,6 +746,8 @@ struct smu_funcs ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0) #define smu_set_azalia_d3_pme(smu) \ ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0) +#define smu_get_dpm_ultimate_freq(smu, param, min, max) \ + ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0) #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \ ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0) #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \ @@ -919,6 +760,10 @@ struct smu_funcs ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0) #define smu_asic_set_performance_level(smu, level) \ ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL); +#define smu_dump_pptable(smu) \ + ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0) +#define smu_get_dpm_uclk_limited(smu, clock, max) \ + ((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL) extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, @@ -928,6 +773,8 @@ extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, extern const struct amd_ip_funcs smu_ip_funcs; extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; +extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; + extern int smu_feature_init_dpm(struct smu_context *smu); extern int smu_feature_is_enabled(struct smu_context *smu, @@ -943,6 +790,7 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int void *table_data, bool drv2smu); bool is_support_sw_smu(struct amdgpu_device *adev); +bool is_support_sw_smu_xgmi(struct amdgpu_device *adev); int smu_reset(struct smu_context *smu); int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor, void *data, uint32_t *size); @@ -961,6 +809,9 @@ extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, b extern int smu_handle_task(struct smu_context *smu, enum amd_dpm_forced_level level, enum amd_pp_task task_id); +int smu_switch_power_profile(struct smu_context *smu, + enum PP_SMC_POWER_PROFILE type, + bool en); int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version); int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type, uint16_t level, uint32_t *value); @@ -976,5 +827,10 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu); int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level); int smu_set_display_count(struct smu_context *smu, uint32_t count); bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type); +int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled); +const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type); +const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature); +size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf); +int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask); #endif |