diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 69 |
1 files changed, 61 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index bdd0c8c4ef97..da154ff26b96 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -9,6 +9,11 @@ #include "i915_reg_defs.h" #include "intel_display_limits.h" +/* DDI Buffer Control */ +#define _DDI_CLK_VALFREQ_A 0x64030 +#define _DDI_CLK_VALFREQ_B 0x64130 +#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B) + /* * Wrapper macro to convert from port number to the index used in some of the * registers. For Display version 20 and above it converts the port number to a @@ -187,7 +192,9 @@ #define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19) #define XELPDP_TBT_CLOCK_ACK REG_BIT(18) #define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12) +#define XE3_DDI_CLOCK_SELECT_MASK REG_GENMASK(16, 12) #define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val) +#define XE3_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XE3_DDI_CLOCK_SELECT_MASK, val) #define XELPDP_DDI_CLOCK_SELECT_NONE 0x0 #define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8 #define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9 @@ -195,11 +202,20 @@ #define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd #define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe #define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf +#define XELPDP_DDI_CLOCK_SELECT_TBT_312_5 0x18 +#define XELPDP_DDI_CLOCK_SELECT_TBT_625 0x19 #define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10) #define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8) #define XELPDP_SSC_ENABLE_PLLA REG_BIT(1) #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0) +#define TCSS_DISP_MAILBOX_IN_CMD _MMIO(0x161300) +#define TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY REG_BIT(31) +#define TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK REG_GENMASK(7, 0) +#define TCSS_DISP_MAILBOX_IN_CMD_DATA(val) REG_FIELD_PREP(TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK, val) + +#define TCSS_DISP_MAILBOX_IN_DATA _MMIO(0x161304) + /* C10 Vendor Registers */ #define PHY_C10_VDR_PLL(idx) (0xC00 + (idx)) #define C10_PLL0_FRACEN REG_BIT8(4) @@ -254,18 +270,52 @@ #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02 #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0) #define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val) -#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx)) -#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx)) + +#define _MTL_C20_A_TX_CNTX_CFG 0xCF2E +#define _MTL_C20_B_TX_CNTX_CFG 0xCF2A +#define _MTL_C20_A_CMN_CNTX_CFG 0xCDAA +#define _MTL_C20_B_CMN_CNTX_CFG 0xCDA5 +#define _MTL_C20_A_MPLLA_CFG 0xCCF0 +#define _MTL_C20_B_MPLLA_CFG 0xCCE5 +#define _MTL_C20_A_MPLLB_CFG 0xCB5A +#define _MTL_C20_B_MPLLB_CFG 0xCB4E + +#define _XE2HPD_C20_A_TX_CNTX_CFG 0xCF5E +#define _XE2HPD_C20_B_TX_CNTX_CFG 0xCF5A +#define _XE2HPD_C20_A_CMN_CNTX_CFG 0xCE8E +#define _XE2HPD_C20_B_CMN_CNTX_CFG 0xCE89 +#define _XE2HPD_C20_A_MPLLA_CFG 0xCE58 +#define _XE2HPD_C20_B_MPLLA_CFG 0xCE4D +#define _XE2HPD_C20_A_MPLLB_CFG 0xCCC2 +#define _XE2HPD_C20_B_MPLLB_CFG 0xCCB6 + +#define _IS_XE2HPD_C20(i915) (DISPLAY_VERx100(i915) == 1401) + +#define PHY_C20_A_TX_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx)) +#define PHY_C20_B_TX_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx)) #define C20_PHY_TX_RATE REG_GENMASK(2, 0) -#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx)) -#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx)) -#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx)) -#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx)) +#define C20_PHY_TX_MISC_MASK REG_GENMASK16(7, 0) +#define C20_PHY_TX_MISC(val) REG_FIELD_PREP16(C20_PHY_TX_MISC_MASK, (val)) + +#define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx)) +#define PHY_C20_B_CMN_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_CMN_CNTX_CFG : _MTL_C20_B_CMN_CNTX_CFG) - (idx)) +#define PHY_C20_A_MPLLA_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLA_CFG : _MTL_C20_A_MPLLA_CFG) - (idx)) +#define PHY_C20_B_MPLLA_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLA_CFG : _MTL_C20_B_MPLLA_CFG) - (idx)) #define C20_MPLLA_FRACEN REG_BIT(14) #define C20_FB_CLK_DIV4_EN REG_BIT(13) #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8) -#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx)) -#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx)) + +#define PHY_C20_A_MPLLB_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLB_CFG : _MTL_C20_A_MPLLB_CFG) - (idx)) +#define PHY_C20_B_MPLLB_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLB_CFG : _MTL_C20_B_MPLLB_CFG) - (idx)) + #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13) #define C20_MPLLB_FRACEN REG_BIT(13) #define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10) @@ -331,4 +381,7 @@ #define HDMI_DIV_MASK REG_GENMASK16(2, 0) #define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val) +#define PICA_PHY_CONFIG_CONTROL _MMIO(0x16FE68) +#define EDP_ON_TYPEC REG_BIT(31) + #endif /* __INTEL_CX0_REG_DEFS_H__ */ |