diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display.c | 40 |
1 files changed, 34 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9e9c03287869..3c7ef2cc3b8b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2389,17 +2389,45 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n, intel_reduce_m_n_ratio(ret_m, ret_n); } +static void +add_bw_alloc_overhead(int link_clock, int bw_overhead, + int pixel_data_rate, int link_data_rate, + u32 *data_m, u32 *data_n) +{ + bool is_uhbr = intel_dp_is_uhbr_rate(link_clock); + int ch_coding_efficiency = + drm_dp_bw_channel_coding_efficiency(is_uhbr); + + /* + * TODO: adjust for actual UHBR channel coding efficiency and BW + * overhead. + */ + if (is_uhbr) { + *data_m = pixel_data_rate; + *data_n = link_data_rate * 8 / 10; + return; + } + + *data_m = DIV_ROUND_UP_ULL(mul_u32_u32(pixel_data_rate, bw_overhead), + 1000000); + *data_n = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_data_rate, ch_coding_efficiency), + 1000000); +} + void intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, int pixel_clock, int link_clock, - struct intel_link_m_n *m_n, - bool fec_enable) + int bw_overhead, + struct intel_link_m_n *m_n) { u32 data_clock = bits_per_pixel * pixel_clock; + u32 data_m; + u32 data_n; - if (fec_enable) - data_clock = intel_dp_mode_to_fec_clock(data_clock); - + add_bw_alloc_overhead(link_clock, bw_overhead, + data_clock, + link_clock * 10 * nlanes, + &data_m, &data_n); /* * Windows/BIOS uses fixed M/N values always. Follow suit. * @@ -2409,7 +2437,7 @@ intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, */ m_n->tu = 64; compute_m_n(&m_n->data_m, &m_n->data_n, - data_clock, link_clock * nlanes * 8, + data_m, data_n, 0x8000000); compute_m_n(&m_n->link_m, &m_n->link_n, |