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path: root/drivers/gpu/drm/i915/display/intel_display_irq.c
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Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_irq.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_display_irq.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index afcd2af82942..d85c33eabc47 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -14,6 +14,7 @@
#include "intel_display_trace.h"
#include "intel_display_types.h"
#include "intel_dp_aux.h"
+#include "intel_dsb.h"
#include "intel_fdi_regs.h"
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
@@ -1164,6 +1165,17 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (iir & gen8_de_pipe_flip_done_mask(dev_priv))
flip_done_handler(dev_priv, pipe);
+ if (HAS_DSB(dev_priv)) {
+ if (iir & GEN12_DSB_INT(INTEL_DSB_0))
+ intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_0);
+
+ if (iir & GEN12_DSB_INT(INTEL_DSB_1))
+ intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_1);
+
+ if (iir & GEN12_DSB_INT(INTEL_DSB_2))
+ intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_2);
+ }
+
if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
hsw_pipe_crc_irq_handler(dev_priv, pipe);
@@ -1736,6 +1748,11 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_port_masked |= DSI0_TE | DSI1_TE;
}
+ if (HAS_DSB(dev_priv))
+ de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) |
+ GEN12_DSB_INT(INTEL_DSB_1) |
+ GEN12_DSB_INT(INTEL_DSB_2);
+
de_pipe_enables = de_pipe_masked |
GEN8_PIPE_VBLANK |
gen8_de_pipe_underrun_mask(dev_priv) |