summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display/intel_dsb.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dsb.h')
-rw-r--r--drivers/gpu/drm/i915/display/intel_dsb.h93
1 files changed, 59 insertions, 34 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 395ef9ce558e..2f31f2c1d0c5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -8,45 +8,70 @@
#include <linux/types.h>
-#include "i915_reg.h"
+#include "i915_reg_defs.h"
+struct intel_atomic_state;
struct intel_crtc;
-struct i915_vma;
-
-enum dsb_id {
- INVALID_DSB = -1,
- DSB1,
- DSB2,
- DSB3,
- MAX_DSB_PER_PIPE
-};
+struct intel_crtc_state;
+struct intel_display;
+struct intel_dsb;
+
+enum pipe;
+
+enum intel_dsb_id {
+ INTEL_DSB_0,
+ INTEL_DSB_1,
+ INTEL_DSB_2,
-struct intel_dsb {
- long refcount;
- enum dsb_id id;
- u32 *cmd_buf;
- struct i915_vma *vma;
-
- /*
- * free_pos will point the first free entry position
- * and help in calculating tail of command buffer.
- */
- int free_pos;
-
- /*
- * ins_start_offset will help to store start address of the dsb
- * instuction and help in identifying the batch of auto-increment
- * register.
- */
- u32 ins_start_offset;
+ I915_MAX_DSBS,
};
-struct intel_dsb *
-intel_dsb_get(struct intel_crtc *crtc);
-void intel_dsb_put(struct intel_dsb *dsb);
-void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
-void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
- u32 val);
+unsigned int intel_dsb_size(struct intel_dsb *dsb);
+unsigned int intel_dsb_head(struct intel_dsb *dsb);
+struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ enum intel_dsb_id dsb_id,
+ unsigned int max_cmds);
+void intel_dsb_finish(struct intel_dsb *dsb);
+void intel_dsb_gosub_finish(struct intel_dsb *dsb);
+void intel_dsb_cleanup(struct intel_dsb *dsb);
+int intel_dsb_exec_time_us(void);
+void intel_dsb_reg_write(struct intel_dsb *dsb,
+ i915_reg_t reg, u32 val);
+void intel_dsb_reg_write_indexed(struct intel_dsb *dsb,
+ i915_reg_t reg, u32 val);
+void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
+ i915_reg_t reg, u32 mask, u32 val);
+void intel_dsb_noop(struct intel_dsb *dsb, int count);
+void intel_dsb_nonpost_start(struct intel_dsb *dsb);
+void intel_dsb_nonpost_end(struct intel_dsb *dsb);
+void intel_dsb_interrupt(struct intel_dsb *dsb);
+void intel_dsb_wait_usec(struct intel_dsb *dsb, int count);
+void intel_dsb_wait_vblanks(struct intel_dsb *dsb, int count);
+void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
+ struct intel_dsb *dsb);
+void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
+ struct intel_dsb *dsb,
+ int lower, int upper);
+void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
+ struct intel_dsb *dsb,
+ int lower, int upper);
+void intel_dsb_vblank_evade(struct intel_atomic_state *state,
+ struct intel_dsb *dsb);
+void intel_dsb_poll(struct intel_dsb *dsb,
+ i915_reg_t reg, u32 mask, u32 val,
+ int wait_us, int count);
+void intel_dsb_gosub(struct intel_dsb *dsb,
+ struct intel_dsb *sub_dsb);
+void intel_dsb_chain(struct intel_atomic_state *state,
+ struct intel_dsb *dsb,
+ struct intel_dsb *chained_dsb,
+ bool wait_for_vblank);
+
void intel_dsb_commit(struct intel_dsb *dsb);
+void intel_dsb_wait(struct intel_dsb *dsb);
+
+void intel_dsb_irq_handler(struct intel_display *display,
+ enum pipe pipe, enum intel_dsb_id dsb_id);
#endif