diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/skl_watermark.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/skl_watermark.h | 88 |
1 files changed, 47 insertions, 41 deletions
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h index 7a5a4e67cd73..6bc2ec9164bf 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.h +++ b/drivers/gpu/drm/i915/display/skl_watermark.h @@ -8,73 +8,79 @@ #include <linux/types.h> -#include "intel_display.h" -#include "intel_global_state.h" -#include "intel_pm_types.h" - -struct drm_i915_private; +enum plane_id; struct intel_atomic_state; -struct intel_bw_state; struct intel_crtc; struct intel_crtc_state; +struct intel_dbuf_state; +struct intel_display; struct intel_plane; +struct intel_plane_state; +struct skl_ddb_entry; +struct skl_pipe_wm; +struct skl_wm_level; -u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915); +u8 intel_enabled_dbuf_slices_mask(struct intel_display *display); void intel_sagv_pre_plane_update(struct intel_atomic_state *state); void intel_sagv_post_plane_update(struct intel_atomic_state *state); -bool intel_can_enable_sagv(struct drm_i915_private *i915, - const struct intel_bw_state *bw_state); +bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state); +bool intel_has_sagv(struct intel_display *display); -u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915, +u32 skl_ddb_dbuf_slice_mask(struct intel_display *display, const struct skl_ddb_entry *entry); -void skl_write_plane_wm(struct intel_plane *plane, - const struct intel_crtc_state *crtc_state); -void skl_write_cursor_wm(struct intel_plane *plane, - const struct intel_crtc_state *crtc_state); - bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, const struct skl_ddb_entry *entries, int num_entries, int ignore_idx); -void skl_wm_get_hw_state(struct drm_i915_private *i915); -void skl_wm_sanitize(struct drm_i915_private *i915); - -void intel_wm_state_verify(struct intel_crtc *crtc, - struct intel_crtc_state *new_crtc_state); +void intel_wm_state_verify(struct intel_atomic_state *state, + struct intel_crtc *crtc); -void skl_watermark_ipc_init(struct drm_i915_private *i915); -void skl_watermark_ipc_update(struct drm_i915_private *i915); -bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); -void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915); +void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc); +void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc, + struct intel_plane *plane); -void skl_wm_init(struct drm_i915_private *i915); +void skl_watermark_ipc_init(struct intel_display *display); +void skl_watermark_ipc_update(struct intel_display *display); +bool skl_watermark_ipc_enabled(struct intel_display *display); +void skl_watermark_debugfs_register(struct intel_display *display); -struct intel_dbuf_state { - struct intel_global_state base; +unsigned int skl_watermark_max_latency(struct intel_display *display, + int initial_wm_level); +void skl_wm_init(struct intel_display *display); - struct skl_ddb_entry ddb[I915_MAX_PIPES]; - unsigned int weight[I915_MAX_PIPES]; - u8 slices[I915_MAX_PIPES]; - u8 enabled_slices; - u8 active_pipes; - bool joined_mbus; -}; +const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, + enum plane_id plane_id, + int level); +const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, + enum plane_id plane_id); +unsigned int skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, + struct intel_plane *plane, int width, + int height, int cpp); struct intel_dbuf_state * intel_atomic_get_dbuf_state(struct intel_atomic_state *state); -#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base) -#define intel_atomic_get_old_dbuf_state(state) \ - to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj)) -#define intel_atomic_get_new_dbuf_state(state) \ - to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj)) +int intel_dbuf_num_enabled_slices(const struct intel_dbuf_state *dbuf_state); +int intel_dbuf_num_active_pipes(const struct intel_dbuf_state *dbuf_state); + +int intel_dbuf_init(struct intel_display *display); +int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, + int ratio); -int intel_dbuf_init(struct drm_i915_private *i915); void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); void intel_dbuf_post_plane_update(struct intel_atomic_state *state); -void intel_mbus_dbox_update(struct intel_atomic_state *state); +void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display, + int ratio, bool joined_mbus); +void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state); +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state); +void intel_program_dpkgc_latency(struct intel_atomic_state *state); + +bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state); + +unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state); +unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state); #endif /* __SKL_WATERMARK_H__ */ |