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path: root/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
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Diffstat (limited to 'drivers/gpu/drm/i915/pxp/intel_pxp_huc.c')
-rw-r--r--drivers/gpu/drm/i915/pxp/intel_pxp_huc.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
index 64609d1b1c0f..9fc575a3d0d5 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
@@ -3,6 +3,8 @@
* Copyright(c) 2021-2022, Intel Corporation. All rights reserved.
*/
+#include <drm/drm_print.h>
+
#include "i915_drv.h"
#include "gem/i915_gem_region.h"
@@ -18,8 +20,8 @@ int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
{
struct intel_gt *gt;
struct intel_huc *huc;
- struct pxp43_start_huc_auth_in huc_in = {0};
- struct pxp43_start_huc_auth_out huc_out = {0};
+ struct pxp43_start_huc_auth_in huc_in = {};
+ struct pxp43_huc_auth_out huc_out = {};
dma_addr_t huc_phys_addr;
u8 client_id = 0;
u8 fence_id = 0;
@@ -38,7 +40,7 @@ int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
huc_in.header.command_id = PXP43_CMDID_START_HUC_AUTH;
huc_in.header.status = 0;
huc_in.header.buffer_len = sizeof(huc_in.huc_base_address);
- huc_in.huc_base_address = huc_phys_addr;
+ huc_in.huc_base_address = cpu_to_le64(huc_phys_addr);
err = intel_pxp_tee_stream_message(pxp, client_id, fence_id,
&huc_in, sizeof(huc_in),