diff options
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 411 |
1 files changed, 375 insertions, 36 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h index e788ed72eb0d..b49d8427b59e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */ +/* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ #ifndef _A6XX_CRASH_DUMP_H_ #define _A6XX_CRASH_DUMP_H_ @@ -51,6 +54,7 @@ static const u32 a6xx_pc_vs_cluster[] = { #define CLUSTER_SP_PS 4 #define CLUSTER_PS 5 #define CLUSTER_VPC_PS 6 +#define CLUSTER_NONE 7 #define CLUSTER(_id, _reg, _sel_reg, _sel_val) \ { .id = _id, .name = #_id,\ @@ -67,8 +71,8 @@ static const struct a6xx_cluster { u32 sel_val; } a6xx_clusters[] = { CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0), - CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0), - CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9), + CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0), + CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9), CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0), CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0), CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0), @@ -208,7 +212,7 @@ static const struct a6xx_shader_block { SHADER(A6XX_SP_LB_5_DATA, 0x200), SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x800), SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280), - SHADER(A6XX_SP_UAV_DATA, 0x80), + SHADER(A6XX_SP_GFX_UAV_BASE_DATA, 0x80), SHADER(A6XX_SP_INST_TAG, 0x80), SHADER(A6XX_SP_CB_BINDLESS_TAG, 0x80), SHADER(A6XX_SP_TMO_UMO_TAG, 0x80), @@ -299,8 +303,8 @@ static const u32 a660_registers[] = { static const struct a6xx_registers a6xx_reglist[] = { REGS(a6xx_registers, 0, 0), REGS(a660_registers, 0, 0), - REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0), - REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9), + REGS(a6xx_rb_rac_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0), + REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 9), }; static const u32 a6xx_ahb_registers[] = { @@ -328,9 +332,8 @@ static const u32 a6xx_gbif_registers[] = { 0x3C00, 0X3C0B, 0X3C40, 0X3C47, 0X3CC0, 0X3CD1, 0xE3A, 0xE3A, }; -static const struct a6xx_registers a6xx_ahb_reglist[] = { - REGS(a6xx_ahb_registers, 0, 0), -}; +static const struct a6xx_registers a6xx_ahb_reglist = + REGS(a6xx_ahb_registers, 0, 0); static const struct a6xx_registers a6xx_vbif_reglist = REGS(a6xx_vbif_registers, 0, 0); @@ -340,34 +343,48 @@ static const struct a6xx_registers a6xx_gbif_reglist = static const u32 a6xx_gmu_gx_registers[] = { /* GMU GX */ - 0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b, - 0x001e, 0x001e, 0x0020, 0x0023, 0x0026, 0x0026, 0x0028, 0x002b, - 0x002e, 0x002e, 0x0030, 0x0033, 0x0036, 0x0036, 0x0038, 0x003b, - 0x003e, 0x003e, 0x0040, 0x0043, 0x0046, 0x0046, 0x0080, 0x0084, - 0x0100, 0x012b, 0x0140, 0x0140, + 0x1a800, 0x1a800, 0x1a810, 0x1a813, 0x1a816, 0x1a816, 0x1a818, 0x1a81b, + 0x1a81e, 0x1a81e, 0x1a820, 0x1a823, 0x1a826, 0x1a826, 0x1a828, 0x1a82b, + 0x1a82e, 0x1a82e, 0x1a830, 0x1a833, 0x1a836, 0x1a836, 0x1a838, 0x1a83b, + 0x1a83e, 0x1a83e, 0x1a840, 0x1a843, 0x1a846, 0x1a846, 0x1a880, 0x1a884, + 0x1a900, 0x1a92b, 0x1a940, 0x1a940, }; static const u32 a6xx_gmu_cx_registers[] = { /* GMU CX */ - 0x4c00, 0x4c07, 0x4c10, 0x4c12, 0x4d00, 0x4d00, 0x4d07, 0x4d0a, - 0x5000, 0x5004, 0x5007, 0x5008, 0x500b, 0x500c, 0x500f, 0x501c, - 0x5024, 0x502a, 0x502d, 0x5030, 0x5040, 0x5053, 0x5087, 0x5089, - 0x50a0, 0x50a2, 0x50a4, 0x50af, 0x50c0, 0x50c3, 0x50d0, 0x50d0, - 0x50e4, 0x50e4, 0x50e8, 0x50ec, 0x5100, 0x5103, 0x5140, 0x5140, - 0x5142, 0x5144, 0x514c, 0x514d, 0x514f, 0x5151, 0x5154, 0x5154, - 0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165, - 0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc, - 0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201, + 0x1f400, 0x1f407, 0x1f410, 0x1f412, 0x1f500, 0x1f500, 0x1f507, 0x1f50a, + 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c, 0x1f80f, 0x1f81c, + 0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f887, 0x1f889, + 0x1f8a0, 0x1f8a2, 0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c3, 0x1f8d0, 0x1f8d0, + 0x1f8e4, 0x1f8e4, 0x1f8e8, 0x1f8ec, 0x1f900, 0x1f903, 0x1f940, 0x1f940, + 0x1f942, 0x1f944, 0x1f94c, 0x1f94d, 0x1f94f, 0x1f951, 0x1f954, 0x1f954, + 0x1f957, 0x1f958, 0x1f95d, 0x1f95d, 0x1f962, 0x1f962, 0x1f964, 0x1f965, + 0x1f980, 0x1f986, 0x1f990, 0x1f99e, 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9cc, + 0x1f9e0, 0x1f9e2, 0x1f9f0, 0x1f9f0, 0x1fa00, 0x1fa01, /* GMU AO */ - 0x9300, 0x9316, 0x9400, 0x9400, + 0x23b00, 0x23b16, 0x23c00, 0x23c00, +}; + +static const u32 a6xx_gmu_gpucc_registers[] = { /* GPU CC */ - 0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b, - 0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40, - 0x9c42, 0x9c49, 0x9c58, 0x9c5a, 0x9d40, 0x9d5e, 0xa000, 0xa002, - 0xa400, 0xa402, 0xac00, 0xac02, 0xb000, 0xb002, 0xb400, 0xb402, - 0xb800, 0xb802, + 0x24000, 0x24012, 0x24040, 0x24052, 0x24400, 0x24404, 0x24407, 0x2440b, + 0x24415, 0x2441c, 0x2441e, 0x2442d, 0x2443c, 0x2443d, 0x2443f, 0x24440, + 0x24442, 0x24449, 0x24458, 0x2445a, 0x24540, 0x2455e, 0x24800, 0x24802, + 0x24c00, 0x24c02, 0x25400, 0x25402, 0x25800, 0x25802, 0x25c00, 0x25c02, + 0x26000, 0x26002, /* GPU CC ACD */ - 0xbc00, 0xbc16, 0xbc20, 0xbc27, + 0x26400, 0x26416, 0x26420, 0x26427, +}; + +static const u32 a621_gmu_gpucc_registers[] = { + /* GPU CC */ + 0x24000, 0x2400e, 0x24400, 0x2440e, 0x25800, 0x25804, 0x25c00, 0x25c04, + 0x26000, 0x26004, 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x26430, + 0x26432, 0x26432, 0x26441, 0x26455, 0x26466, 0x26468, 0x26478, 0x2647a, + 0x26489, 0x2648a, 0x2649c, 0x2649e, 0x264a0, 0x264a3, 0x264b3, 0x264b5, + 0x264c5, 0x264c7, 0x264d6, 0x264d8, 0x264e8, 0x264e9, 0x264f9, 0x264fc, + 0x2650b, 0x2650c, 0x2651c, 0x2651e, 0x26540, 0x26570, 0x26600, 0x26616, + 0x26620, 0x2662d, }; static const u32 a6xx_gmu_cx_rscc_registers[] = { @@ -383,30 +400,68 @@ static const struct a6xx_registers a6xx_gmu_reglist[] = { REGS(a6xx_gmu_gx_registers, 0, 0), }; +static const struct a6xx_registers a6xx_gpucc_reg = REGS(a6xx_gmu_gpucc_registers, 0, 0); +static const struct a6xx_registers a621_gpucc_reg = REGS(a621_gmu_gpucc_registers, 0, 0); + static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu); +static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu); -static struct a6xx_indexed_registers { +struct a6xx_indexed_registers { const char *name; u32 addr; u32 data; u32 count; u32 (*count_fn)(struct msm_gpu *gpu); -} a6xx_indexed_reglist[] = { +}; + +static const struct a6xx_indexed_registers a6xx_indexed_reglist[] = { { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR, REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL }, { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL }, - { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, + { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL }, - { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR, + { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR, REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size}, }; -static struct a6xx_indexed_registers a6xx_cp_mempool_indexed = { - "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR, +static const struct a6xx_indexed_registers a7xx_indexed_reglist[] = { + { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR, + REG_A6XX_CP_SQE_STAT_DATA, 0x40, NULL }, + { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, + REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL }, + { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, + REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL }, + { "CP_BV_SQE_STAT", REG_A7XX_CP_BV_SQE_STAT_ADDR, + REG_A7XX_CP_BV_SQE_STAT_DATA, 0x40, NULL }, + { "CP_BV_DRAW_STATE", REG_A7XX_CP_BV_DRAW_STATE_ADDR, + REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL }, + { "CP_BV_SQE_UCODE_DBG", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR, + REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x8000, NULL }, + { "CP_SQE_AC_STAT", REG_A7XX_CP_SQE_AC_STAT_ADDR, + REG_A7XX_CP_SQE_AC_STAT_DATA, 0x40, NULL }, + { "CP_LPAC_DRAW_STATE", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, + REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL }, + { "CP_SQE_AC_UCODE_DBG", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR, + REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x8000, NULL }, + { "CP_LPAC_FIFO_DBG", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR, + REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x40, NULL }, + { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR, + REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size }, +}; + +static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = { + "CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR, REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL, }; +static const struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = { + { "CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR, + REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2200, NULL }, + { "CP_BV_MEM_POOL_DBG", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR, + REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2200, NULL }, +}; + #define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count } static const struct a6xx_debugbus_block { @@ -479,4 +534,288 @@ static const struct a6xx_debugbus_block a650_debugbus_blocks[] = { DEBUGBUS(A6XX_DBGBUS_SPTP_5, 0x100), }; +static const u32 a7xx_gbif_debugbus_blocks[] = { + A7XX_DBGBUS_GBIF_CX, + A7XX_DBGBUS_GBIF_GX, +}; + +static const struct a6xx_debugbus_block a7xx_cx_debugbus_blocks[] = { + DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100), + DEBUGBUS(A7XX_DBGBUS_CX, 0x100), + DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100), +}; + +#define STATE_NON_CONTEXT 0 +#define STATE_TOGGLE_CTXT 1 +#define STATE_FORCE_CTXT_0 2 +#define STATE_FORCE_CTXT_1 3 + +struct gen7_sel_reg { + unsigned int host_reg; + unsigned int cd_reg; + unsigned int val; +}; + +struct gen7_cluster_registers { + /* cluster_id: Cluster identifier */ + int cluster_id; + /* pipe_id: Pipe Identifier */ + int pipe_id; + /* context_id: one of STATE_ that identifies the context to dump */ + int context_id; + /* regs: Pointer to an array of register pairs */ + const u32 *regs; + /* sel: Pointer to a selector register to write before reading */ + const struct gen7_sel_reg *sel; +}; + +struct gen7_sptp_cluster_registers { + /* cluster_id: Cluster identifier */ + enum a7xx_cluster cluster_id; + /* statetype: SP block state type for the cluster */ + enum a7xx_statetype_id statetype; + /* pipe_id: Pipe identifier */ + enum adreno_pipe pipe_id; + /* context_id: Context identifier */ + int context_id; + /* location_id: Location identifier */ + enum a7xx_state_location location_id; + /* regs: Pointer to the list of register pairs to read */ + const u32 *regs; + /* regbase: Dword offset of the register block in the GPu register space */ + unsigned int regbase; +}; + +struct gen7_shader_block { + /* statetype: Type identifer for the block */ + u32 statetype; + /* size: Size of the block (in dwords) */ + u32 size; + /* num_sps: The SP id to dump */ + u32 num_sps; + /* num_usptps: The number of USPTPs to dump */; + u32 num_usptps; + /* pipe_id: Pipe identifier for the block data */ + u32 pipeid; + /* location: Location identifer for the block data */ + u32 location; +}; + +struct gen7_reg_list { + const u32 *regs; + const struct gen7_sel_reg *sel; +}; + +/* adreno_gen7_x_y_snapshot.h defines which debugbus blocks a given family has, but the + * list of debugbus blocks is global on a7xx. + */ + +#define A7XX_DEBUGBUS(_id, _count) [_id] = { .id = _id, .name = #_id, .count = _count }, +static const struct a6xx_debugbus_block a7xx_debugbus_blocks[] = { + A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RBBM, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VSC, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_COM_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_GX, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_DBGC, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CX, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_LARC, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_SPTP, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_WRAPPER, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_6, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_7, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_6, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_7, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_8, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_9, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_10, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_11, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_6, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_7, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_8, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_9, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_10, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_11, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_SUBCORE, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_CORE, 0x100) +}; + +#define A7XX_NAME(enumval) [enumval] = #enumval +static const char *a7xx_statetype_names[] = { + A7XX_NAME(A7XX_TP0_NCTX_REG), + A7XX_NAME(A7XX_TP0_CTX0_3D_CVS_REG), + A7XX_NAME(A7XX_TP0_CTX0_3D_CPS_REG), + A7XX_NAME(A7XX_TP0_CTX1_3D_CVS_REG), + A7XX_NAME(A7XX_TP0_CTX1_3D_CPS_REG), + A7XX_NAME(A7XX_TP0_CTX2_3D_CPS_REG), + A7XX_NAME(A7XX_TP0_CTX3_3D_CPS_REG), + A7XX_NAME(A7XX_TP0_TMO_DATA), + A7XX_NAME(A7XX_TP0_SMO_DATA), + A7XX_NAME(A7XX_TP0_MIPMAP_BASE_DATA), + A7XX_NAME(A7XX_SP_NCTX_REG), + A7XX_NAME(A7XX_SP_CTX0_3D_CVS_REG), + A7XX_NAME(A7XX_SP_CTX0_3D_CPS_REG), + A7XX_NAME(A7XX_SP_CTX1_3D_CVS_REG), + A7XX_NAME(A7XX_SP_CTX1_3D_CPS_REG), + A7XX_NAME(A7XX_SP_CTX2_3D_CPS_REG), + A7XX_NAME(A7XX_SP_CTX3_3D_CPS_REG), + A7XX_NAME(A7XX_SP_INST_DATA), + A7XX_NAME(A7XX_SP_INST_DATA_1), + A7XX_NAME(A7XX_SP_LB_0_DATA), + A7XX_NAME(A7XX_SP_LB_1_DATA), + A7XX_NAME(A7XX_SP_LB_2_DATA), + A7XX_NAME(A7XX_SP_LB_3_DATA), + A7XX_NAME(A7XX_SP_LB_4_DATA), + A7XX_NAME(A7XX_SP_LB_5_DATA), + A7XX_NAME(A7XX_SP_LB_6_DATA), + A7XX_NAME(A7XX_SP_LB_7_DATA), + A7XX_NAME(A7XX_SP_CB_RAM), + A7XX_NAME(A7XX_SP_LB_13_DATA), + A7XX_NAME(A7XX_SP_LB_14_DATA), + A7XX_NAME(A7XX_SP_INST_TAG), + A7XX_NAME(A7XX_SP_INST_DATA_2), + A7XX_NAME(A7XX_SP_TMO_TAG), + A7XX_NAME(A7XX_SP_SMO_TAG), + A7XX_NAME(A7XX_SP_STATE_DATA), + A7XX_NAME(A7XX_SP_HWAVE_RAM), + A7XX_NAME(A7XX_SP_L0_INST_BUF), + A7XX_NAME(A7XX_SP_LB_8_DATA), + A7XX_NAME(A7XX_SP_LB_9_DATA), + A7XX_NAME(A7XX_SP_LB_10_DATA), + A7XX_NAME(A7XX_SP_LB_11_DATA), + A7XX_NAME(A7XX_SP_LB_12_DATA), + A7XX_NAME(A7XX_HLSQ_DATAPATH_DSTR_META), + A7XX_NAME(A7XX_HLSQ_L2STC_TAG_RAM), + A7XX_NAME(A7XX_HLSQ_L2STC_INFO_CMD), + A7XX_NAME(A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM), + A7XX_NAME(A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM), + A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM), + A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM), + A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_ICB_CVS_CB_BASE_TAG), + A7XX_NAME(A7XX_HLSQ_ICB_CPS_CB_BASE_TAG), + A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM), + A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM), + A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_1), + A7XX_NAME(A7XX_HLSQ_INST_RAM), + A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM), + A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM), + A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_INST_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM), + A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_INST_RAM_1), + A7XX_NAME(A7XX_HLSQ_STPROC_META), + A7XX_NAME(A7XX_HLSQ_BV_BE_META), + A7XX_NAME(A7XX_HLSQ_INST_RAM_2), + A7XX_NAME(A7XX_HLSQ_DATAPATH_META), + A7XX_NAME(A7XX_HLSQ_FRONTEND_META), + A7XX_NAME(A7XX_HLSQ_INDIRECT_META), + A7XX_NAME(A7XX_HLSQ_BACKEND_META), +}; + +static const char *a7xx_pipe_names[] = { + A7XX_NAME(PIPE_NONE), + A7XX_NAME(PIPE_BR), + A7XX_NAME(PIPE_BV), + A7XX_NAME(PIPE_LPAC), +}; + +static const char *a7xx_cluster_names[] = { + A7XX_NAME(A7XX_CLUSTER_NONE), + A7XX_NAME(A7XX_CLUSTER_FE), + A7XX_NAME(A7XX_CLUSTER_SP_VS), + A7XX_NAME(A7XX_CLUSTER_PC_VS), + A7XX_NAME(A7XX_CLUSTER_GRAS), + A7XX_NAME(A7XX_CLUSTER_SP_PS), + A7XX_NAME(A7XX_CLUSTER_VPC_PS), + A7XX_NAME(A7XX_CLUSTER_PS), +}; + #endif |