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path: root/drivers/gpu/drm/msm/adreno/adreno_device.c
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Diffstat (limited to 'drivers/gpu/drm/msm/adreno/adreno_device.c')
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_device.c637
1 files changed, 231 insertions, 406 deletions
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 6dad8015c9a1..554d746f115b 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -8,8 +8,6 @@
#include "adreno_gpu.h"
-#define ANY_ID 0xff
-
bool hang_debug = false;
MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
module_param_named(hang_debug, hang_debug, bool, 0600);
@@ -18,325 +16,50 @@ bool snapshot_debugbus = false;
MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
-bool allow_vram_carveout = false;
-MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
-module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
-
-static const struct adreno_info gpulist[] = {
- {
- .rev = ADRENO_REV(2, 0, 0, 0),
- .revn = 200,
- .name = "A200",
- .fw = {
- [ADRENO_FW_PM4] = "yamato_pm4.fw",
- [ADRENO_FW_PFP] = "yamato_pfp.fw",
- },
- .gmem = SZ_256K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a2xx_gpu_init,
- }, { /* a200 on i.mx51 has only 128kib gmem */
- .rev = ADRENO_REV(2, 0, 0, 1),
- .revn = 201,
- .name = "A200",
- .fw = {
- [ADRENO_FW_PM4] = "yamato_pm4.fw",
- [ADRENO_FW_PFP] = "yamato_pfp.fw",
- },
- .gmem = SZ_128K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a2xx_gpu_init,
- }, {
- .rev = ADRENO_REV(2, 2, 0, ANY_ID),
- .revn = 220,
- .name = "A220",
- .fw = {
- [ADRENO_FW_PM4] = "leia_pm4_470.fw",
- [ADRENO_FW_PFP] = "leia_pfp_470.fw",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a2xx_gpu_init,
- }, {
- .rev = ADRENO_REV(3, 0, 5, ANY_ID),
- .revn = 305,
- .name = "A305",
- .fw = {
- [ADRENO_FW_PM4] = "a300_pm4.fw",
- [ADRENO_FW_PFP] = "a300_pfp.fw",
- },
- .gmem = SZ_256K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- .rev = ADRENO_REV(3, 0, 6, 0),
- .revn = 307, /* because a305c is revn==306 */
- .name = "A306",
- .fw = {
- [ADRENO_FW_PM4] = "a300_pm4.fw",
- [ADRENO_FW_PFP] = "a300_pfp.fw",
- },
- .gmem = SZ_128K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
- .revn = 320,
- .name = "A320",
- .fw = {
- [ADRENO_FW_PM4] = "a300_pm4.fw",
- [ADRENO_FW_PFP] = "a300_pfp.fw",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- .rev = ADRENO_REV(3, 3, 0, ANY_ID),
- .revn = 330,
- .name = "A330",
- .fw = {
- [ADRENO_FW_PM4] = "a330_pm4.fw",
- [ADRENO_FW_PFP] = "a330_pfp.fw",
- },
- .gmem = SZ_1M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- .rev = ADRENO_REV(4, 0, 5, ANY_ID),
- .revn = 405,
- .name = "A405",
- .fw = {
- [ADRENO_FW_PM4] = "a420_pm4.fw",
- [ADRENO_FW_PFP] = "a420_pfp.fw",
- },
- .gmem = SZ_256K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a4xx_gpu_init,
- }, {
- .rev = ADRENO_REV(4, 2, 0, ANY_ID),
- .revn = 420,
- .name = "A420",
- .fw = {
- [ADRENO_FW_PM4] = "a420_pm4.fw",
- [ADRENO_FW_PFP] = "a420_pfp.fw",
- },
- .gmem = (SZ_1M + SZ_512K),
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a4xx_gpu_init,
- }, {
- .rev = ADRENO_REV(4, 3, 0, ANY_ID),
- .revn = 430,
- .name = "A430",
- .fw = {
- [ADRENO_FW_PM4] = "a420_pm4.fw",
- [ADRENO_FW_PFP] = "a420_pfp.fw",
- },
- .gmem = (SZ_1M + SZ_512K),
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a4xx_gpu_init,
- }, {
- .rev = ADRENO_REV(5, 0, 8, ANY_ID),
- .revn = 508,
- .name = "A508",
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = (SZ_128K + SZ_8K),
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- .zapfw = "a508_zap.mdt",
- }, {
- .rev = ADRENO_REV(5, 0, 9, ANY_ID),
- .revn = 509,
- .name = "A509",
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = (SZ_256K + SZ_16K),
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- /* Adreno 509 uses the same ZAP as 512 */
- .zapfw = "a512_zap.mdt",
- }, {
- .rev = ADRENO_REV(5, 1, 0, ANY_ID),
- .revn = 510,
- .name = "A510",
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = SZ_256K,
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .init = a5xx_gpu_init,
- }, {
- .rev = ADRENO_REV(5, 1, 2, ANY_ID),
- .revn = 512,
- .name = "A512",
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = (SZ_256K + SZ_16K),
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- .zapfw = "a512_zap.mdt",
- }, {
- .rev = ADRENO_REV(5, 3, 0, 2),
- .revn = 530,
- .name = "A530",
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
- },
- .gmem = SZ_1M,
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
- ADRENO_QUIRK_FAULT_DETECT_MASK,
- .init = a5xx_gpu_init,
- .zapfw = "a530_zap.mdt",
- }, {
- .rev = ADRENO_REV(5, 4, 0, ANY_ID),
- .revn = 540,
- .name = "A540",
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- [ADRENO_FW_GPMU] = "a540_gpmu.fw2",
- },
- .gmem = SZ_1M,
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- .zapfw = "a540_zap.mdt",
- }, {
- .rev = ADRENO_REV(6, 1, 8, ANY_ID),
- .revn = 618,
- .name = "A618",
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a630_gmu.bin",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a6xx_gpu_init,
- }, {
- .rev = ADRENO_REV(6, 3, 0, ANY_ID),
- .revn = 630,
- .name = "A630",
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a630_gmu.bin",
- },
- .gmem = SZ_1M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a6xx_gpu_init,
- .zapfw = "a630_zap.mdt",
- .hwcg = a630_hwcg,
- }, {
- .rev = ADRENO_REV(6, 4, 0, ANY_ID),
- .revn = 640,
- .name = "A640",
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a640_gmu.bin",
- },
- .gmem = SZ_1M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a6xx_gpu_init,
- .zapfw = "a640_zap.mdt",
- .hwcg = a640_hwcg,
- }, {
- .rev = ADRENO_REV(6, 5, 0, ANY_ID),
- .revn = 650,
- .name = "A650",
- .fw = {
- [ADRENO_FW_SQE] = "a650_sqe.fw",
- [ADRENO_FW_GMU] = "a650_gmu.bin",
- },
- .gmem = SZ_1M + SZ_128K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a6xx_gpu_init,
- .zapfw = "a650_zap.mdt",
- .hwcg = a650_hwcg,
- }, {
- .rev = ADRENO_REV(6, 6, 0, ANY_ID),
- .revn = 660,
- .name = "A660",
- .fw = {
- [ADRENO_FW_SQE] = "a660_sqe.fw",
- [ADRENO_FW_GMU] = "a660_gmu.bin",
- },
- .gmem = SZ_1M + SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a6xx_gpu_init,
- .zapfw = "a660_zap.mdt",
- .hwcg = a660_hwcg,
- },
+int enable_preemption = -1;
+MODULE_PARM_DESC(enable_preemption, "Enable preemption (A7xx only) (1=on , 0=disable, -1=auto (default))");
+module_param(enable_preemption, int, 0600);
+
+bool disable_acd;
+MODULE_PARM_DESC(disable_acd, "Forcefully disable GPU ACD");
+module_param_unsafe(disable_acd, bool, 0400);
+
+static bool skip_gpu;
+MODULE_PARM_DESC(no_gpu, "Disable GPU driver register (0=enable GPU driver register (default), 1=skip GPU driver register");
+module_param(skip_gpu, bool, 0400);
+
+extern const struct adreno_gpulist a2xx_gpulist;
+extern const struct adreno_gpulist a3xx_gpulist;
+extern const struct adreno_gpulist a4xx_gpulist;
+extern const struct adreno_gpulist a5xx_gpulist;
+extern const struct adreno_gpulist a6xx_gpulist;
+extern const struct adreno_gpulist a7xx_gpulist;
+extern const struct adreno_gpulist a8xx_gpulist;
+
+static const struct adreno_gpulist *gpulists[] = {
+ &a2xx_gpulist,
+ &a3xx_gpulist,
+ &a4xx_gpulist,
+ &a5xx_gpulist,
+ &a6xx_gpulist,
+ &a7xx_gpulist,
+ &a8xx_gpulist,
};
-MODULE_FIRMWARE("qcom/a300_pm4.fw");
-MODULE_FIRMWARE("qcom/a300_pfp.fw");
-MODULE_FIRMWARE("qcom/a330_pm4.fw");
-MODULE_FIRMWARE("qcom/a330_pfp.fw");
-MODULE_FIRMWARE("qcom/a420_pm4.fw");
-MODULE_FIRMWARE("qcom/a420_pfp.fw");
-MODULE_FIRMWARE("qcom/a530_pm4.fw");
-MODULE_FIRMWARE("qcom/a530_pfp.fw");
-MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
-MODULE_FIRMWARE("qcom/a530_zap.mdt");
-MODULE_FIRMWARE("qcom/a530_zap.b00");
-MODULE_FIRMWARE("qcom/a530_zap.b01");
-MODULE_FIRMWARE("qcom/a530_zap.b02");
-MODULE_FIRMWARE("qcom/a630_sqe.fw");
-MODULE_FIRMWARE("qcom/a630_gmu.bin");
-MODULE_FIRMWARE("qcom/a630_zap.mbn");
-
-static inline bool _rev_match(uint8_t entry, uint8_t id)
+static const struct adreno_info *adreno_info(uint32_t chip_id)
{
- return (entry == ANY_ID) || (entry == id);
-}
+ /* identify gpu: */
+ for (int i = 0; i < ARRAY_SIZE(gpulists); i++) {
+ for (int j = 0; j < gpulists[i]->gpus_count; j++) {
+ const struct adreno_info *info = &gpulists[i]->gpus[j];
-const struct adreno_info *adreno_info(struct adreno_rev rev)
-{
- int i;
+ if (info->machine && !of_machine_is_compatible(info->machine))
+ continue;
- /* identify gpu: */
- for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
- const struct adreno_info *info = &gpulist[i];
- if (_rev_match(info->rev.core, rev.core) &&
- _rev_match(info->rev.major, rev.major) &&
- _rev_match(info->rev.minor, rev.minor) &&
- _rev_match(info->rev.patchid, rev.patchid))
- return info;
+ for (int k = 0; info->chip_ids[k]; k++)
+ if (info->chip_ids[k] == chip_id)
+ return info;
+ }
}
return NULL;
@@ -370,25 +93,35 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
if (ret)
return NULL;
- /* Make sure pm runtime is active and reset any previous errors */
- pm_runtime_set_active(&pdev->dev);
+ if (gpu->funcs->ucode_load) {
+ ret = gpu->funcs->ucode_load(gpu);
+ if (ret)
+ return NULL;
+ }
+
+ /*
+ * Now that we have firmware loaded, and are ready to begin
+ * booting the gpu, go ahead and enable runpm:
+ */
+ pm_runtime_enable(&pdev->dev);
ret = pm_runtime_get_sync(&pdev->dev);
if (ret < 0) {
- pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_put_noidle(&pdev->dev);
DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
- return NULL;
+ goto err_disable_rpm;
}
- mutex_lock(&dev->struct_mutex);
+ mutex_lock(&gpu->lock);
ret = msm_gpu_hw_init(gpu);
- mutex_unlock(&dev->struct_mutex);
- pm_runtime_put_autosuspend(&pdev->dev);
+ mutex_unlock(&gpu->lock);
if (ret) {
DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
- return NULL;
+ goto err_put_rpm;
}
+ pm_runtime_put_autosuspend(&pdev->dev);
+
#ifdef CONFIG_DEBUG_FS
if (gpu->funcs->debugfs_init) {
gpu->funcs->debugfs_init(gpu, dev->primary);
@@ -397,21 +130,19 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
#endif
return gpu;
-}
-static void set_gpu_pdev(struct drm_device *dev,
- struct platform_device *pdev)
-{
- struct msm_drm_private *priv = dev->dev_private;
- priv->gpu_pdev = pdev;
+err_put_rpm:
+ pm_runtime_put_sync_suspend(&pdev->dev);
+err_disable_rpm:
+ pm_runtime_disable(&pdev->dev);
+
+ return NULL;
}
-static int find_chipid(struct device *dev, struct adreno_rev *rev)
+static int find_chipid(struct device_node *node, uint32_t *chipid)
{
- struct device_node *node = dev->of_node;
const char *compat;
int ret;
- u32 chipid;
/* first search the compat strings for qcom,adreno-XYZ.W: */
ret = of_property_read_string_index(node, "compatible", 0, &compat);
@@ -420,134 +151,146 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
- rev->core = r / 100;
+ uint32_t core, major, minor;
+
+ core = r / 100;
r %= 100;
- rev->major = r / 10;
+ major = r / 10;
r %= 10;
- rev->minor = r;
- rev->patchid = patch;
+ minor = r;
+
+ *chipid = (core << 24) |
+ (major << 16) |
+ (minor << 8) |
+ patch;
return 0;
}
+
+ if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)
+ return 0;
}
/* and if that fails, fall back to legacy "qcom,chipid" property: */
- ret = of_property_read_u32(node, "qcom,chipid", &chipid);
+ ret = of_property_read_u32(node, "qcom,chipid", chipid);
if (ret) {
- DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
+ DRM_ERROR("%pOF: could not parse qcom,chipid: %d\n",
+ node, ret);
return ret;
}
- rev->core = (chipid >> 24) & 0xff;
- rev->major = (chipid >> 16) & 0xff;
- rev->minor = (chipid >> 8) & 0xff;
- rev->patchid = (chipid & 0xff);
-
- dev_warn(dev, "Using legacy qcom,chipid binding!\n");
- dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
- rev->core, rev->major, rev->minor, rev->patchid);
+ pr_warn("%pOF: Using legacy qcom,chipid binding!\n", node);
return 0;
}
+bool adreno_has_gpu(struct device_node *node)
+{
+ const struct adreno_info *info;
+ uint32_t chip_id;
+ int ret;
+
+ if (skip_gpu)
+ return false;
+
+ ret = find_chipid(node, &chip_id);
+ if (ret)
+ return false;
+
+ info = adreno_info(chip_id);
+ if (!info) {
+ pr_warn("%pOF: Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
+ node, ADRENO_CHIPID_ARGS(chip_id));
+ return false;
+ }
+
+ return true;
+}
+
static int adreno_bind(struct device *dev, struct device *master, void *data)
{
static struct adreno_platform_config config = {};
const struct adreno_info *info;
- struct drm_device *drm = dev_get_drvdata(master);
- struct msm_drm_private *priv = drm->dev_private;
+ struct msm_drm_private *priv = dev_get_drvdata(master);
+ struct drm_device *drm = priv->dev;
struct msm_gpu *gpu;
int ret;
- ret = find_chipid(dev, &config.rev);
- if (ret)
+ ret = find_chipid(dev->of_node, &config.chip_id);
+ /* We shouldn't have gotten this far if we can't parse the chip_id */
+ if (WARN_ON(ret))
return ret;
dev->platform_data = &config;
- set_gpu_pdev(drm, to_platform_device(dev));
-
- info = adreno_info(config.rev);
+ priv->gpu_pdev = to_platform_device(dev);
- if (!info) {
- dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
- config.rev.core, config.rev.major,
- config.rev.minor, config.rev.patchid);
+ info = adreno_info(config.chip_id);
+ /* We shouldn't have gotten this far if we don't recognize the GPU: */
+ if (WARN_ON(!info))
return -ENXIO;
- }
- DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
- config.rev.minor, config.rev.patchid);
+ config.info = info;
+
+ DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));
- priv->is_a2xx = config.rev.core == 2;
- priv->has_cached_coherent = config.rev.core >= 6;
+ priv->is_a2xx = info->family < ADRENO_3XX;
+ priv->has_cached_coherent =
+ !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
- gpu = info->init(drm);
+ gpu = info->funcs->init(drm);
if (IS_ERR(gpu)) {
dev_warn(drm->dev, "failed to load adreno gpu\n");
return PTR_ERR(gpu);
}
+ ret = dev_pm_opp_of_find_icc_paths(dev, NULL);
+ if (ret)
+ return ret;
+
return 0;
}
+static int adreno_system_suspend(struct device *dev);
static void adreno_unbind(struct device *dev, struct device *master,
void *data)
{
+ struct msm_drm_private *priv = dev_get_drvdata(master);
struct msm_gpu *gpu = dev_to_gpu(dev);
- pm_runtime_force_suspend(dev);
+ if (pm_runtime_enabled(dev))
+ WARN_ON_ONCE(adreno_system_suspend(dev));
gpu->funcs->destroy(gpu);
- set_gpu_pdev(dev_get_drvdata(master), NULL);
+ priv->gpu_pdev = NULL;
}
static const struct component_ops a3xx_ops = {
- .bind = adreno_bind,
- .unbind = adreno_unbind,
+ .bind = adreno_bind,
+ .unbind = adreno_unbind,
};
-static void adreno_device_register_headless(void)
-{
- /* on imx5, we don't have a top-level mdp/dpu node
- * this creates a dummy node for the driver for that case
- */
- struct platform_device_info dummy_info = {
- .parent = NULL,
- .name = "msm",
- .id = -1,
- .res = NULL,
- .num_res = 0,
- .data = NULL,
- .size_data = 0,
- .dma_mask = ~0,
- };
- platform_device_register_full(&dummy_info);
-}
-
static int adreno_probe(struct platform_device *pdev)
{
+ if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") ||
+ msm_gpu_no_components())
+ return msm_gpu_probe(pdev, &a3xx_ops);
- int ret;
-
- ret = component_add(&pdev->dev, &a3xx_ops);
- if (ret)
- return ret;
-
- if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
- adreno_device_register_headless();
-
- return 0;
+ return component_add(&pdev->dev, &a3xx_ops);
}
-static int adreno_remove(struct platform_device *pdev)
+static void adreno_remove(struct platform_device *pdev)
{
- component_del(&pdev->dev, &a3xx_ops);
- return 0;
+ struct msm_drm_private *priv = platform_get_drvdata(pdev);
+
+ if (priv->kms_init)
+ component_del(&pdev->dev, &a3xx_ops);
+ else
+ msm_gpu_remove(pdev, &a3xx_ops);
}
static void adreno_shutdown(struct platform_device *pdev)
{
- pm_runtime_force_suspend(&pdev->dev);
+ WARN_ON_ONCE(adreno_system_suspend(&pdev->dev));
}
static const struct of_device_id dt_match[] = {
@@ -560,25 +303,101 @@ static const struct of_device_id dt_match[] = {
{}
};
-#ifdef CONFIG_PM
-static int adreno_resume(struct device *dev)
+static int adreno_runtime_resume(struct device *dev)
{
struct msm_gpu *gpu = dev_to_gpu(dev);
return gpu->funcs->pm_resume(gpu);
}
-static int adreno_suspend(struct device *dev)
+static int adreno_runtime_suspend(struct device *dev)
{
struct msm_gpu *gpu = dev_to_gpu(dev);
+ /*
+ * We should be holding a runpm ref, which will prevent
+ * runtime suspend. In the system suspend path, we've
+ * already waited for active jobs to complete.
+ */
+ WARN_ON_ONCE(gpu->active_submits);
+
return gpu->funcs->pm_suspend(gpu);
}
-#endif
+
+static void suspend_scheduler(struct msm_gpu *gpu)
+{
+ int i;
+
+ /*
+ * Shut down the scheduler before we force suspend, so that
+ * suspend isn't racing with scheduler kthread feeding us
+ * more work.
+ *
+ * Note, we just want to park the thread, and let any jobs
+ * that are already on the hw queue complete normally, as
+ * opposed to the drm_sched_stop() path used for handling
+ * faulting/timed-out jobs. We can't really cancel any jobs
+ * already on the hw queue without racing with the GPU.
+ */
+ for (i = 0; i < gpu->nr_rings; i++) {
+ struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
+
+ drm_sched_wqueue_stop(sched);
+ }
+}
+
+static void resume_scheduler(struct msm_gpu *gpu)
+{
+ int i;
+
+ for (i = 0; i < gpu->nr_rings; i++) {
+ struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
+
+ drm_sched_wqueue_start(sched);
+ }
+}
+
+static int adreno_system_suspend(struct device *dev)
+{
+ struct msm_gpu *gpu = dev_to_gpu(dev);
+ int remaining, ret;
+
+ if (!gpu)
+ return 0;
+
+ suspend_scheduler(gpu);
+
+ remaining = wait_event_timeout(gpu->retire_event,
+ gpu->active_submits == 0,
+ msecs_to_jiffies(1000));
+ if (remaining == 0) {
+ dev_err(dev, "Timeout waiting for GPU to suspend\n");
+ ret = -EBUSY;
+ goto out;
+ }
+
+ ret = pm_runtime_force_suspend(dev);
+out:
+ if (ret)
+ resume_scheduler(gpu);
+
+ return ret;
+}
+
+static int adreno_system_resume(struct device *dev)
+{
+ struct msm_gpu *gpu = dev_to_gpu(dev);
+
+ if (!gpu)
+ return 0;
+
+ resume_scheduler(gpu);
+ return pm_runtime_force_resume(dev);
+}
static const struct dev_pm_ops adreno_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
- SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
+ SYSTEM_SLEEP_PM_OPS(adreno_system_suspend, adreno_system_resume)
+ RUNTIME_PM_OPS(adreno_runtime_suspend, adreno_runtime_resume, NULL)
};
static struct platform_driver adreno_driver = {
@@ -594,10 +413,16 @@ static struct platform_driver adreno_driver = {
void __init adreno_register(void)
{
+ if (skip_gpu)
+ return;
+
platform_driver_register(&adreno_driver);
}
void __exit adreno_unregister(void)
{
+ if (skip_gpu)
+ return;
+
platform_driver_unregister(&adreno_driver);
}
generated by cgit (git 2.34.1) at 2025-12-25 15:13:22 +0000