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path: root/drivers/gpu/drm/msm/adreno/adreno_device.c
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Diffstat (limited to 'drivers/gpu/drm/msm/adreno/adreno_device.c')
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_device.c647
1 files changed, 93 insertions, 554 deletions
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 575e7c56219f..554d746f115b 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -16,521 +16,50 @@ bool snapshot_debugbus = false;
MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
-bool allow_vram_carveout = false;
-MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
-module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
-
-static const struct adreno_info gpulist[] = {
- {
- .chip_ids = ADRENO_CHIP_IDS(0x02000000),
- .family = ADRENO_2XX_GEN1,
- .revn = 200,
- .fw = {
- [ADRENO_FW_PM4] = "yamato_pm4.fw",
- [ADRENO_FW_PFP] = "yamato_pfp.fw",
- },
- .gmem = SZ_256K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a2xx_gpu_init,
- }, { /* a200 on i.mx51 has only 128kib gmem */
- .chip_ids = ADRENO_CHIP_IDS(0x02000001),
- .family = ADRENO_2XX_GEN1,
- .revn = 201,
- .fw = {
- [ADRENO_FW_PM4] = "yamato_pm4.fw",
- [ADRENO_FW_PFP] = "yamato_pfp.fw",
- },
- .gmem = SZ_128K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a2xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x02020000),
- .family = ADRENO_2XX_GEN2,
- .revn = 220,
- .fw = {
- [ADRENO_FW_PM4] = "leia_pm4_470.fw",
- [ADRENO_FW_PFP] = "leia_pfp_470.fw",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a2xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x03000512,
- 0x03000520
- ),
- .family = ADRENO_3XX,
- .revn = 305,
- .fw = {
- [ADRENO_FW_PM4] = "a300_pm4.fw",
- [ADRENO_FW_PFP] = "a300_pfp.fw",
- },
- .gmem = SZ_256K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x03000600),
- .family = ADRENO_3XX,
- .revn = 307, /* because a305c is revn==306 */
- .fw = {
- [ADRENO_FW_PM4] = "a300_pm4.fw",
- [ADRENO_FW_PFP] = "a300_pfp.fw",
- },
- .gmem = SZ_128K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x03020000,
- 0x03020001,
- 0x03020002
- ),
- .family = ADRENO_3XX,
- .revn = 320,
- .fw = {
- [ADRENO_FW_PM4] = "a300_pm4.fw",
- [ADRENO_FW_PFP] = "a300_pfp.fw",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x03030000,
- 0x03030001,
- 0x03030002
- ),
- .family = ADRENO_3XX,
- .revn = 330,
- .fw = {
- [ADRENO_FW_PM4] = "a330_pm4.fw",
- [ADRENO_FW_PFP] = "a330_pfp.fw",
- },
- .gmem = SZ_1M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a3xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x04000500),
- .family = ADRENO_4XX,
- .revn = 405,
- .fw = {
- [ADRENO_FW_PM4] = "a420_pm4.fw",
- [ADRENO_FW_PFP] = "a420_pfp.fw",
- },
- .gmem = SZ_256K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a4xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x04020000),
- .family = ADRENO_4XX,
- .revn = 420,
- .fw = {
- [ADRENO_FW_PM4] = "a420_pm4.fw",
- [ADRENO_FW_PFP] = "a420_pfp.fw",
- },
- .gmem = (SZ_1M + SZ_512K),
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a4xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x04030002),
- .family = ADRENO_4XX,
- .revn = 430,
- .fw = {
- [ADRENO_FW_PM4] = "a420_pm4.fw",
- [ADRENO_FW_PFP] = "a420_pfp.fw",
- },
- .gmem = (SZ_1M + SZ_512K),
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a4xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x05000600),
- .family = ADRENO_5XX,
- .revn = 506,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = (SZ_128K + SZ_8K),
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
- ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- .zapfw = "a506_zap.mdt",
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x05000800),
- .family = ADRENO_5XX,
- .revn = 508,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = (SZ_128K + SZ_8K),
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- .zapfw = "a508_zap.mdt",
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x05000900),
- .family = ADRENO_5XX,
- .revn = 509,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = (SZ_256K + SZ_16K),
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- /* Adreno 509 uses the same ZAP as 512 */
- .zapfw = "a512_zap.mdt",
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x05010000),
- .family = ADRENO_5XX,
- .revn = 510,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = SZ_256K,
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .init = a5xx_gpu_init,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x05010200),
- .family = ADRENO_5XX,
- .revn = 512,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- },
- .gmem = (SZ_256K + SZ_16K),
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- .zapfw = "a512_zap.mdt",
- }, {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x05030002,
- 0x05030004
- ),
- .family = ADRENO_5XX,
- .revn = 530,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
- },
- .gmem = SZ_1M,
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
- ADRENO_QUIRK_FAULT_DETECT_MASK,
- .init = a5xx_gpu_init,
- .zapfw = "a530_zap.mdt",
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x05040001),
- .family = ADRENO_5XX,
- .revn = 540,
- .fw = {
- [ADRENO_FW_PM4] = "a530_pm4.fw",
- [ADRENO_FW_PFP] = "a530_pfp.fw",
- [ADRENO_FW_GPMU] = "a540_gpmu.fw2",
- },
- .gmem = SZ_1M,
- /*
- * Increase inactive period to 250 to avoid bouncing
- * the GDSC which appears to make it grumpy
- */
- .inactive_period = 250,
- .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
- .init = a5xx_gpu_init,
- .zapfw = "a540_zap.mdt",
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06010000),
- .family = ADRENO_6XX_GEN1,
- .revn = 610,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- },
- .gmem = (SZ_128K + SZ_4K),
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a6xx_gpu_init,
- .zapfw = "a610_zap.mdt",
- .hwcg = a612_hwcg,
- /*
- * There are (at least) three SoCs implementing A610: SM6125
- * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
- * not have speedbinning, as only a single SKU exists and we
- * don't support khaje upstream yet. Hence, this matching
- * table is only valid for bengal.
- */
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 206, 1 },
- { 200, 2 },
- { 157, 3 },
- { 127, 4 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06010800),
- .family = ADRENO_6XX_GEN1,
- .revn = 618,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a630_gmu.bin",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
- .init = a6xx_gpu_init,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 169, 1 },
- { 174, 2 },
- ),
- }, {
- .machine = "qcom,sm4350",
- .chip_ids = ADRENO_CHIP_IDS(0x06010900),
- .family = ADRENO_6XX_GEN1,
- .revn = 619,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a619_gmu.bin",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a6xx_gpu_init,
- .zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 138, 1 },
- { 92, 2 },
- ),
- }, {
- .machine = "qcom,sm6375",
- .chip_ids = ADRENO_CHIP_IDS(0x06010900),
- .family = ADRENO_6XX_GEN1,
- .revn = 619,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a619_gmu.bin",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .init = a6xx_gpu_init,
- .zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 190, 1 },
- { 177, 2 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06010900),
- .family = ADRENO_6XX_GEN1,
- .revn = 619,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a619_gmu.bin",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
- .init = a6xx_gpu_init,
- .zapfw = "a615_zap.mdt",
- .hwcg = a615_hwcg,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 120, 4 },
- { 138, 3 },
- { 169, 2 },
- { 180, 1 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(
- 0x06030001,
- 0x06030002
- ),
- .family = ADRENO_6XX_GEN1,
- .revn = 630,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a630_gmu.bin",
- },
- .gmem = SZ_1M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
- .init = a6xx_gpu_init,
- .zapfw = "a630_zap.mdt",
- .hwcg = a630_hwcg,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06040001),
- .family = ADRENO_6XX_GEN2,
- .revn = 640,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a640_gmu.bin",
- },
- .gmem = SZ_1M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
- .init = a6xx_gpu_init,
- .zapfw = "a640_zap.mdt",
- .hwcg = a640_hwcg,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 1, 1 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06050002),
- .family = ADRENO_6XX_GEN3,
- .revn = 650,
- .fw = {
- [ADRENO_FW_SQE] = "a650_sqe.fw",
- [ADRENO_FW_GMU] = "a650_gmu.bin",
- },
- .gmem = SZ_1M + SZ_128K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
- ADRENO_QUIRK_HAS_HW_APRIV,
- .init = a6xx_gpu_init,
- .zapfw = "a650_zap.mdt",
- .hwcg = a650_hwcg,
- .address_space_size = SZ_16G,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 1, 1 },
- { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */
- { 3, 2 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06060001),
- .family = ADRENO_6XX_GEN4,
- .revn = 660,
- .fw = {
- [ADRENO_FW_SQE] = "a660_sqe.fw",
- [ADRENO_FW_GMU] = "a660_gmu.bin",
- },
- .gmem = SZ_1M + SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
- ADRENO_QUIRK_HAS_HW_APRIV,
- .init = a6xx_gpu_init,
- .zapfw = "a660_zap.mdt",
- .hwcg = a660_hwcg,
- .address_space_size = SZ_16G,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06030500),
- .family = ADRENO_6XX_GEN4,
- .fw = {
- [ADRENO_FW_SQE] = "a660_sqe.fw",
- [ADRENO_FW_GMU] = "a660_gmu.bin",
- },
- .gmem = SZ_512K,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
- ADRENO_QUIRK_HAS_HW_APRIV,
- .init = a6xx_gpu_init,
- .hwcg = a660_hwcg,
- .address_space_size = SZ_16G,
- .speedbins = ADRENO_SPEEDBINS(
- { 0, 0 },
- { 117, 0 },
- { 190, 1 },
- ),
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06080000),
- .family = ADRENO_6XX_GEN2,
- .revn = 680,
- .fw = {
- [ADRENO_FW_SQE] = "a630_sqe.fw",
- [ADRENO_FW_GMU] = "a640_gmu.bin",
- },
- .gmem = SZ_2M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
- .init = a6xx_gpu_init,
- .zapfw = "a640_zap.mdt",
- .hwcg = a640_hwcg,
- }, {
- .chip_ids = ADRENO_CHIP_IDS(0x06090000),
- .family = ADRENO_6XX_GEN4,
- .fw = {
- [ADRENO_FW_SQE] = "a660_sqe.fw",
- [ADRENO_FW_GMU] = "a660_gmu.bin",
- },
- .gmem = SZ_4M,
- .inactive_period = DRM_MSM_INACTIVE_PERIOD,
- .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
- ADRENO_QUIRK_HAS_HW_APRIV,
- .init = a6xx_gpu_init,
- .zapfw = "a690_zap.mdt",
- .hwcg = a690_hwcg,
- .address_space_size = SZ_16G,
- },
+int enable_preemption = -1;
+MODULE_PARM_DESC(enable_preemption, "Enable preemption (A7xx only) (1=on , 0=disable, -1=auto (default))");
+module_param(enable_preemption, int, 0600);
+
+bool disable_acd;
+MODULE_PARM_DESC(disable_acd, "Forcefully disable GPU ACD");
+module_param_unsafe(disable_acd, bool, 0400);
+
+static bool skip_gpu;
+MODULE_PARM_DESC(no_gpu, "Disable GPU driver register (0=enable GPU driver register (default), 1=skip GPU driver register");
+module_param(skip_gpu, bool, 0400);
+
+extern const struct adreno_gpulist a2xx_gpulist;
+extern const struct adreno_gpulist a3xx_gpulist;
+extern const struct adreno_gpulist a4xx_gpulist;
+extern const struct adreno_gpulist a5xx_gpulist;
+extern const struct adreno_gpulist a6xx_gpulist;
+extern const struct adreno_gpulist a7xx_gpulist;
+extern const struct adreno_gpulist a8xx_gpulist;
+
+static const struct adreno_gpulist *gpulists[] = {
+ &a2xx_gpulist,
+ &a3xx_gpulist,
+ &a4xx_gpulist,
+ &a5xx_gpulist,
+ &a6xx_gpulist,
+ &a7xx_gpulist,
+ &a8xx_gpulist,
};
-MODULE_FIRMWARE("qcom/a300_pm4.fw");
-MODULE_FIRMWARE("qcom/a300_pfp.fw");
-MODULE_FIRMWARE("qcom/a330_pm4.fw");
-MODULE_FIRMWARE("qcom/a330_pfp.fw");
-MODULE_FIRMWARE("qcom/a420_pm4.fw");
-MODULE_FIRMWARE("qcom/a420_pfp.fw");
-MODULE_FIRMWARE("qcom/a530_pm4.fw");
-MODULE_FIRMWARE("qcom/a530_pfp.fw");
-MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
-MODULE_FIRMWARE("qcom/a530_zap.mdt");
-MODULE_FIRMWARE("qcom/a530_zap.b00");
-MODULE_FIRMWARE("qcom/a530_zap.b01");
-MODULE_FIRMWARE("qcom/a530_zap.b02");
-MODULE_FIRMWARE("qcom/a540_gpmu.fw2");
-MODULE_FIRMWARE("qcom/a619_gmu.bin");
-MODULE_FIRMWARE("qcom/a630_sqe.fw");
-MODULE_FIRMWARE("qcom/a630_gmu.bin");
-MODULE_FIRMWARE("qcom/a630_zap.mbn");
-MODULE_FIRMWARE("qcom/a640_gmu.bin");
-MODULE_FIRMWARE("qcom/a650_gmu.bin");
-MODULE_FIRMWARE("qcom/a650_sqe.fw");
-MODULE_FIRMWARE("qcom/a660_gmu.bin");
-MODULE_FIRMWARE("qcom/a660_sqe.fw");
-MODULE_FIRMWARE("qcom/leia_pfp_470.fw");
-MODULE_FIRMWARE("qcom/leia_pm4_470.fw");
-MODULE_FIRMWARE("qcom/yamato_pfp.fw");
-MODULE_FIRMWARE("qcom/yamato_pm4.fw");
-
static const struct adreno_info *adreno_info(uint32_t chip_id)
{
/* identify gpu: */
- for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {
- const struct adreno_info *info = &gpulist[i];
- if (info->machine && !of_machine_is_compatible(info->machine))
- continue;
- for (int j = 0; info->chip_ids[j]; j++)
- if (info->chip_ids[j] == chip_id)
- return info;
+ for (int i = 0; i < ARRAY_SIZE(gpulists); i++) {
+ for (int j = 0; j < gpulists[i]->gpus_count; j++) {
+ const struct adreno_info *info = &gpulists[i]->gpus[j];
+
+ if (info->machine && !of_machine_is_compatible(info->machine))
+ continue;
+
+ for (int k = 0; info->chip_ids[k]; k++)
+ if (info->chip_ids[k] == chip_id)
+ return info;
+ }
}
return NULL;
@@ -610,9 +139,8 @@ err_disable_rpm:
return NULL;
}
-static int find_chipid(struct device *dev, uint32_t *chipid)
+static int find_chipid(struct device_node *node, uint32_t *chipid)
{
- struct device_node *node = dev->of_node;
const char *compat;
int ret;
@@ -646,15 +174,39 @@ static int find_chipid(struct device *dev, uint32_t *chipid)
/* and if that fails, fall back to legacy "qcom,chipid" property: */
ret = of_property_read_u32(node, "qcom,chipid", chipid);
if (ret) {
- DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
+ DRM_ERROR("%pOF: could not parse qcom,chipid: %d\n",
+ node, ret);
return ret;
}
- dev_warn(dev, "Using legacy qcom,chipid binding!\n");
+ pr_warn("%pOF: Using legacy qcom,chipid binding!\n", node);
return 0;
}
+bool adreno_has_gpu(struct device_node *node)
+{
+ const struct adreno_info *info;
+ uint32_t chip_id;
+ int ret;
+
+ if (skip_gpu)
+ return false;
+
+ ret = find_chipid(node, &chip_id);
+ if (ret)
+ return false;
+
+ info = adreno_info(chip_id);
+ if (!info) {
+ pr_warn("%pOF: Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
+ node, ADRENO_CHIPID_ARGS(chip_id));
+ return false;
+ }
+
+ return true;
+}
+
static int adreno_bind(struct device *dev, struct device *master, void *data)
{
static struct adreno_platform_config config = {};
@@ -664,19 +216,18 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
struct msm_gpu *gpu;
int ret;
- ret = find_chipid(dev, &config.chip_id);
- if (ret)
+ ret = find_chipid(dev->of_node, &config.chip_id);
+ /* We shouldn't have gotten this far if we can't parse the chip_id */
+ if (WARN_ON(ret))
return ret;
dev->platform_data = &config;
priv->gpu_pdev = to_platform_device(dev);
info = adreno_info(config.chip_id);
- if (!info) {
- dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",
- ADRENO_CHIPID_ARGS(config.chip_id));
+ /* We shouldn't have gotten this far if we don't recognize the GPU: */
+ if (WARN_ON(!info))
return -ENXIO;
- }
config.info = info;
@@ -686,7 +237,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
priv->has_cached_coherent =
!!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT);
- gpu = info->init(drm);
+ gpu = info->funcs->init(drm);
if (IS_ERR(gpu)) {
dev_warn(drm->dev, "failed to load adreno gpu\n");
return PTR_ERR(gpu);
@@ -718,43 +269,23 @@ static const struct component_ops a3xx_ops = {
.unbind = adreno_unbind,
};
-static void adreno_device_register_headless(void)
-{
- /* on imx5, we don't have a top-level mdp/dpu node
- * this creates a dummy node for the driver for that case
- */
- struct platform_device_info dummy_info = {
- .parent = NULL,
- .name = "msm",
- .id = -1,
- .res = NULL,
- .num_res = 0,
- .data = NULL,
- .size_data = 0,
- .dma_mask = ~0,
- };
- platform_device_register_full(&dummy_info);
-}
-
static int adreno_probe(struct platform_device *pdev)
{
+ if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon") ||
+ msm_gpu_no_components())
+ return msm_gpu_probe(pdev, &a3xx_ops);
- int ret;
-
- ret = component_add(&pdev->dev, &a3xx_ops);
- if (ret)
- return ret;
-
- if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
- adreno_device_register_headless();
-
- return 0;
+ return component_add(&pdev->dev, &a3xx_ops);
}
-static int adreno_remove(struct platform_device *pdev)
+static void adreno_remove(struct platform_device *pdev)
{
- component_del(&pdev->dev, &a3xx_ops);
- return 0;
+ struct msm_drm_private *priv = platform_get_drvdata(pdev);
+
+ if (priv->kms_init)
+ component_del(&pdev->dev, &a3xx_ops);
+ else
+ msm_gpu_remove(pdev, &a3xx_ops);
}
static void adreno_shutdown(struct platform_device *pdev)
@@ -810,7 +341,8 @@ static void suspend_scheduler(struct msm_gpu *gpu)
*/
for (i = 0; i < gpu->nr_rings; i++) {
struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
- kthread_park(sched->thread);
+
+ drm_sched_wqueue_stop(sched);
}
}
@@ -820,7 +352,8 @@ static void resume_scheduler(struct msm_gpu *gpu)
for (i = 0; i < gpu->nr_rings; i++) {
struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
- kthread_unpark(sched->thread);
+
+ drm_sched_wqueue_start(sched);
}
}
@@ -880,10 +413,16 @@ static struct platform_driver adreno_driver = {
void __init adreno_register(void)
{
+ if (skip_gpu)
+ return;
+
platform_driver_register(&adreno_driver);
}
void __exit adreno_unregister(void)
{
+ if (skip_gpu)
+ return;
+
platform_driver_unregister(&adreno_driver);
}
generated by cgit (git 2.34.1) at 2025-12-25 16:11:49 +0000